arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         aliases {
  18                 ethernet0 = &fec1;
  19                 ethernet1 = &fec2;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42                 spi3 = &ecspi4;
  43                 usbphy0 = &usbphy1;
  44                 usbphy1 = &usbphy2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <0>;
  55                         clock-latency = <61036>; /* two CLK32 periods */
  56                         operating-points = <
  57                                 /* kHz  uV */
  58                                 528000  1250000
  59                                 396000  1150000
  60                                 198000  1150000
  61                         >;
  62                         fsl,soc-operating-points = <
  63                                 /* KHz  uV */
  64                                 528000  1250000
  65                                 396000  1150000
  66                                 198000  1150000
  67                         >;
  68                         clocks = <&clks IMX6UL_CLK_ARM>,
  69                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  70                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  71                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  72                                  <&clks IMX6UL_CLK_STEP>,
  73                                  <&clks IMX6UL_CLK_PLL1_SW>,
  74                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  75                                  <&clks IMX6UL_PLL1_BYPASS>,
  76                                  <&clks IMX6UL_CLK_PLL1>,
  77                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  78                                  <&clks IMX6UL_CLK_OSC>;
  79                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  80                                       "secondary_sel", "step", "pll1_sw",
  81                                       "pll1_sys", "pll1_bypass", "pll1",
  82                                       "pll1_bypass_src", "osc";
  83                         arm-supply = <&reg_arm>;
  84                         soc-supply = <&reg_soc>;
  85                 };
  86         };
  87
  88         intc: interrupt-controller@00a01000 {
  89                 compatible = "arm,cortex-a7-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x00a01000 0x1000>,
  93                       <0x00a02000 0x1000>,
  94                       <0x00a04000 0x2000>,
  95                       <0x00a06000 0x2000>;
  96         };
  97
  98         ckil: clock-cli {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         ipp_di0: clock-di0 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <0>;
 116                 clock-output-names = "ipp_di0";
 117         };
 118
 119         ipp_di1: clock-di1 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "ipp_di1";
 124         };
 125
 126         soc {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 compatible = "simple-bus";
 130                 interrupt-parent = <&gpc>;
 131                 ranges;
 132
 133                 pmu {
 134                         compatible = "arm,cortex-a7-pmu";
 135                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 136                         status = "disabled";
 137                 };
 138
 139                 ocram: sram@00900000 {
 140                         compatible = "mmio-sram";
 141                         reg = <0x00900000 0x20000>;
 142                 };
 143
 144                 dma_apbh: dma-apbh@01804000 {
 145                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 146                         reg = <0x01804000 0x2000>;
 147                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 152                         #dma-cells = <1>;
 153                         dma-channels = <4>;
 154                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 155                 };
 156
 157                 gpmi: gpmi-nand@01806000         {
 158                         compatible = "fsl,imx6q-gpmi-nand";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 162                         reg-names = "gpmi-nand", "bch";
 163                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 164                         interrupt-names = "bch";
 165                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 166                                  <&clks IMX6UL_CLK_GPMI_APB>,
 167                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 168                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 169                                  <&clks IMX6UL_CLK_PER_BCH>;
 170                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 171                                       "gpmi_bch_apb", "per1_bch";
 172                         dmas = <&dma_apbh 0>;
 173                         dma-names = "rx-tx";
 174                         status = "disabled";
 175                 };
 176
 177                 aips1: aips-bus@02000000 {
 178                         compatible = "fsl,aips-bus", "simple-bus";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         reg = <0x02000000 0x100000>;
 182                         ranges;
 183
 184                         spba-bus@02000000 {
 185                                 compatible = "fsl,spba-bus", "simple-bus";
 186                                 #address-cells = <1>;
 187                                 #size-cells = <1>;
 188                                 reg = <0x02000000 0x40000>;
 189                                 ranges;
 190
 191                                 ecspi1: ecspi@02008000 {
 192                                         #address-cells = <1>;
 193                                         #size-cells = <0>;
 194                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 195                                         reg = <0x02008000 0x4000>;
 196                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 197                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 198                                                  <&clks IMX6UL_CLK_ECSPI1>;
 199                                         clock-names = "ipg", "per";
 200                                         status = "disabled";
 201                                 };
 202
 203                                 ecspi2: ecspi@0200c000 {
 204                                         #address-cells = <1>;
 205                                         #size-cells = <0>;
 206                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 207                                         reg = <0x0200c000 0x4000>;
 208                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 209                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 210                                                  <&clks IMX6UL_CLK_ECSPI2>;
 211                                         clock-names = "ipg", "per";
 212                                         status = "disabled";
 213                                 };
 214
 215                                 ecspi3: ecspi@02010000 {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 219                                         reg = <0x02010000 0x4000>;
 220                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 222                                                  <&clks IMX6UL_CLK_ECSPI3>;
 223                                         clock-names = "ipg", "per";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi4: ecspi@02014000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x02014000 0x4000>;
 232                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 234                                                  <&clks IMX6UL_CLK_ECSPI4>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 uart7: serial@02018000 {
 240                                         compatible = "fsl,imx6ul-uart",
 241                                                      "fsl,imx6q-uart";
 242                                         reg = <0x02018000 0x4000>;
 243                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 245                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 246                                         clock-names = "ipg", "per";
 247                                         status = "disabled";
 248                                 };
 249
 250                                 uart1: serial@02020000 {
 251                                         compatible = "fsl,imx6ul-uart",
 252                                                      "fsl,imx6q-uart";
 253                                         reg = <0x02020000 0x4000>;
 254                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 255                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 256                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 257                                         clock-names = "ipg", "per";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 uart8: serial@02024000 {
 262                                         compatible = "fsl,imx6ul-uart",
 263                                                      "fsl,imx6q-uart";
 264                                         reg = <0x02024000 0x4000>;
 265                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 267                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 sai1: sai@02028000 {
 273                                         #sound-dai-cells = <0>;
 274                                         compatible = "fsl,imx6sx-sai";
 275                                         reg = <0x02028000 0x4000>;
 276                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 277                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 278                                                  <&clks IMX6UL_CLK_SAI1>,
 279                                                  <&clks 0>, <&clks 0>;
 280                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 281                                         dmas = <&sdma 35 24 0>,
 282                                                <&sdma 36 24 0>;
 283                                         dma-names = "rx", "tx";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 sai2: sai@0202c000 {
 288                                         #sound-dai-cells = <0>;
 289                                         compatible = "fsl,imx6sx-sai";
 290                                         reg = <0x0202c000 0x4000>;
 291                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 293                                                  <&clks IMX6UL_CLK_SAI2>,
 294                                                  <&clks 0>, <&clks 0>;
 295                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 296                                         dmas = <&sdma 37 24 0>,
 297                                                <&sdma 38 24 0>;
 298                                         dma-names = "rx", "tx";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 sai3: sai@02030000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6sx-sai";
 305                                         reg = <0x02030000 0x4000>;
 306                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 308                                                  <&clks IMX6UL_CLK_SAI3>,
 309                                                  <&clks 0>, <&clks 0>;
 310                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 311                                         dmas = <&sdma 39 24 0>,
 312                                                <&sdma 40 24 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316                         };
 317
 318                         tsc: tsc@02040000 {
 319                                 compatible = "fsl,imx6ul-tsc";
 320                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 321                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 322                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clks IMX6UL_CLK_IPG>,
 324                                          <&clks IMX6UL_CLK_ADC2>;
 325                                 clock-names = "tsc", "adc";
 326                                 status = "disabled";
 327                         };
 328
 329                         can1: flexcan@02090000 {
 330                                 compatible = "fsl,imx6q-flexcan";
 331                                 reg = <0x02090000 0x4000>;
 332                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 333                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 334                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 335                                 clock-names = "ipg", "per";
 336                                 status = "disabled";
 337                         };
 338
 339                         can2: flexcan@02094000 {
 340                                 compatible = "fsl,imx6q-flexcan";
 341                                 reg = <0x02094000 0x4000>;
 342                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 343                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 344                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 345                                 clock-names = "ipg", "per";
 346                                 status = "disabled";
 347                         };
 348
 349                         gpt1: gpt@02098000 {
 350                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 351                                 reg = <0x02098000 0x4000>;
 352                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 353                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 354                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 355                                 clock-names = "ipg", "per";
 356                         };
 357
 358                         gpio1: gpio@0209c000 {
 359                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 360                                 reg = <0x0209c000 0x4000>;
 361                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 362                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 363                                 gpio-controller;
 364                                 #gpio-cells = <2>;
 365                                 interrupt-controller;
 366                                 #interrupt-cells = <2>;
 367                         };
 368
 369                         gpio2: gpio@020a0000 {
 370                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 371                                 reg = <0x020a0000 0x4000>;
 372                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 373                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                         };
 379
 380                         gpio3: gpio@020a4000 {
 381                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 382                                 reg = <0x020a4000 0x4000>;
 383                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 384                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 385                                 gpio-controller;
 386                                 #gpio-cells = <2>;
 387                                 interrupt-controller;
 388                                 #interrupt-cells = <2>;
 389                         };
 390
 391                         gpio4: gpio@020a8000 {
 392                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 393                                 reg = <0x020a8000 0x4000>;
 394                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 395                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 396                                 gpio-controller;
 397                                 #gpio-cells = <2>;
 398                                 interrupt-controller;
 399                                 #interrupt-cells = <2>;
 400                         };
 401
 402                         gpio5: gpio@020ac000 {
 403                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 404                                 reg = <0x020ac000 0x4000>;
 405                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 406                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 407                                 gpio-controller;
 408                                 #gpio-cells = <2>;
 409                                 interrupt-controller;
 410                                 #interrupt-cells = <2>;
 411                         };
 412
 413                         fec2: ethernet@020b4000 {
 414                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 415                                 reg = <0x020b4000 0x4000>;
 416                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6UL_CLK_ENET>,
 419                                          <&clks IMX6UL_CLK_ENET_AHB>,
 420                                          <&clks IMX6UL_CLK_ENET_PTP>,
 421                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 422                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 423                                 clock-names = "ipg", "ahb", "ptp",
 424                                               "enet_clk_ref", "enet_out";
 425                                 fsl,num-tx-queues=<1>;
 426                                 fsl,num-rx-queues=<1>;
 427                                 status = "disabled";
 428                         };
 429
 430                         kpp: kpp@020b8000 {
 431                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 432                                 reg = <0x020b8000 0x4000>;
 433                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 434                                 clocks = <&clks IMX6UL_CLK_KPP>;
 435                                 status = "disabled";
 436                         };
 437
 438                         wdog1: wdog@020bc000 {
 439                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 440                                 reg = <0x020bc000 0x4000>;
 441                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 443                         };
 444
 445                         wdog2: wdog@020c0000 {
 446                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 447                                 reg = <0x020c0000 0x4000>;
 448                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 449                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 450                                 status = "disabled";
 451                         };
 452
 453                         clks: ccm@020c4000 {
 454                                 compatible = "fsl,imx6ul-ccm";
 455                                 reg = <0x020c4000 0x4000>;
 456                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 458                                 #clock-cells = <1>;
 459                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 460                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 461                         };
 462
 463                         anatop: anatop@020c8000 {
 464                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 465                                              "syscon", "simple-bus";
 466                                 reg = <0x020c8000 0x1000>;
 467                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 468                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 470
 471                                 reg_3p0: regulator-3p0@120 {
 472                                         compatible = "fsl,anatop-regulator";
 473                                         regulator-name = "vdd3p0";
 474                                         regulator-min-microvolt = <2625000>;
 475                                         regulator-max-microvolt = <3400000>;
 476                                         anatop-reg-offset = <0x120>;
 477                                         anatop-vol-bit-shift = <8>;
 478                                         anatop-vol-bit-width = <5>;
 479                                         anatop-min-bit-val = <0>;
 480                                         anatop-min-voltage = <2625000>;
 481                                         anatop-max-voltage = <3400000>;
 482                                         anatop-enable-bit = <0>;
 483                                 };
 484
 485                                 reg_arm: regulator-vddcore@140 {
 486                                         compatible = "fsl,anatop-regulator";
 487                                         regulator-name = "cpu";
 488                                         regulator-min-microvolt = <725000>;
 489                                         regulator-max-microvolt = <1450000>;
 490                                         regulator-always-on;
 491                                         anatop-reg-offset = <0x140>;
 492                                         anatop-vol-bit-shift = <0>;
 493                                         anatop-vol-bit-width = <5>;
 494                                         anatop-delay-reg-offset = <0x170>;
 495                                         anatop-delay-bit-shift = <24>;
 496                                         anatop-delay-bit-width = <2>;
 497                                         anatop-min-bit-val = <1>;
 498                                         anatop-min-voltage = <725000>;
 499                                         anatop-max-voltage = <1450000>;
 500                                 };
 501
 502                                 reg_soc: regulator-vddsoc@140 {
 503                                         compatible = "fsl,anatop-regulator";
 504                                         regulator-name = "vddsoc";
 505                                         regulator-min-microvolt = <725000>;
 506                                         regulator-max-microvolt = <1450000>;
 507                                         regulator-always-on;
 508                                         anatop-reg-offset = <0x140>;
 509                                         anatop-vol-bit-shift = <18>;
 510                                         anatop-vol-bit-width = <5>;
 511                                         anatop-delay-reg-offset = <0x170>;
 512                                         anatop-delay-bit-shift = <28>;
 513                                         anatop-delay-bit-width = <2>;
 514                                         anatop-min-bit-val = <1>;
 515                                         anatop-min-voltage = <725000>;
 516                                         anatop-max-voltage = <1450000>;
 517                                 };
 518                         };
 519
 520                         usbphy1: usbphy@020c9000 {
 521                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 522                                 reg = <0x020c9000 0x1000>;
 523                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 524                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 525                                 phy-3p0-supply = <&reg_3p0>;
 526                                 fsl,anatop = <&anatop>;
 527                         };
 528
 529                         usbphy2: usbphy@020ca000 {
 530                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 531                                 reg = <0x020ca000 0x1000>;
 532                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 533                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 534                                 phy-3p0-supply = <&reg_3p0>;
 535                                 fsl,anatop = <&anatop>;
 536                         };
 537
 538                         snvs: snvs@020cc000 {
 539                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 540                                 reg = <0x020cc000 0x4000>;
 541
 542                                 snvs_rtc: snvs-rtc-lp {
 543                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 544                                         regmap = <&snvs>;
 545                                         offset = <0x34>;
 546                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 547                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 548                                 };
 549
 550                                 snvs_poweroff: snvs-poweroff {
 551                                         compatible = "syscon-poweroff";
 552                                         regmap = <&snvs>;
 553                                         offset = <0x38>;
 554                                         mask = <0x60>;
 555                                         status = "disabled";
 556                                 };
 557
 558                                 snvs_pwrkey: snvs-powerkey {
 559                                         compatible = "fsl,sec-v4.0-pwrkey";
 560                                         regmap = <&snvs>;
 561                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 562                                         linux,keycode = <KEY_POWER>;
 563                                         wakeup-source;
 564                                 };
 565                         };
 566
 567                         epit1: epit@020d0000 {
 568                                 reg = <0x020d0000 0x4000>;
 569                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 570                         };
 571
 572                         epit2: epit@020d4000 {
 573                                 reg = <0x020d4000 0x4000>;
 574                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 575                         };
 576
 577                         src: src@020d8000 {
 578                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 579                                 reg = <0x020d8000 0x4000>;
 580                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 581                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 582                                 #reset-cells = <1>;
 583                         };
 584
 585                         gpc: gpc@020dc000 {
 586                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 587                                 reg = <0x020dc000 0x4000>;
 588                                 interrupt-controller;
 589                                 #interrupt-cells = <3>;
 590                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 591                                 interrupt-parent = <&intc>;
 592                         };
 593
 594                         iomuxc: iomuxc@020e0000 {
 595                                 compatible = "fsl,imx6ul-iomuxc";
 596                                 reg = <0x020e0000 0x4000>;
 597                         };
 598
 599                         gpr: iomuxc-gpr@020e4000 {
 600                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 601                                 reg = <0x020e4000 0x4000>;
 602                         };
 603
 604                         gpt2: gpt@020e8000 {
 605                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 606                                 reg = <0x020e8000 0x4000>;
 607                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 609                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 610                                 clock-names = "ipg", "per";
 611                         };
 612
 613                         sdma: sdma@020ec000 {
 614                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 615                                 reg = <0x020ec000 0x4000>;
 616                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 617                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 618                                          <&clks IMX6UL_CLK_SDMA>;
 619                                 clock-names = "ipg", "ahb";
 620                                 #dma-cells = <3>;
 621                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 622                         };
 623
 624                         pwm5: pwm@020f0000 {
 625                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 626                                 reg = <0x020f0000 0x4000>;
 627                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 628                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 629                                          <&clks IMX6UL_CLK_PWM5>;
 630                                 clock-names = "ipg", "per";
 631                                 #pwm-cells = <2>;
 632                         };
 633
 634                         pwm6: pwm@020f4000 {
 635                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 636                                 reg = <0x020f4000 0x4000>;
 637                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 638                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 639                                          <&clks IMX6UL_CLK_PWM6>;
 640                                 clock-names = "ipg", "per";
 641                                 #pwm-cells = <2>;
 642                         };
 643
 644                         pwm7: pwm@020f8000 {
 645                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 646                                 reg = <0x020f8000 0x4000>;
 647                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 649                                          <&clks IMX6UL_CLK_PWM7>;
 650                                 clock-names = "ipg", "per";
 651                                 #pwm-cells = <2>;
 652                         };
 653
 654                         pwm8: pwm@020fc000 {
 655                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 656                                 reg = <0x020fc000 0x4000>;
 657                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 658                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 659                                          <&clks IMX6UL_CLK_PWM8>;
 660                                 clock-names = "ipg", "per";
 661                                 #pwm-cells = <2>;
 662                         };
 663                 };
 664
 665                 aips2: aips-bus@02100000 {
 666                         compatible = "fsl,aips-bus", "simple-bus";
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         reg = <0x02100000 0x100000>;
 670                         ranges;
 671
 672                         usbotg1: usb@02184000 {
 673                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 674                                 reg = <0x02184000 0x200>;
 675                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 676                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 677                                 fsl,usbphy = <&usbphy1>;
 678                                 fsl,usbmisc = <&usbmisc 0>;
 679                                 fsl,anatop = <&anatop>;
 680                                 status = "disabled";
 681                         };
 682
 683                         usbotg2: usb@02184200 {
 684                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 685                                 reg = <0x02184200 0x200>;
 686                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 688                                 fsl,usbphy = <&usbphy2>;
 689                                 fsl,usbmisc = <&usbmisc 1>;
 690                                 status = "disabled";
 691                         };
 692
 693                         usbmisc: usbmisc@02184800 {
 694                                 #index-cells = <1>;
 695                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 696                                 reg = <0x02184800 0x200>;
 697                         };
 698
 699                         fec1: ethernet@02188000 {
 700                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 701                                 reg = <0x02188000 0x4000>;
 702                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 703                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6UL_CLK_ENET>,
 705                                          <&clks IMX6UL_CLK_ENET_AHB>,
 706                                          <&clks IMX6UL_CLK_ENET_PTP>,
 707                                          <&clks IMX6UL_CLK_ENET_REF>,
 708                                          <&clks IMX6UL_CLK_ENET_REF>;
 709                                 clock-names = "ipg", "ahb", "ptp",
 710                                               "enet_clk_ref", "enet_out";
 711                                 fsl,num-tx-queues=<1>;
 712                                 fsl,num-rx-queues=<1>;
 713                                 status = "disabled";
 714                         };
 715
 716                         usdhc1: usdhc@02190000 {
 717                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 718                                 reg = <0x02190000 0x4000>;
 719                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 721                                          <&clks IMX6UL_CLK_USDHC1>,
 722                                          <&clks IMX6UL_CLK_USDHC1>;
 723                                 clock-names = "ipg", "ahb", "per";
 724                                 bus-width = <4>;
 725                                 status = "disabled";
 726                         };
 727
 728                         usdhc2: usdhc@02194000 {
 729                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 730                                 reg = <0x02194000 0x4000>;
 731                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 732                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 733                                          <&clks IMX6UL_CLK_USDHC2>,
 734                                          <&clks IMX6UL_CLK_USDHC2>;
 735                                 clock-names = "ipg", "ahb", "per";
 736                                 bus-width = <4>;
 737                                 status = "disabled";
 738                         };
 739
 740                         i2c1: i2c@021a0000 {
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 744                                 reg = <0x021a0000 0x4000>;
 745                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 747                                 status = "disabled";
 748                         };
 749
 750                         i2c2: i2c@021a4000 {
 751                                 #address-cells = <1>;
 752                                 #size-cells = <0>;
 753                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 754                                 reg = <0x021a4000 0x4000>;
 755                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 757                                 status = "disabled";
 758                         };
 759
 760                         i2c3: i2c@021a8000 {
 761                                 #address-cells = <1>;
 762                                 #size-cells = <0>;
 763                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 764                                 reg = <0x021a8000 0x4000>;
 765                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 766                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 767                                 status = "disabled";
 768                         };
 769
 770                         mmdc: mmdc@021b0000 {
 771                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 772                                 reg = <0x021b0000 0x4000>;
 773                         };
 774
 775                         lcdif: lcdif@021c8000 {
 776                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 777                                 reg = <0x021c8000 0x4000>;
 778                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 780                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 781                                          <&clks IMX6UL_CLK_DUMMY>;
 782                                 clock-names = "pix", "axi", "disp_axi";
 783                                 status = "disabled";
 784                         };
 785
 786                         qspi: qspi@021e0000 {
 787                                 #address-cells = <1>;
 788                                 #size-cells = <0>;
 789                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 790                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 791                                 reg-names = "QuadSPI", "QuadSPI-memory";
 792                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 794                                          <&clks IMX6UL_CLK_QSPI>;
 795                                 clock-names = "qspi_en", "qspi";
 796                                 status = "disabled";
 797                         };
 798
 799                         uart2: serial@021e8000 {
 800                                 compatible = "fsl,imx6ul-uart",
 801                                              "fsl,imx6q-uart";
 802                                 reg = <0x021e8000 0x4000>;
 803                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 805                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 806                                 clock-names = "ipg", "per";
 807                                 status = "disabled";
 808                         };
 809
 810                         uart3: serial@021ec000 {
 811                                 compatible = "fsl,imx6ul-uart",
 812                                              "fsl,imx6q-uart";
 813                                 reg = <0x021ec000 0x4000>;
 814                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 816                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 817                                 clock-names = "ipg", "per";
 818                                 status = "disabled";
 819                         };
 820
 821                         uart4: serial@021f0000 {
 822                                 compatible = "fsl,imx6ul-uart",
 823                                              "fsl,imx6q-uart";
 824                                 reg = <0x021f0000 0x4000>;
 825                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 826                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 827                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 828                                 clock-names = "ipg", "per";
 829                                 status = "disabled";
 830                         };
 831
 832                         uart5: serial@021f4000 {
 833                                 compatible = "fsl,imx6ul-uart",
 834                                              "fsl,imx6q-uart";
 835                                 reg = <0x021f4000 0x4000>;
 836                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 837                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 838                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 839                                 clock-names = "ipg", "per";
 840                                 status = "disabled";
 841                         };
 842
 843                         i2c4: i2c@021f8000 {
 844                                 #address-cells = <1>;
 845                                 #size-cells = <0>;
 846                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 847                                 reg = <0x021f8000 0x4000>;
 848                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 849                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 850                                 status = "disabled";
 851                         };
 852
 853                         uart6: serial@021fc000 {
 854                                 compatible = "fsl,imx6ul-uart",
 855                                              "fsl,imx6q-uart";
 856                                 reg = <0x021fc000 0x4000>;
 857                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 859                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 860                                 clock-names = "ipg", "per";
 861                                 status = "disabled";
 862                         };
 863                 };
 864         };
 865 };