arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6ul-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 ethernet0 = &fec1;
  18                 ethernet1 = &fec2;
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 mmc0 = &usdhc1;
  29                 mmc1 = &usdhc2;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usbphy0 = &usbphy1;
  43                 usbphy1 = &usbphy2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         compatible = "arm,cortex-a7";
  52                         device_type = "cpu";
  53                         reg = <0>;
  54                         clock-latency = <61036>; /* two CLK32 periods */
  55                         operating-points = <
  56                                 /* kHz  uV */
  57                                 528000  1250000
  58                                 396000  1150000
  59                                 198000  1150000
  60                         >;
  61                         fsl,soc-operating-points = <
  62                                 /* KHz  uV */
  63                                 528000  1250000
  64                                 396000  1150000
  65                                 198000  1150000
  66                         >;
  67                         clocks = <&clks IMX6UL_CLK_ARM>,
  68                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  69                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  70                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  71                                  <&clks IMX6UL_CLK_STEP>,
  72                                  <&clks IMX6UL_CLK_PLL1_SW>,
  73                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  74                                  <&clks IMX6UL_PLL1_BYPASS>,
  75                                  <&clks IMX6UL_CLK_PLL1>,
  76                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  77                                  <&clks IMX6UL_CLK_OSC>;
  78                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  79                                       "secondary_sel", "step", "pll1_sw",
  80                                       "pll1_sys", "pll1_bypass", "pll1",
  81                                       "pll1_bypass_src", "osc";
  82                         arm-supply = <&reg_arm>;
  83                         soc-supply = <&reg_soc>;
  84                 };
  85         };
  86
  87         intc: interrupt-controller@00a01000 {
  88                 compatible = "arm,cortex-a7-gic";
  89                 #interrupt-cells = <3>;
  90                 interrupt-controller;
  91                 reg = <0x00a01000 0x1000>,
  92                       <0x00a02000 0x1000>,
  93                       <0x00a04000 0x2000>,
  94                       <0x00a06000 0x2000>;
  95         };
  96
  97         ckil: clock-cli {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 clock-frequency = <32768>;
 101                 clock-output-names = "ckil";
 102         };
 103
 104         osc: clock-osc {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <24000000>;
 108                 clock-output-names = "osc";
 109         };
 110
 111         ipp_di0: clock-di0 {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <0>;
 115                 clock-output-names = "ipp_di0";
 116         };
 117
 118         ipp_di1: clock-di1 {
 119                 compatible = "fixed-clock";
 120                 #clock-cells = <0>;
 121                 clock-frequency = <0>;
 122                 clock-output-names = "ipp_di1";
 123         };
 124
 125         soc {
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 compatible = "simple-bus";
 129                 interrupt-parent = <&gpc>;
 130                 ranges;
 131
 132                 pmu {
 133                         compatible = "arm,cortex-a7-pmu";
 134                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 135                         status = "disabled";
 136                 };
 137
 138                 ocram: sram@00900000 {
 139                         compatible = "mmio-sram";
 140                         reg = <0x00900000 0x20000>;
 141                 };
 142
 143                 dma_apbh: dma-apbh@01804000 {
 144                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 145                         reg = <0x01804000 0x2000>;
 146                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 150                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 151                         #dma-cells = <1>;
 152                         dma-channels = <4>;
 153                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 154                 };
 155
 156                 gpmi: gpmi-nand@01806000         {
 157                         compatible = "fsl,imx6q-gpmi-nand";
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 161                         reg-names = "gpmi-nand", "bch";
 162                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 163                         interrupt-names = "bch";
 164                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 165                                  <&clks IMX6UL_CLK_GPMI_APB>,
 166                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 167                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 168                                  <&clks IMX6UL_CLK_PER_BCH>;
 169                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 170                                       "gpmi_bch_apb", "per1_bch";
 171                         dmas = <&dma_apbh 0>;
 172                         dma-names = "rx-tx";
 173                         status = "disabled";
 174                 };
 175
 176                 aips1: aips-bus@02000000 {
 177                         compatible = "fsl,aips-bus", "simple-bus";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         reg = <0x02000000 0x100000>;
 181                         ranges;
 182
 183                         spba-bus@02000000 {
 184                                 compatible = "fsl,spba-bus", "simple-bus";
 185                                 #address-cells = <1>;
 186                                 #size-cells = <1>;
 187                                 reg = <0x02000000 0x40000>;
 188                                 ranges;
 189
 190                                 ecspi1: ecspi@02008000 {
 191                                         #address-cells = <1>;
 192                                         #size-cells = <0>;
 193                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 194                                         reg = <0x02008000 0x4000>;
 195                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 196                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 197                                                  <&clks IMX6UL_CLK_ECSPI1>;
 198                                         clock-names = "ipg", "per";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ecspi2: ecspi@0200c000 {
 203                                         #address-cells = <1>;
 204                                         #size-cells = <0>;
 205                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 206                                         reg = <0x0200c000 0x4000>;
 207                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 208                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 209                                                  <&clks IMX6UL_CLK_ECSPI2>;
 210                                         clock-names = "ipg", "per";
 211                                         status = "disabled";
 212                                 };
 213
 214                                 ecspi3: ecspi@02010000 {
 215                                         #address-cells = <1>;
 216                                         #size-cells = <0>;
 217                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 218                                         reg = <0x02010000 0x4000>;
 219                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 220                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 221                                                  <&clks IMX6UL_CLK_ECSPI3>;
 222                                         clock-names = "ipg", "per";
 223                                         status = "disabled";
 224                                 };
 225
 226                                 ecspi4: ecspi@02014000 {
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 230                                         reg = <0x02014000 0x4000>;
 231                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 232                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 233                                                  <&clks IMX6UL_CLK_ECSPI4>;
 234                                         clock-names = "ipg", "per";
 235                                         status = "disabled";
 236                                 };
 237
 238                                 uart7: serial@02018000 {
 239                                         compatible = "fsl,imx6ul-uart",
 240                                                      "fsl,imx6q-uart";
 241                                         reg = <0x02018000 0x4000>;
 242                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 243                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 244                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 245                                         clock-names = "ipg", "per";
 246                                         status = "disabled";
 247                                 };
 248
 249                                 uart1: serial@02020000 {
 250                                         compatible = "fsl,imx6ul-uart",
 251                                                      "fsl,imx6q-uart";
 252                                         reg = <0x02020000 0x4000>;
 253                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 255                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 256                                         clock-names = "ipg", "per";
 257                                         status = "disabled";
 258                                 };
 259
 260                                 uart8: serial@02024000 {
 261                                         compatible = "fsl,imx6ul-uart",
 262                                                      "fsl,imx6q-uart";
 263                                         reg = <0x02024000 0x4000>;
 264                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 265                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 266                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 267                                         clock-names = "ipg", "per";
 268                                         status = "disabled";
 269                                 };
 270                         };
 271
 272                         gpt1: gpt@02098000 {
 273                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 274                                 reg = <0x02098000 0x4000>;
 275                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 276                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 277                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 278                                 clock-names = "ipg", "per";
 279                         };
 280
 281                         gpio1: gpio@0209c000 {
 282                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 283                                 reg = <0x0209c000 0x4000>;
 284                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 285                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 286                                 gpio-controller;
 287                                 #gpio-cells = <2>;
 288                                 interrupt-controller;
 289                                 #interrupt-cells = <2>;
 290                         };
 291
 292                         gpio2: gpio@020a0000 {
 293                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 294                                 reg = <0x020a0000 0x4000>;
 295                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 296                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 297                                 gpio-controller;
 298                                 #gpio-cells = <2>;
 299                                 interrupt-controller;
 300                                 #interrupt-cells = <2>;
 301                         };
 302
 303                         gpio3: gpio@020a4000 {
 304                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 305                                 reg = <0x020a4000 0x4000>;
 306                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 307                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 308                                 gpio-controller;
 309                                 #gpio-cells = <2>;
 310                                 interrupt-controller;
 311                                 #interrupt-cells = <2>;
 312                         };
 313
 314                         gpio4: gpio@020a8000 {
 315                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 316                                 reg = <0x020a8000 0x4000>;
 317                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 318                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 319                                 gpio-controller;
 320                                 #gpio-cells = <2>;
 321                                 interrupt-controller;
 322                                 #interrupt-cells = <2>;
 323                         };
 324
 325                         gpio5: gpio@020ac000 {
 326                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 327                                 reg = <0x020ac000 0x4000>;
 328                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 329                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 330                                 gpio-controller;
 331                                 #gpio-cells = <2>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                         };
 335
 336                         fec2: ethernet@020b4000 {
 337                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 338                                 reg = <0x020b4000 0x4000>;
 339                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 340                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clks IMX6UL_CLK_ENET>,
 342                                          <&clks IMX6UL_CLK_ENET_AHB>,
 343                                          <&clks IMX6UL_CLK_ENET_PTP>,
 344                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 345                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 346                                 clock-names = "ipg", "ahb", "ptp",
 347                                               "enet_clk_ref", "enet_out";
 348                                 fsl,num-tx-queues=<1>;
 349                                 fsl,num-rx-queues=<1>;
 350                                 status = "disabled";
 351                         };
 352
 353                         wdog1: wdog@020bc000 {
 354                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 355                                 reg = <0x020bc000 0x4000>;
 356                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 358                         };
 359
 360                         wdog2: wdog@020c0000 {
 361                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 362                                 reg = <0x020c0000 0x4000>;
 363                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 365                                 status = "disabled";
 366                         };
 367
 368                         clks: ccm@020c4000 {
 369                                 compatible = "fsl,imx6ul-ccm";
 370                                 reg = <0x020c4000 0x4000>;
 371                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 372                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 373                                 #clock-cells = <1>;
 374                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 375                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 376                         };
 377
 378                         anatop: anatop@020c8000 {
 379                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 380                                              "syscon", "simple-bus";
 381                                 reg = <0x020c8000 0x1000>;
 382                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 383                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 384                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 385
 386                                 reg_3p0: regulator-3p0@120 {
 387                                         compatible = "fsl,anatop-regulator";
 388                                         regulator-name = "vdd3p0";
 389                                         regulator-min-microvolt = <2625000>;
 390                                         regulator-max-microvolt = <3400000>;
 391                                         anatop-reg-offset = <0x120>;
 392                                         anatop-vol-bit-shift = <8>;
 393                                         anatop-vol-bit-width = <5>;
 394                                         anatop-min-bit-val = <0>;
 395                                         anatop-min-voltage = <2625000>;
 396                                         anatop-max-voltage = <3400000>;
 397                                         anatop-enable-bit = <0>;
 398                                 };
 399
 400                                 reg_arm: regulator-vddcore@140 {
 401                                         compatible = "fsl,anatop-regulator";
 402                                         regulator-name = "cpu";
 403                                         regulator-min-microvolt = <725000>;
 404                                         regulator-max-microvolt = <1450000>;
 405                                         regulator-always-on;
 406                                         anatop-reg-offset = <0x140>;
 407                                         anatop-vol-bit-shift = <0>;
 408                                         anatop-vol-bit-width = <5>;
 409                                         anatop-delay-reg-offset = <0x170>;
 410                                         anatop-delay-bit-shift = <24>;
 411                                         anatop-delay-bit-width = <2>;
 412                                         anatop-min-bit-val = <1>;
 413                                         anatop-min-voltage = <725000>;
 414                                         anatop-max-voltage = <1450000>;
 415                                 };
 416
 417                                 reg_soc: regulator-vddsoc@140 {
 418                                         compatible = "fsl,anatop-regulator";
 419                                         regulator-name = "vddsoc";
 420                                         regulator-min-microvolt = <725000>;
 421                                         regulator-max-microvolt = <1450000>;
 422                                         regulator-always-on;
 423                                         anatop-reg-offset = <0x140>;
 424                                         anatop-vol-bit-shift = <18>;
 425                                         anatop-vol-bit-width = <5>;
 426                                         anatop-delay-reg-offset = <0x170>;
 427                                         anatop-delay-bit-shift = <28>;
 428                                         anatop-delay-bit-width = <2>;
 429                                         anatop-min-bit-val = <1>;
 430                                         anatop-min-voltage = <725000>;
 431                                         anatop-max-voltage = <1450000>;
 432                                 };
 433                         };
 434
 435                         usbphy1: usbphy@020c9000 {
 436                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 437                                 reg = <0x020c9000 0x1000>;
 438                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 440                                 phy-3p0-supply = <&reg_3p0>;
 441                                 fsl,anatop = <&anatop>;
 442                         };
 443
 444                         usbphy2: usbphy@020ca000 {
 445                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 446                                 reg = <0x020ca000 0x1000>;
 447                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 449                                 phy-3p0-supply = <&reg_3p0>;
 450                                 fsl,anatop = <&anatop>;
 451                         };
 452
 453                         snvs: snvs@020cc000 {
 454                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 455                                 reg = <0x020cc000 0x4000>;
 456
 457                                 snvs_rtc: snvs-rtc-lp {
 458                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 459                                         regmap = <&snvs>;
 460                                         offset = <0x34>;
 461                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 462                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 463                                 };
 464
 465                                 snvs_poweroff: snvs-poweroff {
 466                                         compatible = "syscon-poweroff";
 467                                         regmap = <&snvs>;
 468                                         offset = <0x38>;
 469                                         mask = <0x60>;
 470                                         status = "disabled";
 471                                 };
 472
 473                                 snvs_pwrkey: snvs-powerkey {
 474                                         compatible = "fsl,sec-v4.0-pwrkey";
 475                                         regmap = <&snvs>;
 476                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 477                                         linux,keycode = <KEY_POWER>;
 478                                         wakeup-source;
 479                                 };
 480                         };
 481
 482                         epit1: epit@020d0000 {
 483                                 reg = <0x020d0000 0x4000>;
 484                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 485                         };
 486
 487                         epit2: epit@020d4000 {
 488                                 reg = <0x020d4000 0x4000>;
 489                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 490                         };
 491
 492                         src: src@020d8000 {
 493                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 494                                 reg = <0x020d8000 0x4000>;
 495                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 496                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 497                                 #reset-cells = <1>;
 498                         };
 499
 500                         gpc: gpc@020dc000 {
 501                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 502                                 reg = <0x020dc000 0x4000>;
 503                                 interrupt-controller;
 504                                 #interrupt-cells = <3>;
 505                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 506                                 interrupt-parent = <&intc>;
 507                         };
 508
 509                         iomuxc: iomuxc@020e0000 {
 510                                 compatible = "fsl,imx6ul-iomuxc";
 511                                 reg = <0x020e0000 0x4000>;
 512                         };
 513
 514                         gpr: iomuxc-gpr@020e4000 {
 515                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 516                                 reg = <0x020e4000 0x4000>;
 517                         };
 518
 519                         gpt2: gpt@020e8000 {
 520                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 521                                 reg = <0x020e8000 0x4000>;
 522                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 523                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 524                                          <&clks IMX6UL_CLK_DUMMY>;
 525                                 clock-names = "ipg", "per";
 526                         };
 527
 528                         pwm5: pwm@020f0000 {
 529                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 530                                 reg = <0x020f0000 0x4000>;
 531                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 532                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 533                                          <&clks IMX6UL_CLK_DUMMY>;
 534                                 clock-names = "ipg", "per";
 535                                 #pwm-cells = <2>;
 536                         };
 537
 538                         pwm6: pwm@020f4000 {
 539                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 540                                 reg = <0x020f4000 0x4000>;
 541                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 542                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 543                                          <&clks IMX6UL_CLK_DUMMY>;
 544                                 clock-names = "ipg", "per";
 545                                 #pwm-cells = <2>;
 546                         };
 547
 548                         pwm7: pwm@020f8000 {
 549                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 550                                 reg = <0x020f8000 0x4000>;
 551                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 552                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 553                                          <&clks IMX6UL_CLK_DUMMY>;
 554                                 clock-names = "ipg", "per";
 555                                 #pwm-cells = <2>;
 556                         };
 557
 558                         pwm8: pwm@020fc000 {
 559                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 560                                 reg = <0x020fc000 0x4000>;
 561                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 562                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 563                                          <&clks IMX6UL_CLK_DUMMY>;
 564                                 clock-names = "ipg", "per";
 565                                 #pwm-cells = <2>;
 566                         };
 567                 };
 568
 569                 aips2: aips-bus@02100000 {
 570                         compatible = "fsl,aips-bus", "simple-bus";
 571                         #address-cells = <1>;
 572                         #size-cells = <1>;
 573                         reg = <0x02100000 0x100000>;
 574                         ranges;
 575
 576                         usbotg1: usb@02184000 {
 577                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 578                                 reg = <0x02184000 0x200>;
 579                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 580                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 581                                 fsl,usbphy = <&usbphy1>;
 582                                 fsl,usbmisc = <&usbmisc 0>;
 583                                 fsl,anatop = <&anatop>;
 584                                 status = "disabled";
 585                         };
 586
 587                         usbotg2: usb@02184200 {
 588                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 589                                 reg = <0x02184200 0x200>;
 590                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 591                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 592                                 fsl,usbphy = <&usbphy2>;
 593                                 fsl,usbmisc = <&usbmisc 1>;
 594                                 status = "disabled";
 595                         };
 596
 597                         usbmisc: usbmisc@02184800 {
 598                                 #index-cells = <1>;
 599                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 600                                 reg = <0x02184800 0x200>;
 601                         };
 602
 603                         fec1: ethernet@02188000 {
 604                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 605                                 reg = <0x02188000 0x4000>;
 606                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 607                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&clks IMX6UL_CLK_ENET>,
 609                                          <&clks IMX6UL_CLK_ENET_AHB>,
 610                                          <&clks IMX6UL_CLK_ENET_PTP>,
 611                                          <&clks IMX6UL_CLK_ENET_REF>,
 612                                          <&clks IMX6UL_CLK_ENET_REF>;
 613                                 clock-names = "ipg", "ahb", "ptp",
 614                                               "enet_clk_ref", "enet_out";
 615                                 fsl,num-tx-queues=<1>;
 616                                 fsl,num-rx-queues=<1>;
 617                                 status = "disabled";
 618                         };
 619
 620                         tsc: tsc@02040000 {
 621                                 compatible = "fsl,imx6ul-tsc";
 622                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 623                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 624                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clks IMX6UL_CLK_IPG>,
 626                                          <&clks IMX6UL_CLK_ADC2>;
 627                                 clock-names = "tsc", "adc";
 628                                 status = "disabled";
 629                         };
 630
 631                         usdhc1: usdhc@02190000 {
 632                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 633                                 reg = <0x02190000 0x4000>;
 634                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 636                                          <&clks IMX6UL_CLK_USDHC1>,
 637                                          <&clks IMX6UL_CLK_USDHC1>;
 638                                 clock-names = "ipg", "ahb", "per";
 639                                 bus-width = <4>;
 640                                 status = "disabled";
 641                         };
 642
 643                         usdhc2: usdhc@02194000 {
 644                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 645                                 reg = <0x02194000 0x4000>;
 646                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 648                                          <&clks IMX6UL_CLK_USDHC2>,
 649                                          <&clks IMX6UL_CLK_USDHC2>;
 650                                 clock-names = "ipg", "ahb", "per";
 651                                 bus-width = <4>;
 652                                 status = "disabled";
 653                         };
 654
 655                         i2c1: i2c@021a0000 {
 656                                 #address-cells = <1>;
 657                                 #size-cells = <0>;
 658                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 659                                 reg = <0x021a0000 0x4000>;
 660                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 661                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 662                                 status = "disabled";
 663                         };
 664
 665                         i2c2: i2c@021a4000 {
 666                                 #address-cells = <1>;
 667                                 #size-cells = <0>;
 668                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 669                                 reg = <0x021a4000 0x4000>;
 670                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 672                                 status = "disabled";
 673                         };
 674
 675                         i2c3: i2c@021a8000 {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 679                                 reg = <0x021a8000 0x4000>;
 680                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 681                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 682                                 status = "disabled";
 683                         };
 684
 685                         mmdc: mmdc@021b0000 {
 686                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 687                                 reg = <0x021b0000 0x4000>;
 688                         };
 689
 690                         lcdif: lcdif@021c8000 {
 691                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 692                                 reg = <0x021c8000 0x4000>;
 693                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 695                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 696                                          <&clks IMX6UL_CLK_DUMMY>;
 697                                 clock-names = "pix", "axi", "disp_axi";
 698                                 status = "disabled";
 699                         };
 700
 701                         qspi: qspi@021e0000 {
 702                                 #address-cells = <1>;
 703                                 #size-cells = <0>;
 704                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 705                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 706                                 reg-names = "QuadSPI", "QuadSPI-memory";
 707                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 709                                          <&clks IMX6UL_CLK_QSPI>;
 710                                 clock-names = "qspi_en", "qspi";
 711                                 status = "disabled";
 712                         };
 713
 714                         uart2: serial@021e8000 {
 715                                 compatible = "fsl,imx6ul-uart",
 716                                              "fsl,imx6q-uart";
 717                                 reg = <0x021e8000 0x4000>;
 718                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 719                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 720                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 721                                 clock-names = "ipg", "per";
 722                                 status = "disabled";
 723                         };
 724
 725                         uart3: serial@021ec000 {
 726                                 compatible = "fsl,imx6ul-uart",
 727                                              "fsl,imx6q-uart";
 728                                 reg = <0x021ec000 0x4000>;
 729                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 730                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 731                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 732                                 clock-names = "ipg", "per";
 733                                 status = "disabled";
 734                         };
 735
 736                         uart4: serial@021f0000 {
 737                                 compatible = "fsl,imx6ul-uart",
 738                                              "fsl,imx6q-uart";
 739                                 reg = <0x021f0000 0x4000>;
 740                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 741                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 742                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 743                                 clock-names = "ipg", "per";
 744                                 status = "disabled";
 745                         };
 746
 747                         uart5: serial@021f4000 {
 748                                 compatible = "fsl,imx6ul-uart",
 749                                              "fsl,imx6q-uart";
 750                                 reg = <0x021f4000 0x4000>;
 751                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 753                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 754                                 clock-names = "ipg", "per";
 755                                 status = "disabled";
 756                         };
 757
 758                         i2c4: i2c@021f8000 {
 759                                 #address-cells = <1>;
 760                                 #size-cells = <0>;
 761                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 762                                 reg = <0x021f8000 0x4000>;
 763                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 764                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 765                                 status = "disabled";
 766                         };
 767
 768                         uart6: serial@021fc000 {
 769                                 compatible = "fsl,imx6ul-uart",
 770                                              "fsl,imx6q-uart";
 771                                 reg = <0x021fc000 0x4000>;
 772                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 774                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 775                                 clock-names = "ipg", "per";
 776                                 status = "disabled";
 777                         };
 778                 };
 779         };
 780 };