arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59         };
  60
  61         L2: l2-cache-controller@48242000 {
  62                 compatible = "arm,pl310-cache";
  63                 reg = <0x48242000 0x1000>;
  64                 cache-unified;
  65                 cache-level = <2>;
  66         };
  67
  68         local-timer@48240600 {
  69                 compatible = "arm,cortex-a9-twd-timer";
  70                 clocks = <&mpu_periphclk>;
  71                 reg = <0x48240600 0x20>;
  72                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap4-mpu";
  83                         ti,hwmods = "mpu";
  84                 };
  85
  86                 dsp {
  87                         compatible = "ti,omap3-c64";
  88                         ti,hwmods = "dsp";
  89                 };
  90
  91                 iva {
  92                         compatible = "ti,ivahd";
  93                         ti,hwmods = "iva";
  94                 };
  95         };
  96
  97         /*
  98          * XXX: Use a flat representation of the OMAP4 interconnect.
  99          * The real OMAP interconnect network is quite complex.
 100          * Since it will not bring real advantage to represent that in DT for
 101          * the moment, just use a fake OCP bus entry to represent the whole bus
 102          * hierarchy.
 103          */
 104         ocp {
 105                 compatible = "ti,omap4-l3-noc", "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 110                 reg = <0x44000000 0x1000>,
 111                       <0x44800000 0x2000>,
 112                       <0x45000000 0x1000>;
 113                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 114                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 115
 116                 cm1: cm1@4a004000 {
 117                         compatible = "ti,omap4-cm1";
 118                         reg = <0x4a004000 0x2000>;
 119
 120                         cm1_clocks: clocks {
 121                                 #address-cells = <1>;
 122                                 #size-cells = <0>;
 123                         };
 124
 125                         cm1_clockdomains: clockdomains {
 126                         };
 127                 };
 128
 129                 prm: prm@4a306000 {
 130                         compatible = "ti,omap4-prm";
 131                         reg = <0x4a306000 0x3000>;
 132
 133                         prm_clocks: clocks {
 134                                 #address-cells = <1>;
 135                                 #size-cells = <0>;
 136                         };
 137
 138                         prm_clockdomains: clockdomains {
 139                         };
 140                 };
 141
 142                 cm2: cm2@4a008000 {
 143                         compatible = "ti,omap4-cm2";
 144                         reg = <0x4a008000 0x3000>;
 145
 146                         cm2_clocks: clocks {
 147                                 #address-cells = <1>;
 148                                 #size-cells = <0>;
 149                         };
 150
 151                         cm2_clockdomains: clockdomains {
 152                         };
 153                 };
 154
 155                 scrm: scrm@4a30a000 {
 156                         compatible = "ti,omap4-scrm";
 157                         reg = <0x4a30a000 0x2000>;
 158
 159                         scrm_clocks: clocks {
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162                         };
 163
 164                         scrm_clockdomains: clockdomains {
 165                         };
 166                 };
 167
 168                 counter32k: counter@4a304000 {
 169                         compatible = "ti,omap-counter32k";
 170                         reg = <0x4a304000 0x20>;
 171                         ti,hwmods = "counter_32k";
 172                 };
 173
 174                 omap4_pmx_core: pinmux@4a100040 {
 175                         compatible = "ti,omap4-padconf", "pinctrl-single";
 176                         reg = <0x4a100040 0x0196>;
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         #interrupt-cells = <1>;
 180                         interrupt-controller;
 181                         pinctrl-single,register-width = <16>;
 182                         pinctrl-single,function-mask = <0x7fff>;
 183                 };
 184                 omap4_pmx_wkup: pinmux@4a31e040 {
 185                         compatible = "ti,omap4-padconf", "pinctrl-single";
 186                         reg = <0x4a31e040 0x0038>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         #interrupt-cells = <1>;
 190                         interrupt-controller;
 191                         pinctrl-single,register-width = <16>;
 192                         pinctrl-single,function-mask = <0x7fff>;
 193                 };
 194
 195                 omap4_padconf_global: tisyscon@4a1005a0 {
 196                         compatible = "syscon";
 197                         reg = <0x4a1005a0 0x170>;
 198                 };
 199
 200                 pbias_regulator: pbias_regulator {
 201                         compatible = "ti,pbias-omap";
 202                         reg = <0x60 0x4>;
 203                         syscon = <&omap4_padconf_global>;
 204                         pbias_mmc_reg: pbias_mmc_omap4 {
 205                                 regulator-name = "pbias_mmc_omap4";
 206                                 regulator-min-microvolt = <1800000>;
 207                                 regulator-max-microvolt = <3000000>;
 208                         };
 209                 };
 210
 211                 sdma: dma-controller@4a056000 {
 212                         compatible = "ti,omap4430-sdma";
 213                         reg = <0x4a056000 0x1000>;
 214                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 218                         #dma-cells = <1>;
 219                         #dma-channels = <32>;
 220                         #dma-requests = <127>;
 221                 };
 222
 223                 gpio1: gpio@4a310000 {
 224                         compatible = "ti,omap4-gpio";
 225                         reg = <0x4a310000 0x200>;
 226                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 227                         ti,hwmods = "gpio1";
 228                         ti,gpio-always-on;
 229                         gpio-controller;
 230                         #gpio-cells = <2>;
 231                         interrupt-controller;
 232                         #interrupt-cells = <2>;
 233                 };
 234
 235                 gpio2: gpio@48055000 {
 236                         compatible = "ti,omap4-gpio";
 237                         reg = <0x48055000 0x200>;
 238                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 239                         ti,hwmods = "gpio2";
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio3: gpio@48057000 {
 247                         compatible = "ti,omap4-gpio";
 248                         reg = <0x48057000 0x200>;
 249                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 250                         ti,hwmods = "gpio3";
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio4: gpio@48059000 {
 258                         compatible = "ti,omap4-gpio";
 259                         reg = <0x48059000 0x200>;
 260                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 261                         ti,hwmods = "gpio4";
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 gpio5: gpio@4805b000 {
 269                         compatible = "ti,omap4-gpio";
 270                         reg = <0x4805b000 0x200>;
 271                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                         ti,hwmods = "gpio5";
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 gpio6: gpio@4805d000 {
 280                         compatible = "ti,omap4-gpio";
 281                         reg = <0x4805d000 0x200>;
 282                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 283                         ti,hwmods = "gpio6";
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gpmc: gpmc@50000000 {
 291                         compatible = "ti,omap4430-gpmc";
 292                         reg = <0x50000000 0x1000>;
 293                         #address-cells = <2>;
 294                         #size-cells = <1>;
 295                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 296                         gpmc,num-cs = <8>;
 297                         gpmc,num-waitpins = <4>;
 298                         ti,hwmods = "gpmc";
 299                         ti,no-idle-on-init;
 300                         clocks = <&l3_div_ck>;
 301                         clock-names = "fck";
 302                 };
 303
 304                 uart1: serial@4806a000 {
 305                         compatible = "ti,omap4-uart";
 306                         reg = <0x4806a000 0x100>;
 307                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 308                         ti,hwmods = "uart1";
 309                         clock-frequency = <48000000>;
 310                 };
 311
 312                 uart2: serial@4806c000 {
 313                         compatible = "ti,omap4-uart";
 314                         reg = <0x4806c000 0x100>;
 315                         interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "uart2";
 317                         clock-frequency = <48000000>;
 318                 };
 319
 320                 uart3: serial@48020000 {
 321                         compatible = "ti,omap4-uart";
 322                         reg = <0x48020000 0x100>;
 323                         interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 324                         ti,hwmods = "uart3";
 325                         clock-frequency = <48000000>;
 326                 };
 327
 328                 uart4: serial@4806e000 {
 329                         compatible = "ti,omap4-uart";
 330                         reg = <0x4806e000 0x100>;
 331                         interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 332                         ti,hwmods = "uart4";
 333                         clock-frequency = <48000000>;
 334                 };
 335
 336                 hwspinlock: spinlock@4a0f6000 {
 337                         compatible = "ti,omap4-hwspinlock";
 338                         reg = <0x4a0f6000 0x1000>;
 339                         ti,hwmods = "spinlock";
 340                         #hwlock-cells = <1>;
 341                 };
 342
 343                 i2c1: i2c@48070000 {
 344                         compatible = "ti,omap4-i2c";
 345                         reg = <0x48070000 0x100>;
 346                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         ti,hwmods = "i2c1";
 350                 };
 351
 352                 i2c2: i2c@48072000 {
 353                         compatible = "ti,omap4-i2c";
 354                         reg = <0x48072000 0x100>;
 355                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         ti,hwmods = "i2c2";
 359                 };
 360
 361                 i2c3: i2c@48060000 {
 362                         compatible = "ti,omap4-i2c";
 363                         reg = <0x48060000 0x100>;
 364                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         ti,hwmods = "i2c3";
 368                 };
 369
 370                 i2c4: i2c@48350000 {
 371                         compatible = "ti,omap4-i2c";
 372                         reg = <0x48350000 0x100>;
 373                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         ti,hwmods = "i2c4";
 377                 };
 378
 379                 mcspi1: spi@48098000 {
 380                         compatible = "ti,omap4-mcspi";
 381                         reg = <0x48098000 0x200>;
 382                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         ti,hwmods = "mcspi1";
 386                         ti,spi-num-cs = <4>;
 387                         dmas = <&sdma 35>,
 388                                <&sdma 36>,
 389                                <&sdma 37>,
 390                                <&sdma 38>,
 391                                <&sdma 39>,
 392                                <&sdma 40>,
 393                                <&sdma 41>,
 394                                <&sdma 42>;
 395                         dma-names = "tx0", "rx0", "tx1", "rx1",
 396                                     "tx2", "rx2", "tx3", "rx3";
 397                 };
 398
 399                 mcspi2: spi@4809a000 {
 400                         compatible = "ti,omap4-mcspi";
 401                         reg = <0x4809a000 0x200>;
 402                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         ti,hwmods = "mcspi2";
 406                         ti,spi-num-cs = <2>;
 407                         dmas = <&sdma 43>,
 408                                <&sdma 44>,
 409                                <&sdma 45>,
 410                                <&sdma 46>;
 411                         dma-names = "tx0", "rx0", "tx1", "rx1";
 412                 };
 413
 414                 mcspi3: spi@480b8000 {
 415                         compatible = "ti,omap4-mcspi";
 416                         reg = <0x480b8000 0x200>;
 417                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "mcspi3";
 421                         ti,spi-num-cs = <2>;
 422                         dmas = <&sdma 15>, <&sdma 16>;
 423                         dma-names = "tx0", "rx0";
 424                 };
 425
 426                 mcspi4: spi@480ba000 {
 427                         compatible = "ti,omap4-mcspi";
 428                         reg = <0x480ba000 0x200>;
 429                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         ti,hwmods = "mcspi4";
 433                         ti,spi-num-cs = <1>;
 434                         dmas = <&sdma 70>, <&sdma 71>;
 435                         dma-names = "tx0", "rx0";
 436                 };
 437
 438                 mmc1: mmc@4809c000 {
 439                         compatible = "ti,omap4-hsmmc";
 440                         reg = <0x4809c000 0x400>;
 441                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 442                         ti,hwmods = "mmc1";
 443                         ti,dual-volt;
 444                         ti,needs-special-reset;
 445                         dmas = <&sdma 61>, <&sdma 62>;
 446                         dma-names = "tx", "rx";
 447                         pbias-supply = <&pbias_mmc_reg>;
 448                 };
 449
 450                 mmc2: mmc@480b4000 {
 451                         compatible = "ti,omap4-hsmmc";
 452                         reg = <0x480b4000 0x400>;
 453                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 454                         ti,hwmods = "mmc2";
 455                         ti,needs-special-reset;
 456                         dmas = <&sdma 47>, <&sdma 48>;
 457                         dma-names = "tx", "rx";
 458                 };
 459
 460                 mmc3: mmc@480ad000 {
 461                         compatible = "ti,omap4-hsmmc";
 462                         reg = <0x480ad000 0x400>;
 463                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 464                         ti,hwmods = "mmc3";
 465                         ti,needs-special-reset;
 466                         dmas = <&sdma 77>, <&sdma 78>;
 467                         dma-names = "tx", "rx";
 468                 };
 469
 470                 mmc4: mmc@480d1000 {
 471                         compatible = "ti,omap4-hsmmc";
 472                         reg = <0x480d1000 0x400>;
 473                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 474                         ti,hwmods = "mmc4";
 475                         ti,needs-special-reset;
 476                         dmas = <&sdma 57>, <&sdma 58>;
 477                         dma-names = "tx", "rx";
 478                 };
 479
 480                 mmc5: mmc@480d5000 {
 481                         compatible = "ti,omap4-hsmmc";
 482                         reg = <0x480d5000 0x400>;
 483                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 484                         ti,hwmods = "mmc5";
 485                         ti,needs-special-reset;
 486                         dmas = <&sdma 59>, <&sdma 60>;
 487                         dma-names = "tx", "rx";
 488                 };
 489
 490                 mmu_dsp: mmu@4a066000 {
 491                         compatible = "ti,omap4-iommu";
 492                         reg = <0x4a066000 0x100>;
 493                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 494                         ti,hwmods = "mmu_dsp";
 495                 };
 496
 497                 mmu_ipu: mmu@55082000 {
 498                         compatible = "ti,omap4-iommu";
 499                         reg = <0x55082000 0x100>;
 500                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 501                         ti,hwmods = "mmu_ipu";
 502                         ti,iommu-bus-err-back;
 503                 };
 504
 505                 wdt2: wdt@4a314000 {
 506                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 507                         reg = <0x4a314000 0x80>;
 508                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 509                         ti,hwmods = "wd_timer2";
 510                 };
 511
 512                 mcpdm: mcpdm@40132000 {
 513                         compatible = "ti,omap4-mcpdm";
 514                         reg = <0x40132000 0x7f>, /* MPU private access */
 515                               <0x49032000 0x7f>; /* L3 Interconnect */
 516                         reg-names = "mpu", "dma";
 517                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 518                         ti,hwmods = "mcpdm";
 519                         dmas = <&sdma 65>,
 520                                <&sdma 66>;
 521                         dma-names = "up_link", "dn_link";
 522                         status = "disabled";
 523                 };
 524
 525                 dmic: dmic@4012e000 {
 526                         compatible = "ti,omap4-dmic";
 527                         reg = <0x4012e000 0x7f>, /* MPU private access */
 528                               <0x4902e000 0x7f>; /* L3 Interconnect */
 529                         reg-names = "mpu", "dma";
 530                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 531                         ti,hwmods = "dmic";
 532                         dmas = <&sdma 67>;
 533                         dma-names = "up_link";
 534                         status = "disabled";
 535                 };
 536
 537                 mcbsp1: mcbsp@40122000 {
 538                         compatible = "ti,omap4-mcbsp";
 539                         reg = <0x40122000 0xff>, /* MPU private access */
 540                               <0x49022000 0xff>; /* L3 Interconnect */
 541                         reg-names = "mpu", "dma";
 542                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 543                         interrupt-names = "common";
 544                         ti,buffer-size = <128>;
 545                         ti,hwmods = "mcbsp1";
 546                         dmas = <&sdma 33>,
 547                                <&sdma 34>;
 548                         dma-names = "tx", "rx";
 549                         status = "disabled";
 550                 };
 551
 552                 mcbsp2: mcbsp@40124000 {
 553                         compatible = "ti,omap4-mcbsp";
 554                         reg = <0x40124000 0xff>, /* MPU private access */
 555                               <0x49024000 0xff>; /* L3 Interconnect */
 556                         reg-names = "mpu", "dma";
 557                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 558                         interrupt-names = "common";
 559                         ti,buffer-size = <128>;
 560                         ti,hwmods = "mcbsp2";
 561                         dmas = <&sdma 17>,
 562                                <&sdma 18>;
 563                         dma-names = "tx", "rx";
 564                         status = "disabled";
 565                 };
 566
 567                 mcbsp3: mcbsp@40126000 {
 568                         compatible = "ti,omap4-mcbsp";
 569                         reg = <0x40126000 0xff>, /* MPU private access */
 570                               <0x49026000 0xff>; /* L3 Interconnect */
 571                         reg-names = "mpu", "dma";
 572                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 573                         interrupt-names = "common";
 574                         ti,buffer-size = <128>;
 575                         ti,hwmods = "mcbsp3";
 576                         dmas = <&sdma 19>,
 577                                <&sdma 20>;
 578                         dma-names = "tx", "rx";
 579                         status = "disabled";
 580                 };
 581
 582                 mcbsp4: mcbsp@48096000 {
 583                         compatible = "ti,omap4-mcbsp";
 584                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 585                         reg-names = "mpu";
 586                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 587                         interrupt-names = "common";
 588                         ti,buffer-size = <128>;
 589                         ti,hwmods = "mcbsp4";
 590                         dmas = <&sdma 31>,
 591                                <&sdma 32>;
 592                         dma-names = "tx", "rx";
 593                         status = "disabled";
 594                 };
 595
 596                 keypad: keypad@4a31c000 {
 597                         compatible = "ti,omap4-keypad";
 598                         reg = <0x4a31c000 0x80>;
 599                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 600                         reg-names = "mpu";
 601                         ti,hwmods = "kbd";
 602                 };
 603
 604                 dmm@4e000000 {
 605                         compatible = "ti,omap4-dmm";
 606                         reg = <0x4e000000 0x800>;
 607                         interrupts = <0 113 0x4>;
 608                         ti,hwmods = "dmm";
 609                 };
 610
 611                 emif1: emif@4c000000 {
 612                         compatible = "ti,emif-4d";
 613                         reg = <0x4c000000 0x100>;
 614                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "emif1";
 616                         ti,no-idle-on-init;
 617                         phy-type = <1>;
 618                         hw-caps-read-idle-ctrl;
 619                         hw-caps-ll-interface;
 620                         hw-caps-temp-alert;
 621                 };
 622
 623                 emif2: emif@4d000000 {
 624                         compatible = "ti,emif-4d";
 625                         reg = <0x4d000000 0x100>;
 626                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 627                         ti,hwmods = "emif2";
 628                         ti,no-idle-on-init;
 629                         phy-type = <1>;
 630                         hw-caps-read-idle-ctrl;
 631                         hw-caps-ll-interface;
 632                         hw-caps-temp-alert;
 633                 };
 634
 635                 ocp2scp@4a0ad000 {
 636                         compatible = "ti,omap-ocp2scp";
 637                         reg = <0x4a0ad000 0x1f>;
 638                         #address-cells = <1>;
 639                         #size-cells = <1>;
 640                         ranges;
 641                         ti,hwmods = "ocp2scp_usb_phy";
 642                         usb2_phy: usb2phy@4a0ad080 {
 643                                 compatible = "ti,omap-usb2";
 644                                 reg = <0x4a0ad080 0x58>;
 645                                 ctrl-module = <&omap_control_usb2phy>;
 646                                 clocks = <&usb_phy_cm_clk32k>;
 647                                 clock-names = "wkupclk";
 648                                 #phy-cells = <0>;
 649                         };
 650                 };
 651
 652                 timer1: timer@4a318000 {
 653                         compatible = "ti,omap3430-timer";
 654                         reg = <0x4a318000 0x80>;
 655                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 656                         ti,hwmods = "timer1";
 657                         ti,timer-alwon;
 658                 };
 659
 660                 timer2: timer@48032000 {
 661                         compatible = "ti,omap3430-timer";
 662                         reg = <0x48032000 0x80>;
 663                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 664                         ti,hwmods = "timer2";
 665                 };
 666
 667                 timer3: timer@48034000 {
 668                         compatible = "ti,omap4430-timer";
 669                         reg = <0x48034000 0x80>;
 670                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 671                         ti,hwmods = "timer3";
 672                 };
 673
 674                 timer4: timer@48036000 {
 675                         compatible = "ti,omap4430-timer";
 676                         reg = <0x48036000 0x80>;
 677                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 678                         ti,hwmods = "timer4";
 679                 };
 680
 681                 timer5: timer@40138000 {
 682                         compatible = "ti,omap4430-timer";
 683                         reg = <0x40138000 0x80>,
 684                               <0x49038000 0x80>;
 685                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 686                         ti,hwmods = "timer5";
 687                         ti,timer-dsp;
 688                 };
 689
 690                 timer6: timer@4013a000 {
 691                         compatible = "ti,omap4430-timer";
 692                         reg = <0x4013a000 0x80>,
 693                               <0x4903a000 0x80>;
 694                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "timer6";
 696                         ti,timer-dsp;
 697                 };
 698
 699                 timer7: timer@4013c000 {
 700                         compatible = "ti,omap4430-timer";
 701                         reg = <0x4013c000 0x80>,
 702                               <0x4903c000 0x80>;
 703                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 704                         ti,hwmods = "timer7";
 705                         ti,timer-dsp;
 706                 };
 707
 708                 timer8: timer@4013e000 {
 709                         compatible = "ti,omap4430-timer";
 710                         reg = <0x4013e000 0x80>,
 711                               <0x4903e000 0x80>;
 712                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "timer8";
 714                         ti,timer-pwm;
 715                         ti,timer-dsp;
 716                 };
 717
 718                 timer9: timer@4803e000 {
 719                         compatible = "ti,omap4430-timer";
 720                         reg = <0x4803e000 0x80>;
 721                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 722                         ti,hwmods = "timer9";
 723                         ti,timer-pwm;
 724                 };
 725
 726                 timer10: timer@48086000 {
 727                         compatible = "ti,omap3430-timer";
 728                         reg = <0x48086000 0x80>;
 729                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 730                         ti,hwmods = "timer10";
 731                         ti,timer-pwm;
 732                 };
 733
 734                 timer11: timer@48088000 {
 735                         compatible = "ti,omap4430-timer";
 736                         reg = <0x48088000 0x80>;
 737                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 738                         ti,hwmods = "timer11";
 739                         ti,timer-pwm;
 740                 };
 741
 742                 usbhstll: usbhstll@4a062000 {
 743                         compatible = "ti,usbhs-tll";
 744                         reg = <0x4a062000 0x1000>;
 745                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "usb_tll_hs";
 747                 };
 748
 749                 usbhshost: usbhshost@4a064000 {
 750                         compatible = "ti,usbhs-host";
 751                         reg = <0x4a064000 0x800>;
 752                         ti,hwmods = "usb_host_hs";
 753                         #address-cells = <1>;
 754                         #size-cells = <1>;
 755                         ranges;
 756                         clocks = <&init_60m_fclk>,
 757                                  <&xclk60mhsp1_ck>,
 758                                  <&xclk60mhsp2_ck>;
 759                         clock-names = "refclk_60m_int",
 760                                       "refclk_60m_ext_p1",
 761                                       "refclk_60m_ext_p2";
 762
 763                         usbhsohci: ohci@4a064800 {
 764                                 compatible = "ti,ohci-omap3";
 765                                 reg = <0x4a064800 0x400>;
 766                                 interrupt-parent = <&gic>;
 767                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 768                         };
 769
 770                         usbhsehci: ehci@4a064c00 {
 771                                 compatible = "ti,ehci-omap";
 772                                 reg = <0x4a064c00 0x400>;
 773                                 interrupt-parent = <&gic>;
 774                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 775                         };
 776                 };
 777
 778                 omap_control_usb2phy: control-phy@4a002300 {
 779                         compatible = "ti,control-phy-usb2";
 780                         reg = <0x4a002300 0x4>;
 781                         reg-names = "power";
 782                 };
 783
 784                 omap_control_usbotg: control-phy@4a00233c {
 785                         compatible = "ti,control-phy-otghs";
 786                         reg = <0x4a00233c 0x4>;
 787                         reg-names = "otghs_control";
 788                 };
 789
 790                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 791                         compatible = "ti,omap4-musb";
 792                         reg = <0x4a0ab000 0x7ff>;
 793                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 794                         interrupt-names = "mc", "dma";
 795                         ti,hwmods = "usb_otg_hs";
 796                         usb-phy = <&usb2_phy>;
 797                         phys = <&usb2_phy>;
 798                         phy-names = "usb2-phy";
 799                         multipoint = <1>;
 800                         num-eps = <16>;
 801                         ram-bits = <12>;
 802                         ctrl-module = <&omap_control_usbotg>;
 803                 };
 804
 805                 aes: aes@4b501000 {
 806                         compatible = "ti,omap4-aes";
 807                         ti,hwmods = "aes";
 808                         reg = <0x4b501000 0xa0>;
 809                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 810                         dmas = <&sdma 111>, <&sdma 110>;
 811                         dma-names = "tx", "rx";
 812                 };
 813
 814                 des: des@480a5000 {
 815                         compatible = "ti,omap4-des";
 816                         ti,hwmods = "des";
 817                         reg = <0x480a5000 0xa0>;
 818                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 819                         dmas = <&sdma 117>, <&sdma 116>;
 820                         dma-names = "tx", "rx";
 821                 };
 822
 823                 abb_mpu: regulator-abb-mpu {
 824                         compatible = "ti,abb-v2";
 825                         regulator-name = "abb_mpu";
 826                         #address-cells = <0>;
 827                         #size-cells = <0>;
 828                         ti,tranxdone-status-mask = <0x80>;
 829                         clocks = <&sys_clkin_ck>;
 830                         ti,settling-time = <50>;
 831                         ti,clock-cycles = <16>;
 832
 833                         status = "disabled";
 834                 };
 835
 836                 abb_iva: regulator-abb-iva {
 837                         compatible = "ti,abb-v2";
 838                         regulator-name = "abb_iva";
 839                         #address-cells = <0>;
 840                         #size-cells = <0>;
 841                         ti,tranxdone-status-mask = <0x80000000>;
 842                         clocks = <&sys_clkin_ck>;
 843                         ti,settling-time = <50>;
 844                         ti,clock-cycles = <16>;
 845
 846                         status = "disabled";
 847                 };
 848
 849                 dss: dss@58000000 {
 850                         compatible = "ti,omap4-dss";
 851                         reg = <0x58000000 0x80>;
 852                         status = "disabled";
 853                         ti,hwmods = "dss_core";
 854                         clocks = <&dss_dss_clk>;
 855                         clock-names = "fck";
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         ranges;
 859
 860                         dispc@58001000 {
 861                                 compatible = "ti,omap4-dispc";
 862                                 reg = <0x58001000 0x1000>;
 863                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 864                                 ti,hwmods = "dss_dispc";
 865                                 clocks = <&dss_dss_clk>;
 866                                 clock-names = "fck";
 867                         };
 868
 869                         rfbi: encoder@58002000  {
 870                                 compatible = "ti,omap4-rfbi";
 871                                 reg = <0x58002000 0x1000>;
 872                                 status = "disabled";
 873                                 ti,hwmods = "dss_rfbi";
 874                                 clocks = <&dss_dss_clk>, <&dss_fck>;
 875                                 clock-names = "fck", "ick";
 876                         };
 877
 878                         venc: encoder@58003000 {
 879                                 compatible = "ti,omap4-venc";
 880                                 reg = <0x58003000 0x1000>;
 881                                 status = "disabled";
 882                                 ti,hwmods = "dss_venc";
 883                                 clocks = <&dss_tv_clk>;
 884                                 clock-names = "fck";
 885                         };
 886
 887                         dsi1: encoder@58004000 {
 888                                 compatible = "ti,omap4-dsi";
 889                                 reg = <0x58004000 0x200>,
 890                                       <0x58004200 0x40>,
 891                                       <0x58004300 0x20>;
 892                                 reg-names = "proto", "phy", "pll";
 893                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 894                                 status = "disabled";
 895                                 ti,hwmods = "dss_dsi1";
 896                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 897                                 clock-names = "fck", "sys_clk";
 898                         };
 899
 900                         dsi2: encoder@58005000 {
 901                                 compatible = "ti,omap4-dsi";
 902                                 reg = <0x58005000 0x200>,
 903                                       <0x58005200 0x40>,
 904                                       <0x58005300 0x20>;
 905                                 reg-names = "proto", "phy", "pll";
 906                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 907                                 status = "disabled";
 908                                 ti,hwmods = "dss_dsi2";
 909                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 910                                 clock-names = "fck", "sys_clk";
 911                         };
 912
 913                         hdmi: encoder@58006000 {
 914                                 compatible = "ti,omap4-hdmi";
 915                                 reg = <0x58006000 0x200>,
 916                                       <0x58006200 0x100>,
 917                                       <0x58006300 0x100>,
 918                                       <0x58006400 0x1000>;
 919                                 reg-names = "wp", "pll", "phy", "core";
 920                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 921                                 status = "disabled";
 922                                 ti,hwmods = "dss_hdmi";
 923                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 924                                 clock-names = "fck", "sys_clk";
 925                                 dmas = <&sdma 76>;
 926                                 dma-names = "audio_tx";
 927                         };
 928                 };
 929         };
 930 };
 931
 932 /include/ "omap44xx-clocks.dtsi"