arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                         clocks = <&clks 12>;
  33                         operating-points = <
  34                                 /* kHz    uV */
  35                                 200000  1025000
  36                                 400000  1025000
  37                                 664000  1050000
  38                                 800000  1100000
  39                         >;
  40                         clock-latency = <150000>;
  41                 };
  42         };
  43
  44         axi {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x40000000 0x40000000 0x80000000>;
  49
  50                 l2-cache-controller@80040000 {
  51                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  52                         reg = <0x80040000 0x1000>;
  53                         interrupts = <59>;
  54                         arm,tag-latency = <1 1 1>;
  55                         arm,data-latency = <1 1 1>;
  56                         arm,filter-ranges = <0 0x40000000>;
  57                 };
  58
  59                 intc: interrupt-controller@80020000 {
  60                         #interrupt-cells = <1>;
  61                         interrupt-controller;
  62                         compatible = "sirf,prima2-intc";
  63                         reg = <0x80020000 0x1000>;
  64                 };
  65
  66                 sys-iobg {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges = <0x88000000 0x88000000 0x40000>;
  71
  72                         clks: clock-controller@88000000 {
  73                                 compatible = "sirf,prima2-clkc";
  74                                 reg = <0x88000000 0x1000>;
  75                                 interrupts = <3>;
  76                                 #clock-cells = <1>;
  77                         };
  78
  79                         reset-controller@88010000 {
  80                                 compatible = "sirf,prima2-rstc";
  81                                 reg = <0x88010000 0x1000>;
  82                         };
  83
  84                         rsc-controller@88020000 {
  85                                 compatible = "sirf,prima2-rsc";
  86                                 reg = <0x88020000 0x1000>;
  87                         };
  88
  89                         cphifbg@88030000 {
  90                                 compatible = "sirf,prima2-cphifbg";
  91                                 reg = <0x88030000 0x1000>;
  92                                 clocks = <&clks 42>;
  93                         };
  94                 };
  95
  96                 mem-iobg {
  97                         compatible = "simple-bus";
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100                         ranges = <0x90000000 0x90000000 0x10000>;
 101
 102                         memory-controller@90000000 {
 103                                 compatible = "sirf,prima2-memc";
 104                                 reg = <0x90000000 0x2000>;
 105                                 interrupts = <27>;
 106                                 clocks = <&clks 5>;
 107                         };
 108
 109                         memc-monitor {
 110                                 compatible = "sirf,prima2-memcmon";
 111                                 reg = <0x90002000 0x200>;
 112                                 interrupts = <4>;
 113                                 clocks = <&clks 32>;
 114                         };
 115                 };
 116
 117                 disp-iobg {
 118                         compatible = "simple-bus";
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         ranges = <0x90010000 0x90010000 0x30000>;
 122
 123                         display@90010000 {
 124                                 compatible = "sirf,prima2-lcd";
 125                                 reg = <0x90010000 0x20000>;
 126                                 interrupts = <30>;
 127                         };
 128
 129                         vpp@90020000 {
 130                                 compatible = "sirf,prima2-vpp";
 131                                 reg = <0x90020000 0x10000>;
 132                                 interrupts = <31>;
 133                                 clocks = <&clks 35>;
 134                         };
 135                 };
 136
 137                 graphics-iobg {
 138                         compatible = "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         ranges = <0x98000000 0x98000000 0x8000000>;
 142
 143                         graphics@98000000 {
 144                                 compatible = "powervr,sgx531";
 145                                 reg = <0x98000000 0x8000000>;
 146                                 interrupts = <6>;
 147                                 clocks = <&clks 32>;
 148                         };
 149                 };
 150
 151                 multimedia-iobg {
 152                         compatible = "simple-bus";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 156
 157                         multimedia@a0000000 {
 158                                 compatible = "sirf,prima2-video-codec";
 159                                 reg = <0xa0000000 0x8000000>;
 160                                 interrupts = <5>;
 161                                 clocks = <&clks 33>;
 162                         };
 163                 };
 164
 165                 dsp-iobg {
 166                         compatible = "simple-bus";
 167                         #address-cells = <1>;
 168                         #size-cells = <1>;
 169                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 170
 171                         dspif@a8000000 {
 172                                 compatible = "sirf,prima2-dspif";
 173                                 reg = <0xa8000000 0x10000>;
 174                                 interrupts = <9>;
 175                         };
 176
 177                         gps@a8010000 {
 178                                 compatible = "sirf,prima2-gps";
 179                                 reg = <0xa8010000 0x10000>;
 180                                 interrupts = <7>;
 181                                 clocks = <&clks 9>;
 182                         };
 183
 184                         dsp@a9000000 {
 185                                 compatible = "sirf,prima2-dsp";
 186                                 reg = <0xa9000000 0x1000000>;
 187                                 interrupts = <8>;
 188                                 clocks = <&clks 8>;
 189                         };
 190                 };
 191
 192                 peri-iobg {
 193                         compatible = "simple-bus";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         ranges = <0xb0000000 0xb0000000 0x180000>,
 197                                <0x56000000 0x56000000 0x1b00000>;
 198
 199                         timer@b0020000 {
 200                                 compatible = "sirf,prima2-tick";
 201                                 reg = <0xb0020000 0x1000>;
 202                                 interrupts = <0>;
 203                         };
 204
 205                         nand@b0030000 {
 206                                 compatible = "sirf,prima2-nand";
 207                                 reg = <0xb0030000 0x10000>;
 208                                 interrupts = <41>;
 209                                 clocks = <&clks 26>;
 210                         };
 211
 212                         audio@b0040000 {
 213                                 compatible = "sirf,prima2-audio";
 214                                 reg = <0xb0040000 0x10000>;
 215                                 interrupts = <35>;
 216                                 clocks = <&clks 27>;
 217                         };
 218
 219                         uart0: uart@b0050000 {
 220                                 cell-index = <0>;
 221                                 compatible = "sirf,prima2-uart";
 222                                 reg = <0xb0050000 0x1000>;
 223                                 interrupts = <17>;
 224                                 fifosize = <128>;
 225                                 clocks = <&clks 13>;
 226                                 sirf,uart-dma-rx-channel = <21>;
 227                                 sirf,uart-dma-tx-channel = <2>;
 228                         };
 229
 230                         uart1: uart@b0060000 {
 231                                 cell-index = <1>;
 232                                 compatible = "sirf,prima2-uart";
 233                                 reg = <0xb0060000 0x1000>;
 234                                 interrupts = <18>;
 235                                 fifosize = <32>;
 236                                 clocks = <&clks 14>;
 237                         };
 238
 239                         uart2: uart@b0070000 {
 240                                 cell-index = <2>;
 241                                 compatible = "sirf,prima2-uart";
 242                                 reg = <0xb0070000 0x1000>;
 243                                 interrupts = <19>;
 244                                 fifosize = <128>;
 245                                 clocks = <&clks 15>;
 246                                 sirf,uart-dma-rx-channel = <6>;
 247                                 sirf,uart-dma-tx-channel = <7>;
 248                         };
 249
 250                         usp0: usp@b0080000 {
 251                                 cell-index = <0>;
 252                                 compatible = "sirf,prima2-usp";
 253                                 reg = <0xb0080000 0x10000>;
 254                                 interrupts = <20>;
 255                                 fifosize = <128>;
 256                                 clocks = <&clks 28>;
 257                                 sirf,usp-dma-rx-channel = <17>;
 258                                 sirf,usp-dma-tx-channel = <18>;
 259                         };
 260
 261                         usp1: usp@b0090000 {
 262                                 cell-index = <1>;
 263                                 compatible = "sirf,prima2-usp";
 264                                 reg = <0xb0090000 0x10000>;
 265                                 interrupts = <21>;
 266                                 fifosize = <128>;
 267                                 clocks = <&clks 29>;
 268                                 sirf,usp-dma-rx-channel = <14>;
 269                                 sirf,usp-dma-tx-channel = <15>;
 270                         };
 271
 272                         usp2: usp@b00a0000 {
 273                                 cell-index = <2>;
 274                                 compatible = "sirf,prima2-usp";
 275                                 reg = <0xb00a0000 0x10000>;
 276                                 interrupts = <22>;
 277                                 fifosize = <128>;
 278                                 clocks = <&clks 30>;
 279                                 sirf,usp-dma-rx-channel = <10>;
 280                                 sirf,usp-dma-tx-channel = <11>;
 281                         };
 282
 283                         dmac0: dma-controller@b00b0000 {
 284                                 cell-index = <0>;
 285                                 compatible = "sirf,prima2-dmac";
 286                                 reg = <0xb00b0000 0x10000>;
 287                                 interrupts = <12>;
 288                                 clocks = <&clks 24>;
 289                                 #dma-cells = <1>;
 290                         };
 291
 292                         dmac1: dma-controller@b0160000 {
 293                                 cell-index = <1>;
 294                                 compatible = "sirf,prima2-dmac";
 295                                 reg = <0xb0160000 0x10000>;
 296                                 interrupts = <13>;
 297                                 clocks = <&clks 25>;
 298                                 #dma-cells = <1>;
 299                         };
 300
 301                         vip@b00C0000 {
 302                                 compatible = "sirf,prima2-vip";
 303                                 reg = <0xb00C0000 0x10000>;
 304                                 clocks = <&clks 31>;
 305                                 interrupts = <14>;
 306                                 sirf,vip-dma-rx-channel = <16>;
 307                         };
 308
 309                         spi0: spi@b00d0000 {
 310                                 cell-index = <0>;
 311                                 compatible = "sirf,prima2-spi";
 312                                 reg = <0xb00d0000 0x10000>;
 313                                 interrupts = <15>;
 314                                 sirf,spi-num-chipselects = <1>;
 315                                 sirf,spi-dma-rx-channel = <25>;
 316                                 sirf,spi-dma-tx-channel = <20>;
 317                                 #address-cells = <1>;
 318                                 #size-cells = <0>;
 319                                 clocks = <&clks 19>;
 320                                 status = "disabled";
 321                         };
 322
 323                         spi1: spi@b0170000 {
 324                                 cell-index = <1>;
 325                                 compatible = "sirf,prima2-spi";
 326                                 reg = <0xb0170000 0x10000>;
 327                                 interrupts = <16>;
 328                                 sirf,spi-num-chipselects = <1>;
 329                                 sirf,spi-dma-rx-channel = <12>;
 330                                 sirf,spi-dma-tx-channel = <13>;
 331                                 #address-cells = <1>;
 332                                 #size-cells = <0>;
 333                                 clocks = <&clks 20>;
 334                                 status = "disabled";
 335                         };
 336
 337                         i2c0: i2c@b00e0000 {
 338                                 cell-index = <0>;
 339                                 compatible = "sirf,prima2-i2c";
 340                                 reg = <0xb00e0000 0x10000>;
 341                                 interrupts = <24>;
 342                                 clocks = <&clks 17>;
 343                                 #address-cells = <1>;
 344                                 #size-cells = <0>;
 345                         };
 346
 347                         i2c1: i2c@b00f0000 {
 348                                 cell-index = <1>;
 349                                 compatible = "sirf,prima2-i2c";
 350                                 reg = <0xb00f0000 0x10000>;
 351                                 interrupts = <25>;
 352                                 clocks = <&clks 18>;
 353                                 #address-cells = <1>;
 354                                 #size-cells = <0>;
 355                         };
 356
 357                         tsc@b0110000 {
 358                                 compatible = "sirf,prima2-tsc";
 359                                 reg = <0xb0110000 0x10000>;
 360                                 interrupts = <33>;
 361                                 clocks = <&clks 16>;
 362                         };
 363
 364                         gpio: pinctrl@b0120000 {
 365                                 #gpio-cells = <2>;
 366                                 #interrupt-cells = <2>;
 367                                 compatible = "sirf,prima2-pinctrl";
 368                                 reg = <0xb0120000 0x10000>;
 369                                 interrupts = <43 44 45 46 47>;
 370                                 gpio-controller;
 371                                 interrupt-controller;
 372
 373                                 lcd_16pins_a: lcd0@0 {
 374                                         lcd {
 375                                                 sirf,pins = "lcd_16bitsgrp";
 376                                                 sirf,function = "lcd_16bits";
 377                                         };
 378                                 };
 379                                 lcd_18pins_a: lcd0@1 {
 380                                         lcd {
 381                                                 sirf,pins = "lcd_18bitsgrp";
 382                                                 sirf,function = "lcd_18bits";
 383                                         };
 384                                 };
 385                                 lcd_24pins_a: lcd0@2 {
 386                                         lcd {
 387                                                 sirf,pins = "lcd_24bitsgrp";
 388                                                 sirf,function = "lcd_24bits";
 389                                         };
 390                                 };
 391                                 lcdrom_pins_a: lcdrom0@0 {
 392                                         lcd {
 393                                                 sirf,pins = "lcdromgrp";
 394                                                 sirf,function = "lcdrom";
 395                                         };
 396                                 };
 397                                 uart0_pins_a: uart0@0 {
 398                                         uart {
 399                                                 sirf,pins = "uart0grp";
 400                                                 sirf,function = "uart0";
 401                                         };
 402                                 };
 403                                 uart0_noflow_pins_a: uart0@1 {
 404                                         uart {
 405                                                 sirf,pins = "uart0_nostreamctrlgrp";
 406                                                 sirf,function = "uart0_nostreamctrl";
 407                                         };
 408                                 };
 409                                 uart1_pins_a: uart1@0 {
 410                                         uart {
 411                                                 sirf,pins = "uart1grp";
 412                                                 sirf,function = "uart1";
 413                                         };
 414                                 };
 415                                 uart2_pins_a: uart2@0 {
 416                                         uart {
 417                                                 sirf,pins = "uart2grp";
 418                                                 sirf,function = "uart2";
 419                                         };
 420                                 };
 421                                 uart2_noflow_pins_a: uart2@1 {
 422                                         uart {
 423                                                 sirf,pins = "uart2_nostreamctrlgrp";
 424                                                 sirf,function = "uart2_nostreamctrl";
 425                                         };
 426                                 };
 427                                 spi0_pins_a: spi0@0 {
 428                                         spi {
 429                                                 sirf,pins = "spi0grp";
 430                                                 sirf,function = "spi0";
 431                                         };
 432                                 };
 433                                 spi1_pins_a: spi1@0 {
 434                                         spi {
 435                                                 sirf,pins = "spi1grp";
 436                                                 sirf,function = "spi1";
 437                                         };
 438                                 };
 439                                 i2c0_pins_a: i2c0@0 {
 440                                         i2c {
 441                                                 sirf,pins = "i2c0grp";
 442                                                 sirf,function = "i2c0";
 443                                         };
 444                                 };
 445                                 i2c1_pins_a: i2c1@0 {
 446                                         i2c {
 447                                                 sirf,pins = "i2c1grp";
 448                                                 sirf,function = "i2c1";
 449                                         };
 450                                 };
 451                                 pwm0_pins_a: pwm0@0 {
 452                                         pwm {
 453                                                 sirf,pins = "pwm0grp";
 454                                                 sirf,function = "pwm0";
 455                                         };
 456                                 };
 457                                 pwm1_pins_a: pwm1@0 {
 458                                         pwm {
 459                                                 sirf,pins = "pwm1grp";
 460                                                 sirf,function = "pwm1";
 461                                         };
 462                                 };
 463                                 pwm2_pins_a: pwm2@0 {
 464                                         pwm {
 465                                                 sirf,pins = "pwm2grp";
 466                                                 sirf,function = "pwm2";
 467                                         };
 468                                 };
 469                                 pwm3_pins_a: pwm3@0 {
 470                                         pwm {
 471                                                 sirf,pins = "pwm3grp";
 472                                                 sirf,function = "pwm3";
 473                                         };
 474                                 };
 475                                 gps_pins_a: gps@0 {
 476                                         gps {
 477                                                 sirf,pins = "gpsgrp";
 478                                                 sirf,function = "gps";
 479                                         };
 480                                 };
 481                                 vip_pins_a: vip@0 {
 482                                         vip {
 483                                                 sirf,pins = "vipgrp";
 484                                                 sirf,function = "vip";
 485                                         };
 486                                 };
 487                                 sdmmc0_pins_a: sdmmc0@0 {
 488                                         sdmmc0 {
 489                                                 sirf,pins = "sdmmc0grp";
 490                                                 sirf,function = "sdmmc0";
 491                                         };
 492                                 };
 493                                 sdmmc1_pins_a: sdmmc1@0 {
 494                                         sdmmc1 {
 495                                                 sirf,pins = "sdmmc1grp";
 496                                                 sirf,function = "sdmmc1";
 497                                         };
 498                                 };
 499                                 sdmmc2_pins_a: sdmmc2@0 {
 500                                         sdmmc2 {
 501                                                 sirf,pins = "sdmmc2grp";
 502                                                 sirf,function = "sdmmc2";
 503                                         };
 504                                 };
 505                                 sdmmc3_pins_a: sdmmc3@0 {
 506                                         sdmmc3 {
 507                                                 sirf,pins = "sdmmc3grp";
 508                                                 sirf,function = "sdmmc3";
 509                                         };
 510                                 };
 511                                 sdmmc4_pins_a: sdmmc4@0 {
 512                                         sdmmc4 {
 513                                                 sirf,pins = "sdmmc4grp";
 514                                                 sirf,function = "sdmmc4";
 515                                         };
 516                                 };
 517                                 sdmmc5_pins_a: sdmmc5@0 {
 518                                         sdmmc5 {
 519                                                 sirf,pins = "sdmmc5grp";
 520                                                 sirf,function = "sdmmc5";
 521                                         };
 522                                 };
 523                                 i2s_pins_a: i2s@0 {
 524                                         i2s {
 525                                                 sirf,pins = "i2sgrp";
 526                                                 sirf,function = "i2s";
 527                                         };
 528                                 };
 529                                 ac97_pins_a: ac97@0 {
 530                                         ac97 {
 531                                                 sirf,pins = "ac97grp";
 532                                                 sirf,function = "ac97";
 533                                         };
 534                                 };
 535                                 nand_pins_a: nand@0 {
 536                                         nand {
 537                                                 sirf,pins = "nandgrp";
 538                                                 sirf,function = "nand";
 539                                         };
 540                                 };
 541                                 usp0_pins_a: usp0@0 {
 542                                         usp0 {
 543                                                 sirf,pins = "usp0grp";
 544                                                 sirf,function = "usp0";
 545                                         };
 546                                 };
 547                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 548                                         usp0 {
 549                                                 sirf,pins =
 550                                                         "usp0_uart_nostreamctrl_grp";
 551                                                 sirf,function =
 552                                                         "usp0_uart_nostreamctrl";
 553                                         };
 554                                 };
 555                                 usp0_only_utfs_pins_a: usp0@2 {
 556                                         usp0 {
 557                                                 sirf,pins = "usp0_only_utfs_grp";
 558                                                 sirf,function = "usp0_only_utfs";
 559                                         };
 560                                 };
 561                                 usp0_only_urfs_pins_a: usp0@3 {
 562                                         usp0 {
 563                                                 sirf,pins = "usp0_only_urfs_grp";
 564                                                 sirf,function = "usp0_only_urfs";
 565                                         };
 566                                 };
 567                                 usp1_pins_a: usp1@0 {
 568                                         usp1 {
 569                                                 sirf,pins = "usp1grp";
 570                                                 sirf,function = "usp1";
 571                                         };
 572                                 };
 573                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 574                                         usp1 {
 575                                                 sirf,pins =
 576                                                         "usp1_uart_nostreamctrl_grp";
 577                                                 sirf,function =
 578                                                         "usp1_uart_nostreamctrl";
 579                                         };
 580                                 };
 581                                 usp2_pins_a: usp2@0 {
 582                                         usp2 {
 583                                                 sirf,pins = "usp2grp";
 584                                                 sirf,function = "usp2";
 585                                         };
 586                                 };
 587                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 588                                         usp2 {
 589                                                 sirf,pins =
 590                                                         "usp2_uart_nostreamctrl_grp";
 591                                                 sirf,function =
 592                                                         "usp2_uart_nostreamctrl";
 593                                         };
 594                                 };
 595                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 596                                         usb0_utmi_drvbus {
 597                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 598                                                 sirf,function = "usb0_utmi_drvbus";
 599                                         };
 600                                 };
 601                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 602                                         usb1_utmi_drvbus {
 603                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 604                                                 sirf,function = "usb1_utmi_drvbus";
 605                                         };
 606                                 };
 607                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 608                                         usb1_dp_dn {
 609                                                 sirf,pins = "usb1_dp_dngrp";
 610                                                 sirf,function = "usb1_dp_dn";
 611                                         };
 612                                 };
 613                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 614                                         uart1_route_io_usb1 {
 615                                                 sirf,pins = "uart1_route_io_usb1grp";
 616                                                 sirf,function = "uart1_route_io_usb1";
 617                                         };
 618                                 };
 619                                 warm_rst_pins_a: warm_rst@0 {
 620                                         warm_rst {
 621                                                 sirf,pins = "warm_rstgrp";
 622                                                 sirf,function = "warm_rst";
 623                                         };
 624                                 };
 625                                 pulse_count_pins_a: pulse_count@0 {
 626                                         pulse_count {
 627                                                 sirf,pins = "pulse_countgrp";
 628                                                 sirf,function = "pulse_count";
 629                                         };
 630                                 };
 631                                 cko0_pins_a: cko0@0 {
 632                                         cko0 {
 633                                                 sirf,pins = "cko0grp";
 634                                                 sirf,function = "cko0";
 635                                         };
 636                                 };
 637                                 cko1_pins_a: cko1@0 {
 638                                         cko1 {
 639                                                 sirf,pins = "cko1grp";
 640                                                 sirf,function = "cko1";
 641                                         };
 642                                 };
 643                         };
 644
 645                         pwm@b0130000 {
 646                                 compatible = "sirf,prima2-pwm";
 647                                 reg = <0xb0130000 0x10000>;
 648                                 clocks = <&clks 21>;
 649                         };
 650
 651                         efusesys@b0140000 {
 652                                 compatible = "sirf,prima2-efuse";
 653                                 reg = <0xb0140000 0x10000>;
 654                                 clocks = <&clks 22>;
 655                         };
 656
 657                         pulsec@b0150000 {
 658                                 compatible = "sirf,prima2-pulsec";
 659                                 reg = <0xb0150000 0x10000>;
 660                                 interrupts = <48>;
 661                                 clocks = <&clks 23>;
 662                         };
 663
 664                         pci-iobg {
 665                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 666                                 #address-cells = <1>;
 667                                 #size-cells = <1>;
 668                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 669
 670                                 sd0: sdhci@56000000 {
 671                                         cell-index = <0>;
 672                                         compatible = "sirf,prima2-sdhc";
 673                                         reg = <0x56000000 0x100000>;
 674                                         interrupts = <38>;
 675                                         status = "disabled";
 676                                         bus-width = <8>;
 677                                         clocks = <&clks 36>;
 678                                 };
 679
 680                                 sd1: sdhci@56100000 {
 681                                         cell-index = <1>;
 682                                         compatible = "sirf,prima2-sdhc";
 683                                         reg = <0x56100000 0x100000>;
 684                                         interrupts = <38>;
 685                                         status = "disabled";
 686                                         bus-width = <4>;
 687                                         clocks = <&clks 36>;
 688                                 };
 689
 690                                 sd2: sdhci@56200000 {
 691                                         cell-index = <2>;
 692                                         compatible = "sirf,prima2-sdhc";
 693                                         reg = <0x56200000 0x100000>;
 694                                         interrupts = <23>;
 695                                         status = "disabled";
 696                                         clocks = <&clks 37>;
 697                                 };
 698
 699                                 sd3: sdhci@56300000 {
 700                                         cell-index = <3>;
 701                                         compatible = "sirf,prima2-sdhc";
 702                                         reg = <0x56300000 0x100000>;
 703                                         interrupts = <23>;
 704                                         status = "disabled";
 705                                         clocks = <&clks 37>;
 706                                 };
 707
 708                                 sd4: sdhci@56400000 {
 709                                         cell-index = <4>;
 710                                         compatible = "sirf,prima2-sdhc";
 711                                         reg = <0x56400000 0x100000>;
 712                                         interrupts = <39>;
 713                                         status = "disabled";
 714                                         clocks = <&clks 38>;
 715                                 };
 716
 717                                 sd5: sdhci@56500000 {
 718                                         cell-index = <5>;
 719                                         compatible = "sirf,prima2-sdhc";
 720                                         reg = <0x56500000 0x100000>;
 721                                         interrupts = <39>;
 722                                         clocks = <&clks 38>;
 723                                 };
 724
 725                                 pci-copy@57900000 {
 726                                         compatible = "sirf,prima2-pcicp";
 727                                         reg = <0x57900000 0x100000>;
 728                                         interrupts = <40>;
 729                                 };
 730
 731                                 rom-interface@57a00000 {
 732                                         compatible = "sirf,prima2-romif";
 733                                         reg = <0x57a00000 0x100000>;
 734                                 };
 735                         };
 736                 };
 737
 738                 rtc-iobg {
 739                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 740                         #address-cells = <1>;
 741                         #size-cells = <1>;
 742                         reg = <0x80030000 0x10000>;
 743
 744                         gpsrtc@1000 {
 745                                 compatible = "sirf,prima2-gpsrtc";
 746                                 reg = <0x1000 0x1000>;
 747                                 interrupts = <55 56 57>;
 748                         };
 749
 750                         sysrtc@2000 {
 751                                 compatible = "sirf,prima2-sysrtc";
 752                                 reg = <0x2000 0x1000>;
 753                                 interrupts = <52 53 54>;
 754                         };
 755
 756                         minigpsrtc@2000 {
 757                                 compatible = "sirf,prima2-minigpsrtc";
 758                                 reg = <0x2000 0x1000>;
 759                                 interrupts = <54>;
 760                         };
 761
 762                         pwrc@3000 {
 763                                 compatible = "sirf,prima2-pwrc";
 764                                 reg = <0x3000 0x1000>;
 765                                 interrupts = <32>;
 766                         };
 767                 };
 768
 769                 uus-iobg {
 770                         compatible = "simple-bus";
 771                         #address-cells = <1>;
 772                         #size-cells = <1>;
 773                         ranges = <0xb8000000 0xb8000000 0x40000>;
 774
 775                         usb0: usb@b00e0000 {
 776                                 compatible = "chipidea,ci13611a-prima2";
 777                                 reg = <0xb8000000 0x10000>;
 778                                 interrupts = <10>;
 779                                 clocks = <&clks 40>;
 780                         };
 781
 782                         usb1: usb@b00f0000 {
 783                                 compatible = "chipidea,ci13611a-prima2";
 784                                 reg = <0xb8010000 0x10000>;
 785                                 interrupts = <11>;
 786                                 clocks = <&clks 41>;
 787                         };
 788
 789                         sata@b00f0000 {
 790                                 compatible = "synopsys,dwc-ahsata";
 791                                 reg = <0xb8020000 0x10000>;
 792                                 interrupts = <37>;
 793                         };
 794
 795                         security@b00f0000 {
 796                                 compatible = "sirf,prima2-security";
 797                                 reg = <0xb8030000 0x10000>;
 798                                 interrupts = <42>;
 799                                 clocks = <&clks 7>;
 800                         };
 801                 };
 802         };
 803 };