arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         model = "Qualcomm APQ8064";
  14         compatible = "qcom,apq8064";
  15         interrupt-parent = <&intc>;
  16
  17         reserved-memory {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 smem_region: smem@80000000 {
  23                         reg = <0x80000000 0x200000>;
  24                         no-map;
  25                 };
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 CPU0: cpu@0 {
  33                         compatible = "qcom,krait";
  34                         enable-method = "qcom,kpss-acc-v1";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc0>;
  39                         qcom,saw = <&saw0>;
  40                         cpu-idle-states = <&CPU_SPC>;
  41                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  42                         clock-names = "cpu", "l2";
  43                         clock-latency = <100000>;
  44                         cooling-min-level = <0>;
  45                         cooling-max-level = <7>;
  46                         #cooling-cells = <2>;
  47                 };
  48
  49                 CPU1: cpu@1 {
  50                         compatible = "qcom,krait";
  51                         enable-method = "qcom,kpss-acc-v1";
  52                         device_type = "cpu";
  53                         reg = <1>;
  54                         next-level-cache = <&L2>;
  55                         qcom,acc = <&acc1>;
  56                         qcom,saw = <&saw1>;
  57                         cpu-idle-states = <&CPU_SPC>;
  58                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  59                         clock-names = "cpu", "l2";
  60                         clock-latency = <100000>;
  61                         cooling-min-level = <0>;
  62                         cooling-max-level = <7>;
  63                         #cooling-cells = <2>;
  64                 };
  65
  66                 CPU2: cpu@2 {
  67                         compatible = "qcom,krait";
  68                         enable-method = "qcom,kpss-acc-v1";
  69                         device_type = "cpu";
  70                         reg = <2>;
  71                         next-level-cache = <&L2>;
  72                         qcom,acc = <&acc2>;
  73                         qcom,saw = <&saw2>;
  74                         cpu-idle-states = <&CPU_SPC>;
  75                         clocks = <&kraitcc 2>, <&kraitcc 4>;
  76                         clock-names = "cpu", "l2";
  77                         clock-latency = <100000>;
  78                         cooling-min-level = <0>;
  79                         cooling-max-level = <7>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 CPU3: cpu@3 {
  84                         compatible = "qcom,krait";
  85                         enable-method = "qcom,kpss-acc-v1";
  86                         device_type = "cpu";
  87                         reg = <3>;
  88                         next-level-cache = <&L2>;
  89                         qcom,acc = <&acc3>;
  90                         qcom,saw = <&saw3>;
  91                         cpu-idle-states = <&CPU_SPC>;
  92                         clocks = <&kraitcc 3>, <&kraitcc 4>;
  93                         clock-names = "cpu", "l2";
  94                         clock-latency = <100000>;
  95                         cooling-min-level = <0>;
  96                         cooling-max-level = <7>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 L2: l2-cache {
 101                         compatible = "cache";
 102                         cache-level = <2>;
 103                 };
 104
 105                 qcom,l2 {
 106                         qcom,l2-rates = <384000000 972000000 1188000000>;
 107                 };
 108
 109                 idle-states {
 110                         CPU_SPC: spc {
 111                                 compatible = "qcom,idle-state-spc",
 112                                                 "arm,idle-state";
 113                                 entry-latency-us = <400>;
 114                                 exit-latency-us = <900>;
 115                                 min-residency-us = <3000>;
 116                         };
 117                 };
 118         };
 119
 120         thermal-zones {
 121                 cpu-thermal0 {
 122                         polling-delay-passive = <250>;
 123                         polling-delay = <1000>;
 124
 125                         thermal-sensors = <&gcc 7>;
 126
 127                         trips {
 128                                 cpu_alert0: trip@0 {
 129                                         temperature = <75000>;
 130                                         hysteresis = <2000>;
 131                                         type = "passive";
 132                                 };
 133                                 cpu_crit0: trip@1 {
 134                                         temperature = <110000>;
 135                                         hysteresis = <2000>;
 136                                         type = "critical";
 137                                 };
 138                         };
 139
 140                         cooling-maps {
 141                                 map0 {
 142                                         trip = <&cpu_alert0>;
 143                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146                 };
 147
 148                 cpu-thermal1 {
 149                         polling-delay-passive = <250>;
 150                         polling-delay = <1000>;
 151
 152                         thermal-sensors = <&gcc 8>;
 153
 154                         trips {
 155                                 cpu_alert1: trip@0 {
 156                                         temperature = <75000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160                                 cpu_crit1: trip@1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166
 167                         cooling-maps {
 168                                 map0 {
 169                                         trip = <&cpu_alert1>;
 170                                         cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 171                                 };
 172                         };
 173                 };
 174
 175                 cpu-thermal2 {
 176                         polling-delay-passive = <250>;
 177                         polling-delay = <1000>;
 178
 179                         thermal-sensors = <&gcc 9>;
 180
 181                         trips {
 182                                 cpu_alert2: trip@0 {
 183                                         temperature = <75000>;
 184                                         hysteresis = <2000>;
 185                                         type = "passive";
 186                                 };
 187                                 cpu_crit2: trip@1 {
 188                                         temperature = <110000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193
 194                         cooling-maps {
 195                                 map0 {
 196                                         trip = <&cpu_alert2>;
 197                                         cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 198                                 };
 199                         };
 200                 };
 201
 202                 cpu-thermal3 {
 203                         polling-delay-passive = <250>;
 204                         polling-delay = <1000>;
 205
 206                         thermal-sensors = <&gcc 10>;
 207
 208                         trips {
 209                                 cpu_alert3: trip@0 {
 210                                         temperature = <75000>;
 211                                         hysteresis = <2000>;
 212                                         type = "passive";
 213                                 };
 214                                 cpu_crit3: trip@1 {
 215                                         temperature = <110000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220
 221                         cooling-maps {
 222                                 map0 {
 223                                         trip = <&cpu_alert3>;
 224                                         cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 225                                 };
 226                         };
 227                 };
 228         };
 229
 230         cpu-pmu {
 231                 compatible = "qcom,krait-pmu";
 232                 interrupts = <1 10 0x304>;
 233         };
 234
 235         clocks {
 236                 cxo_board {
 237                         compatible = "fixed-clock";
 238                         #clock-cells = <0>;
 239                         clock-frequency = <19200000>;
 240                 };
 241
 242                 pxo_board {
 243                         compatible = "fixed-clock";
 244                         #clock-cells = <0>;
 245                         clock-frequency = <27000000>;
 246                 };
 247
 248                 sleep_clk {
 249                         compatible = "fixed-clock";
 250                         #clock-cells = <0>;
 251                         clock-frequency = <32768>;
 252                 };
 253         };
 254
 255         sfpb_mutex: hwmutex {
 256                 compatible = "qcom,sfpb-mutex";
 257                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 258                 #hwlock-cells = <1>;
 259         };
 260
 261         smem {
 262                 compatible = "qcom,smem";
 263                 memory-region = <&smem_region>;
 264
 265                 hwlocks = <&sfpb_mutex 3>;
 266         };
 267
 268         qcom,pvs {
 269                 qcom,pvs-format-a;
 270                 qcom,speed0-pvs0-bin-v0 =
 271                         < 384000000 950000  >,
 272                         < 486000000 975000  >,
 273                         < 594000000 1000000  >,
 274                         < 702000000 1025000  >,
 275                         < 810000000 1075000  >,
 276                         < 918000000 1100000  >,
 277                         < 1026000000 1125000 >,
 278                         < 1080000000 1175000 >,
 279                         < 1134000000 1175000 >,
 280                         < 1188000000 1200000 >,
 281                         < 1242000000 1200000 >,
 282                         < 1296000000 1225000 >,
 283                         < 1350000000 1225000 >,
 284                         < 1404000000 1237500 >,
 285                         < 1458000000 1237500 >,
 286                         < 1512000000 1250000 >;
 287
 288                 qcom,speed0-pvs1-bin-v0 =
 289                         < 384000000 900000  >,
 290                         < 486000000 925000  >,
 291                         < 594000000 950000  >,
 292                         < 702000000 975000  >,
 293                         < 810000000 1025000  >,
 294                         < 918000000 1050000  >,
 295                         < 1026000000 1075000 >,
 296                         < 1080000000 1125000 >,
 297                         < 1134000000 1125000 >,
 298                         < 1188000000 1150000 >,
 299                         < 1242000000 1150000 >,
 300                         < 1296000000 1175000 >,
 301                         < 1350000000 1175000 >,
 302                         < 1404000000 1187500 >,
 303                         < 1458000000 1187500 >,
 304                         < 1512000000 1200000 >;
 305
 306                 qcom,speed0-pvs3-bin-v0 =
 307                         < 384000000 850000  >,
 308                         < 486000000 875000  >,
 309                         < 594000000 900000  >,
 310                         < 702000000 925000  >,
 311                         < 810000000 975000  >,
 312                         < 918000000 1000000  >,
 313                         < 1026000000 1025000 >,
 314                         < 1080000000 1075000 >,
 315                         < 1134000000 1075000 >,
 316                         < 1188000000 1100000 >,
 317                         < 1242000000 1100000 >,
 318                         < 1296000000 1125000 >,
 319                         < 1350000000 1125000 >,
 320                         < 1404000000 1137500 >,
 321                         < 1458000000 1137500 >,
 322                         < 1512000000 1150000 >;
 323
 324                 qcom,speed0-pvs4-bin-v0 =
 325                         < 384000000 850000  >,
 326                         < 486000000 875000  >,
 327                         < 594000000 900000  >,
 328                         < 702000000 925000  >,
 329                         < 810000000 962500  >,
 330                         < 918000000 975000  >,
 331                         < 1026000000 1000000 >,
 332                         < 1080000000 1050000 >,
 333                         < 1134000000 1050000 >,
 334                         < 1188000000 1075000 >,
 335                         < 1242000000 1075000 >,
 336                         < 1296000000 1100000 >,
 337                         < 1350000000 1100000 >,
 338                         < 1404000000 1112500 >,
 339                         < 1458000000 1112500 >,
 340                         < 1512000000 1125000 >;
 341
 342                 qcom,speed1-pvs0-bin-v0 =
 343                         < 384000000 950000  >,
 344                         < 486000000 950000  >,
 345                         < 594000000 950000  >,
 346                         < 702000000 962500  >,
 347                         < 810000000 1000000  >,
 348                         < 918000000 1025000  >,
 349                         < 1026000000 1037500 >,
 350                         < 1134000000 1075000 >,
 351                         < 1242000000 1087500 >,
 352                         < 1350000000 1125000 >,
 353                         < 1458000000 1150000 >,
 354                         < 1566000000 1175000 >,
 355                         < 1674000000 1225000 >,
 356                         < 1728000000 1250000 >;
 357
 358                 qcom,speed1-pvs1-bin-v0 =
 359                         < 384000000 950000  >,
 360                         < 486000000 950000  >,
 361                         < 594000000 950000  >,
 362                         < 702000000 962500  >,
 363                         < 810000000 975000  >,
 364                         < 918000000 1000000 >,
 365                         < 1026000000 1012500 >,
 366                         < 1134000000 1037500 >,
 367                         < 1242000000 1050000 >,
 368                         < 1350000000 1087500 >,
 369                         < 1458000000 1112500 >,
 370                         < 1566000000 1150000 >,
 371                         < 1674000000 1187500 >,
 372                         < 1728000000 1200000 >;
 373
 374                 qcom,speed1-pvs2-bin-v0 =
 375                         < 384000000 925000  >,
 376                         < 486000000 925000  >,
 377                         < 594000000 925000  >,
 378                         < 702000000 925000  >,
 379                         < 810000000 937500  >,
 380                         < 918000000 950000  >,
 381                         < 1026000000 975000 >,
 382                         < 1134000000 1000000 >,
 383                         < 1242000000 1012500 >,
 384                         < 1350000000 1037500 >,
 385                         < 1458000000 1075000 >,
 386                         < 1566000000 1100000 >,
 387                         < 1674000000 1137500 >,
 388                         < 1728000000 1162500 >;
 389
 390                 qcom,speed1-pvs3-bin-v0 =
 391                         < 384000000 900000  >,
 392                         < 486000000 900000  >,
 393                         < 594000000 900000  >,
 394                         < 702000000 900000  >,
 395                         < 810000000 900000  >,
 396                         < 918000000 925000  >,
 397                         < 1026000000 950000 >,
 398                         < 1134000000 975000 >,
 399                         < 1242000000 987500 >,
 400                         < 1350000000 1000000 >,
 401                         < 1458000000 1037500 >,
 402                         < 1566000000 1062500 >,
 403                         < 1674000000 1100000 >,
 404                         < 1728000000 1125000 >;
 405
 406                 qcom,speed1-pvs4-bin-v0 =
 407                         < 384000000 875000  >,
 408                         < 486000000 875000  >,
 409                         < 594000000 875000  >,
 410                         < 702000000 875000  >,
 411                         < 810000000 887500  >,
 412                         < 918000000 900000  >,
 413                         < 1026000000 925000 >,
 414                         < 1134000000 950000 >,
 415                         < 1242000000 962500 >,
 416                         < 1350000000 975000 >,
 417                         < 1458000000 1000000 >,
 418                         < 1566000000 1037500 >,
 419                         < 1674000000 1075000 >,
 420                         < 1728000000 1100000 >;
 421
 422                 qcom,speed1-pvs5-bin-v0 =
 423                         < 384000000 875000  >,
 424                         < 486000000 875000  >,
 425                         < 594000000 875000  >,
 426                         < 702000000 875000  >,
 427                         < 810000000 887500  >,
 428                         < 918000000 900000  >,
 429                         < 1026000000 925000 >,
 430                         < 1134000000 937500 >,
 431                         < 1242000000 950000 >,
 432                         < 1350000000 962500 >,
 433                         < 1458000000 987500 >,
 434                         < 1566000000 1012500 >,
 435                         < 1674000000 1050000 >,
 436                         < 1728000000 1075000 >;
 437
 438                 qcom,speed1-pvs6-bin-v0 =
 439                         < 384000000 875000  >,
 440                         < 486000000 875000  >,
 441                         < 594000000 875000  >,
 442                         < 702000000 875000  >,
 443                         < 810000000 887500  >,
 444                         < 918000000 900000  >,
 445                         < 1026000000 925000 >,
 446                         < 1134000000 937500 >,
 447                         < 1242000000 950000 >,
 448                         < 1350000000 962500 >,
 449                         < 1458000000 975000 >,
 450                         < 1566000000 1000000 >,
 451                         < 1674000000 1025000 >,
 452                         < 1728000000 1050000 >;
 453
 454                 qcom,speed2-pvs0-bin-v0 =
 455                         < 384000000 950000  >,
 456                         < 486000000 950000  >,
 457                         < 594000000 950000  >,
 458                         < 702000000 950000  >,
 459                         < 810000000 962500  >,
 460                         < 918000000 975000  >,
 461                         < 1026000000 1000000 >,
 462                         < 1134000000 1025000 >,
 463                         < 1242000000 1037500 >,
 464                         < 1350000000 1062500 >,
 465                         < 1458000000 1100000 >,
 466                         < 1566000000 1125000 >,
 467                         < 1674000000 1175000 >,
 468                         < 1782000000 1225000 >,
 469                         < 1890000000 1287500 >;
 470
 471                 qcom,speed2-pvs1-bin-v0 =
 472                         < 384000000 925000  >,
 473                         < 486000000 925000  >,
 474                         < 594000000 925000  >,
 475                         < 702000000 925000  >,
 476                         < 810000000 937500  >,
 477                         < 918000000 950000  >,
 478                         < 1026000000 975000 >,
 479                         < 1134000000 1000000 >,
 480                         < 1242000000 1012500 >,
 481                         < 1350000000 1037500 >,
 482                         < 1458000000 1075000 >,
 483                         < 1566000000 1100000 >,
 484                         < 1674000000 1137500 >,
 485                         < 1782000000 1187500 >,
 486                         < 1890000000 1250000 >;
 487
 488                 qcom,speed2-pvs2-bin-v0 =
 489                         < 384000000 900000  >,
 490                         < 486000000 900000  >,
 491                         < 594000000 900000  >,
 492                         < 702000000 900000  >,
 493                         < 810000000 912500  >,
 494                         < 918000000 925000  >,
 495                         < 1026000000 950000 >,
 496                         < 1134000000 975000 >,
 497                         < 1242000000 987500 >,
 498                         < 1350000000 1012500 >,
 499                         < 1458000000 1050000 >,
 500                         < 1566000000 1075000 >,
 501                         < 1674000000 1112500 >,
 502                         < 1782000000 1162500 >,
 503                         < 1890000000 1212500 >;
 504
 505                 qcom,speed2-pvs3-bin-v0 =
 506                         < 384000000 900000  >,
 507                         < 486000000 900000  >,
 508                         < 594000000 900000  >,
 509                         < 702000000 900000  >,
 510                         < 810000000 900000  >,
 511                         < 918000000 912500  >,
 512                         < 1026000000 937500 >,
 513                         < 1134000000 962500 >,
 514                         < 1242000000 975000 >,
 515                         < 1350000000 1000000 >,
 516                         < 1458000000 1025000 >,
 517                         < 1566000000 1050000 >,
 518                         < 1674000000 1087500 >,
 519                         < 1782000000 1137500 >,
 520                         < 1890000000 1175000 >;
 521
 522                 qcom,speed2-pvs4-bin-v0 =
 523                         < 384000000 875000  >,
 524                         < 486000000 875000  >,
 525                         < 594000000 875000  >,
 526                         < 702000000 875000  >,
 527                         < 810000000 887500  >,
 528                         < 918000000 900000  >,
 529                         < 1026000000 925000 >,
 530                         < 1134000000 950000 >,
 531                         < 1242000000 962500 >,
 532                         < 1350000000 975000 >,
 533                         < 1458000000 1000000 >,
 534                         < 1566000000 1037500 >,
 535                         < 1674000000 1075000 >,
 536                         < 1782000000 1112500 >,
 537                         < 1890000000 1150000 >;
 538
 539                 qcom,speed2-pvs5-bin-v0 =
 540                         < 384000000 875000  >,
 541                         < 486000000 875000  >,
 542                         < 594000000 875000  >,
 543                         < 702000000 875000  >,
 544                         < 810000000 887500  >,
 545                         < 918000000 900000  >,
 546                         < 1026000000 925000 >,
 547                         < 1134000000 937500 >,
 548                         < 1242000000 950000 >,
 549                         < 1350000000 962500 >,
 550                         < 1458000000 987500 >,
 551                         < 1566000000 1012500 >,
 552                         < 1674000000 1050000 >,
 553                         < 1782000000 1087500 >,
 554                         < 1890000000 1125000 >;
 555
 556                 qcom,speed2-pvs6-bin-v0 =
 557                         < 384000000 875000  >,
 558                         < 486000000 875000  >,
 559                         < 594000000 875000  >,
 560                         < 702000000 875000  >,
 561                         < 810000000 887500  >,
 562                         < 918000000 900000  >,
 563                         < 1026000000 925000 >,
 564                         < 1134000000 937500 >,
 565                         < 1242000000 950000 >,
 566                         < 1350000000 962500 >,
 567                         < 1458000000 975000 >,
 568                         < 1566000000 1000000 >,
 569                         < 1674000000 1025000 >,
 570                         < 1782000000 1062500 >,
 571                         < 1890000000 1100000 >;
 572
 573                 qcom,speed14-pvs0-bin-v0 =
 574                         < 384000000 950000 >,
 575                         < 486000000 950000 >,
 576                         < 594000000 950000 >,
 577                         < 702000000 962500 >,
 578                         < 810000000 1000000 >,
 579                         < 918000000 1025000 >,
 580                         < 1026000000 1037500 >,
 581                         < 1134000000 1075000 >,
 582                         < 1242000000 1087500 >,
 583                         < 1350000000 1125000 >,
 584                         < 1458000000 1150000 >,
 585                         < 1512000000 1162500 >;
 586
 587                 qcom,speed14-pvs1-bin-v0 =
 588                         < 384000000 950000 >,
 589                         < 486000000 950000 >,
 590                         < 594000000 950000 >,
 591                         < 702000000 962500 >,
 592                         < 810000000 975000 >,
 593                         < 918000000 1000000 >,
 594                         < 1026000000 1012500 >,
 595                         < 1134000000 1037500 >,
 596                         < 1242000000 1050000 >,
 597                         < 1350000000 1087500 >,
 598                         < 1458000000 1112500 >,
 599                         < 1512000000 1125000 >;
 600
 601                 qcom,speed14-pvs2-bin-v0 =
 602                         < 384000000 925000 >,
 603                         < 486000000 925000 >,
 604                         < 594000000 925000 >,
 605                         < 702000000 925000 >,
 606                         < 810000000 937500 >,
 607                         < 918000000 950000 >,
 608                         < 1026000000 975000 >,
 609                         < 1134000000 1000000 >,
 610                         < 1242000000 1012500 >,
 611                         < 1350000000 1037500 >,
 612                         < 1458000000 1075000 >,
 613                         < 1512000000 1087500 >;
 614
 615                 qcom,speed14-pvs3-bin-v0 =
 616                         < 384000000 900000 >,
 617                         < 486000000 900000 >,
 618                         < 594000000 900000 >,
 619                         < 702000000 900000 >,
 620                         < 810000000 900000 >,
 621                         < 918000000 925000 >,
 622                         < 1026000000 950000 >,
 623                         < 1134000000 975000 >,
 624                         < 1242000000 987500 >,
 625                         < 1350000000 1000000 >,
 626                         < 1458000000 1037500 >,
 627                         < 1512000000 1050000 >;
 628
 629                 qcom,speed14-pvs4-bin-v0 =
 630                         < 384000000 875000 >,
 631                         < 486000000 875000 >,
 632                         < 594000000 875000 >,
 633                         < 702000000 875000 >,
 634                         < 810000000 887500 >,
 635                         < 918000000 900000 >,
 636                         < 1026000000 925000 >,
 637                         < 1134000000 950000 >,
 638                         < 1242000000 962500 >,
 639                         < 1350000000 975000 >,
 640                         < 1458000000 1000000 >,
 641                         < 1512000000 1012500 >;
 642
 643                 qcom,speed14-pvs5-bin-v0 =
 644                         < 384000000 875000 >,
 645                         < 486000000 875000 >,
 646                         < 594000000 875000 >,
 647                         < 702000000 875000 >,
 648                         < 810000000 887500 >,
 649                         < 918000000 900000 >,
 650                         < 1026000000 925000 >,
 651                         < 1134000000 937500 >,
 652                         < 1242000000 950000 >,
 653                         < 1350000000 962500 >,
 654                         < 1458000000 987500 >,
 655                         < 1512000000 1000000 >;
 656
 657                 qcom,speed14-pvs6-bin-v0 =
 658                         < 384000000 875000 >,
 659                         < 486000000 875000 >,
 660                         < 594000000 875000 >,
 661                         < 702000000 875000 >,
 662                         < 810000000 887500 >,
 663                         < 918000000 900000 >,
 664                         < 1026000000 925000 >,
 665                         < 1134000000 937500 >,
 666                         < 1242000000 950000 >,
 667                         < 1350000000 962500 >,
 668                         < 1458000000 975000 >,
 669                         < 1512000000 987500 >;
 670         };
 671
 672         kraitcc: clock-controller {
 673                 compatible = "qcom,krait-cc-v1";
 674                 #clock-cells = <1>;
 675         };
 676
 677         clocks {
 678                 sleep_clk: sleep_clk {
 679                         compatible = "fixed-clock";
 680                         clock-frequency = <32768>;
 681                         #clock-cells = <0>;
 682                 };
 683         };
 684
 685         clocks {
 686                 cxo_board {
 687                         compatible = "fixed-clock";
 688                         #clock-cells = <0>;
 689                         clock-frequency = <19200000>;
 690                 };
 691
 692                 pxo_board {
 693                         compatible = "fixed-clock";
 694                         #clock-cells = <0>;
 695                         clock-frequency = <27000000>;
 696                 };
 697
 698                 sleep_clk {
 699                         compatible = "fixed-clock";
 700                         #clock-cells = <0>;
 701                         clock-frequency = <32768>;
 702                 };
 703         };
 704
 705         firmware {
 706                 compatible = "simple-bus";
 707
 708                 scm {
 709                         compatible = "qcom,scm";
 710                 };
 711         };
 712
 713         smd {
 714                 compatible = "qcom,smd";
 715
 716                 modem@0 {
 717                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 718
 719                         qcom,ipc = <&l2cc 8 3>;
 720                         qcom,smd-edge = <0>;
 721
 722                         status = "disabled";
 723                 };
 724
 725                 q6@1 {
 726                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 727
 728                         qcom,ipc = <&l2cc 8 15>;
 729                         qcom,smd-edge = <1>;
 730
 731                         status = "disabled";
 732
 733                         apr {
 734                                 compatible = "qcom,apr";
 735                                 qcom,smd-channels = "apr_audio_svc";
 736                                 rproc = <&pil_q6v4>;
 737                         };
 738                 };
 739
 740                 dsps@3 {
 741                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 742
 743                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 744                         qcom,smd-edge = <3>;
 745
 746                         status = "disabled";
 747                 };
 748
 749                 riva@6 {
 750                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 751
 752                         qcom,ipc = <&l2cc 8 25>;
 753                         qcom,smd-edge = <6>;
 754
 755                         status = "disabled";
 756                 };
 757         };
 758
 759         smsm {
 760                 compatible = "qcom,smsm";
 761
 762                 #address-cells = <1>;
 763                 #size-cells = <0>;
 764
 765                 qcom,ipc-1 = <&l2cc 8 4>;
 766                 qcom,ipc-2 = <&l2cc 8 14>;
 767                 qcom,ipc-3 = <&l2cc 8 23>;
 768                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 769
 770                 apps_smsm: apps@0 {
 771                         reg = <0>;
 772                         #qcom,state-cells = <1>;
 773                 };
 774
 775                 modem_smsm: modem@1 {
 776                         reg = <1>;
 777                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <2>;
 781                 };
 782
 783                 q6_smsm: q6@2 {
 784                         reg = <2>;
 785                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 786
 787                         interrupt-controller;
 788                         #interrupt-cells = <2>;
 789                 };
 790
 791                 wcnss_smsm: wcnss@3 {
 792                         reg = <3>;
 793                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 794
 795                         interrupt-controller;
 796                         #interrupt-cells = <2>;
 797                 };
 798
 799                 dsps_smsm: dsps@4 {
 800                         reg = <4>;
 801                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 802
 803                         interrupt-controller;
 804                         #interrupt-cells = <2>;
 805                 };
 806         };
 807
 808         soc: soc {
 809                 #address-cells = <1>;
 810                 #size-cells = <1>;
 811                 ranges;
 812                 compatible = "simple-bus";
 813
 814                 tlmm_pinmux: pinctrl@800000 {
 815                         compatible = "qcom,apq8064-pinctrl";
 816                         reg = <0x800000 0x4000>;
 817
 818                         gpio-controller;
 819                         #gpio-cells = <2>;
 820                         interrupt-controller;
 821                         #interrupt-cells = <2>;
 822                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 823
 824                         pinctrl-names = "default";
 825                         pinctrl-0 = <&ps_hold>;
 826                 };
 827
 828                 sfpb_wrapper_mutex: syscon@1200000 {
 829                         compatible = "syscon";
 830                         reg = <0x01200000 0x8000>;
 831                 };
 832
 833                 intc: interrupt-controller@2000000 {
 834                         compatible = "qcom,msm-qgic2";
 835                         interrupt-controller;
 836                         #interrupt-cells = <3>;
 837                         reg = <0x02000000 0x1000>,
 838                               <0x02002000 0x1000>;
 839                 };
 840
 841                 timer@200a000 {
 842                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 843                         interrupts = <1 1 0x301>,
 844                                      <1 2 0x301>,
 845                                      <1 3 0x301>;
 846                         reg = <0x0200a000 0x100>;
 847                         clock-frequency = <27000000>,
 848                                           <32768>;
 849                         cpu-offset = <0x80000>;
 850                 };
 851
 852                 watchdog@208a038 {
 853                         compatible = "qcom,kpss-wdt-apq8064";
 854                         reg = <0x0208a038 0x40>;
 855                         clocks = <&sleep_clk>;
 856                         timeout-sec = <10>;
 857                 };
 858
 859                 acc0: clock-controller@2088000 {
 860                         compatible = "qcom,kpss-acc-v1";
 861                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 862                         clock-output-names = "acpu0_aux";
 863                 };
 864
 865                 acc1: clock-controller@2098000 {
 866                         compatible = "qcom,kpss-acc-v1";
 867                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 868                         clock-output-names = "acpu1_aux";
 869                 };
 870
 871                 acc2: clock-controller@20a8000 {
 872                         compatible = "qcom,kpss-acc-v1";
 873                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 874                         clock-output-names = "acpu2_aux";
 875                 };
 876
 877                 acc3: clock-controller@20b8000 {
 878                         compatible = "qcom,kpss-acc-v1";
 879                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 880                         clock-output-names = "acpu3_aux";
 881                 };
 882
 883                 saw0: power-controller@2089000 {
 884                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 885                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 886                         regulator;
 887                         regulator-name = "krait0";
 888                         regulator-always-on;
 889                         regulator-min-microvolt = <825000>;
 890                         regulator-max-microvolt = <1250000>;
 891                 };
 892
 893                 saw1: power-controller@2099000 {
 894                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 895                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 896                         regulator;
 897                         regulator-name = "krait1";
 898                         regulator-always-on;
 899                         regulator-min-microvolt = <825000>;
 900                         regulator-max-microvolt = <1250000>;
 901                 };
 902
 903                 saw2: power-controller@20a9000 {
 904                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 905                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 906                         regulator;
 907                         regulator-name = "krait2";
 908                         regulator-always-on;
 909                         regulator-min-microvolt = <825000>;
 910                         regulator-max-microvolt = <1250000>;
 911                 };
 912
 913                 saw3: power-controller@20b9000 {
 914                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 915                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 916                         regulator;
 917                         regulator-name = "krait3";
 918                         regulator-always-on;
 919                         regulator-min-microvolt = <825000>;
 920                         regulator-max-microvolt = <1250000>;
 921                 };
 922
 923                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 924                         compatible      = "syscon";
 925                         reg             = <0x12100000 0x10000>;
 926                 };
 927
 928                 gsbi1: gsbi@12440000 {
 929                         status = "disabled";
 930                         compatible = "qcom,gsbi-v1.0.0";
 931                         cell-index = <1>;
 932                         reg = <0x12440000 0x100>;
 933                         clocks = <&gcc GSBI1_H_CLK>;
 934                         clock-names = "iface";
 935                         #address-cells = <1>;
 936                         #size-cells = <1>;
 937                         ranges;
 938
 939                         syscon-tcsr = <&tcsr>;
 940
 941                         gsbi1_serial: serial@12450000 {
 942                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 943                                 reg = <0x12450000 0x100>,
 944                                       <0x12400000 0x03>;
 945                                 interrupts = <0 193 0x0>;
 946                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 947                                 clock-names = "core", "iface";
 948                                 status = "disabled";
 949                         };
 950
 951                         gsbi1_i2c: i2c@12460000 {
 952                                 compatible = "qcom,i2c-qup-v1.1.1";
 953                                 pinctrl-0 = <&i2c1_pins>;
 954                                 pinctrl-1 = <&i2c1_pins_sleep>;
 955                                 pinctrl-names = "default", "sleep";
 956                                 reg = <0x12460000 0x1000>;
 957                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 958                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 959                                 clock-names = "core", "iface";
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                         };
 963
 964                 };
 965
 966                 gsbi2: gsbi@12480000 {
 967                         status = "disabled";
 968                         compatible = "qcom,gsbi-v1.0.0";
 969                         cell-index = <2>;
 970                         reg = <0x12480000 0x100>;
 971                         clocks = <&gcc GSBI2_H_CLK>;
 972                         clock-names = "iface";
 973                         #address-cells = <1>;
 974                         #size-cells = <1>;
 975                         ranges;
 976
 977                         syscon-tcsr = <&tcsr>;
 978
 979                         gsbi2_i2c: i2c@124a0000 {
 980                                 compatible = "qcom,i2c-qup-v1.1.1";
 981                                 reg = <0x124a0000 0x1000>;
 982                                 pinctrl-0 = <&i2c2_pins>;
 983                                 pinctrl-1 = <&i2c2_pins_sleep>;
 984                                 pinctrl-names = "default", "sleep";
 985                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 986                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 987                                 clock-names = "core", "iface";
 988                                 #address-cells = <1>;
 989                                 #size-cells = <0>;
 990                         };
 991                 };
 992
 993                 gsbi3: gsbi@16200000 {
 994                         status = "disabled";
 995                         compatible = "qcom,gsbi-v1.0.0";
 996                         cell-index = <3>;
 997                         reg = <0x16200000 0x100>;
 998                         clocks = <&gcc GSBI3_H_CLK>;
 999                         clock-names = "iface";
1000                         #address-cells = <1>;
1001                         #size-cells = <1>;
1002                         ranges;
1003                         gsbi3_i2c: i2c@16280000 {
1004                                 compatible = "qcom,i2c-qup-v1.1.1";
1005                                 pinctrl-0 = <&i2c3_pins>;
1006                                 pinctrl-1 = <&i2c3_pins_sleep>;
1007                                 pinctrl-names = "default", "sleep";
1008                                 reg = <0x16280000 0x1000>;
1009                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
1010                                 clocks = <&gcc GSBI3_QUP_CLK>,
1011                                          <&gcc GSBI3_H_CLK>;
1012                                 clock-names = "core", "iface";
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                         };
1016                 };
1017
1018                 gsbi4: gsbi@16300000 {
1019                         status = "disabled";
1020                         compatible = "qcom,gsbi-v1.0.0";
1021                         cell-index = <4>;
1022                         reg = <0x16300000 0x03>;
1023                         clocks = <&gcc GSBI4_H_CLK>;
1024                         clock-names = "iface";
1025                         #address-cells = <1>;
1026                         #size-cells = <1>;
1027                         ranges;
1028
1029                         gsbi4_i2c: i2c@16380000 {
1030                                 compatible = "qcom,i2c-qup-v1.1.1";
1031                                 pinctrl-0 = <&i2c4_pins>;
1032                                 pinctrl-1 = <&i2c4_pins_sleep>;
1033                                 pinctrl-names = "default", "sleep";
1034                                 reg = <0x16380000 0x1000>;
1035                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
1036                                 clocks = <&gcc GSBI4_QUP_CLK>,
1037                                          <&gcc GSBI4_H_CLK>;
1038                                 clock-names = "core", "iface";
1039                         };
1040                 };
1041
1042                 gsbi5: gsbi@1a200000 {
1043                         status = "disabled";
1044                         compatible = "qcom,gsbi-v1.0.0";
1045                         cell-index = <5>;
1046                         reg = <0x1a200000 0x03>;
1047                         clocks = <&gcc GSBI5_H_CLK>;
1048                         clock-names = "iface";
1049                         #address-cells = <1>;
1050                         #size-cells = <1>;
1051                         ranges;
1052
1053                         gsbi5_serial: serial@1a240000 {
1054                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1055                                 reg = <0x1a240000 0x100>,
1056                                       <0x1a200000 0x03>;
1057                                 interrupts = <0 154 0x0>;
1058                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1059                                 clock-names = "core", "iface";
1060                                 status = "disabled";
1061                         };
1062
1063                         gsbi5_spi: spi@1a280000 {
1064                                 compatible = "qcom,spi-qup-v1.1.1";
1065                                 reg = <0x1a280000 0x1000>;
1066                                 interrupts = <0 155 0>;
1067                                 pinctrl-0 = <&spi5_default>;
1068                                 pinctrl-1 = <&spi5_sleep>;
1069                                 pinctrl-names = "default", "sleep";
1070                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1071                                 clock-names = "core", "iface";
1072                                 status = "disabled";
1073                                 #address-cells = <1>;
1074                                 #size-cells = <0>;
1075                         };
1076                 };
1077
1078                 gsbi6: gsbi@16500000 {
1079                         status = "disabled";
1080                         compatible = "qcom,gsbi-v1.0.0";
1081                         cell-index = <6>;
1082                         reg = <0x16500000 0x03>;
1083                         clocks = <&gcc GSBI6_H_CLK>;
1084                         clock-names = "iface";
1085                         #address-cells = <1>;
1086                         #size-cells = <1>;
1087                         ranges;
1088                         syscon-tcsr = <&tcsr>;
1089
1090                         gsbi6_serial: serial@16540000 {
1091                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1092                                 reg = <0x16540000 0x100>,
1093                                       <0x16500000 0x03>;
1094                                 interrupts = <0 156 0x0>;
1095                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1096                                 clock-names = "core", "iface";
1097
1098                                 qcom,rx-crci = <11>;
1099                                 qcom,tx-crci = <6>;
1100
1101                                 dmas = <&adm 6>, <&adm 7>;
1102                                 dma-names = "rx", "tx";
1103
1104                                 status = "disabled";
1105                         };
1106
1107                         gsbi6_i2c: i2c@16580000 {
1108                                 compatible = "qcom,i2c-qup-v1.1.1";
1109                                 pinctrl-0 = <&i2c6_pins>;
1110                                 pinctrl-1 = <&i2c6_pins_sleep>;
1111                                 pinctrl-names = "default", "sleep";
1112                                 reg = <0x16580000 0x1000>;
1113                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
1114                                 clocks = <&gcc GSBI6_QUP_CLK>,
1115                                          <&gcc GSBI6_H_CLK>;
1116                                 clock-names = "core", "iface";
1117                         };
1118                 };
1119
1120                 gsbi7: gsbi@16600000 {
1121                         status = "disabled";
1122                         compatible = "qcom,gsbi-v1.0.0";
1123                         cell-index = <7>;
1124                         reg = <0x16600000 0x100>;
1125                         clocks = <&gcc GSBI7_H_CLK>;
1126                         clock-names = "iface";
1127                         #address-cells = <1>;
1128                         #size-cells = <1>;
1129                         ranges;
1130                         syscon-tcsr = <&tcsr>;
1131
1132                         gsbi7_serial: serial@16640000 {
1133                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1134                                 reg = <0x16640000 0x1000>,
1135                                       <0x16600000 0x1000>;
1136                                 interrupts = <0 158 0x0>;
1137                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1138                                 clock-names = "core", "iface";
1139                                 status = "disabled";
1140                         };
1141
1142                         gsbi7_i2c: i2c@16680000 {
1143                                 compatible = "qcom,i2c-qup-v1.1.1";
1144                                 pinctrl-0 = <&i2c7_pins>;
1145                                 pinctrl-1 = <&i2c7_pins_sleep>;
1146                                 pinctrl-names = "default", "sleep";
1147                                 reg = <0x16680000 0x1000>;
1148                                 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
1149                                 clocks = <&gcc GSBI7_QUP_CLK>,
1150                                          <&gcc GSBI7_H_CLK>;
1151                                 clock-names = "core", "iface";
1152                                 status = "disabled";
1153                         };
1154                 };
1155
1156                 rng@1a500000 {
1157                         compatible = "qcom,prng";
1158                         reg = <0x1a500000 0x200>;
1159                         clocks = <&gcc PRNG_CLK>;
1160                         clock-names = "core";
1161                 };
1162
1163                 qcom,ssbi@500000 {
1164                         compatible = "qcom,ssbi";
1165                         reg = <0x00500000 0x1000>;
1166                         qcom,controller-type = "pmic-arbiter";
1167
1168                         pmicintc: pmic@0 {
1169                                 compatible = "qcom,pm8921";
1170                                 interrupt-parent = <&tlmm_pinmux>;
1171                                 interrupts = <74 8>;
1172                                 #interrupt-cells = <2>;
1173                                 interrupt-controller;
1174                                 #address-cells = <1>;
1175                                 #size-cells = <0>;
1176
1177                                 pm8921_gpio: gpio@150 {
1178
1179                                         compatible = "qcom,pm8921-gpio",
1180                                                      "qcom,ssbi-gpio";
1181                                         reg = <0x150>;
1182                                         interrupts = <192 1>, <193 1>, <194 1>,
1183                                                      <195 1>, <196 1>, <197 1>,
1184                                                      <198 1>, <199 1>, <200 1>,
1185                                                      <201 1>, <202 1>, <203 1>,
1186                                                      <204 1>, <205 1>, <206 1>,
1187                                                      <207 1>, <208 1>, <209 1>,
1188                                                      <210 1>, <211 1>, <212 1>,
1189                                                      <213 1>, <214 1>, <215 1>,
1190                                                      <216 1>, <217 1>, <218 1>,
1191                                                      <219 1>, <220 1>, <221 1>,
1192                                                      <222 1>, <223 1>, <224 1>,
1193                                                      <225 1>, <226 1>, <227 1>,
1194                                                      <228 1>, <229 1>, <230 1>,
1195                                                      <231 1>, <232 1>, <233 1>,
1196                                                      <234 1>, <235 1>;
1197
1198                                         gpio-controller;
1199                                         #gpio-cells = <2>;
1200
1201                                 };
1202
1203                                 pm8921_mpps: mpps@50 {
1204                                         compatible = "qcom,pm8921-mpp",
1205                                                      "qcom,ssbi-mpp";
1206                                         reg = <0x50>;
1207                                         gpio-controller;
1208                                         #gpio-cells = <2>;
1209                                         interrupts =
1210                                         <128 1>, <129 1>, <130 1>, <131 1>,
1211                                         <132 1>, <133 1>, <134 1>, <135 1>,
1212                                         <136 1>, <137 1>, <138 1>, <139 1>;
1213                                 };
1214
1215                                 rtc@11d {
1216                                         compatible = "qcom,pm8921-rtc";
1217                                         interrupt-parent = <&pmicintc>;
1218                                         interrupts = <39 1>;
1219                                         reg = <0x11d>;
1220                                         allow-set-time;
1221                                 };
1222
1223                                 pwrkey@1c {
1224                                         compatible = "qcom,pm8921-pwrkey";
1225                                         reg = <0x1c>;
1226                                         interrupt-parent = <&pmicintc>;
1227                                         interrupts = <50 1>, <51 1>;
1228                                         debounce = <15625>;
1229                                         pull-up;
1230                                 };
1231                         };
1232                 };
1233
1234                 qfprom: qfprom@00700000 {
1235                         compatible      = "qcom,qfprom";
1236                         reg             = <0x00700000 0x1000>;
1237                         #address-cells  = <1>;
1238                         #size-cells     = <1>;
1239                         ranges;
1240                         tsens_calib: calib {
1241                                 reg = <0x404 0x10>;
1242                         };
1243                         tsens_backup: backup_calib {
1244                                 reg = <0x414 0x10>;
1245                         };
1246                 };
1247
1248                 gcc: clock-controller@900000 {
1249                         compatible = "qcom,gcc-apq8064";
1250                         reg = <0x00900000 0x4000>;
1251                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1252                         nvmem-cell-names = "calib", "calib_backup";
1253                         qcom,tsens-slopes = <1176 1176 1154 1176 1111
1254                                 1132 1132 1199 1132 1199 1132>;
1255                         #clock-cells = <1>;
1256                         #reset-cells = <1>;
1257                         #thermal-sensor-cells = <1>;
1258                 };
1259
1260                 lcc: clock-controller@28000000 {
1261                         compatible = "qcom,lcc-apq8064";
1262                         reg = <0x28000000 0x1000>;
1263                         #clock-cells = <1>;
1264                         #reset-cells = <1>;
1265                 };
1266
1267                 mmcc: clock-controller@4000000 {
1268                         compatible = "qcom,mmcc-apq8064";
1269                         reg = <0x4000000 0x1000>;
1270                         #clock-cells = <1>;
1271                         #reset-cells = <1>;
1272                 };
1273
1274                 l2cc: clock-controller@2011000 {
1275                         compatible      = "syscon";
1276                         reg             = <0x2011000 0x1000>;
1277                 };
1278
1279                 rpm@108000 {
1280                         compatible      = "qcom,rpm-apq8064";
1281                         reg             = <0x108000 0x1000>;
1282                         qcom,ipc        = <&l2cc 0x8 2>;
1283
1284                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1285                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1286                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1287                         interrupt-names = "ack", "err", "wakeup";
1288
1289                         rpmcc: clock-controller {
1290                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1291                                 #clock-cells = <1>;
1292                         };
1293
1294                         regulators {
1295                                 compatible = "qcom,rpm-pm8921-regulators";
1296
1297                                 pm8921_s1: s1 {};
1298                                 pm8921_s2: s2 {};
1299                                 pm8921_s3: s3 {};
1300                                 pm8921_s4: s4 {};
1301                                 pm8921_s7: s7 {};
1302                                 pm8921_s8: s8 {};
1303
1304                                 pm8921_l1: l1 {};
1305                                 pm8921_l2: l2 {};
1306                                 pm8921_l3: l3 {};
1307                                 pm8921_l4: l4 {};
1308                                 pm8921_l5: l5 {};
1309                                 pm8921_l6: l6 {};
1310                                 pm8921_l7: l7 {};
1311                                 pm8921_l8: l8 {};
1312                                 pm8921_l9: l9 {};
1313                                 pm8921_l10: l10 {};
1314                                 pm8921_l11: l11 {};
1315                                 pm8921_l12: l12 {};
1316                                 pm8921_l14: l14 {};
1317                                 pm8921_l15: l15 {};
1318                                 pm8921_l16: l16 {};
1319                                 pm8921_l17: l17 {};
1320                                 pm8921_l18: l18 {};
1321                                 pm8921_l21: l21 {};
1322                                 pm8921_l22: l22 {};
1323                                 pm8921_l23: l23 {};
1324                                 pm8921_l24: l24 {};
1325                                 pm8921_l25: l25 {};
1326                                 pm8921_l26: l26 {};
1327                                 pm8921_l27: l27 {};
1328                                 pm8921_l28: l28 {};
1329                                 pm8921_l29: l29 {};
1330
1331                                 pm8921_lvs1: lvs1 {};
1332                                 pm8921_lvs2: lvs2 {};
1333                                 pm8921_lvs3: lvs3 {};
1334                                 pm8921_lvs4: lvs4 {};
1335                                 pm8921_lvs5: lvs5 {};
1336                                 pm8921_lvs6: lvs6 {};
1337                                 pm8921_lvs7: lvs7 {};
1338
1339                                 pm8921_usb_switch: usb-switch {};
1340
1341                                 pm8921_hdmi_switch: hdmi-switch {
1342                                         bias-pull-down;
1343                                 };
1344
1345                                 pm8921_ncp: ncp {};
1346                         };
1347                 };
1348
1349                 usb1_phy: phy@12500000 {
1350                         compatible      = "qcom,usb-otg-ci";
1351                         reg             = <0x12500000 0x400>;
1352                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1353                         status          = "disabled";
1354                         dr_mode         = "host";
1355
1356                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
1357                                           <&gcc USB_HS1_H_CLK>;
1358                         clock-names     = "core", "iface";
1359
1360                         resets          = <&gcc USB_HS1_RESET>;
1361                         reset-names     = "link";
1362                 };
1363
1364                 usb3_phy: phy@12520000 {
1365                         compatible      = "qcom,usb-otg-ci";
1366                         reg             = <0x12520000 0x400>;
1367                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1368                         status          = "disabled";
1369                         dr_mode         = "host";
1370
1371                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
1372                                           <&gcc USB_HS3_H_CLK>;
1373                         clock-names     = "core", "iface";
1374
1375                         resets          = <&gcc USB_HS3_RESET>;
1376                         reset-names     = "link";
1377                 };
1378
1379                 usb4_phy: phy@12530000 {
1380                         compatible      = "qcom,usb-otg-ci";
1381                         reg             = <0x12530000 0x400>;
1382                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1383                         status          = "disabled";
1384                         dr_mode         = "host";
1385
1386                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
1387                                           <&gcc USB_HS4_H_CLK>;
1388                         clock-names     = "core", "iface";
1389
1390                         resets          = <&gcc USB_HS4_RESET>;
1391                         reset-names     = "link";
1392                 };
1393
1394                 gadget1: gadget@12500000 {
1395                         compatible      = "qcom,ci-hdrc";
1396                         reg             = <0x12500000 0x400>;
1397                         status          = "disabled";
1398                         dr_mode         = "peripheral";
1399                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1400                         usb-phy         = <&usb1_phy>;
1401                 };
1402
1403                 usb1: usb@12500000 {
1404                         compatible      = "qcom,ehci-host";
1405                         reg             = <0x12500000 0x400>;
1406                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1407                         status          = "disabled";
1408                         usb-phy         = <&usb1_phy>;
1409                 };
1410
1411                 usb3: usb@12520000 {
1412                         compatible      = "qcom,ehci-host";
1413                         reg             = <0x12520000 0x400>;
1414                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1415                         status          = "disabled";
1416                         usb-phy         = <&usb3_phy>;
1417                 };
1418
1419                 usb4: usb@12530000 {
1420                         compatible      = "qcom,ehci-host";
1421                         reg             = <0x12530000 0x400>;
1422                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1423                         status          = "disabled";
1424                         usb-phy         = <&usb4_phy>;
1425                 };
1426
1427                 sata_phy0: phy@1b400000 {
1428                         compatible      = "qcom,apq8064-sata-phy";
1429                         status          = "disabled";
1430                         reg             = <0x1b400000 0x200>;
1431                         reg-names       = "phy_mem";
1432                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
1433                         clock-names     = "cfg";
1434                         #phy-cells      = <0>;
1435                 };
1436
1437                 sata0: sata@29000000 {
1438                         compatible              = "qcom,apq8064-ahci", "generic-ahci";
1439                         status                  = "disabled";
1440                         reg                     = <0x29000000 0x180>;
1441                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
1442
1443                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
1444                                                 <&gcc SATA_H_CLK>,
1445                                                 <&gcc SATA_A_CLK>,
1446                                                 <&gcc SATA_RXOOB_CLK>,
1447                                                 <&gcc SATA_PMALIVE_CLK>;
1448                         clock-names             = "slave_iface",
1449                                                 "iface",
1450                                                 "bus",
1451                                                 "rxoob",
1452                                                 "core_pmalive";
1453
1454                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
1455                                                 <&gcc SATA_PMALIVE_CLK>;
1456                         assigned-clock-rates    = <100000000>, <100000000>;
1457
1458                         phys                    = <&sata_phy0>;
1459                         phy-names               = "sata-phy";
1460                         ports-implemented       = <0x1>;
1461                 };
1462
1463                 /* Temporary fixed regulator */
1464                 sdcc1bam:dma@12402000{
1465                         compatible = "qcom,bam-v1.3.0";
1466                         reg = <0x12402000 0x8000>;
1467                         interrupts = <0 98 0>;
1468                         clocks = <&gcc SDC1_H_CLK>;
1469                         clock-names = "bam_clk";
1470                         #dma-cells = <1>;
1471                         qcom,ee = <0>;
1472                 };
1473
1474                 sdcc3bam:dma@12182000{
1475                         compatible = "qcom,bam-v1.3.0";
1476                         reg = <0x12182000 0x8000>;
1477                         interrupts = <0 96 0>;
1478                         clocks = <&gcc SDC3_H_CLK>;
1479                         clock-names = "bam_clk";
1480                         #dma-cells = <1>;
1481                         qcom,ee = <0>;
1482                 };
1483
1484                 sdcc4bam:dma@121c2000{
1485                         compatible = "qcom,bam-v1.3.0";
1486                         reg = <0x121c2000 0x8000>;
1487                         interrupts = <0 95 0>;
1488                         clocks = <&gcc SDC4_H_CLK>;
1489                         clock-names = "bam_clk";
1490                         #dma-cells = <1>;
1491                         qcom,ee = <0>;
1492                 };
1493
1494                 amba {
1495                         compatible = "arm,amba-bus";
1496                         #address-cells = <1>;
1497                         #size-cells = <1>;
1498                         ranges;
1499                         sdcc1: sdcc@12400000 {
1500                                 status          = "disabled";
1501                                 compatible      = "arm,pl18x", "arm,primecell";
1502                                 arm,primecell-periphid = <0x00051180>;
1503                                 reg             = <0x12400000 0x2000>;
1504                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1505                                 interrupt-names = "cmd_irq";
1506                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1507                                 clock-names     = "mclk", "apb_pclk";
1508                                 bus-width       = <8>;
1509                                 max-frequency   = <96000000>;
1510                                 non-removable;
1511                                 cap-sd-highspeed;
1512                                 cap-mmc-highspeed;
1513                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1514                                 dma-names = "tx", "rx";
1515                         };
1516
1517                         sdcc3: sdcc@12180000 {
1518                                 compatible      = "arm,pl18x", "arm,primecell";
1519                                 arm,primecell-periphid = <0x00051180>;
1520                                 status          = "disabled";
1521                                 reg             = <0x12180000 0x2000>;
1522                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1523                                 interrupt-names = "cmd_irq";
1524                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1525                                 clock-names     = "mclk", "apb_pclk";
1526                                 bus-width       = <4>;
1527                                 cap-sd-highspeed;
1528                                 cap-mmc-highspeed;
1529                                 max-frequency   = <192000000>;
1530                                 no-1-8-v;
1531                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1532                                 dma-names = "tx", "rx";
1533                         };
1534
1535                         sdcc4: sdcc@121c0000 {
1536                                 compatible      = "arm,pl18x", "arm,primecell";
1537                                 arm,primecell-periphid = <0x00051180>;
1538                                 status          = "disabled";
1539                                 reg             = <0x121c0000 0x2000>;
1540                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1541                                 interrupt-names = "cmd_irq";
1542                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1543                                 clock-names     = "mclk", "apb_pclk";
1544                                 bus-width       = <4>;
1545                                 cap-sd-highspeed;
1546                                 cap-mmc-highspeed;
1547                                 max-frequency   = <48000000>;
1548                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1549                                 dma-names = "tx", "rx";
1550                                 pinctrl-names = "default";
1551                                 pinctrl-0 = <&sdc4_gpios>;
1552                         };
1553                 };
1554
1555                 adm: dma@18320000 {
1556                         compatible = "qcom,adm";
1557                         reg = <0x18320000 0xE0000>;
1558                         interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1559                         #dma-cells = <1>;
1560
1561                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1562                         clock-names = "core", "iface";
1563
1564                         resets = <&gcc ADM0_RESET>,
1565                                  <&gcc ADM0_PBUS_RESET>,
1566                                  <&gcc ADM0_C0_RESET>,
1567                                  <&gcc ADM0_C1_RESET>,
1568                                  <&gcc ADM0_C2_RESET>;
1569                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1570                         qcom,ee = <1>;
1571
1572                         status = "disabled";
1573                 };
1574
1575                 tcsr: syscon@1a400000 {
1576                         compatible = "qcom,tcsr-apq8064", "syscon";
1577                         reg = <0x1a400000 0x100>;
1578                 };
1579
1580                 pcie: pci@1b500000 {
1581                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1582                         reg = <0x1b500000 0x1000
1583                                0x1b502000 0x80
1584                                0x1b600000 0x100
1585                                0x0ff00000 0x100000>;
1586                         reg-names = "dbi", "elbi", "parf", "config";
1587                         device_type = "pci";
1588                         linux,pci-domain = <0>;
1589                         bus-range = <0x00 0xff>;
1590                         num-lanes = <1>;
1591                         #address-cells = <3>;
1592                         #size-cells = <2>;
1593                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1594                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1595                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1596                         interrupt-names = "msi";
1597                         #interrupt-cells = <1>;
1598                         interrupt-map-mask = <0 0 0 0x7>;
1599                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1600                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1601                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1602                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1603                         clocks = <&gcc PCIE_A_CLK>,
1604                                  <&gcc PCIE_H_CLK>,
1605                                  <&gcc PCIE_PHY_REF_CLK>;
1606                         clock-names = "core", "iface", "phy";
1607                         resets = <&gcc PCIE_ACLK_RESET>,
1608                                  <&gcc PCIE_HCLK_RESET>,
1609                                  <&gcc PCIE_POR_RESET>,
1610                                  <&gcc PCIE_PCI_RESET>,
1611                                  <&gcc PCIE_PHY_RESET>;
1612                         reset-names = "axi", "ahb", "por", "pci", "phy";
1613                         status = "disabled";
1614                 };
1615
1616                 pil_q6v4: pil@28800000 {
1617                         compatible      = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1618                         qcom,firmware-name = "q6";
1619                         reg             = <0x28800000 0x100>;
1620                         reg-names       = "qdsp6_base";
1621                         qcom,pas-id             = <1>; /* PAS_Q6 */
1622                 };
1623
1624                 dai_fe: dai_fe {
1625                         compatible      = "qcom,msm-dai-fe";
1626                         #sound-dai-cells = <0>;
1627                 };
1628
1629                 hdmi_dai: dai_hdmi {
1630                         compatible = "qcom,msm-dai-q6-hdmi";
1631                         #sound-dai-cells = <0>;
1632                 };
1633
1634                 hdmi_codec: codec_hdmi {
1635                         compatible = "linux,hdmi-audio";
1636                         #sound-dai-cells = <0>;
1637                 };
1638
1639                 q6_pcm: msm_pcm {
1640                         compatible = "qcom,msm-pcm-dsp";
1641                         #sound-dai-cells = <0>;
1642                 };
1643
1644                 q6_route: msm_pcm_routing {
1645                         compatible = "qcom,msm-pcm-routing";
1646                         #sound-dai-cells = <0>;
1647                 };
1648
1649                 snd {
1650                         compatible      = "qcom,snd-apq8064";
1651                 };
1652
1653
1654                 hdmi: qcom,hdmi-tx@4a00000 {
1655                         compatible = "qcom,hdmi-tx-8960";
1656                         reg-names = "core_physical";
1657                         reg = <0x04a00000 0x1000>;
1658                         interrupts = <GIC_SPI 79 0>;
1659                         clock-names =
1660                             "core_clk",
1661                             "master_iface_clk",
1662                             "slave_iface_clk";
1663                         clocks =
1664                             <&mmcc HDMI_APP_CLK>,
1665                             <&mmcc HDMI_M_AHB_CLK>,
1666                             <&mmcc HDMI_S_AHB_CLK>;
1667                         qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1668                         qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1669                         qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1670                         pinctrl-names = "default";
1671                         pinctrl-0 = <&hdmi_pinctrl>;
1672                 };
1673
1674                 gpu: qcom,adreno-3xx@4300000 {
1675                         compatible = "qcom,adreno-3xx";
1676                         reg = <0x04300000 0x20000>;
1677                         reg-names = "kgsl_3d0_reg_memory";
1678                         interrupts = <GIC_SPI 80 0>;
1679                         interrupt-names = "kgsl_3d0_irq";
1680                         clock-names =
1681                             "core_clk",
1682                             "iface_clk",
1683                             "mem_clk",
1684                             "mem_iface_clk";
1685                         clocks =
1686                             <&mmcc GFX3D_CLK>,
1687                             <&mmcc GFX3D_AHB_CLK>,
1688                             <&mmcc GFX3D_AXI_CLK>,
1689                             <&mmcc MMSS_IMEM_AHB_CLK>;
1690                         qcom,chipid = <0x03020002>;
1691
1692                          iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1693                                    &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1694                                    &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1695                                    &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1696
1697                         qcom,gpu-pwrlevels {
1698                                 compatible = "qcom,gpu-pwrlevels";
1699                                 qcom,gpu-pwrlevel@0 {
1700                                         qcom,gpu-freq = <450000000>;
1701                                 };
1702                                 qcom,gpu-pwrlevel@1 {
1703                                         qcom,gpu-freq = <27000000>;
1704                                 };
1705                         };
1706                 };
1707
1708                 mdp: qcom,mdp@5100000 {
1709                         compatible = "qcom,mdp";
1710                         reg = <0x05100000 0xf0000>;
1711                         interrupts = <GIC_SPI 75 0>;
1712                         connectors = <&hdmi>;
1713                         gpus = <&gpu>;
1714                         clock-names =
1715                             "core_clk",
1716                             "iface_clk",
1717                             "lut_clk",
1718                             "src_clk",
1719                             "hdmi_clk",
1720                             "mdp_clk",
1721                             "mdp_axi_clk";
1722                         clocks =
1723                             <&mmcc MDP_CLK>,
1724                             <&mmcc MDP_AHB_CLK>,
1725                             <&mmcc MDP_LUT_CLK>,
1726                             <&mmcc TV_SRC>,
1727                             <&mmcc HDMI_TV_CLK>,
1728                             <&mmcc MDP_TV_CLK>,
1729                             <&mmcc MDP_AXI_CLK>;
1730
1731                         iommus = <&mdp_port0 0 2
1732                                   &mdp_port1 0 2>;
1733                 };
1734
1735                 mdp_port0: qcom,iommu@7500000 {
1736                         compatible = "qcom,iommu-v0";
1737                         #iommu-cells = <2>;
1738                         clock-names =
1739                             "smmu_pclk",
1740                             "iommu_clk";
1741                         clocks =
1742                             <&mmcc SMMU_AHB_CLK>,
1743                             <&mmcc MDP_AXI_CLK>;
1744                         reg = <0x07500000 0x100000>;
1745                         interrupts =
1746                             <GIC_SPI 63 0>,
1747                             <GIC_SPI 64 0>;
1748                         ncb = <2>;
1749                 };
1750
1751                 mdp_port1: qcom,iommu@7600000 {
1752                         compatible = "qcom,iommu";
1753                         #iommu-cells = <2>;
1754                         clock-names =
1755                             "smmu_pclk",
1756                             "iommu_clk";
1757                         clocks =
1758                             <&mmcc SMMU_AHB_CLK>,
1759                             <&mmcc MDP_AXI_CLK>;
1760                         reg = <0x07600000 0x100000>;
1761                         interrupts =
1762                             <GIC_SPI 61 0>,
1763                             <GIC_SPI 62 0>;
1764                         ncb = <2>;
1765                 };
1766
1767                 gfx3d: qcom,iommu@7c00000 {
1768                         compatible = "qcom,iommu-v0";
1769                         #iommu-cells = <16>;
1770                         clock-names =
1771                             "smmu_pclk",
1772                             "iommu_clk";
1773                         clocks =
1774                             <&mmcc SMMU_AHB_CLK>,
1775                             <&mmcc GFX3D_AXI_CLK>;
1776                         reg = <0x07c00000 0x100000>;
1777                         interrupts =
1778                             <GIC_SPI 69 0>,
1779                             <GIC_SPI 70 0>;
1780                         ncb = <3>;
1781                 };
1782
1783                 gfx3d1: qcom,iommu@7d00000 {
1784                         compatible = "qcom,iommu-v0";
1785                         #iommu-cells = <16>;
1786                         clock-names =
1787                             "smmu_pclk",
1788                             "iommu_clk";
1789                         clocks =
1790                             <&mmcc SMMU_AHB_CLK>,
1791                             <&mmcc GFX3D_AXI_CLK>;
1792                         reg = <0x07d00000 0x100000>;
1793                         interrupts =
1794                             <GIC_SPI 210 0>,
1795                             <GIC_SPI 211 0>;
1796                         ncb = <3>;
1797                 };
1798         };
1799 };
1800
1801 #include "qcom-apq8064-coresight.dtsi"
1802 #include "qcom-apq8064-pins.dtsi"