arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 smem_region: smem@fa00000 {
  18                         reg = <0xfa00000 0x200000>;
  19                         no-map;
  20                 };
  21         };
  22
  23         firmware {
  24                 compatible = "simple-bus";
  25
  26                 scm {
  27                         compatible = "qcom,scm";
  28                         clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>,
  29                                  <&gcc GCC_CE1_AHB_CLK>;
  30                         clock-names = "core", "bus", "iface";
  31                 };
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37                 interrupts = <1 9 0xf04>;
  38
  39                 cpu@0 {
  40                         compatible = "qcom,krait";
  41                         enable-method = "qcom,kpss-acc-v2";
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc0>;
  46                         qcom,saw = <&saw0>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 cpu@1 {
  51                         compatible = "qcom,krait";
  52                         enable-method = "qcom,kpss-acc-v2";
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc1>;
  57                         qcom,saw = <&saw1>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 cpu@2 {
  62                         compatible = "qcom,krait";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         device_type = "cpu";
  65                         reg = <2>;
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc2>;
  68                         qcom,saw = <&saw2>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 cpu@3 {
  73                         compatible = "qcom,krait";
  74                         enable-method = "qcom,kpss-acc-v2";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                         qcom,acc = <&acc3>;
  79                         qcom,saw = <&saw3>;
  80                         cpu-idle-states = <&CPU_SPC>;
  81                 };
  82
  83                 L2: l2-cache {
  84                         compatible = "cache";
  85                         cache-level = <2>;
  86                         qcom,saw = <&saw_l2>;
  87                 };
  88
  89                 idle-states {
  90                         CPU_SPC: spc {
  91                                 compatible = "qcom,idle-state-spc",
  92                                                 "arm,idle-state";
  93                                 entry-latency-us = <150>;
  94                                 exit-latency-us = <200>;
  95                                 min-residency-us = <2000>;
  96                         };
  97                 };
  98         };
  99
 100         cpu-pmu {
 101                 compatible = "qcom,krait-pmu";
 102                 interrupts = <1 7 0xf04>;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupts = <1 2 0xf08>,
 108                              <1 3 0xf08>,
 109                              <1 4 0xf08>,
 110                              <1 1 0xf08>;
 111                 clock-frequency = <19200000>;
 112         };
 113
 114         smem {
 115                 compatible = "qcom,smem";
 116
 117                 memory-region = <&smem_region>;
 118                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 119
 120                 hwlocks = <&tcsr_mutex 3>;
 121         };
 122
 123         soc: soc {
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 ranges;
 127                 compatible = "simple-bus";
 128
 129                 intc: interrupt-controller@f9000000 {
 130                         compatible = "qcom,msm-qgic2";
 131                         interrupt-controller;
 132                         #interrupt-cells = <3>;
 133                         reg = <0xf9000000 0x1000>,
 134                               <0xf9002000 0x1000>;
 135                 };
 136
 137                 apcs: syscon@f9011000 {
 138                         compatible = "syscon";
 139                         reg = <0xf9011000 0x1000>;
 140                 };
 141
 142                 timer@f9020000 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         ranges;
 146                         compatible = "arm,armv7-timer-mem";
 147                         reg = <0xf9020000 0x1000>;
 148                         clock-frequency = <19200000>;
 149
 150                         frame@f9021000 {
 151                                 frame-number = <0>;
 152                                 interrupts = <0 8 0x4>,
 153                                              <0 7 0x4>;
 154                                 reg = <0xf9021000 0x1000>,
 155                                       <0xf9022000 0x1000>;
 156                         };
 157
 158                         frame@f9023000 {
 159                                 frame-number = <1>;
 160                                 interrupts = <0 9 0x4>;
 161                                 reg = <0xf9023000 0x1000>;
 162                                 status = "disabled";
 163                         };
 164
 165                         frame@f9024000 {
 166                                 frame-number = <2>;
 167                                 interrupts = <0 10 0x4>;
 168                                 reg = <0xf9024000 0x1000>;
 169                                 status = "disabled";
 170                         };
 171
 172                         frame@f9025000 {
 173                                 frame-number = <3>;
 174                                 interrupts = <0 11 0x4>;
 175                                 reg = <0xf9025000 0x1000>;
 176                                 status = "disabled";
 177                         };
 178
 179                         frame@f9026000 {
 180                                 frame-number = <4>;
 181                                 interrupts = <0 12 0x4>;
 182                                 reg = <0xf9026000 0x1000>;
 183                                 status = "disabled";
 184                         };
 185
 186                         frame@f9027000 {
 187                                 frame-number = <5>;
 188                                 interrupts = <0 13 0x4>;
 189                                 reg = <0xf9027000 0x1000>;
 190                                 status = "disabled";
 191                         };
 192
 193                         frame@f9028000 {
 194                                 frame-number = <6>;
 195                                 interrupts = <0 14 0x4>;
 196                                 reg = <0xf9028000 0x1000>;
 197                                 status = "disabled";
 198                         };
 199                 };
 200
 201                 saw0: power-controller@f9089000 {
 202                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 203                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 204                 };
 205
 206                 saw1: power-controller@f9099000 {
 207                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 208                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 209                 };
 210
 211                 saw2: power-controller@f90a9000 {
 212                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 213                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 214                 };
 215
 216                 saw3: power-controller@f90b9000 {
 217                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 218                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 219                 };
 220
 221                 saw_l2: power-controller@f9012000 {
 222                         compatible = "qcom,saw2";
 223                         reg = <0xf9012000 0x1000>;
 224                         regulator;
 225                 };
 226
 227                 acc0: clock-controller@f9088000 {
 228                         compatible = "qcom,kpss-acc-v2";
 229                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 230                 };
 231
 232                 acc1: clock-controller@f9098000 {
 233                         compatible = "qcom,kpss-acc-v2";
 234                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 235                 };
 236
 237                 acc2: clock-controller@f90a8000 {
 238                         compatible = "qcom,kpss-acc-v2";
 239                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 240                 };
 241
 242                 acc3: clock-controller@f90b8000 {
 243                         compatible = "qcom,kpss-acc-v2";
 244                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 245                 };
 246
 247                 restart@fc4ab000 {
 248                         compatible = "qcom,pshold";
 249                         reg = <0xfc4ab000 0x4>;
 250                 };
 251
 252                 gcc: clock-controller@fc400000 {
 253                         compatible = "qcom,gcc-msm8974";
 254                         #clock-cells = <1>;
 255                         #reset-cells = <1>;
 256                         #power-domain-cells = <1>;
 257                         reg = <0xfc400000 0x4000>;
 258                 };
 259
 260                 tcsr_mutex_block: syscon@fd484000 {
 261                         compatible = "syscon";
 262                         reg = <0xfd484000 0x2000>;
 263                 };
 264
 265                 mmcc: clock-controller@fd8c0000 {
 266                         compatible = "qcom,mmcc-msm8974";
 267                         #clock-cells = <1>;
 268                         #reset-cells = <1>;
 269                         #power-domain-cells = <1>;
 270                         reg = <0xfd8c0000 0x6000>;
 271                 };
 272
 273                 tcsr_mutex: tcsr-mutex {
 274                         compatible = "qcom,tcsr-mutex";
 275                         syscon = <&tcsr_mutex_block 0 0x80>;
 276
 277                         #hwlock-cells = <1>;
 278                 };
 279
 280                 rpm_msg_ram: memory@fc428000 {
 281                         compatible = "qcom,rpm-msg-ram";
 282                         reg = <0xfc428000 0x4000>;
 283                 };
 284
 285                 blsp1_uart2: serial@f991e000 {
 286                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 287                         reg = <0xf991e000 0x1000>;
 288                         interrupts = <0 108 0x0>;
 289                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 290                         clock-names = "core", "iface";
 291                         status = "disabled";
 292                 };
 293
 294                 sdhci@f9824900 {
 295                         compatible = "qcom,sdhci-msm-v4";
 296                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 297                         reg-names = "hc_mem", "core_mem";
 298                         interrupts = <0 123 0>, <0 138 0>;
 299                         interrupt-names = "hc_irq", "pwr_irq";
 300                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 301                         clock-names = "core", "iface";
 302                         status = "disabled";
 303                 };
 304
 305                 sdhci@f98a4900 {
 306                         compatible = "qcom,sdhci-msm-v4";
 307                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 308                         reg-names = "hc_mem", "core_mem";
 309                         interrupts = <0 125 0>, <0 221 0>;
 310                         interrupt-names = "hc_irq", "pwr_irq";
 311                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 312                         clock-names = "core", "iface";
 313                         status = "disabled";
 314                 };
 315
 316                 rng@f9bff000 {
 317                         compatible = "qcom,prng";
 318                         reg = <0xf9bff000 0x200>;
 319                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 320                         clock-names = "core";
 321                 };
 322
 323                 msmgpio: pinctrl@fd510000 {
 324                         compatible = "qcom,msm8974-pinctrl";
 325                         reg = <0xfd510000 0x4000>;
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                         interrupts = <0 208 0>;
 331                 };
 332
 333                 blsp_i2c11: i2c@f9967000 {
 334                         status = "disabled";
 335                         compatible = "qcom,i2c-qup-v2.1.1";
 336                         reg = <0xf9967000 0x1000>;
 337                         interrupts = <0 105 IRQ_TYPE_NONE>;
 338                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 339                         clock-names = "core", "iface";
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                 };
 343
 344                 spmi_bus: spmi@fc4cf000 {
 345                         compatible = "qcom,spmi-pmic-arb";
 346                         reg-names = "core", "intr", "cnfg";
 347                         reg = <0xfc4cf000 0x1000>,
 348                               <0xfc4cb000 0x1000>,
 349                               <0xfc4ca000 0x1000>;
 350                         interrupt-names = "periph_irq";
 351                         interrupts = <0 190 0>;
 352                         qcom,ee = <0>;
 353                         qcom,channel = <0>;
 354                         #address-cells = <2>;
 355                         #size-cells = <0>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <4>;
 358                 };
 359         };
 360
 361         smd {
 362                 compatible = "qcom,smd";
 363
 364                 rpm {
 365                         interrupts = <0 168 1>;
 366                         qcom,ipc = <&apcs 8 0>;
 367                         qcom,smd-edge = <15>;
 368
 369                         rpm_requests {
 370                                 compatible = "qcom,rpm-msm8974";
 371                                 qcom,smd-channels = "rpm_requests";
 372
 373                                 pm8841-regulators {
 374                                         compatible = "qcom,rpm-pm8841-regulators";
 375
 376                                         pm8841_s1: s1 {};
 377                                         pm8841_s2: s2 {};
 378                                         pm8841_s3: s3 {};
 379                                         pm8841_s4: s4 {};
 380                                         pm8841_s5: s5 {};
 381                                         pm8841_s6: s6 {};
 382                                         pm8841_s7: s7 {};
 383                                         pm8841_s8: s8 {};
 384                                 };
 385
 386                                 pm8941-regulators {
 387                                         compatible = "qcom,rpm-pm8941-regulators";
 388
 389                                         pm8941_s1: s1 {};
 390                                         pm8941_s2: s2 {};
 391                                         pm8941_s3: s3 {};
 392                                         pm8941_5v: s4 {};
 393
 394                                         pm8941_l1: l1 {};
 395                                         pm8941_l2: l2 {};
 396                                         pm8941_l3: l3 {};
 397                                         pm8941_l4: l4 {};
 398                                         pm8941_l5: l5 {};
 399                                         pm8941_l6: l6 {};
 400                                         pm8941_l7: l7 {};
 401                                         pm8941_l8: l8 {};
 402                                         pm8941_l9: l9 {};
 403                                         pm8941_l10: l10 {};
 404                                         pm8941_l11: l11 {};
 405                                         pm8941_l12: l12 {};
 406                                         pm8941_l13: l13 {};
 407                                         pm8941_l14: l14 {};
 408                                         pm8941_l15: l15 {};
 409                                         pm8941_l16: l16 {};
 410                                         pm8941_l17: l17 {};
 411                                         pm8941_l18: l18 {};
 412                                         pm8941_l19: l19 {};
 413                                         pm8941_l20: l20 {};
 414                                         pm8941_l21: l21 {};
 415                                         pm8941_l22: l22 {};
 416                                         pm8941_l23: l23 {};
 417                                         pm8941_l24: l24 {};
 418
 419                                         pm8941_lvs1: lvs1 {};
 420                                         pm8941_lvs2: lvs2 {};
 421                                         pm8941_lvs3: lvs3 {};
 422
 423                                         pm8941_5vs1: 5vs1 {};
 424                                         pm8941_5vs2: 5vs2 {};
 425                                 };
 426                         };
 427                 };
 428         };
 429 };