arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7791-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7791";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &i2c4;
  30                 i2c5 = &i2c5;
  31                 i2c6 = &i2c6;
  32                 i2c7 = &i2c7;
  33                 i2c8 = &i2c8;
  34                 spi0 = &qspi;
  35                 spi1 = &msiof0;
  36                 spi2 = &msiof1;
  37                 spi3 = &msiof2;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 enable-method = "renesas,apmu";
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0>;
  52                         clock-frequency = <1500000000>;
  53                         voltage-tolerance = <1>; /* 1% */
  54                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  55                         clock-latency = <300000>; /* 300 us */
  56                         power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
  57                         next-level-cache = <&L2_CA15>;
  58
  59                         /* kHz - uV - OPPs unknown yet */
  60                         operating-points = <1500000 1000000>,
  61                                            <1312500 1000000>,
  62                                            <1125000 1000000>,
  63                                            < 937500 1000000>,
  64                                            < 750000 1000000>,
  65                                            < 375000 1000000>;
  66                 };
  67
  68                 cpu1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a15";
  71                         reg = <1>;
  72                         clock-frequency = <1500000000>;
  73                         power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
  74                         next-level-cache = <&L2_CA15>;
  75                 };
  76
  77                 L2_CA15: cache-controller-0 {
  78                         compatible = "cache";
  79                         power-domains = <&sysc R8A7791_PD_CA15_SCU>;
  80                         cache-unified;
  81                         cache-level = <2>;
  82                 };
  83         };
  84
  85         thermal-zones {
  86                 cpu_thermal: cpu-thermal {
  87                         polling-delay-passive   = <0>;
  88                         polling-delay           = <0>;
  89
  90                         thermal-sensors = <&thermal>;
  91
  92                         trips {
  93                                 cpu-crit {
  94                                         temperature     = <115000>;
  95                                         hysteresis      = <0>;
  96                                         type            = "critical";
  97                                 };
  98                         };
  99                         cooling-maps {
 100                         };
 101                 };
 102         };
 103
 104         apmu@e6152000 {
 105                 compatible = "renesas,r8a7791-apmu", "renesas,apmu";
 106                 reg = <0 0xe6152000 0 0x188>;
 107                 cpus = <&cpu0 &cpu1>;
 108         };
 109
 110         gic: interrupt-controller@f1001000 {
 111                 compatible = "arm,gic-400";
 112                 #interrupt-cells = <3>;
 113                 #address-cells = <0>;
 114                 interrupt-controller;
 115                 reg = <0 0xf1001000 0 0x1000>,
 116                         <0 0xf1002000 0 0x2000>,
 117                         <0 0xf1004000 0 0x2000>,
 118                         <0 0xf1006000 0 0x2000>;
 119                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 120                 clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
 121                 clock-names = "clk";
 122                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 123         };
 124
 125         gpio0: gpio@e6050000 {
 126                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 127                 reg = <0 0xe6050000 0 0x50>;
 128                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 0 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
 135                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 136         };
 137
 138         gpio1: gpio@e6051000 {
 139                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 140                 reg = <0 0xe6051000 0 0x50>;
 141                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 32 26>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 148                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 149         };
 150
 151         gpio2: gpio@e6052000 {
 152                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 153                 reg = <0 0xe6052000 0 0x50>;
 154                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 64 32>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 161                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 162         };
 163
 164         gpio3: gpio@e6053000 {
 165                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 166                 reg = <0 0xe6053000 0 0x50>;
 167                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 168                 #gpio-cells = <2>;
 169                 gpio-controller;
 170                 gpio-ranges = <&pfc 0 96 32>;
 171                 #interrupt-cells = <2>;
 172                 interrupt-controller;
 173                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 174                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 175         };
 176
 177         gpio4: gpio@e6054000 {
 178                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 179                 reg = <0 0xe6054000 0 0x50>;
 180                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 181                 #gpio-cells = <2>;
 182                 gpio-controller;
 183                 gpio-ranges = <&pfc 0 128 32>;
 184                 #interrupt-cells = <2>;
 185                 interrupt-controller;
 186                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 187                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 188         };
 189
 190         gpio5: gpio@e6055000 {
 191                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 192                 reg = <0 0xe6055000 0 0x50>;
 193                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 194                 #gpio-cells = <2>;
 195                 gpio-controller;
 196                 gpio-ranges = <&pfc 0 160 32>;
 197                 #interrupt-cells = <2>;
 198                 interrupt-controller;
 199                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 200                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 201         };
 202
 203         gpio6: gpio@e6055400 {
 204                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 205                 reg = <0 0xe6055400 0 0x50>;
 206                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 207                 #gpio-cells = <2>;
 208                 gpio-controller;
 209                 gpio-ranges = <&pfc 0 192 32>;
 210                 #interrupt-cells = <2>;
 211                 interrupt-controller;
 212                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 213                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 214         };
 215
 216         gpio7: gpio@e6055800 {
 217                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 218                 reg = <0 0xe6055800 0 0x50>;
 219                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 220                 #gpio-cells = <2>;
 221                 gpio-controller;
 222                 gpio-ranges = <&pfc 0 224 26>;
 223                 #interrupt-cells = <2>;
 224                 interrupt-controller;
 225                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 226                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 227         };
 228
 229         thermal: thermal@e61f0000 {
 230                 compatible =    "renesas,thermal-r8a7791",
 231                                 "renesas,rcar-gen2-thermal",
 232                                 "renesas,rcar-thermal";
 233                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 234                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 236                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 237                 #thermal-sensor-cells = <0>;
 238         };
 239
 240         timer {
 241                 compatible = "arm,armv7-timer";
 242                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 243                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 244                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 245                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 246         };
 247
 248         cmt0: timer@ffca0000 {
 249                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 250                 reg = <0 0xffca0000 0 0x1004>;
 251                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 254                 clock-names = "fck";
 255                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 256
 257                 renesas,channels-mask = <0x60>;
 258
 259                 status = "disabled";
 260         };
 261
 262         cmt1: timer@e6130000 {
 263                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 264                 reg = <0 0xe6130000 0 0x1004>;
 265                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 274                 clock-names = "fck";
 275                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 276
 277                 renesas,channels-mask = <0xff>;
 278
 279                 status = "disabled";
 280         };
 281
 282         irqc0: interrupt-controller@e61c0000 {
 283                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 284                 #interrupt-cells = <2>;
 285                 interrupt-controller;
 286                 reg = <0 0xe61c0000 0 0x200>;
 287                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 298                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 299         };
 300
 301         dmac0: dma-controller@e6700000 {
 302                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 303                 reg = <0 0xe6700000 0 0x20000>;
 304                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 311                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 312                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 313                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 314                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 315                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 316                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 317                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 318                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 319                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 320                 interrupt-names = "error",
 321                                 "ch0", "ch1", "ch2", "ch3",
 322                                 "ch4", "ch5", "ch6", "ch7",
 323                                 "ch8", "ch9", "ch10", "ch11",
 324                                 "ch12", "ch13", "ch14";
 325                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 326                 clock-names = "fck";
 327                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 328                 #dma-cells = <1>;
 329                 dma-channels = <15>;
 330         };
 331
 332         dmac1: dma-controller@e6720000 {
 333                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 334                 reg = <0 0xe6720000 0 0x20000>;
 335                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 343                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 344                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 345                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 346                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 347                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 348                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 349                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 350                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 351                 interrupt-names = "error",
 352                                 "ch0", "ch1", "ch2", "ch3",
 353                                 "ch4", "ch5", "ch6", "ch7",
 354                                 "ch8", "ch9", "ch10", "ch11",
 355                                 "ch12", "ch13", "ch14";
 356                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 357                 clock-names = "fck";
 358                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 359                 #dma-cells = <1>;
 360                 dma-channels = <15>;
 361         };
 362
 363         audma0: dma-controller@ec700000 {
 364                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 365                 reg = <0 0xec700000 0 0x10000>;
 366                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 367                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 368                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 369                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 370                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 371                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 372                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 373                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 374                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 375                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 376                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 377                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 378                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 379                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 380                 interrupt-names = "error",
 381                                 "ch0", "ch1", "ch2", "ch3",
 382                                 "ch4", "ch5", "ch6", "ch7",
 383                                 "ch8", "ch9", "ch10", "ch11",
 384                                 "ch12";
 385                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 386                 clock-names = "fck";
 387                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 388                 #dma-cells = <1>;
 389                 dma-channels = <13>;
 390         };
 391
 392         audma1: dma-controller@ec720000 {
 393                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 394                 reg = <0 0xec720000 0 0x10000>;
 395                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 396                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 397                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 398                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 399                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 400                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 401                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 402                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 403                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 404                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 405                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 406                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 407                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 408                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 409                 interrupt-names = "error",
 410                                 "ch0", "ch1", "ch2", "ch3",
 411                                 "ch4", "ch5", "ch6", "ch7",
 412                                 "ch8", "ch9", "ch10", "ch11",
 413                                 "ch12";
 414                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 415                 clock-names = "fck";
 416                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 417                 #dma-cells = <1>;
 418                 dma-channels = <13>;
 419         };
 420
 421         usb_dmac0: dma-controller@e65a0000 {
 422                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 423                 reg = <0 0xe65a0000 0 0x100>;
 424                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 425                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 426                 interrupt-names = "ch0", "ch1";
 427                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 428                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 429                 #dma-cells = <1>;
 430                 dma-channels = <2>;
 431         };
 432
 433         usb_dmac1: dma-controller@e65b0000 {
 434                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 435                 reg = <0 0xe65b0000 0 0x100>;
 436                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 437                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 438                 interrupt-names = "ch0", "ch1";
 439                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 440                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 441                 #dma-cells = <1>;
 442                 dma-channels = <2>;
 443         };
 444
 445         /* The memory map in the User's Manual maps the cores to bus numbers */
 446         i2c0: i2c@e6508000 {
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 450                 reg = <0 0xe6508000 0 0x40>;
 451                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 453                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 454                 i2c-scl-internal-delay-ns = <6>;
 455                 status = "disabled";
 456         };
 457
 458         i2c1: i2c@e6518000 {
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 462                 reg = <0 0xe6518000 0 0x40>;
 463                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 465                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 466                 i2c-scl-internal-delay-ns = <6>;
 467                 status = "disabled";
 468         };
 469
 470         i2c2: i2c@e6530000 {
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 474                 reg = <0 0xe6530000 0 0x40>;
 475                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 477                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 478                 i2c-scl-internal-delay-ns = <6>;
 479                 status = "disabled";
 480         };
 481
 482         i2c3: i2c@e6540000 {
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 486                 reg = <0 0xe6540000 0 0x40>;
 487                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 489                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 490                 i2c-scl-internal-delay-ns = <6>;
 491                 status = "disabled";
 492         };
 493
 494         i2c4: i2c@e6520000 {
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 498                 reg = <0 0xe6520000 0 0x40>;
 499                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 500                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 501                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 502                 i2c-scl-internal-delay-ns = <6>;
 503                 status = "disabled";
 504         };
 505
 506         i2c5: i2c@e6528000 {
 507                 /* doesn't need pinmux */
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 511                 reg = <0 0xe6528000 0 0x40>;
 512                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 513                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 514                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 515                 i2c-scl-internal-delay-ns = <110>;
 516                 status = "disabled";
 517         };
 518
 519         i2c6: i2c@e60b0000 {
 520                 /* doesn't need pinmux */
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 524                              "renesas,rmobile-iic";
 525                 reg = <0 0xe60b0000 0 0x425>;
 526                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 528                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 529                        <&dmac1 0x77>, <&dmac1 0x78>;
 530                 dma-names = "tx", "rx", "tx", "rx";
 531                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 532                 status = "disabled";
 533         };
 534
 535         i2c7: i2c@e6500000 {
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 539                              "renesas,rmobile-iic";
 540                 reg = <0 0xe6500000 0 0x425>;
 541                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 543                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 544                        <&dmac1 0x61>, <&dmac1 0x62>;
 545                 dma-names = "tx", "rx", "tx", "rx";
 546                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 547                 status = "disabled";
 548         };
 549
 550         i2c8: i2c@e6510000 {
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 554                              "renesas,rmobile-iic";
 555                 reg = <0 0xe6510000 0 0x425>;
 556                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 557                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 558                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 559                        <&dmac1 0x65>, <&dmac1 0x66>;
 560                 dma-names = "tx", "rx", "tx", "rx";
 561                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 562                 status = "disabled";
 563         };
 564
 565         pfc: pin-controller@e6060000 {
 566                 compatible = "renesas,pfc-r8a7791";
 567                 reg = <0 0xe6060000 0 0x250>;
 568         };
 569
 570         mmcif0: mmc@ee200000 {
 571                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 572                 reg = <0 0xee200000 0 0x80>;
 573                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 574                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 575                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 576                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 577                 dma-names = "tx", "rx", "tx", "rx";
 578                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 579                 reg-io-width = <4>;
 580                 status = "disabled";
 581                 max-frequency = <97500000>;
 582         };
 583
 584         sdhi0: sd@ee100000 {
 585                 compatible = "renesas,sdhi-r8a7791";
 586                 reg = <0 0xee100000 0 0x328>;
 587                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 589                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 590                        <&dmac1 0xcd>, <&dmac1 0xce>;
 591                 dma-names = "tx", "rx", "tx", "rx";
 592                 max-frequency = <195000000>;
 593                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 594                 status = "disabled";
 595         };
 596
 597         sdhi1: sd@ee140000 {
 598                 compatible = "renesas,sdhi-r8a7791";
 599                 reg = <0 0xee140000 0 0x100>;
 600                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 602                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 603                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 604                 dma-names = "tx", "rx", "tx", "rx";
 605                 max-frequency = <97500000>;
 606                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 607                 status = "disabled";
 608         };
 609
 610         sdhi2: sd@ee160000 {
 611                 compatible = "renesas,sdhi-r8a7791";
 612                 reg = <0 0xee160000 0 0x100>;
 613                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 615                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 616                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 617                 dma-names = "tx", "rx", "tx", "rx";
 618                 max-frequency = <97500000>;
 619                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 620                 status = "disabled";
 621         };
 622
 623         scifa0: serial@e6c40000 {
 624                 compatible = "renesas,scifa-r8a7791",
 625                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 626                 reg = <0 0xe6c40000 0 64>;
 627                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 629                 clock-names = "fck";
 630                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 631                        <&dmac1 0x21>, <&dmac1 0x22>;
 632                 dma-names = "tx", "rx", "tx", "rx";
 633                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 634                 status = "disabled";
 635         };
 636
 637         scifa1: serial@e6c50000 {
 638                 compatible = "renesas,scifa-r8a7791",
 639                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 640                 reg = <0 0xe6c50000 0 64>;
 641                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 643                 clock-names = "fck";
 644                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 645                        <&dmac1 0x25>, <&dmac1 0x26>;
 646                 dma-names = "tx", "rx", "tx", "rx";
 647                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 648                 status = "disabled";
 649         };
 650
 651         scifa2: serial@e6c60000 {
 652                 compatible = "renesas,scifa-r8a7791",
 653                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 654                 reg = <0 0xe6c60000 0 64>;
 655                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 656                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 657                 clock-names = "fck";
 658                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 659                        <&dmac1 0x27>, <&dmac1 0x28>;
 660                 dma-names = "tx", "rx", "tx", "rx";
 661                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 662                 status = "disabled";
 663         };
 664
 665         scifa3: serial@e6c70000 {
 666                 compatible = "renesas,scifa-r8a7791",
 667                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 668                 reg = <0 0xe6c70000 0 64>;
 669                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 670                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 671                 clock-names = "fck";
 672                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 673                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 674                 dma-names = "tx", "rx", "tx", "rx";
 675                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 676                 status = "disabled";
 677         };
 678
 679         scifa4: serial@e6c78000 {
 680                 compatible = "renesas,scifa-r8a7791",
 681                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 682                 reg = <0 0xe6c78000 0 64>;
 683                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 685                 clock-names = "fck";
 686                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 687                        <&dmac1 0x1f>, <&dmac1 0x20>;
 688                 dma-names = "tx", "rx", "tx", "rx";
 689                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 690                 status = "disabled";
 691         };
 692
 693         scifa5: serial@e6c80000 {
 694                 compatible = "renesas,scifa-r8a7791",
 695                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 696                 reg = <0 0xe6c80000 0 64>;
 697                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 699                 clock-names = "fck";
 700                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 701                        <&dmac1 0x23>, <&dmac1 0x24>;
 702                 dma-names = "tx", "rx", "tx", "rx";
 703                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 704                 status = "disabled";
 705         };
 706
 707         scifb0: serial@e6c20000 {
 708                 compatible = "renesas,scifb-r8a7791",
 709                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 710                 reg = <0 0xe6c20000 0 0x100>;
 711                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 713                 clock-names = "fck";
 714                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 715                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 716                 dma-names = "tx", "rx", "tx", "rx";
 717                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 718                 status = "disabled";
 719         };
 720
 721         scifb1: serial@e6c30000 {
 722                 compatible = "renesas,scifb-r8a7791",
 723                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 724                 reg = <0 0xe6c30000 0 0x100>;
 725                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 726                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 727                 clock-names = "fck";
 728                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 729                        <&dmac1 0x19>, <&dmac1 0x1a>;
 730                 dma-names = "tx", "rx", "tx", "rx";
 731                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 732                 status = "disabled";
 733         };
 734
 735         scifb2: serial@e6ce0000 {
 736                 compatible = "renesas,scifb-r8a7791",
 737                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 738                 reg = <0 0xe6ce0000 0 0x100>;
 739                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 740                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 741                 clock-names = "fck";
 742                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 743                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 744                 dma-names = "tx", "rx", "tx", "rx";
 745                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 746                 status = "disabled";
 747         };
 748
 749         scif0: serial@e6e60000 {
 750                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 751                              "renesas,scif";
 752                 reg = <0 0xe6e60000 0 64>;
 753                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
 755                          <&scif_clk>;
 756                 clock-names = "fck", "brg_int", "scif_clk";
 757                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 758                        <&dmac1 0x29>, <&dmac1 0x2a>;
 759                 dma-names = "tx", "rx", "tx", "rx";
 760                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 761                 status = "disabled";
 762         };
 763
 764         scif1: serial@e6e68000 {
 765                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 766                              "renesas,scif";
 767                 reg = <0 0xe6e68000 0 64>;
 768                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
 770                          <&scif_clk>;
 771                 clock-names = "fck", "brg_int", "scif_clk";
 772                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 773                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 774                 dma-names = "tx", "rx", "tx", "rx";
 775                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 776                 status = "disabled";
 777         };
 778
 779         adc: adc@e6e54000 {
 780                 compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
 781                 reg = <0 0xe6e54000 0 64>;
 782                 clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
 783                 clock-names = "fck";
 784                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 785                 status = "disabled";
 786         };
 787
 788         scif2: serial@e6e58000 {
 789                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 790                              "renesas,scif";
 791                 reg = <0 0xe6e58000 0 64>;
 792                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
 794                          <&scif_clk>;
 795                 clock-names = "fck", "brg_int", "scif_clk";
 796                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 797                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 798                 dma-names = "tx", "rx", "tx", "rx";
 799                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 800                 status = "disabled";
 801         };
 802
 803         scif3: serial@e6ea8000 {
 804                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 805                              "renesas,scif";
 806                 reg = <0 0xe6ea8000 0 64>;
 807                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
 809                          <&scif_clk>;
 810                 clock-names = "fck", "brg_int", "scif_clk";
 811                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 812                        <&dmac1 0x2f>, <&dmac1 0x30>;
 813                 dma-names = "tx", "rx", "tx", "rx";
 814                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 815                 status = "disabled";
 816         };
 817
 818         scif4: serial@e6ee0000 {
 819                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 820                              "renesas,scif";
 821                 reg = <0 0xe6ee0000 0 64>;
 822                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 823                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
 824                          <&scif_clk>;
 825                 clock-names = "fck", "brg_int", "scif_clk";
 826                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 827                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 828                 dma-names = "tx", "rx", "tx", "rx";
 829                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 830                 status = "disabled";
 831         };
 832
 833         scif5: serial@e6ee8000 {
 834                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 835                              "renesas,scif";
 836                 reg = <0 0xe6ee8000 0 64>;
 837                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 838                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
 839                          <&scif_clk>;
 840                 clock-names = "fck", "brg_int", "scif_clk";
 841                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 842                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 843                 dma-names = "tx", "rx", "tx", "rx";
 844                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 845                 status = "disabled";
 846         };
 847
 848         hscif0: serial@e62c0000 {
 849                 compatible = "renesas,hscif-r8a7791",
 850                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 851                 reg = <0 0xe62c0000 0 96>;
 852                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 853                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
 854                          <&scif_clk>;
 855                 clock-names = "fck", "brg_int", "scif_clk";
 856                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 857                        <&dmac1 0x39>, <&dmac1 0x3a>;
 858                 dma-names = "tx", "rx", "tx", "rx";
 859                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 860                 status = "disabled";
 861         };
 862
 863         hscif1: serial@e62c8000 {
 864                 compatible = "renesas,hscif-r8a7791",
 865                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 866                 reg = <0 0xe62c8000 0 96>;
 867                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 868                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
 869                          <&scif_clk>;
 870                 clock-names = "fck", "brg_int", "scif_clk";
 871                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 872                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 873                 dma-names = "tx", "rx", "tx", "rx";
 874                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 875                 status = "disabled";
 876         };
 877
 878         hscif2: serial@e62d0000 {
 879                 compatible = "renesas,hscif-r8a7791",
 880                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 881                 reg = <0 0xe62d0000 0 96>;
 882                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 883                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
 884                          <&scif_clk>;
 885                 clock-names = "fck", "brg_int", "scif_clk";
 886                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 887                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 888                 dma-names = "tx", "rx", "tx", "rx";
 889                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 890                 status = "disabled";
 891         };
 892
 893         ether: ethernet@ee700000 {
 894                 compatible = "renesas,ether-r8a7791";
 895                 reg = <0 0xee700000 0 0x400>;
 896                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 898                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 899                 phy-mode = "rmii";
 900                 #address-cells = <1>;
 901                 #size-cells = <0>;
 902                 status = "disabled";
 903         };
 904
 905         avb: ethernet@e6800000 {
 906                 compatible = "renesas,etheravb-r8a7791",
 907                              "renesas,etheravb-rcar-gen2";
 908                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 909                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 910                 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
 911                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 912                 #address-cells = <1>;
 913                 #size-cells = <0>;
 914                 status = "disabled";
 915         };
 916
 917         sata0: sata@ee300000 {
 918                 compatible = "renesas,sata-r8a7791";
 919                 reg = <0 0xee300000 0 0x2000>;
 920                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 921                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 922                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 923                 status = "disabled";
 924         };
 925
 926         sata1: sata@ee500000 {
 927                 compatible = "renesas,sata-r8a7791";
 928                 reg = <0 0xee500000 0 0x2000>;
 929                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 930                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 931                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 932                 status = "disabled";
 933         };
 934
 935         hsusb: usb@e6590000 {
 936                 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
 937                 reg = <0 0xe6590000 0 0x100>;
 938                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 939                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 940                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 941                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 942                 dma-names = "ch0", "ch1", "ch2", "ch3";
 943                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 944                 renesas,buswait = <4>;
 945                 phys = <&usb0 1>;
 946                 phy-names = "usb";
 947                 status = "disabled";
 948         };
 949
 950         usbphy: usb-phy@e6590100 {
 951                 compatible = "renesas,usb-phy-r8a7791",
 952                              "renesas,rcar-gen2-usb-phy";
 953                 reg = <0 0xe6590100 0 0x100>;
 954                 #address-cells = <1>;
 955                 #size-cells = <0>;
 956                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 957                 clock-names = "usbhs";
 958                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 959                 status = "disabled";
 960
 961                 usb0: usb-channel@0 {
 962                         reg = <0>;
 963                         #phy-cells = <1>;
 964                 };
 965                 usb2: usb-channel@2 {
 966                         reg = <2>;
 967                         #phy-cells = <1>;
 968                 };
 969         };
 970
 971         vin0: video@e6ef0000 {
 972                 compatible = "renesas,vin-r8a7791";
 973                 reg = <0 0xe6ef0000 0 0x1000>;
 974                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 975                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 976                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 977                 status = "disabled";
 978         };
 979
 980         vin1: video@e6ef1000 {
 981                 compatible = "renesas,vin-r8a7791";
 982                 reg = <0 0xe6ef1000 0 0x1000>;
 983                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 984                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 985                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 986                 status = "disabled";
 987         };
 988
 989         vin2: video@e6ef2000 {
 990                 compatible = "renesas,vin-r8a7791";
 991                 reg = <0 0xe6ef2000 0 0x1000>;
 992                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 993                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 994                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 995                 status = "disabled";
 996         };
 997
 998         vsp1@fe928000 {
 999                 compatible = "renesas,vsp1";
1000                 reg = <0 0xfe928000 0 0x8000>;
1001                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1002                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
1003                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1004         };
1005
1006         vsp1@fe930000 {
1007                 compatible = "renesas,vsp1";
1008                 reg = <0 0xfe930000 0 0x8000>;
1009                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
1011                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1012         };
1013
1014         vsp1@fe938000 {
1015                 compatible = "renesas,vsp1";
1016                 reg = <0 0xfe938000 0 0x8000>;
1017                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
1019                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1020         };
1021
1022         du: display@feb00000 {
1023                 compatible = "renesas,du-r8a7791";
1024                 reg = <0 0xfeb00000 0 0x40000>,
1025                       <0 0xfeb90000 0 0x1c>;
1026                 reg-names = "du", "lvds.0";
1027                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1028                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1029                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
1030                          <&mstp7_clks R8A7791_CLK_DU1>,
1031                          <&mstp7_clks R8A7791_CLK_LVDS0>;
1032                 clock-names = "du.0", "du.1", "lvds.0";
1033                 status = "disabled";
1034
1035                 ports {
1036                         #address-cells = <1>;
1037                         #size-cells = <0>;
1038
1039                         port@0 {
1040                                 reg = <0>;
1041                                 du_out_rgb: endpoint {
1042                                 };
1043                         };
1044                         port@1 {
1045                                 reg = <1>;
1046                                 du_out_lvds0: endpoint {
1047                                 };
1048                         };
1049                 };
1050         };
1051
1052         can0: can@e6e80000 {
1053                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1054                 reg = <0 0xe6e80000 0 0x1000>;
1055                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1056                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1057                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1058                 clock-names = "clkp1", "clkp2", "can_clk";
1059                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1060                 status = "disabled";
1061         };
1062
1063         can1: can@e6e88000 {
1064                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1065                 reg = <0 0xe6e88000 0 0x1000>;
1066                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1068                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1069                 clock-names = "clkp1", "clkp2", "can_clk";
1070                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1071                 status = "disabled";
1072         };
1073
1074         jpu: jpeg-codec@fe980000 {
1075                 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1076                 reg = <0 0xfe980000 0 0x10300>;
1077                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1078                 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1079                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1080         };
1081
1082         clocks {
1083                 #address-cells = <2>;
1084                 #size-cells = <2>;
1085                 ranges;
1086
1087                 /* External root clock */
1088                 extal_clk: extal {
1089                         compatible = "fixed-clock";
1090                         #clock-cells = <0>;
1091                         /* This value must be overriden by the board. */
1092                         clock-frequency = <0>;
1093                 };
1094
1095                 /*
1096                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1097                  * default. Boards that provide audio clocks should override them.
1098                  */
1099                 audio_clk_a: audio_clk_a {
1100                         compatible = "fixed-clock";
1101                         #clock-cells = <0>;
1102                         clock-frequency = <0>;
1103                 };
1104                 audio_clk_b: audio_clk_b {
1105                         compatible = "fixed-clock";
1106                         #clock-cells = <0>;
1107                         clock-frequency = <0>;
1108                 };
1109                 audio_clk_c: audio_clk_c {
1110                         compatible = "fixed-clock";
1111                         #clock-cells = <0>;
1112                         clock-frequency = <0>;
1113                 };
1114
1115                 /* External PCIe clock - can be overridden by the board */
1116                 pcie_bus_clk: pcie_bus {
1117                         compatible = "fixed-clock";
1118                         #clock-cells = <0>;
1119                         clock-frequency = <0>;
1120                 };
1121
1122                 /* External SCIF clock */
1123                 scif_clk: scif {
1124                         compatible = "fixed-clock";
1125                         #clock-cells = <0>;
1126                         /* This value must be overridden by the board. */
1127                         clock-frequency = <0>;
1128                 };
1129
1130                 /* External USB clock - can be overridden by the board */
1131                 usb_extal_clk: usb_extal {
1132                         compatible = "fixed-clock";
1133                         #clock-cells = <0>;
1134                         clock-frequency = <48000000>;
1135                 };
1136
1137                 /* External CAN clock */
1138                 can_clk: can {
1139                         compatible = "fixed-clock";
1140                         #clock-cells = <0>;
1141                         /* This value must be overridden by the board. */
1142                         clock-frequency = <0>;
1143                 };
1144
1145                 /* Special CPG clocks */
1146                 cpg_clocks: cpg_clocks@e6150000 {
1147                         compatible = "renesas,r8a7791-cpg-clocks",
1148                                      "renesas,rcar-gen2-cpg-clocks";
1149                         reg = <0 0xe6150000 0 0x1000>;
1150                         clocks = <&extal_clk &usb_extal_clk>;
1151                         #clock-cells = <1>;
1152                         clock-output-names = "main", "pll0", "pll1", "pll3",
1153                                              "lb", "qspi", "sdh", "sd0", "z",
1154                                              "rcan", "adsp";
1155                         #power-domain-cells = <0>;
1156                 };
1157
1158                 /* Variable factor clocks */
1159                 sd2_clk: sd2@e6150078 {
1160                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1161                         reg = <0 0xe6150078 0 4>;
1162                         clocks = <&pll1_div2_clk>;
1163                         #clock-cells = <0>;
1164                 };
1165                 sd3_clk: sd3@e615026c {
1166                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1167                         reg = <0 0xe615026c 0 4>;
1168                         clocks = <&pll1_div2_clk>;
1169                         #clock-cells = <0>;
1170                 };
1171                 mmc0_clk: mmc0@e6150240 {
1172                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1173                         reg = <0 0xe6150240 0 4>;
1174                         clocks = <&pll1_div2_clk>;
1175                         #clock-cells = <0>;
1176                 };
1177                 ssp_clk: ssp@e6150248 {
1178                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1179                         reg = <0 0xe6150248 0 4>;
1180                         clocks = <&pll1_div2_clk>;
1181                         #clock-cells = <0>;
1182                 };
1183                 ssprs_clk: ssprs@e615024c {
1184                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1185                         reg = <0 0xe615024c 0 4>;
1186                         clocks = <&pll1_div2_clk>;
1187                         #clock-cells = <0>;
1188                 };
1189
1190                 /* Fixed factor clocks */
1191                 pll1_div2_clk: pll1_div2 {
1192                         compatible = "fixed-factor-clock";
1193                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1194                         #clock-cells = <0>;
1195                         clock-div = <2>;
1196                         clock-mult = <1>;
1197                 };
1198                 zg_clk: zg {
1199                         compatible = "fixed-factor-clock";
1200                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1201                         #clock-cells = <0>;
1202                         clock-div = <3>;
1203                         clock-mult = <1>;
1204                 };
1205                 zx_clk: zx {
1206                         compatible = "fixed-factor-clock";
1207                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1208                         #clock-cells = <0>;
1209                         clock-div = <3>;
1210                         clock-mult = <1>;
1211                 };
1212                 zs_clk: zs {
1213                         compatible = "fixed-factor-clock";
1214                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1215                         #clock-cells = <0>;
1216                         clock-div = <6>;
1217                         clock-mult = <1>;
1218                 };
1219                 hp_clk: hp {
1220                         compatible = "fixed-factor-clock";
1221                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1222                         #clock-cells = <0>;
1223                         clock-div = <12>;
1224                         clock-mult = <1>;
1225                 };
1226                 i_clk: i {
1227                         compatible = "fixed-factor-clock";
1228                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1229                         #clock-cells = <0>;
1230                         clock-div = <2>;
1231                         clock-mult = <1>;
1232                 };
1233                 b_clk: b {
1234                         compatible = "fixed-factor-clock";
1235                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1236                         #clock-cells = <0>;
1237                         clock-div = <12>;
1238                         clock-mult = <1>;
1239                 };
1240                 p_clk: p {
1241                         compatible = "fixed-factor-clock";
1242                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1243                         #clock-cells = <0>;
1244                         clock-div = <24>;
1245                         clock-mult = <1>;
1246                 };
1247                 cl_clk: cl {
1248                         compatible = "fixed-factor-clock";
1249                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1250                         #clock-cells = <0>;
1251                         clock-div = <48>;
1252                         clock-mult = <1>;
1253                 };
1254                 m2_clk: m2 {
1255                         compatible = "fixed-factor-clock";
1256                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1257                         #clock-cells = <0>;
1258                         clock-div = <8>;
1259                         clock-mult = <1>;
1260                 };
1261                 rclk_clk: rclk {
1262                         compatible = "fixed-factor-clock";
1263                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1264                         #clock-cells = <0>;
1265                         clock-div = <(48 * 1024)>;
1266                         clock-mult = <1>;
1267                 };
1268                 oscclk_clk: oscclk {
1269                         compatible = "fixed-factor-clock";
1270                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1271                         #clock-cells = <0>;
1272                         clock-div = <(12 * 1024)>;
1273                         clock-mult = <1>;
1274                 };
1275                 zb3_clk: zb3 {
1276                         compatible = "fixed-factor-clock";
1277                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1278                         #clock-cells = <0>;
1279                         clock-div = <4>;
1280                         clock-mult = <1>;
1281                 };
1282                 zb3d2_clk: zb3d2 {
1283                         compatible = "fixed-factor-clock";
1284                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1285                         #clock-cells = <0>;
1286                         clock-div = <8>;
1287                         clock-mult = <1>;
1288                 };
1289                 ddr_clk: ddr {
1290                         compatible = "fixed-factor-clock";
1291                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1292                         #clock-cells = <0>;
1293                         clock-div = <8>;
1294                         clock-mult = <1>;
1295                 };
1296                 mp_clk: mp {
1297                         compatible = "fixed-factor-clock";
1298                         clocks = <&pll1_div2_clk>;
1299                         #clock-cells = <0>;
1300                         clock-div = <15>;
1301                         clock-mult = <1>;
1302                 };
1303                 cp_clk: cp {
1304                         compatible = "fixed-factor-clock";
1305                         clocks = <&extal_clk>;
1306                         #clock-cells = <0>;
1307                         clock-div = <2>;
1308                         clock-mult = <1>;
1309                 };
1310
1311                 /* Gate clocks */
1312                 mstp0_clks: mstp0_clks@e6150130 {
1313                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1314                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1315                         clocks = <&mp_clk>;
1316                         #clock-cells = <1>;
1317                         clock-indices = <R8A7791_CLK_MSIOF0>;
1318                         clock-output-names = "msiof0";
1319                 };
1320                 mstp1_clks: mstp1_clks@e6150134 {
1321                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1322                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1323                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1324                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1325                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1326                                  <&zs_clk>;
1327                         #clock-cells = <1>;
1328                         clock-indices = <
1329                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1330                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1331                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1332                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1333                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1334                                 R8A7791_CLK_VSP1_S
1335                         >;
1336                         clock-output-names =
1337                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1338                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1339                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1340                 };
1341                 mstp2_clks: mstp2_clks@e6150138 {
1342                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1343                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1344                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1345                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1346                                  <&zs_clk>, <&zs_clk>;
1347                         #clock-cells = <1>;
1348                         clock-indices = <
1349                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1350                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1351                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1352                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1353                         >;
1354                         clock-output-names =
1355                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1356                                 "scifb1", "msiof1", "scifb2",
1357                                 "sys-dmac1", "sys-dmac0";
1358                 };
1359                 mstp3_clks: mstp3_clks@e615013c {
1360                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1361                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1362                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1363                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1364                                  <&hp_clk>, <&hp_clk>;
1365                         #clock-cells = <1>;
1366                         clock-indices = <
1367                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1368                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1369                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1370                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1371                         >;
1372                         clock-output-names =
1373                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1374                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1375                                 "usbdmac0", "usbdmac1";
1376                 };
1377                 mstp4_clks: mstp4_clks@e6150140 {
1378                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1379                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1380                         clocks = <&cp_clk>, <&zs_clk>;
1381                         #clock-cells = <1>;
1382                         clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>;
1383                         clock-output-names = "irqc", "intc-sys";
1384                 };
1385                 mstp5_clks: mstp5_clks@e6150144 {
1386                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1387                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1388                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1389                                  <&extal_clk>, <&p_clk>;
1390                         #clock-cells = <1>;
1391                         clock-indices = <
1392                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1393                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1394                                 R8A7791_CLK_PWM
1395                         >;
1396                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1397                                              "thermal", "pwm";
1398                 };
1399                 mstp7_clks: mstp7_clks@e615014c {
1400                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1401                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1402                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1403                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1404                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1405                         #clock-cells = <1>;
1406                         clock-indices = <
1407                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1408                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1409                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1410                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1411                                 R8A7791_CLK_LVDS0
1412                         >;
1413                         clock-output-names =
1414                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1415                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1416                 };
1417                 mstp8_clks: mstp8_clks@e6150990 {
1418                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1419                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1420                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1421                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1422                                  <&zs_clk>;
1423                         #clock-cells = <1>;
1424                         clock-indices = <
1425                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1426                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1427                                 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1428                                 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1429                         >;
1430                         clock-output-names =
1431                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1432                                 "etheravb", "ether", "sata1", "sata0";
1433                 };
1434                 mstp9_clks: mstp9_clks@e6150994 {
1435                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1436                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1437                         clocks = <&p_clk>,
1438                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1439                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1440                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1441                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1442                                  <&hp_clk>, <&hp_clk>;
1443                         #clock-cells = <1>;
1444                         clock-indices = <
1445                                 R8A7791_CLK_GYROADC
1446                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1447                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1448                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1449                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1450                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1451                         >;
1452                         clock-output-names =
1453                                 "gyroadc",
1454                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1455                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1456                                 "i2c1", "i2c0";
1457                 };
1458                 mstp10_clks: mstp10_clks@e6150998 {
1459                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1460                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1461                         clocks = <&p_clk>,
1462                                 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1463                                 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1464                                 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1465                                 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1466                                 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1467                                 <&p_clk>,
1468                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1469                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1470                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1471                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1472                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1473                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1474                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1475
1476                         #clock-cells = <1>;
1477                         clock-indices = <
1478                                 R8A7791_CLK_SSI_ALL
1479                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1480                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1481                                 R8A7791_CLK_SCU_ALL
1482                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1483                                 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1484                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1485                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1486                         >;
1487                         clock-output-names =
1488                                 "ssi-all",
1489                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1490                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1491                                 "scu-all",
1492                                 "scu-dvc1", "scu-dvc0",
1493                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1494                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1495                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1496                 };
1497                 mstp11_clks: mstp11_clks@e615099c {
1498                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1499                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1500                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1501                         #clock-cells = <1>;
1502                         clock-indices = <
1503                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1504                         >;
1505                         clock-output-names = "scifa3", "scifa4", "scifa5";
1506                 };
1507         };
1508
1509         rst: reset-controller@e6160000 {
1510                 compatible = "renesas,r8a7791-rst";
1511                 reg = <0 0xe6160000 0 0x0100>;
1512         };
1513
1514         prr: chipid@ff000044 {
1515                 compatible = "renesas,prr";
1516                 reg = <0 0xff000044 0 4>;
1517         };
1518
1519         sysc: system-controller@e6180000 {
1520                 compatible = "renesas,r8a7791-sysc";
1521                 reg = <0 0xe6180000 0 0x0200>;
1522                 #power-domain-cells = <1>;
1523         };
1524
1525         qspi: spi@e6b10000 {
1526                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1527                 reg = <0 0xe6b10000 0 0x2c>;
1528                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1529                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1530                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1531                        <&dmac1 0x17>, <&dmac1 0x18>;
1532                 dma-names = "tx", "rx", "tx", "rx";
1533                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1534                 num-cs = <1>;
1535                 #address-cells = <1>;
1536                 #size-cells = <0>;
1537                 status = "disabled";
1538         };
1539
1540         msiof0: spi@e6e20000 {
1541                 compatible = "renesas,msiof-r8a7791",
1542                              "renesas,rcar-gen2-msiof";
1543                 reg = <0 0xe6e20000 0 0x0064>;
1544                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1545                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1546                 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1547                        <&dmac1 0x51>, <&dmac1 0x52>;
1548                 dma-names = "tx", "rx", "tx", "rx";
1549                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1550                 #address-cells = <1>;
1551                 #size-cells = <0>;
1552                 status = "disabled";
1553         };
1554
1555         msiof1: spi@e6e10000 {
1556                 compatible = "renesas,msiof-r8a7791",
1557                              "renesas,rcar-gen2-msiof";
1558                 reg = <0 0xe6e10000 0 0x0064>;
1559                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1560                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1561                 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1562                        <&dmac1 0x55>, <&dmac1 0x56>;
1563                 dma-names = "tx", "rx", "tx", "rx";
1564                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1565                 #address-cells = <1>;
1566                 #size-cells = <0>;
1567                 status = "disabled";
1568         };
1569
1570         msiof2: spi@e6e00000 {
1571                 compatible = "renesas,msiof-r8a7791",
1572                              "renesas,rcar-gen2-msiof";
1573                 reg = <0 0xe6e00000 0 0x0064>;
1574                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1575                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1576                 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1577                        <&dmac1 0x41>, <&dmac1 0x42>;
1578                 dma-names = "tx", "rx", "tx", "rx";
1579                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1580                 #address-cells = <1>;
1581                 #size-cells = <0>;
1582                 status = "disabled";
1583         };
1584
1585         xhci: usb@ee000000 {
1586                 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1587                 reg = <0 0xee000000 0 0xc00>;
1588                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1589                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1590                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1591                 phys = <&usb2 1>;
1592                 phy-names = "usb";
1593                 status = "disabled";
1594         };
1595
1596         pci0: pci@ee090000 {
1597                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1598                 device_type = "pci";
1599                 reg = <0 0xee090000 0 0xc00>,
1600                       <0 0xee080000 0 0x1100>;
1601                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1602                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1603                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1604                 status = "disabled";
1605
1606                 bus-range = <0 0>;
1607                 #address-cells = <3>;
1608                 #size-cells = <2>;
1609                 #interrupt-cells = <1>;
1610                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1611                 interrupt-map-mask = <0xff00 0 0 0x7>;
1612                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1613                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1614                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1615
1616                 usb@1,0 {
1617                         reg = <0x800 0 0 0 0>;
1618                         phys = <&usb0 0>;
1619                         phy-names = "usb";
1620                 };
1621
1622                 usb@2,0 {
1623                         reg = <0x1000 0 0 0 0>;
1624                         phys = <&usb0 0>;
1625                         phy-names = "usb";
1626                 };
1627         };
1628
1629         pci1: pci@ee0d0000 {
1630                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1631                 device_type = "pci";
1632                 reg = <0 0xee0d0000 0 0xc00>,
1633                       <0 0xee0c0000 0 0x1100>;
1634                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1635                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1636                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1637                 status = "disabled";
1638
1639                 bus-range = <1 1>;
1640                 #address-cells = <3>;
1641                 #size-cells = <2>;
1642                 #interrupt-cells = <1>;
1643                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1644                 interrupt-map-mask = <0xff00 0 0 0x7>;
1645                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1646                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1647                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1648
1649                 usb@1,0 {
1650                         reg = <0x10800 0 0 0 0>;
1651                         phys = <&usb2 0>;
1652                         phy-names = "usb";
1653                 };
1654
1655                 usb@2,0 {
1656                         reg = <0x11000 0 0 0 0>;
1657                         phys = <&usb2 0>;
1658                         phy-names = "usb";
1659                 };
1660         };
1661
1662         pciec: pcie@fe000000 {
1663                 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
1664                 reg = <0 0xfe000000 0 0x80000>;
1665                 #address-cells = <3>;
1666                 #size-cells = <2>;
1667                 bus-range = <0x00 0xff>;
1668                 device_type = "pci";
1669                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1670                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1671                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1672                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1673                 /* Map all possible DDR as inbound ranges */
1674                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1675                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1676                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1677                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1678                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1679                 #interrupt-cells = <1>;
1680                 interrupt-map-mask = <0 0 0 0>;
1681                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1682                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1683                 clock-names = "pcie", "pcie_bus";
1684                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1685                 status = "disabled";
1686         };
1687
1688         ipmmu_sy0: mmu@e6280000 {
1689                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1690                 reg = <0 0xe6280000 0 0x1000>;
1691                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1692                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1693                 #iommu-cells = <1>;
1694                 status = "disabled";
1695         };
1696
1697         ipmmu_sy1: mmu@e6290000 {
1698                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1699                 reg = <0 0xe6290000 0 0x1000>;
1700                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1701                 #iommu-cells = <1>;
1702                 status = "disabled";
1703         };
1704
1705         ipmmu_ds: mmu@e6740000 {
1706                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1707                 reg = <0 0xe6740000 0 0x1000>;
1708                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1709                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1710                 #iommu-cells = <1>;
1711                 status = "disabled";
1712         };
1713
1714         ipmmu_mp: mmu@ec680000 {
1715                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1716                 reg = <0 0xec680000 0 0x1000>;
1717                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1718                 #iommu-cells = <1>;
1719                 status = "disabled";
1720         };
1721
1722         ipmmu_mx: mmu@fe951000 {
1723                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1724                 reg = <0 0xfe951000 0 0x1000>;
1725                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1726                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1727                 #iommu-cells = <1>;
1728                 status = "disabled";
1729         };
1730
1731         ipmmu_rt: mmu@ffc80000 {
1732                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1733                 reg = <0 0xffc80000 0 0x1000>;
1734                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1735                 #iommu-cells = <1>;
1736                 status = "disabled";
1737         };
1738
1739         ipmmu_gp: mmu@e62a0000 {
1740                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1741                 reg = <0 0xe62a0000 0 0x1000>;
1742                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1743                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1744                 #iommu-cells = <1>;
1745                 status = "disabled";
1746         };
1747
1748         rcar_sound: sound@ec500000 {
1749                 /*
1750                  * #sound-dai-cells is required
1751                  *
1752                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1753                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1754                  */
1755                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1756                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1757                         <0 0xec5a0000 0 0x100>,  /* ADG */
1758                         <0 0xec540000 0 0x1000>, /* SSIU */
1759                         <0 0xec541000 0 0x280>,  /* SSI */
1760                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1761                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1762
1763                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1764                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1765                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1766                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1767                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1768                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1769                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1770                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1771                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1772                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1773                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1774                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1775                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1776                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1777                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1778                 clock-names = "ssi-all",
1779                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1780                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1781                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1782                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1783                                 "ctu.0", "ctu.1",
1784                                 "mix.0", "mix.1",
1785                                 "dvc.0", "dvc.1",
1786                                 "clk_a", "clk_b", "clk_c", "clk_i";
1787                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1788
1789                 status = "disabled";
1790
1791                 rcar_sound,dvc {
1792                         dvc0: dvc-0 {
1793                                 dmas = <&audma1 0xbc>;
1794                                 dma-names = "tx";
1795                         };
1796                         dvc1: dvc-1 {
1797                                 dmas = <&audma1 0xbe>;
1798                                 dma-names = "tx";
1799                         };
1800                 };
1801
1802                 rcar_sound,mix {
1803                         mix0: mix-0 { };
1804                         mix1: mix-1 { };
1805                 };
1806
1807                 rcar_sound,ctu {
1808                         ctu00: ctu-0 { };
1809                         ctu01: ctu-1 { };
1810                         ctu02: ctu-2 { };
1811                         ctu03: ctu-3 { };
1812                         ctu10: ctu-4 { };
1813                         ctu11: ctu-5 { };
1814                         ctu12: ctu-6 { };
1815                         ctu13: ctu-7 { };
1816                 };
1817
1818                 rcar_sound,src {
1819                         src0: src-0 {
1820                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1821                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1822                                 dma-names = "rx", "tx";
1823                         };
1824                         src1: src-1 {
1825                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1826                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1827                                 dma-names = "rx", "tx";
1828                         };
1829                         src2: src-2 {
1830                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1831                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1832                                 dma-names = "rx", "tx";
1833                         };
1834                         src3: src-3 {
1835                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1836                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1837                                 dma-names = "rx", "tx";
1838                         };
1839                         src4: src-4 {
1840                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1841                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1842                                 dma-names = "rx", "tx";
1843                         };
1844                         src5: src-5 {
1845                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1846                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1847                                 dma-names = "rx", "tx";
1848                         };
1849                         src6: src-6 {
1850                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1851                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1852                                 dma-names = "rx", "tx";
1853                         };
1854                         src7: src-7 {
1855                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1856                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1857                                 dma-names = "rx", "tx";
1858                         };
1859                         src8: src-8 {
1860                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1861                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1862                                 dma-names = "rx", "tx";
1863                         };
1864                         src9: src-9 {
1865                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1866                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1867                                 dma-names = "rx", "tx";
1868                         };
1869                 };
1870
1871                 rcar_sound,ssi {
1872                         ssi0: ssi-0 {
1873                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1874                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1875                                 dma-names = "rx", "tx", "rxu", "txu";
1876                         };
1877                         ssi1: ssi-1 {
1878                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1879                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1880                                 dma-names = "rx", "tx", "rxu", "txu";
1881                         };
1882                         ssi2: ssi-2 {
1883                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1884                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1885                                 dma-names = "rx", "tx", "rxu", "txu";
1886                         };
1887                         ssi3: ssi-3 {
1888                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1889                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1890                                 dma-names = "rx", "tx", "rxu", "txu";
1891                         };
1892                         ssi4: ssi-4 {
1893                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1894                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1895                                 dma-names = "rx", "tx", "rxu", "txu";
1896                         };
1897                         ssi5: ssi-5 {
1898                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1899                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1900                                 dma-names = "rx", "tx", "rxu", "txu";
1901                         };
1902                         ssi6: ssi-6 {
1903                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1904                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1905                                 dma-names = "rx", "tx", "rxu", "txu";
1906                         };
1907                         ssi7: ssi-7 {
1908                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1909                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1910                                 dma-names = "rx", "tx", "rxu", "txu";
1911                         };
1912                         ssi8: ssi-8 {
1913                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1914                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1915                                 dma-names = "rx", "tx", "rxu", "txu";
1916                         };
1917                         ssi9: ssi-9 {
1918                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1919                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1920                                 dma-names = "rx", "tx", "rxu", "txu";
1921                         };
1922                 };
1923         };
1924 };