arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  51 #include <dt-bindings/dma/sun4i-a10.h>
  52 #include <dt-bindings/pinctrl/sun4i-a10.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 framebuffer@0 {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  71                                  <&ahb_gates 44>, <&dram_gates 26>;
  72                         status = "disabled";
  73                 };
  74
  75                 framebuffer@1 {
  76                         compatible = "allwinner,simple-framebuffer",
  77                                      "simple-framebuffer";
  78                         allwinner,pipeline = "de_be0-lcd0";
  79                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  80                                  <&dram_gates 26>;
  81                         status = "disabled";
  82                 };
  83
  84                 framebuffer@2 {
  85                         compatible = "allwinner,simple-framebuffer",
  86                                      "simple-framebuffer";
  87                         allwinner,pipeline = "de_be0-lcd0-tve0";
  88                         clocks = <&pll5 1>,
  89                                  <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
  90                                  <&dram_gates 5>, <&dram_gates 26>;
  91                         status = "disabled";
  92                 };
  93         };
  94
  95         cpus {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 cpu0: cpu@0 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <0>;
 103                         clocks = <&cpu>;
 104                         clock-latency = <244144>; /* 8 32k periods */
 105                         operating-points = <
 106                                 /* kHz    uV */
 107                                 960000  1400000
 108                                 912000  1400000
 109                                 864000  1300000
 110                                 720000  1200000
 111                                 528000  1100000
 112                                 312000  1000000
 113                                 144000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                         cooling-min-level = <0>;
 117                         cooling-max-level = <6>;
 118                 };
 119
 120                 cpu@1 {
 121                         compatible = "arm,cortex-a7";
 122                         device_type = "cpu";
 123                         reg = <1>;
 124                 };
 125         };
 126
 127         thermal-zones {
 128                 cpu_thermal {
 129                         /* milliseconds */
 130                         polling-delay-passive = <250>;
 131                         polling-delay = <1000>;
 132                         thermal-sensors = <&rtp>;
 133
 134                         cooling-maps {
 135                                 map0 {
 136                                         trip = <&cpu_alert0>;
 137                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 138                                 };
 139                         };
 140
 141                         trips {
 142                                 cpu_alert0: cpu_alert0 {
 143                                         /* milliCelsius */
 144                                         temperature = <75000>;
 145                                         hysteresis = <2000>;
 146                                         type = "passive";
 147                                 };
 148
 149                                 cpu_crit: cpu_crit {
 150                                         /* milliCelsius */
 151                                         temperature = <100000>;
 152                                         hysteresis = <2000>;
 153                                         type = "critical";
 154                                 };
 155                         };
 156                 };
 157         };
 158
 159         memory {
 160                 reg = <0x40000000 0x80000000>;
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv7-timer";
 165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         pmu {
 172                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 173                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 175         };
 176
 177         clocks {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 osc24M: clk@01c20050 {
 183                         #clock-cells = <0>;
 184                         compatible = "allwinner,sun4i-a10-osc-clk";
 185                         reg = <0x01c20050 0x4>;
 186                         clock-frequency = <24000000>;
 187                         clock-output-names = "osc24M";
 188                 };
 189
 190                 osc3M: osc3M_clk {
 191                         #clock-cells = <0>;
 192                         compatible = "fixed-factor-clock";
 193                         clock-div = <8>;
 194                         clock-mult = <1>;
 195                         clocks = <&osc24M>;
 196                         clock-output-names = "osc3M";
 197                 };
 198
 199                 osc32k: clk@0 {
 200                         #clock-cells = <0>;
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <32768>;
 203                         clock-output-names = "osc32k";
 204                 };
 205
 206                 pll1: clk@01c20000 {
 207                         #clock-cells = <0>;
 208                         compatible = "allwinner,sun4i-a10-pll1-clk";
 209                         reg = <0x01c20000 0x4>;
 210                         clocks = <&osc24M>;
 211                         clock-output-names = "pll1";
 212                 };
 213
 214                 pll2: clk@01c20008 {
 215                         #clock-cells = <1>;
 216                         compatible = "allwinner,sun4i-a10-pll2-clk";
 217                         reg = <0x01c20008 0x8>;
 218                         clocks = <&osc24M>;
 219                         clock-output-names = "pll2-1x", "pll2-2x",
 220                                              "pll2-4x", "pll2-8x";
 221                 };
 222
 223                 pll3: clk@01c20010 {
 224                         #clock-cells = <0>;
 225                         compatible = "allwinner,sun4i-a10-pll3-clk";
 226                         reg = <0x01c20010 0x4>;
 227                         clocks = <&osc3M>;
 228                         clock-output-names = "pll3";
 229                 };
 230
 231                 pll3x2: pll3x2_clk {
 232                         #clock-cells = <0>;
 233                         compatible = "fixed-factor-clock";
 234                         clock-div = <1>;
 235                         clock-mult = <2>;
 236                         clock-output-names = "pll3-2x";
 237                 };
 238
 239                 pll4: clk@01c20018 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun7i-a20-pll4-clk";
 242                         reg = <0x01c20018 0x4>;
 243                         clocks = <&osc24M>;
 244                         clock-output-names = "pll4";
 245                 };
 246
 247                 pll5: clk@01c20020 {
 248                         #clock-cells = <1>;
 249                         compatible = "allwinner,sun4i-a10-pll5-clk";
 250                         reg = <0x01c20020 0x4>;
 251                         clocks = <&osc24M>;
 252                         clock-output-names = "pll5_ddr", "pll5_other";
 253                 };
 254
 255                 pll6: clk@01c20028 {
 256                         #clock-cells = <1>;
 257                         compatible = "allwinner,sun4i-a10-pll6-clk";
 258                         reg = <0x01c20028 0x4>;
 259                         clocks = <&osc24M>;
 260                         clock-output-names = "pll6_sata", "pll6_other", "pll6",
 261                                              "pll6_div_4";
 262                 };
 263
 264                 pll7: clk@01c20030 {
 265                         #clock-cells = <0>;
 266                         compatible = "allwinner,sun4i-a10-pll3-clk";
 267                         reg = <0x01c20030 0x4>;
 268                         clocks = <&osc3M>;
 269                         clock-output-names = "pll7";
 270                 };
 271
 272                 pll7x2: pll7x2_clk {
 273                         #clock-cells = <0>;
 274                         compatible = "fixed-factor-clock";
 275                         clock-div = <1>;
 276                         clock-mult = <2>;
 277                         clock-output-names = "pll7-2x";
 278                 };
 279
 280                 pll8: clk@01c20040 {
 281                         #clock-cells = <0>;
 282                         compatible = "allwinner,sun7i-a20-pll4-clk";
 283                         reg = <0x01c20040 0x4>;
 284                         clocks = <&osc24M>;
 285                         clock-output-names = "pll8";
 286                 };
 287
 288                 cpu: cpu@01c20054 {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun4i-a10-cpu-clk";
 291                         reg = <0x01c20054 0x4>;
 292                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 293                         clock-output-names = "cpu";
 294                 };
 295
 296                 axi: axi@01c20054 {
 297                         #clock-cells = <0>;
 298                         compatible = "allwinner,sun4i-a10-axi-clk";
 299                         reg = <0x01c20054 0x4>;
 300                         clocks = <&cpu>;
 301                         clock-output-names = "axi";
 302                 };
 303
 304                 ahb: ahb@01c20054 {
 305                         #clock-cells = <0>;
 306                         compatible = "allwinner,sun5i-a13-ahb-clk";
 307                         reg = <0x01c20054 0x4>;
 308                         clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 309                         clock-output-names = "ahb";
 310                         /*
 311                          * Use PLL6 as parent, instead of CPU/AXI
 312                          * which has rate changes due to cpufreq
 313                          */
 314                         assigned-clocks = <&ahb>;
 315                         assigned-clock-parents = <&pll6 3>;
 316                 };
 317
 318                 ahb_gates: clk@01c20060 {
 319                         #clock-cells = <1>;
 320                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 321                         reg = <0x01c20060 0x8>;
 322                         clocks = <&ahb>;
 323                         clock-indices = <0>, <1>,
 324                                         <2>, <3>, <4>,
 325                                         <5>, <6>, <7>, <8>,
 326                                         <9>, <10>, <11>, <12>,
 327                                         <13>, <14>, <16>,
 328                                         <17>, <18>, <20>, <21>,
 329                                         <22>, <23>, <25>,
 330                                         <28>, <32>, <33>, <34>,
 331                                         <35>, <36>, <37>, <40>,
 332                                         <41>, <42>, <43>,
 333                                         <44>, <45>, <46>,
 334                                         <47>, <49>, <50>,
 335                                         <52>;
 336                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 337                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 338                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 339                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 340                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 341                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 342                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 343                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 344                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 345                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 346                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 347                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 348                                 "ahb_mali";
 349                 };
 350
 351                 apb0: apb0@01c20054 {
 352                         #clock-cells = <0>;
 353                         compatible = "allwinner,sun4i-a10-apb0-clk";
 354                         reg = <0x01c20054 0x4>;
 355                         clocks = <&ahb>;
 356                         clock-output-names = "apb0";
 357                 };
 358
 359                 apb0_gates: clk@01c20068 {
 360                         #clock-cells = <1>;
 361                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 362                         reg = <0x01c20068 0x4>;
 363                         clocks = <&apb0>;
 364                         clock-indices = <0>, <1>,
 365                                         <2>, <3>, <4>,
 366                                         <5>, <6>, <7>,
 367                                         <8>, <10>;
 368                         clock-output-names = "apb0_codec", "apb0_spdif",
 369                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 370                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 371                                 "apb0_iis2", "apb0_keypad";
 372                 };
 373
 374                 apb1: clk@01c20058 {
 375                         #clock-cells = <0>;
 376                         compatible = "allwinner,sun4i-a10-apb1-clk";
 377                         reg = <0x01c20058 0x4>;
 378                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 379                         clock-output-names = "apb1";
 380                 };
 381
 382                 apb1_gates: clk@01c2006c {
 383                         #clock-cells = <1>;
 384                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 385                         reg = <0x01c2006c 0x4>;
 386                         clocks = <&apb1>;
 387                         clock-indices = <0>, <1>,
 388                                         <2>, <3>, <4>,
 389                                         <5>, <6>, <7>,
 390                                         <15>, <16>, <17>,
 391                                         <18>, <19>, <20>,
 392                                         <21>, <22>, <23>;
 393                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 394                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 395                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 396                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 397                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 398                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 399                 };
 400
 401                 nand_clk: clk@01c20080 {
 402                         #clock-cells = <0>;
 403                         compatible = "allwinner,sun4i-a10-mod0-clk";
 404                         reg = <0x01c20080 0x4>;
 405                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 406                         clock-output-names = "nand";
 407                 };
 408
 409                 ms_clk: clk@01c20084 {
 410                         #clock-cells = <0>;
 411                         compatible = "allwinner,sun4i-a10-mod0-clk";
 412                         reg = <0x01c20084 0x4>;
 413                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 414                         clock-output-names = "ms";
 415                 };
 416
 417                 mmc0_clk: clk@01c20088 {
 418                         #clock-cells = <1>;
 419                         compatible = "allwinner,sun4i-a10-mmc-clk";
 420                         reg = <0x01c20088 0x4>;
 421                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 422                         clock-output-names = "mmc0",
 423                                              "mmc0_output",
 424                                              "mmc0_sample";
 425                 };
 426
 427                 mmc1_clk: clk@01c2008c {
 428                         #clock-cells = <1>;
 429                         compatible = "allwinner,sun4i-a10-mmc-clk";
 430                         reg = <0x01c2008c 0x4>;
 431                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 432                         clock-output-names = "mmc1",
 433                                              "mmc1_output",
 434                                              "mmc1_sample";
 435                 };
 436
 437                 mmc2_clk: clk@01c20090 {
 438                         #clock-cells = <1>;
 439                         compatible = "allwinner,sun4i-a10-mmc-clk";
 440                         reg = <0x01c20090 0x4>;
 441                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 442                         clock-output-names = "mmc2",
 443                                              "mmc2_output",
 444                                              "mmc2_sample";
 445                 };
 446
 447                 mmc3_clk: clk@01c20094 {
 448                         #clock-cells = <1>;
 449                         compatible = "allwinner,sun4i-a10-mmc-clk";
 450                         reg = <0x01c20094 0x4>;
 451                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 452                         clock-output-names = "mmc3",
 453                                              "mmc3_output",
 454                                              "mmc3_sample";
 455                 };
 456
 457                 ts_clk: clk@01c20098 {
 458                         #clock-cells = <0>;
 459                         compatible = "allwinner,sun4i-a10-mod0-clk";
 460                         reg = <0x01c20098 0x4>;
 461                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 462                         clock-output-names = "ts";
 463                 };
 464
 465                 ss_clk: clk@01c2009c {
 466                         #clock-cells = <0>;
 467                         compatible = "allwinner,sun4i-a10-mod0-clk";
 468                         reg = <0x01c2009c 0x4>;
 469                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 470                         clock-output-names = "ss";
 471                 };
 472
 473                 spi0_clk: clk@01c200a0 {
 474                         #clock-cells = <0>;
 475                         compatible = "allwinner,sun4i-a10-mod0-clk";
 476                         reg = <0x01c200a0 0x4>;
 477                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 478                         clock-output-names = "spi0";
 479                 };
 480
 481                 spi1_clk: clk@01c200a4 {
 482                         #clock-cells = <0>;
 483                         compatible = "allwinner,sun4i-a10-mod0-clk";
 484                         reg = <0x01c200a4 0x4>;
 485                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 486                         clock-output-names = "spi1";
 487                 };
 488
 489                 spi2_clk: clk@01c200a8 {
 490                         #clock-cells = <0>;
 491                         compatible = "allwinner,sun4i-a10-mod0-clk";
 492                         reg = <0x01c200a8 0x4>;
 493                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 494                         clock-output-names = "spi2";
 495                 };
 496
 497                 pata_clk: clk@01c200ac {
 498                         #clock-cells = <0>;
 499                         compatible = "allwinner,sun4i-a10-mod0-clk";
 500                         reg = <0x01c200ac 0x4>;
 501                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 502                         clock-output-names = "pata";
 503                 };
 504
 505                 ir0_clk: clk@01c200b0 {
 506                         #clock-cells = <0>;
 507                         compatible = "allwinner,sun4i-a10-mod0-clk";
 508                         reg = <0x01c200b0 0x4>;
 509                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 510                         clock-output-names = "ir0";
 511                 };
 512
 513                 ir1_clk: clk@01c200b4 {
 514                         #clock-cells = <0>;
 515                         compatible = "allwinner,sun4i-a10-mod0-clk";
 516                         reg = <0x01c200b4 0x4>;
 517                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 518                         clock-output-names = "ir1";
 519                 };
 520
 521                 spdif_clk: clk@01c200c0 {
 522                         #clock-cells = <0>;
 523                         compatible = "allwinner,sun4i-a10-mod1-clk";
 524                         reg = <0x01c200c0 0x4>;
 525                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 526                                  <&pll2 SUN4I_A10_PLL2_4X>,
 527                                  <&pll2 SUN4I_A10_PLL2_2X>,
 528                                  <&pll2 SUN4I_A10_PLL2_1X>;
 529                         clock-output-names = "spdif";
 530                 };
 531
 532                 keypad_clk: clk@01c200c4 {
 533                         #clock-cells = <0>;
 534                         compatible = "allwinner,sun4i-a10-mod0-clk";
 535                         reg = <0x01c200c4 0x4>;
 536                         clocks = <&osc24M>;
 537                         clock-output-names = "keypad";
 538                 };
 539
 540                 usb_clk: clk@01c200cc {
 541                         #clock-cells = <1>;
 542                         #reset-cells = <1>;
 543                         compatible = "allwinner,sun4i-a10-usb-clk";
 544                         reg = <0x01c200cc 0x4>;
 545                         clocks = <&pll6 1>;
 546                         clock-output-names = "usb_ohci0", "usb_ohci1",
 547                                              "usb_phy";
 548                 };
 549
 550                 spi3_clk: clk@01c200d4 {
 551                         #clock-cells = <0>;
 552                         compatible = "allwinner,sun4i-a10-mod0-clk";
 553                         reg = <0x01c200d4 0x4>;
 554                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 555                         clock-output-names = "spi3";
 556                 };
 557
 558                 dram_gates: clk@01c20100 {
 559                         #clock-cells = <1>;
 560                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 561                         reg = <0x01c20100 0x4>;
 562                         clocks = <&pll5 0>;
 563                         clock-indices = <0>,
 564                                         <1>, <2>,
 565                                         <3>,
 566                                         <4>,
 567                                         <5>, <6>,
 568                                         <15>,
 569                                         <24>, <25>,
 570                                         <26>, <27>,
 571                                         <28>, <29>;
 572                         clock-output-names = "dram_ve",
 573                                              "dram_csi0", "dram_csi1",
 574                                              "dram_ts",
 575                                              "dram_tvd",
 576                                              "dram_tve0", "dram_tve1",
 577                                              "dram_output",
 578                                              "dram_de_fe1", "dram_de_fe0",
 579                                              "dram_de_be0", "dram_de_be1",
 580                                              "dram_de_mp", "dram_ace";
 581                 };
 582
 583                 ve_clk: clk@01c2013c {
 584                         #clock-cells = <0>;
 585                         #reset-cells = <0>;
 586                         compatible = "allwinner,sun4i-a10-ve-clk";
 587                         reg = <0x01c2013c 0x4>;
 588                         clocks = <&pll4>;
 589                         clock-output-names = "ve";
 590                 };
 591
 592                 codec_clk: clk@01c20140 {
 593                         #clock-cells = <0>;
 594                         compatible = "allwinner,sun4i-a10-codec-clk";
 595                         reg = <0x01c20140 0x4>;
 596                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 597                         clock-output-names = "codec";
 598                 };
 599
 600                 mbus_clk: clk@01c2015c {
 601                         #clock-cells = <0>;
 602                         compatible = "allwinner,sun5i-a13-mbus-clk";
 603                         reg = <0x01c2015c 0x4>;
 604                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 605                         clock-output-names = "mbus";
 606                 };
 607
 608                 /*
 609                  * The following two are dummy clocks, placeholders
 610                  * used in the gmac_tx clock. The gmac driver will
 611                  * choose one parent depending on the PHY interface
 612                  * mode, using clk_set_rate auto-reparenting.
 613                  *
 614                  * The actual TX clock rate is not controlled by the
 615                  * gmac_tx clock.
 616                  */
 617                 mii_phy_tx_clk: clk@2 {
 618                         #clock-cells = <0>;
 619                         compatible = "fixed-clock";
 620                         clock-frequency = <25000000>;
 621                         clock-output-names = "mii_phy_tx";
 622                 };
 623
 624                 gmac_int_tx_clk: clk@3 {
 625                         #clock-cells = <0>;
 626                         compatible = "fixed-clock";
 627                         clock-frequency = <125000000>;
 628                         clock-output-names = "gmac_int_tx";
 629                 };
 630
 631                 gmac_tx_clk: clk@01c20164 {
 632                         #clock-cells = <0>;
 633                         compatible = "allwinner,sun7i-a20-gmac-clk";
 634                         reg = <0x01c20164 0x4>;
 635                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 636                         clock-output-names = "gmac_tx";
 637                 };
 638
 639                 /*
 640                  * Dummy clock used by output clocks
 641                  */
 642                 osc24M_32k: clk@1 {
 643                         #clock-cells = <0>;
 644                         compatible = "fixed-factor-clock";
 645                         clock-div = <750>;
 646                         clock-mult = <1>;
 647                         clocks = <&osc24M>;
 648                         clock-output-names = "osc24M_32k";
 649                 };
 650
 651                 clk_out_a: clk@01c201f0 {
 652                         #clock-cells = <0>;
 653                         compatible = "allwinner,sun7i-a20-out-clk";
 654                         reg = <0x01c201f0 0x4>;
 655                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 656                         clock-output-names = "clk_out_a";
 657                 };
 658
 659                 clk_out_b: clk@01c201f4 {
 660                         #clock-cells = <0>;
 661                         compatible = "allwinner,sun7i-a20-out-clk";
 662                         reg = <0x01c201f4 0x4>;
 663                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 664                         clock-output-names = "clk_out_b";
 665                 };
 666         };
 667
 668         soc@01c00000 {
 669                 compatible = "simple-bus";
 670                 #address-cells = <1>;
 671                 #size-cells = <1>;
 672                 ranges;
 673
 674                 sram-controller@01c00000 {
 675                         compatible = "allwinner,sun4i-a10-sram-controller";
 676                         reg = <0x01c00000 0x30>;
 677                         #address-cells = <1>;
 678                         #size-cells = <1>;
 679                         ranges;
 680
 681                         sram_a: sram@00000000 {
 682                                 compatible = "mmio-sram";
 683                                 reg = <0x00000000 0xc000>;
 684                                 #address-cells = <1>;
 685                                 #size-cells = <1>;
 686                                 ranges = <0 0x00000000 0xc000>;
 687
 688                                 emac_sram: sram-section@8000 {
 689                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 690                                         reg = <0x8000 0x4000>;
 691                                         status = "disabled";
 692                                 };
 693                         };
 694
 695                         sram_d: sram@00010000 {
 696                                 compatible = "mmio-sram";
 697                                 reg = <0x00010000 0x1000>;
 698                                 #address-cells = <1>;
 699                                 #size-cells = <1>;
 700                                 ranges = <0 0x00010000 0x1000>;
 701
 702                                 otg_sram: sram-section@0000 {
 703                                         compatible = "allwinner,sun4i-a10-sram-d";
 704                                         reg = <0x0000 0x1000>;
 705                                         status = "disabled";
 706                                 };
 707                         };
 708                 };
 709
 710                 nmi_intc: interrupt-controller@01c00030 {
 711                         compatible = "allwinner,sun7i-a20-sc-nmi";
 712                         interrupt-controller;
 713                         #interrupt-cells = <2>;
 714                         reg = <0x01c00030 0x0c>;
 715                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 716                 };
 717
 718                 dma: dma-controller@01c02000 {
 719                         compatible = "allwinner,sun4i-a10-dma";
 720                         reg = <0x01c02000 0x1000>;
 721                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&ahb_gates 6>;
 723                         #dma-cells = <2>;
 724                 };
 725
 726                 spi0: spi@01c05000 {
 727                         compatible = "allwinner,sun4i-a10-spi";
 728                         reg = <0x01c05000 0x1000>;
 729                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 731                         clock-names = "ahb", "mod";
 732                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 733                                <&dma SUN4I_DMA_DEDICATED 26>;
 734                         dma-names = "rx", "tx";
 735                         status = "disabled";
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738                 };
 739
 740                 spi1: spi@01c06000 {
 741                         compatible = "allwinner,sun4i-a10-spi";
 742                         reg = <0x01c06000 0x1000>;
 743                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 745                         clock-names = "ahb", "mod";
 746                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 747                                <&dma SUN4I_DMA_DEDICATED 8>;
 748                         dma-names = "rx", "tx";
 749                         status = "disabled";
 750                         #address-cells = <1>;
 751                         #size-cells = <0>;
 752                 };
 753
 754                 emac: ethernet@01c0b000 {
 755                         compatible = "allwinner,sun4i-a10-emac";
 756                         reg = <0x01c0b000 0x1000>;
 757                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 758                         clocks = <&ahb_gates 17>;
 759                         allwinner,sram = <&emac_sram 1>;
 760                         status = "disabled";
 761                 };
 762
 763                 mdio: mdio@01c0b080 {
 764                         compatible = "allwinner,sun4i-a10-mdio";
 765                         reg = <0x01c0b080 0x14>;
 766                         status = "disabled";
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769                 };
 770
 771                 mmc0: mmc@01c0f000 {
 772                         compatible = "allwinner,sun5i-a13-mmc";
 773                         reg = <0x01c0f000 0x1000>;
 774                         clocks = <&ahb_gates 8>,
 775                                  <&mmc0_clk 0>,
 776                                  <&mmc0_clk 1>,
 777                                  <&mmc0_clk 2>;
 778                         clock-names = "ahb",
 779                                       "mmc",
 780                                       "output",
 781                                       "sample";
 782                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 783                         status = "disabled";
 784                         #address-cells = <1>;
 785                         #size-cells = <0>;
 786                 };
 787
 788                 mmc1: mmc@01c10000 {
 789                         compatible = "allwinner,sun5i-a13-mmc";
 790                         reg = <0x01c10000 0x1000>;
 791                         clocks = <&ahb_gates 9>,
 792                                  <&mmc1_clk 0>,
 793                                  <&mmc1_clk 1>,
 794                                  <&mmc1_clk 2>;
 795                         clock-names = "ahb",
 796                                       "mmc",
 797                                       "output",
 798                                       "sample";
 799                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 800                         status = "disabled";
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803                 };
 804
 805                 mmc2: mmc@01c11000 {
 806                         compatible = "allwinner,sun5i-a13-mmc";
 807                         reg = <0x01c11000 0x1000>;
 808                         clocks = <&ahb_gates 10>,
 809                                  <&mmc2_clk 0>,
 810                                  <&mmc2_clk 1>,
 811                                  <&mmc2_clk 2>;
 812                         clock-names = "ahb",
 813                                       "mmc",
 814                                       "output",
 815                                       "sample";
 816                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 817                         status = "disabled";
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820                 };
 821
 822                 mmc3: mmc@01c12000 {
 823                         compatible = "allwinner,sun5i-a13-mmc";
 824                         reg = <0x01c12000 0x1000>;
 825                         clocks = <&ahb_gates 11>,
 826                                  <&mmc3_clk 0>,
 827                                  <&mmc3_clk 1>,
 828                                  <&mmc3_clk 2>;
 829                         clock-names = "ahb",
 830                                       "mmc",
 831                                       "output",
 832                                       "sample";
 833                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 834                         status = "disabled";
 835                         #address-cells = <1>;
 836                         #size-cells = <0>;
 837                 };
 838
 839                 usb_otg: usb@01c13000 {
 840                         compatible = "allwinner,sun4i-a10-musb";
 841                         reg = <0x01c13000 0x0400>;
 842                         clocks = <&ahb_gates 0>;
 843                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 844                         interrupt-names = "mc";
 845                         phys = <&usbphy 0>;
 846                         phy-names = "usb";
 847                         extcon = <&usbphy 0>;
 848                         allwinner,sram = <&otg_sram 1>;
 849                         status = "disabled";
 850                 };
 851
 852                 usbphy: phy@01c13400 {
 853                         #phy-cells = <1>;
 854                         compatible = "allwinner,sun7i-a20-usb-phy";
 855                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 856                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 857                         clocks = <&usb_clk 8>;
 858                         clock-names = "usb_phy";
 859                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 860                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 861                         status = "disabled";
 862                 };
 863
 864                 ehci0: usb@01c14000 {
 865                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 866                         reg = <0x01c14000 0x100>;
 867                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 868                         clocks = <&ahb_gates 1>;
 869                         phys = <&usbphy 1>;
 870                         phy-names = "usb";
 871                         status = "disabled";
 872                 };
 873
 874                 ohci0: usb@01c14400 {
 875                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 876                         reg = <0x01c14400 0x100>;
 877                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 878                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 879                         phys = <&usbphy 1>;
 880                         phy-names = "usb";
 881                         status = "disabled";
 882                 };
 883
 884                 crypto: crypto-engine@01c15000 {
 885                         compatible = "allwinner,sun4i-a10-crypto";
 886                         reg = <0x01c15000 0x1000>;
 887                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 888                         clocks = <&ahb_gates 5>, <&ss_clk>;
 889                         clock-names = "ahb", "mod";
 890                 };
 891
 892                 spi2: spi@01c17000 {
 893                         compatible = "allwinner,sun4i-a10-spi";
 894                         reg = <0x01c17000 0x1000>;
 895                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 897                         clock-names = "ahb", "mod";
 898                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 899                                <&dma SUN4I_DMA_DEDICATED 28>;
 900                         dma-names = "rx", "tx";
 901                         status = "disabled";
 902                         #address-cells = <1>;
 903                         #size-cells = <0>;
 904                 };
 905
 906                 ahci: sata@01c18000 {
 907                         compatible = "allwinner,sun4i-a10-ahci";
 908                         reg = <0x01c18000 0x1000>;
 909                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 910                         clocks = <&pll6 0>, <&ahb_gates 25>;
 911                         status = "disabled";
 912                 };
 913
 914                 ehci1: usb@01c1c000 {
 915                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 916                         reg = <0x01c1c000 0x100>;
 917                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 918                         clocks = <&ahb_gates 3>;
 919                         phys = <&usbphy 2>;
 920                         phy-names = "usb";
 921                         status = "disabled";
 922                 };
 923
 924                 ohci1: usb@01c1c400 {
 925                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 926                         reg = <0x01c1c400 0x100>;
 927                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 928                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 929                         phys = <&usbphy 2>;
 930                         phy-names = "usb";
 931                         status = "disabled";
 932                 };
 933
 934                 spi3: spi@01c1f000 {
 935                         compatible = "allwinner,sun4i-a10-spi";
 936                         reg = <0x01c1f000 0x1000>;
 937                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 938                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 939                         clock-names = "ahb", "mod";
 940                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 941                                <&dma SUN4I_DMA_DEDICATED 30>;
 942                         dma-names = "rx", "tx";
 943                         status = "disabled";
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                 };
 947
 948                 pio: pinctrl@01c20800 {
 949                         compatible = "allwinner,sun7i-a20-pinctrl";
 950                         reg = <0x01c20800 0x400>;
 951                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 952                         clocks = <&apb0_gates 5>;
 953                         gpio-controller;
 954                         interrupt-controller;
 955                         #interrupt-cells = <3>;
 956                         #gpio-cells = <3>;
 957
 958                         pwm0_pins_a: pwm0@0 {
 959                                 allwinner,pins = "PB2";
 960                                 allwinner,function = "pwm";
 961                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 962                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 963                         };
 964
 965                         pwm1_pins_a: pwm1@0 {
 966                                 allwinner,pins = "PI3";
 967                                 allwinner,function = "pwm";
 968                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 969                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 970                         };
 971
 972                         uart0_pins_a: uart0@0 {
 973                                 allwinner,pins = "PB22", "PB23";
 974                                 allwinner,function = "uart0";
 975                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 976                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 977                         };
 978
 979                         uart2_pins_a: uart2@0 {
 980                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 981                                 allwinner,function = "uart2";
 982                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 983                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 984                         };
 985
 986                         uart3_pins_a: uart3@0 {
 987                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 988                                 allwinner,function = "uart3";
 989                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 990                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 991                         };
 992
 993                         uart3_pins_b: uart3@1 {
 994                                 allwinner,pins = "PH0", "PH1";
 995                                 allwinner,function = "uart3";
 996                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 997                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 998                         };
 999
1000                         uart4_pins_a: uart4@0 {
1001                                 allwinner,pins = "PG10", "PG11";
1002                                 allwinner,function = "uart4";
1003                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1004                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1005                         };
1006
1007                         uart4_pins_b: uart4@1 {
1008                                 allwinner,pins = "PH4", "PH5";
1009                                 allwinner,function = "uart4";
1010                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1011                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1012                         };
1013
1014                         uart5_pins_a: uart5@0 {
1015                                 allwinner,pins = "PI10", "PI11";
1016                                 allwinner,function = "uart5";
1017                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1018                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1019                         };
1020
1021                         uart6_pins_a: uart6@0 {
1022                                 allwinner,pins = "PI12", "PI13";
1023                                 allwinner,function = "uart6";
1024                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1025                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1026                         };
1027
1028                         uart7_pins_a: uart7@0 {
1029                                 allwinner,pins = "PI20", "PI21";
1030                                 allwinner,function = "uart7";
1031                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1032                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1033                         };
1034
1035                         i2c0_pins_a: i2c0@0 {
1036                                 allwinner,pins = "PB0", "PB1";
1037                                 allwinner,function = "i2c0";
1038                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1039                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1040                         };
1041
1042                         i2c1_pins_a: i2c1@0 {
1043                                 allwinner,pins = "PB18", "PB19";
1044                                 allwinner,function = "i2c1";
1045                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1046                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1047                         };
1048
1049                         i2c2_pins_a: i2c2@0 {
1050                                 allwinner,pins = "PB20", "PB21";
1051                                 allwinner,function = "i2c2";
1052                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1053                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1054                         };
1055
1056                         i2c3_pins_a: i2c3@0 {
1057                                 allwinner,pins = "PI0", "PI1";
1058                                 allwinner,function = "i2c3";
1059                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1060                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1061                         };
1062
1063                         emac_pins_a: emac0@0 {
1064                                 allwinner,pins = "PA0", "PA1", "PA2",
1065                                                 "PA3", "PA4", "PA5", "PA6",
1066                                                 "PA7", "PA8", "PA9", "PA10",
1067                                                 "PA11", "PA12", "PA13", "PA14",
1068                                                 "PA15", "PA16";
1069                                 allwinner,function = "emac";
1070                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1071                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1072                         };
1073
1074                         clk_out_a_pins_a: clk_out_a@0 {
1075                                 allwinner,pins = "PI12";
1076                                 allwinner,function = "clk_out_a";
1077                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1078                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1079                         };
1080
1081                         clk_out_b_pins_a: clk_out_b@0 {
1082                                 allwinner,pins = "PI13";
1083                                 allwinner,function = "clk_out_b";
1084                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1085                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1086                         };
1087
1088                         gmac_pins_mii_a: gmac_mii@0 {
1089                                 allwinner,pins = "PA0", "PA1", "PA2",
1090                                                 "PA3", "PA4", "PA5", "PA6",
1091                                                 "PA7", "PA8", "PA9", "PA10",
1092                                                 "PA11", "PA12", "PA13", "PA14",
1093                                                 "PA15", "PA16";
1094                                 allwinner,function = "gmac";
1095                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1096                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1097                         };
1098
1099                         gmac_pins_rgmii_a: gmac_rgmii@0 {
1100                                 allwinner,pins = "PA0", "PA1", "PA2",
1101                                                 "PA3", "PA4", "PA5", "PA6",
1102                                                 "PA7", "PA8", "PA10",
1103                                                 "PA11", "PA12", "PA13",
1104                                                 "PA15", "PA16";
1105                                 allwinner,function = "gmac";
1106                                 /*
1107                                  * data lines in RGMII mode use DDR mode
1108                                  * and need a higher signal drive strength
1109                                  */
1110                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1111                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1112                         };
1113
1114                         spi0_pins_a: spi0@0 {
1115                                 allwinner,pins = "PI11", "PI12", "PI13";
1116                                 allwinner,function = "spi0";
1117                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1118                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1119                         };
1120
1121                         spi0_cs0_pins_a: spi0_cs0@0 {
1122                                 allwinner,pins = "PI10";
1123                                 allwinner,function = "spi0";
1124                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1125                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1126                         };
1127
1128                         spi0_cs1_pins_a: spi0_cs1@0 {
1129                                 allwinner,pins = "PI14";
1130                                 allwinner,function = "spi0";
1131                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1132                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1133                         };
1134
1135                         spi1_pins_a: spi1@0 {
1136                                 allwinner,pins = "PI17", "PI18", "PI19";
1137                                 allwinner,function = "spi1";
1138                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1139                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1140                         };
1141
1142                         spi1_cs0_pins_a: spi1_cs0@0 {
1143                                 allwinner,pins = "PI16";
1144                                 allwinner,function = "spi1";
1145                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1146                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1147                         };
1148
1149                         spi2_pins_a: spi2@0 {
1150                                 allwinner,pins = "PC20", "PC21", "PC22";
1151                                 allwinner,function = "spi2";
1152                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1153                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1154                         };
1155
1156                         spi2_pins_b: spi2@1 {
1157                                 allwinner,pins = "PB15", "PB16", "PB17";
1158                                 allwinner,function = "spi2";
1159                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1160                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1161                         };
1162
1163                         spi2_cs0_pins_a: spi2_cs0@0 {
1164                                 allwinner,pins = "PC19";
1165                                 allwinner,function = "spi2";
1166                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1167                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1168                         };
1169
1170                         spi2_cs0_pins_b: spi2_cs0@1 {
1171                                 allwinner,pins = "PB14";
1172                                 allwinner,function = "spi2";
1173                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1174                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1175                         };
1176
1177                         mmc0_pins_a: mmc0@0 {
1178                                 allwinner,pins = "PF0", "PF1", "PF2",
1179                                                  "PF3", "PF4", "PF5";
1180                                 allwinner,function = "mmc0";
1181                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1182                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1183                         };
1184
1185                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1186                                 allwinner,pins = "PH1";
1187                                 allwinner,function = "gpio_in";
1188                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1189                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1190                         };
1191
1192                         mmc2_pins_a: mmc2@0 {
1193                                 allwinner,pins = "PC6", "PC7", "PC8",
1194                                                  "PC9", "PC10", "PC11";
1195                                 allwinner,function = "mmc2";
1196                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1197                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1198                         };
1199
1200                         mmc3_pins_a: mmc3@0 {
1201                                 allwinner,pins = "PI4", "PI5", "PI6",
1202                                                  "PI7", "PI8", "PI9";
1203                                 allwinner,function = "mmc3";
1204                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1205                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1206                         };
1207
1208                         ir0_rx_pins_a: ir0@0 {
1209                                     allwinner,pins = "PB4";
1210                                     allwinner,function = "ir0";
1211                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1212                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1213                         };
1214
1215                         ir0_tx_pins_a: ir0@1 {
1216                                     allwinner,pins = "PB3";
1217                                     allwinner,function = "ir0";
1218                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1219                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1220                         };
1221
1222                         ir1_rx_pins_a: ir1@0 {
1223                                     allwinner,pins = "PB23";
1224                                     allwinner,function = "ir1";
1225                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1226                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1227                         };
1228
1229                         ir1_tx_pins_a: ir1@1 {
1230                                     allwinner,pins = "PB22";
1231                                     allwinner,function = "ir1";
1232                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1233                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1234                         };
1235
1236                         ps20_pins_a: ps20@0 {
1237                                 allwinner,pins = "PI20", "PI21";
1238                                 allwinner,function = "ps2";
1239                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1240                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1241                         };
1242
1243                         ps21_pins_a: ps21@0 {
1244                                 allwinner,pins = "PH12", "PH13";
1245                                 allwinner,function = "ps2";
1246                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1247                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1248                         };
1249
1250                         spdif_tx_pins_a: spdif@0 {
1251                                 allwinner,pins = "PB13";
1252                                 allwinner,function = "spdif";
1253                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1254                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1255                         };
1256                 };
1257
1258                 timer@01c20c00 {
1259                         compatible = "allwinner,sun4i-a10-timer";
1260                         reg = <0x01c20c00 0x90>;
1261                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1262                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1264                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1267                         clocks = <&osc24M>;
1268                 };
1269
1270                 wdt: watchdog@01c20c90 {
1271                         compatible = "allwinner,sun4i-a10-wdt";
1272                         reg = <0x01c20c90 0x10>;
1273                 };
1274
1275                 rtc: rtc@01c20d00 {
1276                         compatible = "allwinner,sun7i-a20-rtc";
1277                         reg = <0x01c20d00 0x20>;
1278                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1279                 };
1280
1281                 pwm: pwm@01c20e00 {
1282                         compatible = "allwinner,sun7i-a20-pwm";
1283                         reg = <0x01c20e00 0xc>;
1284                         clocks = <&osc24M>;
1285                         #pwm-cells = <3>;
1286                         status = "disabled";
1287                 };
1288
1289                 spdif: spdif@01c21000 {
1290                         #sound-dai-cells = <0>;
1291                         compatible = "allwinner,sun4i-a10-spdif";
1292                         reg = <0x01c21000 0x400>;
1293                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1294                         clocks = <&apb0_gates 1>, <&spdif_clk>;
1295                         clock-names = "apb", "spdif";
1296                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1297                                <&dma SUN4I_DMA_NORMAL 2>;
1298                         dma-names = "rx", "tx";
1299                         status = "disabled";
1300                 };
1301
1302                 ir0: ir@01c21800 {
1303                         compatible = "allwinner,sun4i-a10-ir";
1304                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1305                         clock-names = "apb", "ir";
1306                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1307                         reg = <0x01c21800 0x40>;
1308                         status = "disabled";
1309                 };
1310
1311                 ir1: ir@01c21c00 {
1312                         compatible = "allwinner,sun4i-a10-ir";
1313                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1314                         clock-names = "apb", "ir";
1315                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1316                         reg = <0x01c21c00 0x40>;
1317                         status = "disabled";
1318                 };
1319
1320                 lradc: lradc@01c22800 {
1321                         compatible = "allwinner,sun4i-a10-lradc-keys";
1322                         reg = <0x01c22800 0x100>;
1323                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1324                         status = "disabled";
1325                 };
1326
1327                 codec: codec@01c22c00 {
1328                         #sound-dai-cells = <0>;
1329                         compatible = "allwinner,sun7i-a20-codec";
1330                         reg = <0x01c22c00 0x40>;
1331                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1332                         clocks = <&apb0_gates 0>, <&codec_clk>;
1333                         clock-names = "apb", "codec";
1334                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1335                                <&dma SUN4I_DMA_NORMAL 19>;
1336                         dma-names = "rx", "tx";
1337                         status = "disabled";
1338                 };
1339
1340                 sid: eeprom@01c23800 {
1341                         compatible = "allwinner,sun7i-a20-sid";
1342                         reg = <0x01c23800 0x200>;
1343                 };
1344
1345                 rtp: rtp@01c25000 {
1346                         compatible = "allwinner,sun5i-a13-ts";
1347                         reg = <0x01c25000 0x100>;
1348                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1349                         #thermal-sensor-cells = <0>;
1350                 };
1351
1352                 uart0: serial@01c28000 {
1353                         compatible = "snps,dw-apb-uart";
1354                         reg = <0x01c28000 0x400>;
1355                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1356                         reg-shift = <2>;
1357                         reg-io-width = <4>;
1358                         clocks = <&apb1_gates 16>;
1359                         status = "disabled";
1360                 };
1361
1362                 uart1: serial@01c28400 {
1363                         compatible = "snps,dw-apb-uart";
1364                         reg = <0x01c28400 0x400>;
1365                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1366                         reg-shift = <2>;
1367                         reg-io-width = <4>;
1368                         clocks = <&apb1_gates 17>;
1369                         status = "disabled";
1370                 };
1371
1372                 uart2: serial@01c28800 {
1373                         compatible = "snps,dw-apb-uart";
1374                         reg = <0x01c28800 0x400>;
1375                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1376                         reg-shift = <2>;
1377                         reg-io-width = <4>;
1378                         clocks = <&apb1_gates 18>;
1379                         status = "disabled";
1380                 };
1381
1382                 uart3: serial@01c28c00 {
1383                         compatible = "snps,dw-apb-uart";
1384                         reg = <0x01c28c00 0x400>;
1385                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1386                         reg-shift = <2>;
1387                         reg-io-width = <4>;
1388                         clocks = <&apb1_gates 19>;
1389                         status = "disabled";
1390                 };
1391
1392                 uart4: serial@01c29000 {
1393                         compatible = "snps,dw-apb-uart";
1394                         reg = <0x01c29000 0x400>;
1395                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1396                         reg-shift = <2>;
1397                         reg-io-width = <4>;
1398                         clocks = <&apb1_gates 20>;
1399                         status = "disabled";
1400                 };
1401
1402                 uart5: serial@01c29400 {
1403                         compatible = "snps,dw-apb-uart";
1404                         reg = <0x01c29400 0x400>;
1405                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1406                         reg-shift = <2>;
1407                         reg-io-width = <4>;
1408                         clocks = <&apb1_gates 21>;
1409                         status = "disabled";
1410                 };
1411
1412                 uart6: serial@01c29800 {
1413                         compatible = "snps,dw-apb-uart";
1414                         reg = <0x01c29800 0x400>;
1415                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1416                         reg-shift = <2>;
1417                         reg-io-width = <4>;
1418                         clocks = <&apb1_gates 22>;
1419                         status = "disabled";
1420                 };
1421
1422                 uart7: serial@01c29c00 {
1423                         compatible = "snps,dw-apb-uart";
1424                         reg = <0x01c29c00 0x400>;
1425                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1426                         reg-shift = <2>;
1427                         reg-io-width = <4>;
1428                         clocks = <&apb1_gates 23>;
1429                         status = "disabled";
1430                 };
1431
1432                 i2c0: i2c@01c2ac00 {
1433                         compatible = "allwinner,sun7i-a20-i2c",
1434                                      "allwinner,sun4i-a10-i2c";
1435                         reg = <0x01c2ac00 0x400>;
1436                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1437                         clocks = <&apb1_gates 0>;
1438                         status = "disabled";
1439                         #address-cells = <1>;
1440                         #size-cells = <0>;
1441                 };
1442
1443                 i2c1: i2c@01c2b000 {
1444                         compatible = "allwinner,sun7i-a20-i2c",
1445                                      "allwinner,sun4i-a10-i2c";
1446                         reg = <0x01c2b000 0x400>;
1447                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1448                         clocks = <&apb1_gates 1>;
1449                         status = "disabled";
1450                         #address-cells = <1>;
1451                         #size-cells = <0>;
1452                 };
1453
1454                 i2c2: i2c@01c2b400 {
1455                         compatible = "allwinner,sun7i-a20-i2c",
1456                                      "allwinner,sun4i-a10-i2c";
1457                         reg = <0x01c2b400 0x400>;
1458                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1459                         clocks = <&apb1_gates 2>;
1460                         status = "disabled";
1461                         #address-cells = <1>;
1462                         #size-cells = <0>;
1463                 };
1464
1465                 i2c3: i2c@01c2b800 {
1466                         compatible = "allwinner,sun7i-a20-i2c",
1467                                      "allwinner,sun4i-a10-i2c";
1468                         reg = <0x01c2b800 0x400>;
1469                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&apb1_gates 3>;
1471                         status = "disabled";
1472                         #address-cells = <1>;
1473                         #size-cells = <0>;
1474                 };
1475
1476                 i2c4: i2c@01c2c000 {
1477                         compatible = "allwinner,sun7i-a20-i2c",
1478                                      "allwinner,sun4i-a10-i2c";
1479                         reg = <0x01c2c000 0x400>;
1480                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1481                         clocks = <&apb1_gates 15>;
1482                         status = "disabled";
1483                         #address-cells = <1>;
1484                         #size-cells = <0>;
1485                 };
1486
1487                 gmac: ethernet@01c50000 {
1488                         compatible = "allwinner,sun7i-a20-gmac";
1489                         reg = <0x01c50000 0x10000>;
1490                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1491                         interrupt-names = "macirq";
1492                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1493                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1494                         snps,pbl = <2>;
1495                         snps,fixed-burst;
1496                         snps,force_sf_dma_mode;
1497                         status = "disabled";
1498                         #address-cells = <1>;
1499                         #size-cells = <0>;
1500                 };
1501
1502                 hstimer@01c60000 {
1503                         compatible = "allwinner,sun7i-a20-hstimer";
1504                         reg = <0x01c60000 0x1000>;
1505                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1506                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1507                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1508                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1509                         clocks = <&ahb_gates 28>;
1510                 };
1511
1512                 gic: interrupt-controller@01c81000 {
1513                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1514                         reg = <0x01c81000 0x1000>,
1515                               <0x01c82000 0x1000>,
1516                               <0x01c84000 0x2000>,
1517                               <0x01c86000 0x2000>;
1518                         interrupt-controller;
1519                         #interrupt-cells = <3>;
1520                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1521                 };
1522
1523                 ps20: ps2@01c2a000 {
1524                         compatible = "allwinner,sun4i-a10-ps2";
1525                         reg = <0x01c2a000 0x400>;
1526                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1527                         clocks = <&apb1_gates 6>;
1528                         status = "disabled";
1529                 };
1530
1531                 ps21: ps2@01c2a400 {
1532                         compatible = "allwinner,sun4i-a10-ps2";
1533                         reg = <0x01c2a400 0x400>;
1534                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1535                         clocks = <&apb1_gates 7>;
1536                         status = "disabled";
1537                 };
1538         };
1539 };