arch/arm/boot/dts/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  44 #include <dt-bindings/clock/sun8i-r-ccu.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  47 #include <dt-bindings/reset/sun8i-r-ccu.h>
  48
  49 / {
  50         interrupt-parent = <&gic>;
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         clocks {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 osc24M: osc24M_clk {
  60                         #clock-cells = <0>;
  61                         compatible = "fixed-clock";
  62                         clock-frequency = <24000000>;
  63                         clock-output-names = "osc24M";
  64                 };
  65
  66                 osc32k: osc32k_clk {
  67                         #clock-cells = <0>;
  68                         compatible = "fixed-clock";
  69                         clock-frequency = <32768>;
  70                         clock-output-names = "osc32k";
  71                 };
  72
  73                 iosc: internal-osc-clk {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <16000000>;
  77                         clock-accuracy = <300000000>;
  78                         clock-output-names = "iosc";
  79                 };
  80         };
  81
  82         soc {
  83                 compatible = "simple-bus";
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges;
  87
  88                 syscon: syscon@1c00000 {
  89                         compatible = "allwinner,sun8i-h3-system-controller",
  90                                 "syscon";
  91                         reg = <0x01c00000 0x1000>;
  92                 };
  93
  94                 dma: dma-controller@01c02000 {
  95                         compatible = "allwinner,sun8i-h3-dma";
  96                         reg = <0x01c02000 0x1000>;
  97                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  98                         clocks = <&ccu CLK_BUS_DMA>;
  99                         resets = <&ccu RST_BUS_DMA>;
 100                         #dma-cells = <1>;
 101                 };
 102
 103                 mmc0: mmc@01c0f000 {
 104                         /* compatible and clocks are in per SoC .dtsi file */
 105                         reg = <0x01c0f000 0x1000>;
 106                         resets = <&ccu RST_BUS_MMC0>;
 107                         reset-names = "ahb";
 108                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 109                         status = "disabled";
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                 };
 113
 114                 mmc1: mmc@01c10000 {
 115                         /* compatible and clocks are in per SoC .dtsi file */
 116                         reg = <0x01c10000 0x1000>;
 117                         resets = <&ccu RST_BUS_MMC1>;
 118                         reset-names = "ahb";
 119                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 120                         status = "disabled";
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                 };
 124
 125                 mmc2: mmc@01c11000 {
 126                         /* compatible and clocks are in per SoC .dtsi file */
 127                         reg = <0x01c11000 0x1000>;
 128                         resets = <&ccu RST_BUS_MMC2>;
 129                         reset-names = "ahb";
 130                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 131                         status = "disabled";
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                 };
 135
 136                 usb_otg: usb@01c19000 {
 137                         compatible = "allwinner,sun8i-h3-musb";
 138                         reg = <0x01c19000 0x400>;
 139                         clocks = <&ccu CLK_BUS_OTG>;
 140                         resets = <&ccu RST_BUS_OTG>;
 141                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 142                         interrupt-names = "mc";
 143                         phys = <&usbphy 0>;
 144                         phy-names = "usb";
 145                         extcon = <&usbphy 0>;
 146                         status = "disabled";
 147                 };
 148
 149                 usbphy: phy@01c19400 {
 150                         compatible = "allwinner,sun8i-h3-usb-phy";
 151                         reg = <0x01c19400 0x2c>,
 152                               <0x01c1a800 0x4>,
 153                               <0x01c1b800 0x4>,
 154                               <0x01c1c800 0x4>,
 155                               <0x01c1d800 0x4>;
 156                         reg-names = "phy_ctrl",
 157                                     "pmu0",
 158                                     "pmu1",
 159                                     "pmu2",
 160                                     "pmu3";
 161                         clocks = <&ccu CLK_USB_PHY0>,
 162                                  <&ccu CLK_USB_PHY1>,
 163                                  <&ccu CLK_USB_PHY2>,
 164                                  <&ccu CLK_USB_PHY3>;
 165                         clock-names = "usb0_phy",
 166                                       "usb1_phy",
 167                                       "usb2_phy",
 168                                       "usb3_phy";
 169                         resets = <&ccu RST_USB_PHY0>,
 170                                  <&ccu RST_USB_PHY1>,
 171                                  <&ccu RST_USB_PHY2>,
 172                                  <&ccu RST_USB_PHY3>;
 173                         reset-names = "usb0_reset",
 174                                       "usb1_reset",
 175                                       "usb2_reset",
 176                                       "usb3_reset";
 177                         status = "disabled";
 178                         #phy-cells = <1>;
 179                 };
 180
 181                 ehci0: usb@01c1a000 {
 182                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 183                         reg = <0x01c1a000 0x100>;
 184                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 185                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 186                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 187                         status = "disabled";
 188                 };
 189
 190                 ohci0: usb@01c1a400 {
 191                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 192                         reg = <0x01c1a400 0x100>;
 193                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 195                                  <&ccu CLK_USB_OHCI0>;
 196                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 197                         status = "disabled";
 198                 };
 199
 200                 ehci1: usb@01c1b000 {
 201                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 202                         reg = <0x01c1b000 0x100>;
 203                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 205                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 206                         phys = <&usbphy 1>;
 207                         phy-names = "usb";
 208                         status = "disabled";
 209                 };
 210
 211                 ohci1: usb@01c1b400 {
 212                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 213                         reg = <0x01c1b400 0x100>;
 214                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 216                                  <&ccu CLK_USB_OHCI1>;
 217                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 218                         phys = <&usbphy 1>;
 219                         phy-names = "usb";
 220                         status = "disabled";
 221                 };
 222
 223                 ehci2: usb@01c1c000 {
 224                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 225                         reg = <0x01c1c000 0x100>;
 226                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 227                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 228                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 229                         phys = <&usbphy 2>;
 230                         phy-names = "usb";
 231                         status = "disabled";
 232                 };
 233
 234                 ohci2: usb@01c1c400 {
 235                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 236                         reg = <0x01c1c400 0x100>;
 237                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 239                                  <&ccu CLK_USB_OHCI2>;
 240                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 241                         phys = <&usbphy 2>;
 242                         phy-names = "usb";
 243                         status = "disabled";
 244                 };
 245
 246                 ehci3: usb@01c1d000 {
 247                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 248                         reg = <0x01c1d000 0x100>;
 249                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 251                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 252                         phys = <&usbphy 3>;
 253                         phy-names = "usb";
 254                         status = "disabled";
 255                 };
 256
 257                 ohci3: usb@01c1d400 {
 258                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 259                         reg = <0x01c1d400 0x100>;
 260                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 262                                  <&ccu CLK_USB_OHCI3>;
 263                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 264                         phys = <&usbphy 3>;
 265                         phy-names = "usb";
 266                         status = "disabled";
 267                 };
 268
 269                 ccu: clock@01c20000 {
 270                         /* compatible is in per SoC .dtsi file */
 271                         reg = <0x01c20000 0x400>;
 272                         clocks = <&osc24M>, <&osc32k>;
 273                         clock-names = "hosc", "losc";
 274                         #clock-cells = <1>;
 275                         #reset-cells = <1>;
 276                 };
 277
 278                 pio: pinctrl@01c20800 {
 279                         /* compatible is in per SoC .dtsi file */
 280                         reg = <0x01c20800 0x400>;
 281                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 284                         clock-names = "apb", "hosc", "losc";
 285                         gpio-controller;
 286                         #gpio-cells = <3>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <3>;
 289
 290                         emac_rgmii_pins: emac0 {
 291                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 292                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 293                                        "PD12", "PD13", "PD15", "PD16", "PD17";
 294                                 function = "emac";
 295                                 drive-strength = <40>;
 296                         };
 297
 298                         i2c0_pins: i2c0 {
 299                                 pins = "PA11", "PA12";
 300                                 function = "i2c0";
 301                         };
 302
 303                         i2c1_pins: i2c1 {
 304                                 pins = "PA18", "PA19";
 305                                 function = "i2c1";
 306                         };
 307
 308                         i2c2_pins: i2c2 {
 309                                 pins = "PE12", "PE13";
 310                                 function = "i2c2";
 311                         };
 312
 313                         mmc0_pins_a: mmc0@0 {
 314                                 pins = "PF0", "PF1", "PF2", "PF3",
 315                                        "PF4", "PF5";
 316                                 function = "mmc0";
 317                                 drive-strength = <30>;
 318                                 bias-pull-up;
 319                         };
 320
 321                         mmc0_cd_pin: mmc0_cd_pin@0 {
 322                                 pins = "PF6";
 323                                 function = "gpio_in";
 324                                 bias-pull-up;
 325                         };
 326
 327                         mmc1_pins_a: mmc1@0 {
 328                                 pins = "PG0", "PG1", "PG2", "PG3",
 329                                        "PG4", "PG5";
 330                                 function = "mmc1";
 331                                 drive-strength = <30>;
 332                                 bias-pull-up;
 333                         };
 334
 335                         mmc2_8bit_pins: mmc2_8bit {
 336                                 pins = "PC5", "PC6", "PC8",
 337                                        "PC9", "PC10", "PC11",
 338                                        "PC12", "PC13", "PC14",
 339                                        "PC15", "PC16";
 340                                 function = "mmc2";
 341                                 drive-strength = <30>;
 342                                 bias-pull-up;
 343                         };
 344
 345                         spdif_tx_pins_a: spdif@0 {
 346                                 pins = "PA17";
 347                                 function = "spdif";
 348                         };
 349
 350                         spi0_pins: spi0 {
 351                                 pins = "PC0", "PC1", "PC2", "PC3";
 352                                 function = "spi0";
 353                         };
 354
 355                         spi1_pins: spi1 {
 356                                 pins = "PA15", "PA16", "PA14", "PA13";
 357                                 function = "spi1";
 358                         };
 359
 360                         uart0_pins_a: uart0@0 {
 361                                 pins = "PA4", "PA5";
 362                                 function = "uart0";
 363                         };
 364
 365                         uart1_pins: uart1 {
 366                                 pins = "PG6", "PG7";
 367                                 function = "uart1";
 368                         };
 369
 370                         uart1_rts_cts_pins: uart1_rts_cts {
 371                                 pins = "PG8", "PG9";
 372                                 function = "uart1";
 373                         };
 374
 375                         uart2_pins: uart2 {
 376                                 pins = "PA0", "PA1";
 377                                 function = "uart2";
 378                         };
 379
 380                         uart3_pins: uart3 {
 381                                 pins = "PA13", "PA14";
 382                                 function = "uart3";
 383                         };
 384                 };
 385
 386                 timer@01c20c00 {
 387                         compatible = "allwinner,sun4i-a10-timer";
 388                         reg = <0x01c20c00 0xa0>;
 389                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&osc24M>;
 392                 };
 393
 394                 emac: ethernet@1c30000 {
 395                         compatible = "allwinner,sun8i-h3-emac";
 396                         syscon = <&syscon>;
 397                         reg = <0x01c30000 0x10000>;
 398                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 399                         interrupt-names = "macirq";
 400                         resets = <&ccu RST_BUS_EMAC>;
 401                         reset-names = "stmmaceth";
 402                         clocks = <&ccu CLK_BUS_EMAC>;
 403                         clock-names = "stmmaceth";
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         status = "disabled";
 407
 408                         mdio: mdio {
 409                                 #address-cells = <1>;
 410                                 #size-cells = <0>;
 411                                 int_mii_phy: ethernet-phy@1 {
 412                                         compatible = "ethernet-phy-ieee802.3-c22";
 413                                         reg = <1>;
 414                                         clocks = <&ccu CLK_BUS_EPHY>;
 415                                         resets = <&ccu RST_BUS_EPHY>;
 416                                 };
 417                         };
 418                 };
 419
 420                 spi0: spi@01c68000 {
 421                         compatible = "allwinner,sun8i-h3-spi";
 422                         reg = <0x01c68000 0x1000>;
 423                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 425                         clock-names = "ahb", "mod";
 426                         dmas = <&dma 23>, <&dma 23>;
 427                         dma-names = "rx", "tx";
 428                         pinctrl-names = "default";
 429                         pinctrl-0 = <&spi0_pins>;
 430                         resets = <&ccu RST_BUS_SPI0>;
 431                         status = "disabled";
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                 };
 435
 436                 spi1: spi@01c69000 {
 437                         compatible = "allwinner,sun8i-h3-spi";
 438                         reg = <0x01c69000 0x1000>;
 439                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 441                         clock-names = "ahb", "mod";
 442                         dmas = <&dma 24>, <&dma 24>;
 443                         dma-names = "rx", "tx";
 444                         pinctrl-names = "default";
 445                         pinctrl-0 = <&spi1_pins>;
 446                         resets = <&ccu RST_BUS_SPI1>;
 447                         status = "disabled";
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                 };
 451
 452                 wdt0: watchdog@01c20ca0 {
 453                         compatible = "allwinner,sun6i-a31-wdt";
 454                         reg = <0x01c20ca0 0x20>;
 455                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 456                 };
 457
 458                 spdif: spdif@01c21000 {
 459                         #sound-dai-cells = <0>;
 460                         compatible = "allwinner,sun8i-h3-spdif";
 461                         reg = <0x01c21000 0x400>;
 462                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 464                         resets = <&ccu RST_BUS_SPDIF>;
 465                         clock-names = "apb", "spdif";
 466                         dmas = <&dma 2>;
 467                         dma-names = "tx";
 468                         status = "disabled";
 469                 };
 470
 471                 pwm: pwm@01c21400 {
 472                         compatible = "allwinner,sun8i-h3-pwm";
 473                         reg = <0x01c21400 0x8>;
 474                         clocks = <&osc24M>;
 475                         #pwm-cells = <3>;
 476                         status = "disabled";
 477                 };
 478
 479                 codec: codec@01c22c00 {
 480                         #sound-dai-cells = <0>;
 481                         compatible = "allwinner,sun8i-h3-codec";
 482                         reg = <0x01c22c00 0x400>;
 483                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 485                         clock-names = "apb", "codec";
 486                         resets = <&ccu RST_BUS_CODEC>;
 487                         dmas = <&dma 15>, <&dma 15>;
 488                         dma-names = "rx", "tx";
 489                         allwinner,codec-analog-controls = <&codec_analog>;
 490                         status = "disabled";
 491                 };
 492
 493                 uart0: serial@01c28000 {
 494                         compatible = "snps,dw-apb-uart";
 495                         reg = <0x01c28000 0x400>;
 496                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 497                         reg-shift = <2>;
 498                         reg-io-width = <4>;
 499                         clocks = <&ccu CLK_BUS_UART0>;
 500                         resets = <&ccu RST_BUS_UART0>;
 501                         dmas = <&dma 6>, <&dma 6>;
 502                         dma-names = "rx", "tx";
 503                         status = "disabled";
 504                 };
 505
 506                 uart1: serial@01c28400 {
 507                         compatible = "snps,dw-apb-uart";
 508                         reg = <0x01c28400 0x400>;
 509                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 510                         reg-shift = <2>;
 511                         reg-io-width = <4>;
 512                         clocks = <&ccu CLK_BUS_UART1>;
 513                         resets = <&ccu RST_BUS_UART1>;
 514                         dmas = <&dma 7>, <&dma 7>;
 515                         dma-names = "rx", "tx";
 516                         status = "disabled";
 517                 };
 518
 519                 uart2: serial@01c28800 {
 520                         compatible = "snps,dw-apb-uart";
 521                         reg = <0x01c28800 0x400>;
 522                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 523                         reg-shift = <2>;
 524                         reg-io-width = <4>;
 525                         clocks = <&ccu CLK_BUS_UART2>;
 526                         resets = <&ccu RST_BUS_UART2>;
 527                         dmas = <&dma 8>, <&dma 8>;
 528                         dma-names = "rx", "tx";
 529                         status = "disabled";
 530                 };
 531
 532                 uart3: serial@01c28c00 {
 533                         compatible = "snps,dw-apb-uart";
 534                         reg = <0x01c28c00 0x400>;
 535                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 536                         reg-shift = <2>;
 537                         reg-io-width = <4>;
 538                         clocks = <&ccu CLK_BUS_UART3>;
 539                         resets = <&ccu RST_BUS_UART3>;
 540                         dmas = <&dma 9>, <&dma 9>;
 541                         dma-names = "rx", "tx";
 542                         status = "disabled";
 543                 };
 544
 545                 i2c0: i2c@01c2ac00 {
 546                         compatible = "allwinner,sun6i-a31-i2c";
 547                         reg = <0x01c2ac00 0x400>;
 548                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&ccu CLK_BUS_I2C0>;
 550                         resets = <&ccu RST_BUS_I2C0>;
 551                         pinctrl-names = "default";
 552                         pinctrl-0 = <&i2c0_pins>;
 553                         status = "disabled";
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                 };
 557
 558                 i2c1: i2c@01c2b000 {
 559                         compatible = "allwinner,sun6i-a31-i2c";
 560                         reg = <0x01c2b000 0x400>;
 561                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&ccu CLK_BUS_I2C1>;
 563                         resets = <&ccu RST_BUS_I2C1>;
 564                         pinctrl-names = "default";
 565                         pinctrl-0 = <&i2c1_pins>;
 566                         status = "disabled";
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                 };
 570
 571                 i2c2: i2c@01c2b400 {
 572                         compatible = "allwinner,sun6i-a31-i2c";
 573                         reg = <0x01c2b000 0x400>;
 574                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&ccu CLK_BUS_I2C2>;
 576                         resets = <&ccu RST_BUS_I2C2>;
 577                         pinctrl-names = "default";
 578                         pinctrl-0 = <&i2c2_pins>;
 579                         status = "disabled";
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                 };
 583
 584                 gic: interrupt-controller@01c81000 {
 585                         compatible = "arm,gic-400";
 586                         reg = <0x01c81000 0x1000>,
 587                               <0x01c82000 0x2000>,
 588                               <0x01c84000 0x2000>,
 589                               <0x01c86000 0x2000>;
 590                         interrupt-controller;
 591                         #interrupt-cells = <3>;
 592                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 593                 };
 594
 595                 rtc: rtc@01f00000 {
 596                         compatible = "allwinner,sun6i-a31-rtc";
 597                         reg = <0x01f00000 0x54>;
 598                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 600                 };
 601
 602                 r_ccu: clock@1f01400 {
 603                         compatible = "allwinner,sun8i-h3-r-ccu";
 604                         reg = <0x01f01400 0x100>;
 605                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 606                                  <&ccu 9>;
 607                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 608                         #clock-cells = <1>;
 609                         #reset-cells = <1>;
 610                 };
 611
 612                 codec_analog: codec-analog@01f015c0 {
 613                         compatible = "allwinner,sun8i-h3-codec-analog";
 614                         reg = <0x01f015c0 0x4>;
 615                 };
 616
 617                 ir: ir@01f02000 {
 618                         compatible = "allwinner,sun5i-a13-ir";
 619                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 620                         clock-names = "apb", "ir";
 621                         resets = <&r_ccu RST_APB0_IR>;
 622                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 623                         reg = <0x01f02000 0x40>;
 624                         status = "disabled";
 625                 };
 626
 627                 r_pio: pinctrl@01f02c00 {
 628                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 629                         reg = <0x01f02c00 0x400>;
 630                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 632                         clock-names = "apb", "hosc", "losc";
 633                         gpio-controller;
 634                         #gpio-cells = <3>;
 635                         interrupt-controller;
 636                         #interrupt-cells = <3>;
 637
 638                         ir_pins_a: ir@0 {
 639                                 pins = "PL11";
 640                                 function = "s_cir_rx";
 641                         };
 642                 };
 643         };
 644 };