arch/arm/boot/dts/tegra124-apalis.dtsi

   1 /*
   2  * Copyright 2016 Toradex AG
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include "tegra124.dtsi"
  43 #include "tegra124-apalis-emc.dtsi"
  44
  45 /*
  46  * Toradex Apalis TK1 Module Device Tree
  47  * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
  48  */
  49 / {
  50         model = "Toradex Apalis TK1";
  51         compatible = "toradex,apalis-tk1", "nvidia,tegra124";
  52
  53         memory {
  54                 reg = <0x0 0x80000000 0x0 0x80000000>;
  55         };
  56
  57         pcie@1003000 {
  58                 status = "okay";
  59
  60                 avddio-pex-supply = <&vdd_1v05>;
  61                 avdd-pex-pll-supply = <&vdd_1v05>;
  62                 avdd-pll-erefe-supply = <&avdd_1v05>;
  63                 dvddio-pex-supply = <&vdd_1v05>;
  64                 hvdd-pex-pll-e-supply = <&reg_3v3>;
  65                 hvdd-pex-supply = <&reg_3v3>;
  66                 vddio-pex-ctl-supply = <&reg_3v3>;
  67
  68                 /* Apalis PCIe (additional lane Apalis type specific) */
  69                 pci@1,0 {
  70                         /* PCIE1_RX/TX and TS_DIFF1/2 */
  71                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
  72                                <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  73                         phy-names = "pcie-0", "pcie-1";
  74                 };
  75
  76                 /* I210 Gigabit Ethernet Controller (On-module) */
  77                 pci@2,0 {
  78                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  79                         phy-names = "pcie-0";
  80                         status = "okay";
  81                 };
  82         };
  83
  84         host1x@50000000 {
  85                 hdmi@54280000 {
  86                         pll-supply = <&reg_1v05_avdd_hdmi_pll>;
  87                         vdd-supply = <&reg_3v3_avdd_hdmi>;
  88
  89                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  90                         nvidia,hpd-gpio =
  91                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  92                 };
  93         };
  94
  95         gpu@0,57000000 {
  96                 /*
  97                  * Node left disabled on purpose - the bootloader will enable
  98                  * it after having set the VPR up
  99                  */
 100                 vdd-supply = <&vdd_gpu>;
 101         };
 102
 103         pinmux: pinmux@70000868 {
 104                 pinctrl-names = "default";
 105                 pinctrl-0 = <&state_default>;
 106
 107                 state_default: pinmux {
 108                         /* Analogue Audio (On-module) */
 109                         dap3_fs_pp0 {
 110                                 nvidia,pins = "dap3_fs_pp0";
 111                                 nvidia,function = "i2s2";
 112                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 113                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 114                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 115                         };
 116                         dap3_din_pp1 {
 117                                 nvidia,pins = "dap3_din_pp1";
 118                                 nvidia,function = "i2s2";
 119                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 120                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 121                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 122                         };
 123                         dap3_dout_pp2 {
 124                                 nvidia,pins = "dap3_dout_pp2";
 125                                 nvidia,function = "i2s2";
 126                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 127                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 128                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 129                         };
 130                         dap3_sclk_pp3 {
 131                                 nvidia,pins = "dap3_sclk_pp3";
 132                                 nvidia,function = "i2s2";
 133                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 134                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 135                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 136                         };
 137                         dap_mclk1_pw4 {
 138                                 nvidia,pins = "dap_mclk1_pw4";
 139                                 nvidia,function = "extperiph1";
 140                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 141                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 142                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 143                         };
 144
 145                         /* Apalis BKL1_ON */
 146                         pbb5 {
 147                                 nvidia,pins = "pbb5";
 148                                 nvidia,function = "vgp5";
 149                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 150                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 151                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 152                         };
 153
 154                         /* Apalis BKL1_PWM */
 155                         pu6 {
 156                                 nvidia,pins = "pu6";
 157                                 nvidia,function = "pwm3";
 158                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 159                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 160                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 161                         };
 162
 163                         /* Apalis CAM1_MCLK */
 164                         cam_mclk_pcc0 {
 165                                 nvidia,pins = "cam_mclk_pcc0";
 166                                 nvidia,function = "vi_alt3";
 167                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 168                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 169                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 170                         };
 171
 172                         /* Apalis Digital Audio */
 173                         dap2_fs_pa2 {
 174                                 nvidia,pins = "dap2_fs_pa2";
 175                                 nvidia,function = "hda";
 176                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 177                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 178                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 179                         };
 180                         dap2_sclk_pa3 {
 181                                 nvidia,pins = "dap2_sclk_pa3";
 182                                 nvidia,function = "hda";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 185                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 186                         };
 187                         dap2_din_pa4 {
 188                                 nvidia,pins = "dap2_din_pa4";
 189                                 nvidia,function = "hda";
 190                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 191                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 192                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 193                         };
 194                         dap2_dout_pa5 {
 195                                 nvidia,pins = "dap2_dout_pa5";
 196                                 nvidia,function = "hda";
 197                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 198                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 199                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 200                         };
 201                         pbb3 { /* DAP1_RESET */
 202                                 nvidia,pins = "pbb3";
 203                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 204                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 205                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 206                         };
 207                         clk3_out_pee0 {
 208                                 nvidia,pins = "clk3_out_pee0";
 209                                 nvidia,function = "extperiph3";
 210                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 211                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 212                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 213                         };
 214
 215                         /* Apalis GPIO */
 216                         ddc_scl_pv4 {
 217                                 nvidia,pins = "ddc_scl_pv4";
 218                                 nvidia,function = "rsvd2";
 219                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 220                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 221                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 222                         };
 223                         ddc_sda_pv5 {
 224                                 nvidia,pins = "ddc_sda_pv5";
 225                                 nvidia,function = "rsvd2";
 226                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 227                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 228                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 229                         };
 230                         pex_l0_rst_n_pdd1 {
 231                                 nvidia,pins = "pex_l0_rst_n_pdd1";
 232                                 nvidia,function = "rsvd2";
 233                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 234                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 235                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 236                         };
 237                         pex_l0_clkreq_n_pdd2 {
 238                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
 239                                 nvidia,function = "rsvd2";
 240                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 241                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 242                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 243                         };
 244                         pex_l1_rst_n_pdd5 {
 245                                 nvidia,pins = "pex_l1_rst_n_pdd5";
 246                                 nvidia,function = "rsvd2";
 247                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 248                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 249                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 250                         };
 251                         pex_l1_clkreq_n_pdd6 {
 252                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
 253                                 nvidia,function = "rsvd2";
 254                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 255                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 256                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 257                         };
 258                         dp_hpd_pff0 {
 259                                 nvidia,pins = "dp_hpd_pff0";
 260                                 nvidia,function = "dp";
 261                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 262                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 263                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 264                         };
 265                         pff2 {
 266                                 nvidia,pins = "pff2";
 267                                 nvidia,function = "rsvd2";
 268                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 269                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 270                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 271                         };
 272                         owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
 273                                 nvidia,pins = "owr";
 274                                 nvidia,function = "rsvd2";
 275                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 276                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 277                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 278                                 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 279                         };
 280
 281                         /* Apalis HDMI1_CEC */
 282                         hdmi_cec_pee3 {
 283                                 nvidia,pins = "hdmi_cec_pee3";
 284                                 nvidia,function = "cec";
 285                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 286                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 287                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 288                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 289                         };
 290
 291                         /* Apalis HDMI1_HPD */
 292                         hdmi_int_pn7 {
 293                                 nvidia,pins = "hdmi_int_pn7";
 294                                 nvidia,function = "rsvd1";
 295                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 296                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 297                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 298                                 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 299                         };
 300
 301                         /* Apalis I2C1 */
 302                         gen1_i2c_scl_pc4 {
 303                                 nvidia,pins = "gen1_i2c_scl_pc4";
 304                                 nvidia,function = "i2c1";
 305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 306                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 307                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 308                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 309                         };
 310                         gen1_i2c_sda_pc5 {
 311                                 nvidia,pins = "gen1_i2c_sda_pc5";
 312                                 nvidia,function = "i2c1";
 313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 314                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 315                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 316                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 317                         };
 318
 319                         /* Apalis I2C2 (DDC) */
 320                         gen2_i2c_scl_pt5 {
 321                                 nvidia,pins = "gen2_i2c_scl_pt5";
 322                                 nvidia,function = "i2c2";
 323                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 324                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 325                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 326                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 327                         };
 328                         gen2_i2c_sda_pt6 {
 329                                 nvidia,pins = "gen2_i2c_sda_pt6";
 330                                 nvidia,function = "i2c2";
 331                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 332                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 333                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 334                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 335                         };
 336
 337                         /* Apalis I2C3 (CAM) */
 338                         cam_i2c_scl_pbb1 {
 339                                 nvidia,pins = "cam_i2c_scl_pbb1";
 340                                 nvidia,function = "i2c3";
 341                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 342                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 343                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 344                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 345                         };
 346                         cam_i2c_sda_pbb2 {
 347                                 nvidia,pins = "cam_i2c_sda_pbb2";
 348                                 nvidia,function = "i2c3";
 349                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 350                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 351                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 352                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 353                         };
 354
 355                         /* Apalis MMC1 */
 356                         sdmmc1_cd_n_pv3 { /* CD# GPIO */
 357                                 nvidia,pins = "sdmmc1_wp_n_pv3";
 358                                 nvidia,function = "sdmmc1";
 359                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 360                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 361                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 362                         };
 363                         clk2_out_pw5 { /* D5 GPIO */
 364                                 nvidia,pins = "clk2_out_pw5";
 365                                 nvidia,function = "rsvd2";
 366                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 367                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 368                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 369                         };
 370                         sdmmc1_dat3_py4 {
 371                                 nvidia,pins = "sdmmc1_dat3_py4";
 372                                 nvidia,function = "sdmmc1";
 373                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 374                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 375                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 376                         };
 377                         sdmmc1_dat2_py5 {
 378                                 nvidia,pins = "sdmmc1_dat2_py5";
 379                                 nvidia,function = "sdmmc1";
 380                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 381                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 382                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 383                         };
 384                         sdmmc1_dat1_py6 {
 385                                 nvidia,pins = "sdmmc1_dat1_py6";
 386                                 nvidia,function = "sdmmc1";
 387                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 388                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 389                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 390                         };
 391                         sdmmc1_dat0_py7 {
 392                                 nvidia,pins = "sdmmc1_dat0_py7";
 393                                 nvidia,function = "sdmmc1";
 394                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 395                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 396                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 397                         };
 398                         sdmmc1_clk_pz0 {
 399                                 nvidia,pins = "sdmmc1_clk_pz0";
 400                                 nvidia,function = "sdmmc1";
 401                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 402                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 403                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 404                         };
 405                         sdmmc1_cmd_pz1 {
 406                                 nvidia,pins = "sdmmc1_cmd_pz1";
 407                                 nvidia,function = "sdmmc1";
 408                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 409                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 410                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 411                         };
 412                         clk2_req_pcc5 { /* D4 GPIO */
 413                                 nvidia,pins = "clk2_req_pcc5";
 414                                 nvidia,function = "rsvd2";
 415                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 416                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 417                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 418                         };
 419                         sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
 420                                 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
 421                                 nvidia,function = "rsvd2";
 422                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 423                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 424                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 425                         };
 426                         usb_vbus_en2_pff1 { /* D7 GPIO */
 427                                 nvidia,pins = "usb_vbus_en2_pff1";
 428                                 nvidia,function = "rsvd2";
 429                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 430                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 431                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 432                         };
 433
 434                         /* Apalis PWM */
 435                         ph0 {
 436                                 nvidia,pins = "ph0";
 437                                 nvidia,function = "pwm0";
 438                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 439                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 440                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 441                         };
 442                         ph1 {
 443                                 nvidia,pins = "ph1";
 444                                 nvidia,function = "pwm1";
 445                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 446                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 447                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 448                         };
 449                         ph2 {
 450                                 nvidia,pins = "ph2";
 451                                 nvidia,function = "pwm2";
 452                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 453                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 454                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 455                         };
 456                         /* PWM3 active on pu6 being Apalis BKL1_PWM */
 457                         ph3 {
 458                                 nvidia,pins = "ph3";
 459                                 nvidia,function = "gmi";
 460                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 461                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 462                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 463                         };
 464
 465                         /* Apalis SATA1_ACT# */
 466                         dap1_dout_pn2 {
 467                                 nvidia,pins = "dap1_dout_pn2";
 468                                 nvidia,function = "gmi";
 469                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 470                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 471                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 472                         };
 473
 474                         /* Apalis SD1 */
 475                         sdmmc3_clk_pa6 {
 476                                 nvidia,pins = "sdmmc3_clk_pa6";
 477                                 nvidia,function = "sdmmc3";
 478                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 479                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 480                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 481                         };
 482                         sdmmc3_cmd_pa7 {
 483                                 nvidia,pins = "sdmmc3_cmd_pa7";
 484                                 nvidia,function = "sdmmc3";
 485                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 486                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 487                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 488                         };
 489                         sdmmc3_dat3_pb4 {
 490                                 nvidia,pins = "sdmmc3_dat3_pb4";
 491                                 nvidia,function = "sdmmc3";
 492                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 493                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 494                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 495                         };
 496                         sdmmc3_dat2_pb5 {
 497                                 nvidia,pins = "sdmmc3_dat2_pb5";
 498                                 nvidia,function = "sdmmc3";
 499                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 500                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 501                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 502                         };
 503                         sdmmc3_dat1_pb6 {
 504                                 nvidia,pins = "sdmmc3_dat1_pb6";
 505                                 nvidia,function = "sdmmc3";
 506                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 507                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 508                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 509                         };
 510                         sdmmc3_dat0_pb7 {
 511                                 nvidia,pins = "sdmmc3_dat0_pb7";
 512                                 nvidia,function = "sdmmc3";
 513                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 514                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 515                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 516                         };
 517                         sdmmc3_cd_n_pv2 { /* CD# GPIO */
 518                                 nvidia,pins = "sdmmc3_cd_n_pv2";
 519                                 nvidia,function = "rsvd3";
 520                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 521                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 522                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 523                         };
 524
 525                         /* Apalis SPDIF */
 526                         spdif_out_pk5 {
 527                                 nvidia,pins = "spdif_out_pk5";
 528                                 nvidia,function = "spdif";
 529                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 530                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 531                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 532                         };
 533                         spdif_in_pk6 {
 534                                 nvidia,pins = "spdif_in_pk6";
 535                                 nvidia,function = "spdif";
 536                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 537                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 538                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 539                         };
 540
 541                         /* Apalis SPI1 */
 542                         ulpi_clk_py0 {
 543                                 nvidia,pins = "ulpi_clk_py0";
 544                                 nvidia,function = "spi1";
 545                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 546                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 547                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 548                         };
 549                         ulpi_dir_py1 {
 550                                 nvidia,pins = "ulpi_dir_py1";
 551                                 nvidia,function = "spi1";
 552                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 553                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 554                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 555                         };
 556                         ulpi_nxt_py2 {
 557                                 nvidia,pins = "ulpi_nxt_py2";
 558                                 nvidia,function = "spi1";
 559                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 560                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 561                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 562                         };
 563                         ulpi_stp_py3 {
 564                                 nvidia,pins = "ulpi_stp_py3";
 565                                 nvidia,function = "spi1";
 566                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 567                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 568                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 569                         };
 570
 571                         /* Apalis SPI2 */
 572                         pg5 {
 573                                 nvidia,pins = "pg5";
 574                                 nvidia,function = "spi4";
 575                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 576                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 577                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 578                         };
 579                         pg6 {
 580                                 nvidia,pins = "pg6";
 581                                 nvidia,function = "spi4";
 582                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 583                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 584                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 585                         };
 586                         pg7 {
 587                                 nvidia,pins = "pg7";
 588                                 nvidia,function = "spi4";
 589                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 590                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 591                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 592                         };
 593                         pi3 {
 594                                 nvidia,pins = "pi3";
 595                                 nvidia,function = "spi4";
 596                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 597                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 598                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 599                         };
 600
 601                         /* Apalis UART1 */
 602                         pb1 { /* DCD GPIO */
 603                                 nvidia,pins = "pb1";
 604                                 nvidia,function = "rsvd2";
 605                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 606                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 607                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 608                         };
 609                         pk7 { /* RI GPIO */
 610                                 nvidia,pins = "pk7";
 611                                 nvidia,function = "rsvd2";
 612                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 613                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 614                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 615                         };
 616                         uart1_txd_pu0 {
 617                                 nvidia,pins = "pu0";
 618                                 nvidia,function = "uarta";
 619                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 620                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 621                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 622                         };
 623                         uart1_rxd_pu1 {
 624                                 nvidia,pins = "pu1";
 625                                 nvidia,function = "uarta";
 626                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 627                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 628                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 629                         };
 630                         uart1_cts_n_pu2 {
 631                                 nvidia,pins = "pu2";
 632                                 nvidia,function = "uarta";
 633                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 634                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 635                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 636                         };
 637                         uart1_rts_n_pu3 {
 638                                 nvidia,pins = "pu3";
 639                                 nvidia,function = "uarta";
 640                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 641                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 642                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 643                         };
 644                         uart3_cts_n_pa1 { /* DSR GPIO */
 645                                 nvidia,pins = "uart3_cts_n_pa1";
 646                                 nvidia,function = "gmi";
 647                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 648                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 649                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 650                         };
 651                         uart3_rts_n_pc0 { /* DTR GPIO */
 652                                 nvidia,pins = "uart3_rts_n_pc0";
 653                                 nvidia,function = "gmi";
 654                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 655                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 656                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 657                         };
 658
 659                         /* Apalis UART2 */
 660                         uart2_txd_pc2 {
 661                                 nvidia,pins = "uart2_txd_pc2";
 662                                 nvidia,function = "irda";
 663                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 664                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 665                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 666                         };
 667                         uart2_rxd_pc3 {
 668                                 nvidia,pins = "uart2_rxd_pc3";
 669                                 nvidia,function = "irda";
 670                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 671                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 672                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 673                         };
 674                         uart2_cts_n_pj5 {
 675                                 nvidia,pins = "uart2_cts_n_pj5";
 676                                 nvidia,function = "uartb";
 677                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 678                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 679                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 680                         };
 681                         uart2_rts_n_pj6 {
 682                                 nvidia,pins = "uart2_rts_n_pj6";
 683                                 nvidia,function = "uartb";
 684                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 685                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 686                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 687                         };
 688
 689                         /* Apalis UART3 */
 690                         uart3_txd_pw6 {
 691                                 nvidia,pins = "uart3_txd_pw6";
 692                                 nvidia,function = "uartc";
 693                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 694                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 695                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 696                         };
 697                         uart3_rxd_pw7 {
 698                                 nvidia,pins = "uart3_rxd_pw7";
 699                                 nvidia,function = "uartc";
 700                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 701                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 702                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 703                         };
 704
 705                         /* Apalis UART4 */
 706                         uart4_rxd_pb0 {
 707                                 nvidia,pins = "pb0";
 708                                 nvidia,function = "uartd";
 709                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 710                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 711                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 712                         };
 713                         uart4_txd_pj7 {
 714                                 nvidia,pins = "pj7";
 715                                 nvidia,function = "uartd";
 716                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 717                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 718                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 719                         };
 720
 721                         /* Apalis USBH_EN */
 722                         usb_vbus_en1_pn5 {
 723                                 nvidia,pins = "usb_vbus_en1_pn5";
 724                                 nvidia,function = "rsvd2";
 725                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 726                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 727                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 728                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 729                         };
 730
 731                         /* Apalis USBH_OC# */
 732                         pbb0 {
 733                                 nvidia,pins = "pbb0";
 734                                 nvidia,function = "vgp6";
 735                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 736                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 737                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 738                         };
 739
 740                         /* Apalis USBO1_EN */
 741                         usb_vbus_en0_pn4 {
 742                                 nvidia,pins = "usb_vbus_en0_pn4";
 743                                 nvidia,function = "rsvd2";
 744                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 745                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 746                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 747                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 748                         };
 749
 750                         /* Apalis USBO1_OC# */
 751                         pbb4 {
 752                                 nvidia,pins = "pbb4";
 753                                 nvidia,function = "vgp4";
 754                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 755                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 756                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 757                         };
 758
 759                         /* Apalis WAKE1_MICO */
 760                         pex_wake_n_pdd3 {
 761                                 nvidia,pins = "pex_wake_n_pdd3";
 762                                 nvidia,function = "rsvd2";
 763                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 764                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 765                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 766                         };
 767
 768                         /* CORE_PWR_REQ */
 769                         core_pwr_req {
 770                                 nvidia,pins = "core_pwr_req";
 771                                 nvidia,function = "pwron";
 772                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 773                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 774                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 775                         };
 776
 777                         /* CPU_PWR_REQ */
 778                         cpu_pwr_req {
 779                                 nvidia,pins = "cpu_pwr_req";
 780                                 nvidia,function = "cpu";
 781                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 782                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 783                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 784                         };
 785
 786                         /* DVFS */
 787                         dvfs_pwm_px0 {
 788                                 nvidia,pins = "dvfs_pwm_px0";
 789                                 nvidia,function = "cldvfs";
 790                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 791                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 792                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 793                         };
 794                         dvfs_clk_px2 {
 795                                 nvidia,pins = "dvfs_clk_px2";
 796                                 nvidia,function = "cldvfs";
 797                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 798                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 799                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 800                         };
 801
 802                         /* eMMC */
 803                         sdmmc4_dat0_paa0 {
 804                                 nvidia,pins = "sdmmc4_dat0_paa0";
 805                                 nvidia,function = "sdmmc4";
 806                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 807                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 808                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 809                         };
 810                         sdmmc4_dat1_paa1 {
 811                                 nvidia,pins = "sdmmc4_dat1_paa1";
 812                                 nvidia,function = "sdmmc4";
 813                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 814                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 815                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 816                         };
 817                         sdmmc4_dat2_paa2 {
 818                                 nvidia,pins = "sdmmc4_dat2_paa2";
 819                                 nvidia,function = "sdmmc4";
 820                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 821                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 822                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 823                         };
 824                         sdmmc4_dat3_paa3 {
 825                                 nvidia,pins = "sdmmc4_dat3_paa3";
 826                                 nvidia,function = "sdmmc4";
 827                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 828                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 829                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 830                         };
 831                         sdmmc4_dat4_paa4 {
 832                                 nvidia,pins = "sdmmc4_dat4_paa4";
 833                                 nvidia,function = "sdmmc4";
 834                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 835                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 836                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 837                         };
 838                         sdmmc4_dat5_paa5 {
 839                                 nvidia,pins = "sdmmc4_dat5_paa5";
 840                                 nvidia,function = "sdmmc4";
 841                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 842                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 843                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 844                         };
 845                         sdmmc4_dat6_paa6 {
 846                                 nvidia,pins = "sdmmc4_dat6_paa6";
 847                                 nvidia,function = "sdmmc4";
 848                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 849                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 850                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 851                         };
 852                         sdmmc4_dat7_paa7 {
 853                                 nvidia,pins = "sdmmc4_dat7_paa7";
 854                                 nvidia,function = "sdmmc4";
 855                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 856                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 857                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 858                         };
 859                         sdmmc4_clk_pcc4 {
 860                                 nvidia,pins = "sdmmc4_clk_pcc4";
 861                                 nvidia,function = "sdmmc4";
 862                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 863                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 864                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 865                         };
 866                         sdmmc4_cmd_pt7 {
 867                                 nvidia,pins = "sdmmc4_cmd_pt7";
 868                                 nvidia,function = "sdmmc4";
 869                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 870                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 871                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 872                         };
 873
 874                         /* JTAG_RTCK */
 875                         jtag_rtck {
 876                                 nvidia,pins = "jtag_rtck";
 877                                 nvidia,function = "rtck";
 878                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 879                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 880                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 881                         };
 882
 883                         /* LAN_DEV_OFF# */
 884                         ulpi_data5_po6 {
 885                                 nvidia,pins = "ulpi_data5_po6";
 886                                 nvidia,function = "ulpi";
 887                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 888                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 889                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 890                         };
 891
 892                         /* LAN_RESET# */
 893                         kb_row10_ps2 {
 894                                 nvidia,pins = "kb_row10_ps2";
 895                                 nvidia,function = "rsvd2";
 896                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 897                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 898                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 899                         };
 900
 901                         /* LAN_WAKE# */
 902                         ulpi_data4_po5 {
 903                                 nvidia,pins = "ulpi_data4_po5";
 904                                 nvidia,function = "ulpi";
 905                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 906                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 907                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 908                         };
 909
 910                         /* MCU_INT1# */
 911                         pk2 {
 912                                 nvidia,pins = "pk2";
 913                                 nvidia,function = "rsvd1";
 914                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 915                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 916                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 917                         };
 918
 919                         /* MCU_INT2# */
 920                         pj2 {
 921                                 nvidia,pins = "pj2";
 922                                 nvidia,function = "rsvd1";
 923                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 924                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 925                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 926                         };
 927
 928                         /* MCU_INT3# */
 929                         pi5 {
 930                                 nvidia,pins = "pi5";
 931                                 nvidia,function = "rsvd2";
 932                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 933                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 934                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 935                         };
 936
 937                         /* MCU_INT4# */
 938                         pj0 {
 939                                 nvidia,pins = "pj0";
 940                                 nvidia,function = "rsvd1";
 941                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 942                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 943                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 944                         };
 945
 946                         /* MCU_RESET */
 947                         pbb6 {
 948                                 nvidia,pins = "pbb6";
 949                                 nvidia,function = "rsvd2";
 950                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 951                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 952                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 953                         };
 954
 955                         /* MCU SPI */
 956                         gpio_x4_aud_px4 {
 957                                 nvidia,pins = "gpio_x4_aud_px4";
 958                                 nvidia,function = "spi2";
 959                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 960                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 961                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 962                         };
 963                         gpio_x5_aud_px5 {
 964                                 nvidia,pins = "gpio_x5_aud_px5";
 965                                 nvidia,function = "spi2";
 966                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 967                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 968                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 969                         };
 970                         gpio_x6_aud_px6 { /* MCU_CS */
 971                                 nvidia,pins = "gpio_x6_aud_px6";
 972                                 nvidia,function = "spi2";
 973                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 974                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 975                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 976                         };
 977                         gpio_x7_aud_px7 {
 978                                 nvidia,pins = "gpio_x7_aud_px7";
 979                                 nvidia,function = "spi2";
 980                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 981                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 982                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 983                         };
 984                         gpio_w2_aud_pw2 { /* MCU_CSEZP */
 985                                 nvidia,pins = "gpio_w2_aud_pw2";
 986                                 nvidia,function = "spi2";
 987                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 988                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 989                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 990                         };
 991
 992                         /* PMIC_CLK_32K */
 993                         clk_32k_in {
 994                                 nvidia,pins = "clk_32k_in";
 995                                 nvidia,function = "clk";
 996                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 997                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 998                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 999                         };
1000
1001                         /* PMIC_CPU_OC_INT */
1002                         clk_32k_out_pa0 {
1003                                 nvidia,pins = "clk_32k_out_pa0";
1004                                 nvidia,function = "soc";
1005                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1006                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1007                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1008                         };
1009
1010                         /* PWR_I2C */
1011                         pwr_i2c_scl_pz6 {
1012                                 nvidia,pins = "pwr_i2c_scl_pz6";
1013                                 nvidia,function = "i2cpwr";
1014                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1015                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1016                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1017                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1018                         };
1019                         pwr_i2c_sda_pz7 {
1020                                 nvidia,pins = "pwr_i2c_sda_pz7";
1021                                 nvidia,function = "i2cpwr";
1022                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1023                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1024                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1025                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1026                         };
1027
1028                         /* PWR_INT_N */
1029                         pwr_int_n {
1030                                 nvidia,pins = "pwr_int_n";
1031                                 nvidia,function = "pmi";
1032                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1033                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1034                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1035                         };
1036
1037                         /* RESET_MOCI_CTRL */
1038                         pu4 {
1039                                 nvidia,pins = "pu4";
1040                                 nvidia,function = "gmi";
1041                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1042                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1043                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1044                         };
1045
1046                         /* RESET_OUT_N */
1047                         reset_out_n {
1048                                 nvidia,pins = "reset_out_n";
1049                                 nvidia,function = "reset_out_n";
1050                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1051                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1052                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1053                         };
1054
1055                         /* SHIFT_CTRL_DIR_IN */
1056                         kb_row0_pr0 {
1057                                 nvidia,pins = "kb_row0_pr0";
1058                                 nvidia,function = "rsvd2";
1059                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1060                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1061                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1062                         };
1063                         kb_row1_pr1 {
1064                                 nvidia,pins = "kb_row1_pr1";
1065                                 nvidia,function = "rsvd2";
1066                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1067                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1068                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1069                         };
1070
1071                         /* Configure level-shifter as output for HDA */
1072                         kb_row11_ps3 {
1073                                 nvidia,pins = "kb_row11_ps3";
1074                                 nvidia,function = "rsvd2";
1075                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1076                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1077                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1078                         };
1079
1080                         /* SHIFT_CTRL_DIR_OUT */
1081                         kb_col5_pq5 {
1082                                 nvidia,pins = "kb_col5_pq5";
1083                                 nvidia,function = "rsvd2";
1084                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1085                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1086                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1087                         };
1088                         kb_col6_pq6 {
1089                                 nvidia,pins = "kb_col6_pq6";
1090                                 nvidia,function = "rsvd2";
1091                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1092                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1093                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1094                         };
1095                         kb_col7_pq7 {
1096                                 nvidia,pins = "kb_col7_pq7";
1097                                 nvidia,function = "rsvd2";
1098                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1099                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1100                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1101                         };
1102
1103                         /* SHIFT_CTRL_OE */
1104                         kb_col0_pq0 {
1105                                 nvidia,pins = "kb_col0_pq0";
1106                                 nvidia,function = "rsvd2";
1107                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1108                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1109                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1110                         };
1111                         kb_col1_pq1 {
1112                                 nvidia,pins = "kb_col1_pq1";
1113                                 nvidia,function = "rsvd2";
1114                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1115                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1116                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1117                         };
1118                         kb_col2_pq2 {
1119                                 nvidia,pins = "kb_col2_pq2";
1120                                 nvidia,function = "rsvd2";
1121                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1122                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1123                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1124                         };
1125                         kb_col4_pq4 {
1126                                 nvidia,pins = "kb_col4_pq4";
1127                                 nvidia,function = "kbc";
1128                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1129                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1130                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1131                         };
1132                         kb_row2_pr2 {
1133                                 nvidia,pins = "kb_row2_pr2";
1134                                 nvidia,function = "rsvd2";
1135                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1136                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1137                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1138                         };
1139
1140                         /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1141                         pi6 {
1142                                 nvidia,pins = "pi6";
1143                                 nvidia,function = "rsvd1";
1144                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1145                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1146                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1147                         };
1148
1149                         /* TOUCH_INT */
1150                         gpio_w3_aud_pw3 {
1151                                 nvidia,pins = "gpio_w3_aud_pw3";
1152                                 nvidia,function = "spi6";
1153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1154                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1155                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1156                         };
1157
1158                         pc7 { /* NC */
1159                                 nvidia,pins = "pc7";
1160                                 nvidia,function = "rsvd1";
1161                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1162                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1164                         };
1165                         pg0 { /* NC */
1166                                 nvidia,pins = "pg0";
1167                                 nvidia,function = "rsvd1";
1168                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1169                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1170                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1171                         };
1172                         pg1 { /* NC */
1173                                 nvidia,pins = "pg1";
1174                                 nvidia,function = "rsvd1";
1175                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1176                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1177                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1178                         };
1179                         pg2 { /* NC */
1180                                 nvidia,pins = "pg2";
1181                                 nvidia,function = "rsvd1";
1182                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1183                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1184                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1185                         };
1186                         pg3 { /* NC */
1187                                 nvidia,pins = "pg3";
1188                                 nvidia,function = "rsvd1";
1189                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1190                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1191                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1192                         };
1193                         pg4 { /* NC */
1194                                 nvidia,pins = "pg4";
1195                                 nvidia,function = "rsvd1";
1196                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1197                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1198                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1199                         };
1200                         ph4 { /* NC */
1201                                 nvidia,pins = "ph4";
1202                                 nvidia,function = "rsvd2";
1203                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1204                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1205                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1206                         };
1207                         ph5 { /* NC */
1208                                 nvidia,pins = "ph5";
1209                                 nvidia,function = "rsvd2";
1210                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1211                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1212                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1213                         };
1214                         ph6 { /* NC */
1215                                 nvidia,pins = "ph6";
1216                                 nvidia,function = "gmi";
1217                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1218                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1219                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1220                         };
1221                         ph7 { /* NC */
1222                                 nvidia,pins = "ph7";
1223                                 nvidia,function = "gmi";
1224                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1225                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1226                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1227                         };
1228                         pi0 { /* NC */
1229                                 nvidia,pins = "pi0";
1230                                 nvidia,function = "rsvd1";
1231                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1232                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1233                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1234                         };
1235                         pi1 { /* NC */
1236                                 nvidia,pins = "pi1";
1237                                 nvidia,function = "rsvd1";
1238                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1239                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1240                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1241                         };
1242                         pi2 { /* NC */
1243                                 nvidia,pins = "pi2";
1244                                 nvidia,function = "rsvd4";
1245                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1246                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1247                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1248                         };
1249                         pi4 { /* NC */
1250                                 nvidia,pins = "pi4";
1251                                 nvidia,function = "gmi";
1252                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1253                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1254                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1255                         };
1256                         pi7 { /* NC */
1257                                 nvidia,pins = "pi7";
1258                                 nvidia,function = "rsvd1";
1259                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1260                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1261                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1262                         };
1263                         pk0 { /* NC */
1264                                 nvidia,pins = "pk0";
1265                                 nvidia,function = "rsvd1";
1266                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1267                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1268                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1269                         };
1270                         pk1 { /* NC */
1271                                 nvidia,pins = "pk1";
1272                                 nvidia,function = "rsvd4";
1273                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1274                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1275                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1276                         };
1277                         pk3 { /* NC */
1278                                 nvidia,pins = "pk3";
1279                                 nvidia,function = "gmi";
1280                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1281                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1282                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1283                         };
1284                         pk4 { /* NC */
1285                                 nvidia,pins = "pk4";
1286                                 nvidia,function = "rsvd2";
1287                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1288                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1289                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1290                         };
1291                         dap1_fs_pn0 { /* NC */
1292                                 nvidia,pins = "dap1_fs_pn0";
1293                                 nvidia,function = "rsvd4";
1294                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1295                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1296                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1297                         };
1298                         dap1_din_pn1 { /* NC */
1299                                 nvidia,pins = "dap1_din_pn1";
1300                                 nvidia,function = "rsvd4";
1301                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1302                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1303                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1304                         };
1305                         dap1_sclk_pn3 { /* NC */
1306                                 nvidia,pins = "dap1_sclk_pn3";
1307                                 nvidia,function = "rsvd4";
1308                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1309                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1310                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1311                         };
1312                         ulpi_data7_po0 { /* NC */
1313                                 nvidia,pins = "ulpi_data7_po0";
1314                                 nvidia,function = "ulpi";
1315                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1316                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1317                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1318                         };
1319                         ulpi_data0_po1 { /* NC */
1320                                 nvidia,pins = "ulpi_data0_po1";
1321                                 nvidia,function = "ulpi";
1322                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1323                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1324                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1325                         };
1326                         ulpi_data1_po2 { /* NC */
1327                                 nvidia,pins = "ulpi_data1_po2";
1328                                 nvidia,function = "ulpi";
1329                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1330                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1331                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1332                         };
1333                         ulpi_data2_po3 { /* NC */
1334                                 nvidia,pins = "ulpi_data2_po3";
1335                                 nvidia,function = "ulpi";
1336                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1337                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1338                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1339                         };
1340                         ulpi_data3_po4 { /* NC */
1341                                 nvidia,pins = "ulpi_data3_po4";
1342                                 nvidia,function = "ulpi";
1343                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1344                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1345                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1346                         };
1347                         ulpi_data6_po7 { /* NC */
1348                                 nvidia,pins = "ulpi_data6_po7";
1349                                 nvidia,function = "ulpi";
1350                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1351                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1352                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1353                         };
1354                         dap4_fs_pp4 { /* NC */
1355                                 nvidia,pins = "dap4_fs_pp4";
1356                                 nvidia,function = "rsvd4";
1357                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1358                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1359                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1360                         };
1361                         dap4_din_pp5 { /* NC */
1362                                 nvidia,pins = "dap4_din_pp5";
1363                                 nvidia,function = "rsvd3";
1364                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1365                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1366                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1367                         };
1368                         dap4_dout_pp6 { /* NC */
1369                                 nvidia,pins = "dap4_dout_pp6";
1370                                 nvidia,function = "rsvd4";
1371                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1372                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1373                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1374                         };
1375                         dap4_sclk_pp7 { /* NC */
1376                                 nvidia,pins = "dap4_sclk_pp7";
1377                                 nvidia,function = "rsvd3";
1378                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1379                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1380                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1381                         };
1382                         kb_col3_pq3 { /* NC */
1383                                 nvidia,pins = "kb_col3_pq3";
1384                                 nvidia,function = "kbc";
1385                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1386                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1387                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1388                         };
1389                         kb_row3_pr3 { /* NC */
1390                                 nvidia,pins = "kb_row3_pr3";
1391                                 nvidia,function = "kbc";
1392                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1393                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1394                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1395                         };
1396                         kb_row4_pr4 { /* NC */
1397                                 nvidia,pins = "kb_row4_pr4";
1398                                 nvidia,function = "rsvd3";
1399                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1400                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1401                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1402                         };
1403                         kb_row5_pr5 { /* NC */
1404                                 nvidia,pins = "kb_row5_pr5";
1405                                 nvidia,function = "rsvd3";
1406                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1407                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1408                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1409                         };
1410                         kb_row6_pr6 { /* NC */
1411                                 nvidia,pins = "kb_row6_pr6";
1412                                 nvidia,function = "kbc";
1413                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1414                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1415                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1416                         };
1417                         kb_row7_pr7 { /* NC */
1418                                 nvidia,pins = "kb_row7_pr7";
1419                                 nvidia,function = "rsvd2";
1420                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1421                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1422                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1423                         };
1424                         kb_row8_ps0 { /* NC */
1425                                 nvidia,pins = "kb_row8_ps0";
1426                                 nvidia,function = "rsvd2";
1427                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1428                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1429                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1430                         };
1431                         kb_row9_ps1 { /* NC */
1432                                 nvidia,pins = "kb_row9_ps1";
1433                                 nvidia,function = "rsvd2";
1434                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1435                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1436                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1437                         };
1438                         kb_row12_ps4 { /* NC */
1439                                 nvidia,pins = "kb_row12_ps4";
1440                                 nvidia,function = "rsvd2";
1441                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1442                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1443                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1444                         };
1445                         kb_row13_ps5 { /* NC */
1446                                 nvidia,pins = "kb_row13_ps5";
1447                                 nvidia,function = "rsvd2";
1448                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1449                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1450                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1451                         };
1452                         kb_row14_ps6 { /* NC */
1453                                 nvidia,pins = "kb_row14_ps6";
1454                                 nvidia,function = "rsvd2";
1455                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1456                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1457                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1458                         };
1459                         kb_row15_ps7 { /* NC */
1460                                 nvidia,pins = "kb_row15_ps7";
1461                                 nvidia,function = "rsvd3";
1462                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1463                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1464                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1465                         };
1466                         kb_row16_pt0 { /* NC */
1467                                 nvidia,pins = "kb_row16_pt0";
1468                                 nvidia,function = "rsvd2";
1469                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1470                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1471                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1472                         };
1473                         kb_row17_pt1 { /* NC */
1474                                 nvidia,pins = "kb_row17_pt1";
1475                                 nvidia,function = "rsvd2";
1476                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1477                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1478                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1479                         };
1480                         pu5 { /* NC */
1481                                 nvidia,pins = "pu5";
1482                                 nvidia,function = "gmi";
1483                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1484                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1485                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1486                         };
1487                         pv0 { /* NC */
1488                                 nvidia,pins = "pv0";
1489                                 nvidia,function = "rsvd1";
1490                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1491                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1492                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1493                         };
1494                         pv1 { /* NC */
1495                                 nvidia,pins = "pv1";
1496                                 nvidia,function = "rsvd1";
1497                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1498                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1499                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1500                         };
1501                         gpio_x1_aud_px1 { /* NC */
1502                                 nvidia,pins = "gpio_x1_aud_px1";
1503                                 nvidia,function = "rsvd2";
1504                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1505                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1506                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1507                         };
1508                         gpio_x3_aud_px3 { /* NC */
1509                                 nvidia,pins = "gpio_x3_aud_px3";
1510                                 nvidia,function = "rsvd4";
1511                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1512                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1513                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1514                         };
1515                         pbb7 { /* NC */
1516                                 nvidia,pins = "pbb7";
1517                                 nvidia,function = "rsvd2";
1518                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1519                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1520                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1521                         };
1522                         pcc1 { /* NC */
1523                                 nvidia,pins = "pcc1";
1524                                 nvidia,function = "rsvd2";
1525                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1526                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1527                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1528                         };
1529                         pcc2 { /* NC */
1530                                 nvidia,pins = "pcc2";
1531                                 nvidia,function = "rsvd2";
1532                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1533                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1534                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1535                         };
1536                         clk3_req_pee1 { /* NC */
1537                                 nvidia,pins = "clk3_req_pee1";
1538                                 nvidia,function = "rsvd2";
1539                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1540                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1541                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1542                         };
1543                         dap_mclk1_req_pee2 { /* NC */
1544                                 nvidia,pins = "dap_mclk1_req_pee2";
1545                                 nvidia,function = "rsvd4";
1546                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1547                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1548                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1549                         };
1550                         /*
1551                          * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1552                          * driver enabled aka not tristated and input driver
1553                          * enabled as well as it features some magic properties
1554                          * even though the external loopback is disabled and the
1555                          * internal loopback used as per
1556                          * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1557                          * bits being set to 0xfffd according to the TRM!
1558                          */
1559                         sdmmc3_clk_lb_out_pee4 { /* NC */
1560                                 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1561                                 nvidia,function = "sdmmc3";
1562                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1563                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1564                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1565                         };
1566                 };
1567         };
1568
1569         serial@70006040 {
1570                 compatible = "nvidia,tegra124-hsuart";
1571         };
1572
1573         serial@70006200 {
1574                 compatible = "nvidia,tegra124-hsuart";
1575         };
1576
1577         serial@70006300 {
1578                 compatible = "nvidia,tegra124-hsuart";
1579         };
1580
1581         hdmi_ddc: i2c@7000c400 {
1582                 clock-frequency = <100000>;
1583         };
1584
1585         /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1586         i2c@7000d000 {
1587                 status = "okay";
1588                 clock-frequency = <400000>;
1589
1590                 /* SGTL5000 audio codec */
1591                 sgtl5000: codec@a {
1592                         compatible = "fsl,sgtl5000";
1593                         reg = <0x0a>;
1594                         VDDA-supply = <&reg_3v3>;
1595                         VDDIO-supply = <&vddio_1v8>;
1596                         clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1597                 };
1598
1599                 pmic: pmic@40 {
1600                         compatible = "ams,as3722";
1601                         reg = <0x40>;
1602                         interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1603
1604                         ams,system-power-controller;
1605
1606                         #interrupt-cells = <2>;
1607                         interrupt-controller;
1608
1609                         gpio-controller;
1610                         #gpio-cells = <2>;
1611
1612                         pinctrl-names = "default";
1613                         pinctrl-0 = <&as3722_default>;
1614
1615                         as3722_default: pinmux {
1616                                 gpio2_7 {
1617                                         pins = "gpio2", /* PWR_EN_+V3.3 */
1618                                                "gpio7"; /* +V1.6_LPO */
1619                                         function = "gpio";
1620                                         bias-pull-up;
1621                                 };
1622
1623                                 gpio1_3_4_5_6 {
1624                                         pins = "gpio1", "gpio3", "gpio4",
1625                                                "gpio5", "gpio6";
1626                                         bias-high-impedance;
1627                                 };
1628                         };
1629
1630                         regulators {
1631                                 vsup-sd2-supply = <&reg_3v3>;
1632                                 vsup-sd3-supply = <&reg_3v3>;
1633                                 vsup-sd4-supply = <&reg_3v3>;
1634                                 vsup-sd5-supply = <&reg_3v3>;
1635                                 vin-ldo0-supply = <&vddio_ddr_1v35>;
1636                                 vin-ldo1-6-supply = <&reg_3v3>;
1637                                 vin-ldo2-5-7-supply = <&vddio_1v8>;
1638                                 vin-ldo3-4-supply = <&reg_3v3>;
1639                                 vin-ldo9-10-supply = <&reg_3v3>;
1640                                 vin-ldo11-supply = <&reg_3v3>;
1641
1642                                 vdd_cpu: sd0 {
1643                                         regulator-name = "+VDD_CPU_AP";
1644                                         regulator-min-microvolt = <700000>;
1645                                         regulator-max-microvolt = <1400000>;
1646                                         regulator-min-microamp = <3500000>;
1647                                         regulator-max-microamp = <3500000>;
1648                                         regulator-always-on;
1649                                         regulator-boot-on;
1650                                         ams,ext-control = <2>;
1651                                 };
1652
1653                                 sd1 {
1654                                         regulator-name = "+VDD_CORE";
1655                                         regulator-min-microvolt = <700000>;
1656                                         regulator-max-microvolt = <1350000>;
1657                                         regulator-min-microamp = <2500000>;
1658                                         regulator-max-microamp = <4000000>;
1659                                         regulator-always-on;
1660                                         regulator-boot-on;
1661                                         ams,ext-control = <1>;
1662                                 };
1663
1664                                 vddio_ddr_1v35: sd2 {
1665                                         regulator-name =
1666                                                 "+V1.35_VDDIO_DDR(sd2)";
1667                                         regulator-min-microvolt = <1350000>;
1668                                         regulator-max-microvolt = <1350000>;
1669                                         regulator-always-on;
1670                                         regulator-boot-on;
1671                                 };
1672
1673                                 sd3 {
1674                                         regulator-name =
1675                                                 "+V1.35_VDDIO_DDR(sd3)";
1676                                         regulator-min-microvolt = <1350000>;
1677                                         regulator-max-microvolt = <1350000>;
1678                                         regulator-always-on;
1679                                         regulator-boot-on;
1680                                 };
1681
1682                                 vdd_1v05: sd4 {
1683                                         regulator-name = "+V1.05";
1684                                         regulator-min-microvolt = <1050000>;
1685                                         regulator-max-microvolt = <1050000>;
1686                                 };
1687
1688                                 vddio_1v8: sd5 {
1689                                         regulator-name = "+V1.8";
1690                                         regulator-min-microvolt = <1800000>;
1691                                         regulator-max-microvolt = <1800000>;
1692                                         regulator-boot-on;
1693                                         regulator-always-on;
1694                                 };
1695
1696                                 vdd_gpu: sd6 {
1697                                         regulator-name = "+VDD_GPU_AP";
1698                                         regulator-min-microvolt = <650000>;
1699                                         regulator-max-microvolt = <1200000>;
1700                                         regulator-min-microamp = <3500000>;
1701                                         regulator-max-microamp = <3500000>;
1702                                         regulator-boot-on;
1703                                         regulator-always-on;
1704                                 };
1705
1706                                 avdd_1v05: ldo0 {
1707                                         regulator-name = "+V1.05_AVDD";
1708                                         regulator-min-microvolt = <1050000>;
1709                                         regulator-max-microvolt = <1050000>;
1710                                         regulator-boot-on;
1711                                         regulator-always-on;
1712                                         ams,ext-control = <1>;
1713                                 };
1714
1715                                 vddio_sdmmc1: ldo1 {
1716                                         regulator-name = "VDDIO_SDMMC1";
1717                                         regulator-min-microvolt = <1800000>;
1718                                         regulator-max-microvolt = <3300000>;
1719                                 };
1720
1721                                 ldo2 {
1722                                         regulator-name = "+V1.2";
1723                                         regulator-min-microvolt = <1200000>;
1724                                         regulator-max-microvolt = <1200000>;
1725                                         regulator-boot-on;
1726                                         regulator-always-on;
1727                                 };
1728
1729                                 ldo3 {
1730                                         regulator-name = "+V1.05_RTC";
1731                                         regulator-min-microvolt = <1000000>;
1732                                         regulator-max-microvolt = <1000000>;
1733                                         regulator-boot-on;
1734                                         regulator-always-on;
1735                                         ams,enable-tracking;
1736                                 };
1737
1738                                 /* 1.8V for LVDS, 3.3V for eDP */
1739                                 ldo4 {
1740                                         regulator-name = "AVDD_LVDS0_PLL";
1741                                         regulator-min-microvolt = <1800000>;
1742                                         regulator-max-microvolt = <1800000>;
1743                                 };
1744
1745                                 /* LDO5 not used */
1746
1747                                 vddio_sdmmc3: ldo6 {
1748                                         regulator-name = "VDDIO_SDMMC3";
1749                                         regulator-min-microvolt = <1800000>;
1750                                         regulator-max-microvolt = <3300000>;
1751                                 };
1752
1753                                 /* LDO7 not used */
1754
1755                                 ldo9 {
1756                                         regulator-name = "+V3.3_ETH(ldo9)";
1757                                         regulator-min-microvolt = <3300000>;
1758                                         regulator-max-microvolt = <3300000>;
1759                                         regulator-always-on;
1760                                 };
1761
1762                                 ldo10 {
1763                                         regulator-name = "+V3.3_ETH(ldo10)";
1764                                         regulator-min-microvolt = <3300000>;
1765                                         regulator-max-microvolt = <3300000>;
1766                                         regulator-always-on;
1767                                 };
1768
1769                                 ldo11 {
1770                                         regulator-name = "+V1.8_VPP_FUSE";
1771                                         regulator-min-microvolt = <1800000>;
1772                                         regulator-max-microvolt = <1800000>;
1773                                 };
1774                         };
1775                 };
1776
1777                 /*
1778                  * TMP451 temperature sensor
1779                  * Note: THERM_N directly connected to AS3722 PMIC THERM
1780                  */
1781                 temperature-sensor@4c {
1782                         compatible = "ti,tmp451";
1783                         reg = <0x4c>;
1784                         interrupt-parent = <&gpio>;
1785                         interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1786
1787                         #thermal-sensor-cells = <1>;
1788                 };
1789         };
1790
1791         /* SPI2: MCU SPI */
1792         spi@7000d600 {
1793                 status = "okay";
1794                 spi-max-frequency = <25000000>;
1795         };
1796
1797         pmc@7000e400 {
1798                 nvidia,invert-interrupt;
1799                 nvidia,suspend-mode = <1>;
1800                 nvidia,cpu-pwr-good-time = <500>;
1801                 nvidia,cpu-pwr-off-time = <300>;
1802                 nvidia,core-pwr-good-time = <641 3845>;
1803                 nvidia,core-pwr-off-time = <61036>;
1804                 nvidia,core-power-req-active-high;
1805                 nvidia,sys-clock-req-active-high;
1806
1807                 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1808                 i2c-thermtrip {
1809                         nvidia,i2c-controller-id = <4>;
1810                         nvidia,bus-addr = <0x40>;
1811                         nvidia,reg-addr = <0x36>;
1812                         nvidia,reg-data = <0x2>;
1813                 };
1814         };
1815
1816         sata@70020000 {
1817                 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1818                 phy-names = "sata-0";
1819
1820                 avdd-supply = <&vdd_1v05>;
1821                 hvdd-supply = <&reg_3v3>;
1822                 vddio-supply = <&vdd_1v05>;
1823         };
1824
1825         usb@70090000 {
1826                 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1827                 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1828                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1829                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1830                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1831                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1832                 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1833
1834                 avddio-pex-supply = <&vdd_1v05>;
1835                 avdd-pll-erefe-supply = <&avdd_1v05>;
1836                 avdd-pll-utmip-supply = <&vddio_1v8>;
1837                 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1838                 avdd-usb-supply = <&reg_3v3>;
1839                 dvddio-pex-supply = <&vdd_1v05>;
1840                 hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
1841                 hvdd-usb-ss-supply = <&reg_3v3>;
1842         };
1843
1844         padctl@7009f000 {
1845                 pads {
1846                         usb2 {
1847                                 status = "okay";
1848
1849                                 lanes {
1850                                         usb2-0 {
1851                                                 nvidia,function = "xusb";
1852                                                 status = "okay";
1853                                         };
1854
1855                                         usb2-1 {
1856                                                 nvidia,function = "xusb";
1857                                                 status = "okay";
1858                                         };
1859
1860                                         usb2-2 {
1861                                                 nvidia,function = "xusb";
1862                                                 status = "okay";
1863                                         };
1864                                 };
1865                         };
1866
1867                         pcie {
1868                                 status = "okay";
1869
1870                                 lanes {
1871                                         pcie-0 {
1872                                                 nvidia,function = "usb3-ss";
1873                                                 status = "okay";
1874                                         };
1875
1876                                         pcie-1 {
1877                                                 nvidia,function = "usb3-ss";
1878                                                 status = "okay";
1879                                         };
1880
1881                                         pcie-2 {
1882                                                 nvidia,function = "pcie";
1883                                                 status = "okay";
1884                                         };
1885
1886                                         pcie-3 {
1887                                                 nvidia,function = "pcie";
1888                                                 status = "okay";
1889                                         };
1890
1891                                         pcie-4 {
1892                                                 nvidia,function = "pcie";
1893                                                 status = "okay";
1894                                         };
1895                                 };
1896                         };
1897
1898                         sata {
1899                                 status = "okay";
1900
1901                                 lanes {
1902                                         sata-0 {
1903                                                 nvidia,function = "sata";
1904                                                 status = "okay";
1905                                         };
1906                                 };
1907                         };
1908                 };
1909
1910                 ports {
1911                         /* USBO1 */
1912                         usb2-0 {
1913                                 status = "okay";
1914                                 mode = "otg";
1915
1916                                 vbus-supply = <&reg_usbo1_vbus>;
1917                         };
1918
1919                         /* USBH2 */
1920                         usb2-1 {
1921                                 status = "okay";
1922                                 mode = "host";
1923
1924                                 vbus-supply = <&reg_usbh_vbus>;
1925                         };
1926
1927                         /* USBH4 */
1928                         usb2-2 {
1929                                 status = "okay";
1930                                 mode = "host";
1931
1932                                 vbus-supply = <&reg_usbh_vbus>;
1933                         };
1934
1935                         usb3-0 {
1936                                 nvidia,usb2-companion = <2>;
1937                                 status = "okay";
1938                         };
1939
1940                         usb3-1 {
1941                                 nvidia,usb2-companion = <0>;
1942                                 status = "okay";
1943                         };
1944                 };
1945         };
1946
1947         /* eMMC */
1948         sdhci@700b0600 {
1949                 status = "okay";
1950                 bus-width = <8>;
1951                 non-removable;
1952         };
1953
1954         /* CPU DFLL clock */
1955         clock@70110000 {
1956                 status = "okay";
1957                 vdd-cpu-supply = <&vdd_cpu>;
1958                 nvidia,i2c-fs-rate = <400000>;
1959         };
1960
1961         ahub@70300000 {
1962                 i2s@70301200 {
1963                         status = "okay";
1964                 };
1965         };
1966
1967         clocks {
1968                 compatible = "simple-bus";
1969                 #address-cells = <1>;
1970                 #size-cells = <0>;
1971
1972                 clk32k_in: clock@0 {
1973                         compatible = "fixed-clock";
1974                         reg = <0>;
1975                         #clock-cells = <0>;
1976                         clock-frequency = <32768>;
1977                 };
1978         };
1979
1980         cpus {
1981                 cpu@0 {
1982                         vdd-cpu-supply = <&vdd_cpu>;
1983                 };
1984         };
1985
1986         reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1987                 compatible = "regulator-fixed";
1988                 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1989                 regulator-min-microvolt = <1050000>;
1990                 regulator-max-microvolt = <1050000>;
1991                 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1992                 vin-supply = <&vdd_1v05>;
1993         };
1994
1995         reg_3v3_mxm: regulator-3v3-mxm {
1996                 compatible = "regulator-fixed";
1997                 regulator-name = "+V3.3_MXM";
1998                 regulator-min-microvolt = <3300000>;
1999                 regulator-max-microvolt = <3300000>;
2000                 regulator-always-on;
2001                 regulator-boot-on;
2002         };
2003
2004         reg_3v3: regulator-3v3 {
2005                 compatible = "regulator-fixed";
2006                 regulator-name = "+V3.3";
2007                 regulator-min-microvolt = <3300000>;
2008                 regulator-max-microvolt = <3300000>;
2009                 regulator-always-on;
2010                 regulator-boot-on;
2011                 /* PWR_EN_+V3.3 */
2012                 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2013                 enable-active-high;
2014                 vin-supply = <&reg_3v3_mxm>;
2015         };
2016
2017         reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
2018                 compatible = "regulator-fixed";
2019                 regulator-name = "+V3.3_AVDD_HDMI";
2020                 regulator-min-microvolt = <3300000>;
2021                 regulator-max-microvolt = <3300000>;
2022                 vin-supply = <&vdd_1v05>;
2023         };
2024
2025         sound {
2026                 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2027                              "nvidia,tegra-audio-sgtl5000";
2028                 nvidia,model = "Toradex Apalis TK1";
2029                 nvidia,audio-routing =
2030                         "Headphone Jack", "HP_OUT",
2031                         "LINE_IN", "Line In Jack",
2032                         "MIC_IN", "Mic Jack";
2033                 nvidia,i2s-controller = <&tegra_i2s2>;
2034                 nvidia,audio-codec = <&sgtl5000>;
2035                 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2036                          <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2037                          <&tegra_car TEGRA124_CLK_EXTERN1>;
2038                 clock-names = "pll_a", "pll_a_out0", "mclk";
2039         };
2040
2041         thermal-zones {
2042                 cpu {
2043                         trips {
2044                                 trip@0 {
2045                                         temperature = <101000>;
2046                                         hysteresis = <0>;
2047                                         type = "critical";
2048                                 };
2049                         };
2050
2051                         cooling-maps {
2052                                 /*
2053                                  * There are currently no cooling maps because
2054                                  * there are no cooling devices
2055                                  */
2056                         };
2057                 };
2058
2059                 mem {
2060                         trips {
2061                                 trip@0 {
2062                                         temperature = <101000>;
2063                                         hysteresis = <0>;
2064                                         type = "critical";
2065                                 };
2066                         };
2067
2068                         cooling-maps {
2069                                 /*
2070                                  * There are currently no cooling maps because
2071                                  * there are no cooling devices
2072                                  */
2073                         };
2074                 };
2075
2076                 gpu {
2077                         trips {
2078                                 trip@0 {
2079                                         temperature = <101000>;
2080                                         hysteresis = <0>;
2081                                         type = "critical";
2082                                 };
2083                         };
2084
2085                         cooling-maps {
2086                                 /*
2087                                  * There are currently no cooling maps because
2088                                  * there are no cooling devices
2089                                  */
2090                         };
2091                 };
2092         };
2093 };