arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra30-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra30";
  11         interrupt-parent = <&lic>;
  12
  13         pcie@3000 {
  14                 compatible = "nvidia,tegra30-pcie";
  15                 device_type = "pci";
  16                 reg = <0x00003000 0x00000800   /* PADS registers */
  17                        0x00003800 0x00000200   /* AFI registers */
  18                        0x10000000 0x10000000>; /* configuration space */
  19                 reg-names = "pads", "afi", "cs";
  20                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  21                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  22                 interrupt-names = "intr", "msi";
  23
  24                 #interrupt-cells = <1>;
  25                 interrupt-map-mask = <0 0 0 0>;
  26                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  27
  28                 bus-range = <0x00 0xff>;
  29                 #address-cells = <3>;
  30                 #size-cells = <2>;
  31
  32                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  33                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  34                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  35                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  36                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  37                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  38
  39                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  40                          <&tegra_car TEGRA30_CLK_AFI>,
  41                          <&tegra_car TEGRA30_CLK_PLL_E>,
  42                          <&tegra_car TEGRA30_CLK_CML0>;
  43                 clock-names = "pex", "afi", "pll_e", "cml";
  44                 resets = <&tegra_car 70>,
  45                          <&tegra_car 72>,
  46                          <&tegra_car 74>;
  47                 reset-names = "pex", "afi", "pcie_x";
  48                 status = "disabled";
  49
  50                 pci@1,0 {
  51                         device_type = "pci";
  52                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  53                         reg = <0x000800 0 0 0 0>;
  54                         bus-range = <0x00 0xff>;
  55                         status = "disabled";
  56
  57                         #address-cells = <3>;
  58                         #size-cells = <2>;
  59                         ranges;
  60
  61                         nvidia,num-lanes = <2>;
  62                 };
  63
  64                 pci@2,0 {
  65                         device_type = "pci";
  66                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  67                         reg = <0x001000 0 0 0 0>;
  68                         bus-range = <0x00 0xff>;
  69                         status = "disabled";
  70
  71                         #address-cells = <3>;
  72                         #size-cells = <2>;
  73                         ranges;
  74
  75                         nvidia,num-lanes = <2>;
  76                 };
  77
  78                 pci@3,0 {
  79                         device_type = "pci";
  80                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  81                         reg = <0x001800 0 0 0 0>;
  82                         bus-range = <0x00 0xff>;
  83                         status = "disabled";
  84
  85                         #address-cells = <3>;
  86                         #size-cells = <2>;
  87                         ranges;
  88
  89                         nvidia,num-lanes = <2>;
  90                 };
  91         };
  92
  93         host1x@50000000 {
  94                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  95                 reg = <0x50000000 0x00024000>;
  96                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  97                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  98                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  99                 resets = <&tegra_car 28>;
 100                 reset-names = "host1x";
 101
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104
 105                 ranges = <0x54000000 0x54000000 0x04000000>;
 106
 107                 mpe@54040000 {
 108                         compatible = "nvidia,tegra30-mpe";
 109                         reg = <0x54040000 0x00040000>;
 110                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 111                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 112                         resets = <&tegra_car 60>;
 113                         reset-names = "mpe";
 114                 };
 115
 116                 vi@54080000 {
 117                         compatible = "nvidia,tegra30-vi";
 118                         reg = <0x54080000 0x00040000>;
 119                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 121                         resets = <&tegra_car 20>;
 122                         reset-names = "vi";
 123                 };
 124
 125                 epp@540c0000 {
 126                         compatible = "nvidia,tegra30-epp";
 127                         reg = <0x540c0000 0x00040000>;
 128                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 130                         resets = <&tegra_car 19>;
 131                         reset-names = "epp";
 132                 };
 133
 134                 isp@54100000 {
 135                         compatible = "nvidia,tegra30-isp";
 136                         reg = <0x54100000 0x00040000>;
 137                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 139                         resets = <&tegra_car 23>;
 140                         reset-names = "isp";
 141                 };
 142
 143                 gr2d@54140000 {
 144                         compatible = "nvidia,tegra30-gr2d";
 145                         reg = <0x54140000 0x00040000>;
 146                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 148                         resets = <&tegra_car 21>;
 149                         reset-names = "2d";
 150                 };
 151
 152                 gr3d@54180000 {
 153                         compatible = "nvidia,tegra30-gr3d";
 154                         reg = <0x54180000 0x00040000>;
 155                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 156                                   &tegra_car TEGRA30_CLK_GR3D2>;
 157                         clock-names = "3d", "3d2";
 158                         resets = <&tegra_car 24>,
 159                                  <&tegra_car 98>;
 160                         reset-names = "3d", "3d2";
 161                 };
 162
 163                 dc@54200000 {
 164                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 165                         reg = <0x54200000 0x00040000>;
 166                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 168                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 169                         clock-names = "dc", "parent";
 170                         resets = <&tegra_car 27>;
 171                         reset-names = "dc";
 172
 173                         iommus = <&mc TEGRA_SWGROUP_DC>;
 174
 175                         nvidia,head = <0>;
 176
 177                         rgb {
 178                                 status = "disabled";
 179                         };
 180                 };
 181
 182                 dc@54240000 {
 183                         compatible = "nvidia,tegra30-dc";
 184                         reg = <0x54240000 0x00040000>;
 185                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 187                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 188                         clock-names = "dc", "parent";
 189                         resets = <&tegra_car 26>;
 190                         reset-names = "dc";
 191
 192                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 193
 194                         nvidia,head = <1>;
 195
 196                         rgb {
 197                                 status = "disabled";
 198                         };
 199                 };
 200
 201                 hdmi@54280000 {
 202                         compatible = "nvidia,tegra30-hdmi";
 203                         reg = <0x54280000 0x00040000>;
 204                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 206                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 207                         clock-names = "hdmi", "parent";
 208                         resets = <&tegra_car 51>;
 209                         reset-names = "hdmi";
 210                         status = "disabled";
 211                 };
 212
 213                 tvo@542c0000 {
 214                         compatible = "nvidia,tegra30-tvo";
 215                         reg = <0x542c0000 0x00040000>;
 216                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 218                         status = "disabled";
 219                 };
 220
 221                 dsi@54300000 {
 222                         compatible = "nvidia,tegra30-dsi";
 223                         reg = <0x54300000 0x00040000>;
 224                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 225                         resets = <&tegra_car 48>;
 226                         reset-names = "dsi";
 227                         status = "disabled";
 228                 };
 229         };
 230
 231         timer@50040600 {
 232                 compatible = "arm,cortex-a9-twd-timer";
 233                 reg = <0x50040600 0x20>;
 234                 interrupt-parent = <&intc>;
 235                 interrupts = <GIC_PPI 13
 236                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 237                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 238         };
 239
 240         intc: interrupt-controller@50041000 {
 241                 compatible = "arm,cortex-a9-gic";
 242                 reg = <0x50041000 0x1000
 243                        0x50040100 0x0100>;
 244                 interrupt-controller;
 245                 #interrupt-cells = <3>;
 246                 interrupt-parent = <&intc>;
 247         };
 248
 249         cache-controller@50043000 {
 250                 compatible = "arm,pl310-cache";
 251                 reg = <0x50043000 0x1000>;
 252                 arm,data-latency = <6 6 2>;
 253                 arm,tag-latency = <5 5 2>;
 254                 cache-unified;
 255                 cache-level = <2>;
 256         };
 257
 258         lic: interrupt-controller@60004000 {
 259                 compatible = "nvidia,tegra30-ictlr";
 260                 reg = <0x60004000 0x100>,
 261                       <0x60004100 0x50>,
 262                       <0x60004200 0x50>,
 263                       <0x60004300 0x50>,
 264                       <0x60004400 0x50>;
 265                 interrupt-controller;
 266                 #interrupt-cells = <3>;
 267                 interrupt-parent = <&intc>;
 268         };
 269
 270         timer@60005000 {
 271                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 272                 reg = <0x60005000 0x400>;
 273                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 280         };
 281
 282         tegra_car: clock@60006000 {
 283                 compatible = "nvidia,tegra30-car";
 284                 reg = <0x60006000 0x1000>;
 285                 #clock-cells = <1>;
 286                 #reset-cells = <1>;
 287         };
 288
 289         flow-controller@60007000 {
 290                 compatible = "nvidia,tegra30-flowctrl";
 291                 reg = <0x60007000 0x1000>;
 292         };
 293
 294         apbdma: dma@6000a000 {
 295                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 296                 reg = <0x6000a000 0x1400>;
 297                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 330                 resets = <&tegra_car 34>;
 331                 reset-names = "dma";
 332                 #dma-cells = <1>;
 333         };
 334
 335         ahb: ahb@6000c000 {
 336                 compatible = "nvidia,tegra30-ahb";
 337                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 338         };
 339
 340         gpio: gpio@6000d000 {
 341                 compatible = "nvidia,tegra30-gpio";
 342                 reg = <0x6000d000 0x1000>;
 343                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 351                 #gpio-cells = <2>;
 352                 gpio-controller;
 353                 #interrupt-cells = <2>;
 354                 interrupt-controller;
 355                 /*
 356                 gpio-ranges = <&pinmux 0 0 248>;
 357                 */
 358         };
 359
 360         apbmisc@70000800 {
 361                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 362                 reg = <0x70000800 0x64   /* Chip revision */
 363                        0x70000008 0x04>; /* Strapping options */
 364         };
 365
 366         pinmux: pinmux@70000868 {
 367                 compatible = "nvidia,tegra30-pinmux";
 368                 reg = <0x70000868 0xd4    /* Pad control registers */
 369                        0x70003000 0x3e4>; /* Mux registers */
 370         };
 371
 372         /*
 373          * There are two serial driver i.e. 8250 based simple serial
 374          * driver and APB DMA based serial driver for higher baudrate
 375          * and performace. To enable the 8250 based driver, the compatible
 376          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 377          * the APB DMA based serial driver, the compatible is
 378          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 379          */
 380         uarta: serial@70006000 {
 381                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 382                 reg = <0x70006000 0x40>;
 383                 reg-shift = <2>;
 384                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 385                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 386                 resets = <&tegra_car 6>;
 387                 reset-names = "serial";
 388                 dmas = <&apbdma 8>, <&apbdma 8>;
 389                 dma-names = "rx", "tx";
 390                 status = "disabled";
 391         };
 392
 393         uartb: serial@70006040 {
 394                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 395                 reg = <0x70006040 0x40>;
 396                 reg-shift = <2>;
 397                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 399                 resets = <&tegra_car 7>;
 400                 reset-names = "serial";
 401                 dmas = <&apbdma 9>, <&apbdma 9>;
 402                 dma-names = "rx", "tx";
 403                 status = "disabled";
 404         };
 405
 406         uartc: serial@70006200 {
 407                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 408                 reg = <0x70006200 0x100>;
 409                 reg-shift = <2>;
 410                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 412                 resets = <&tegra_car 55>;
 413                 reset-names = "serial";
 414                 dmas = <&apbdma 10>, <&apbdma 10>;
 415                 dma-names = "rx", "tx";
 416                 status = "disabled";
 417         };
 418
 419         uartd: serial@70006300 {
 420                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 421                 reg = <0x70006300 0x100>;
 422                 reg-shift = <2>;
 423                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 425                 resets = <&tegra_car 65>;
 426                 reset-names = "serial";
 427                 dmas = <&apbdma 19>, <&apbdma 19>;
 428                 dma-names = "rx", "tx";
 429                 status = "disabled";
 430         };
 431
 432         uarte: serial@70006400 {
 433                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 434                 reg = <0x70006400 0x100>;
 435                 reg-shift = <2>;
 436                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 438                 resets = <&tegra_car 66>;
 439                 reset-names = "serial";
 440                 dmas = <&apbdma 20>, <&apbdma 20>;
 441                 dma-names = "rx", "tx";
 442                 status = "disabled";
 443         };
 444
 445         gmi@70009000 {
 446                 compatible = "nvidia,tegra30-gmi";
 447                 reg = <0x70009000 0x1000>;
 448                 #address-cells = <2>;
 449                 #size-cells = <1>;
 450                 ranges = <0 0 0x48000000 0x7ffffff>;
 451                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 452                 clock-names = "gmi";
 453                 resets = <&tegra_car 42>;
 454                 reset-names = "gmi";
 455                 status = "disabled";
 456         };
 457
 458         pwm: pwm@7000a000 {
 459                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 460                 reg = <0x7000a000 0x100>;
 461                 #pwm-cells = <2>;
 462                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 463                 resets = <&tegra_car 17>;
 464                 reset-names = "pwm";
 465                 status = "disabled";
 466         };
 467
 468         rtc@7000e000 {
 469                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 470                 reg = <0x7000e000 0x100>;
 471                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 473         };
 474
 475         i2c@7000c000 {
 476                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 477                 reg = <0x7000c000 0x100>;
 478                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 482                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 483                 clock-names = "div-clk", "fast-clk";
 484                 resets = <&tegra_car 12>;
 485                 reset-names = "i2c";
 486                 dmas = <&apbdma 21>, <&apbdma 21>;
 487                 dma-names = "rx", "tx";
 488                 status = "disabled";
 489         };
 490
 491         i2c@7000c400 {
 492                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 493                 reg = <0x7000c400 0x100>;
 494                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 498                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 499                 clock-names = "div-clk", "fast-clk";
 500                 resets = <&tegra_car 54>;
 501                 reset-names = "i2c";
 502                 dmas = <&apbdma 22>, <&apbdma 22>;
 503                 dma-names = "rx", "tx";
 504                 status = "disabled";
 505         };
 506
 507         i2c@7000c500 {
 508                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 509                 reg = <0x7000c500 0x100>;
 510                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 514                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 515                 clock-names = "div-clk", "fast-clk";
 516                 resets = <&tegra_car 67>;
 517                 reset-names = "i2c";
 518                 dmas = <&apbdma 23>, <&apbdma 23>;
 519                 dma-names = "rx", "tx";
 520                 status = "disabled";
 521         };
 522
 523         i2c@7000c700 {
 524                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 525                 reg = <0x7000c700 0x100>;
 526                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 530                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 531                 resets = <&tegra_car 103>;
 532                 reset-names = "i2c";
 533                 clock-names = "div-clk", "fast-clk";
 534                 dmas = <&apbdma 26>, <&apbdma 26>;
 535                 dma-names = "rx", "tx";
 536                 status = "disabled";
 537         };
 538
 539         i2c@7000d000 {
 540                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 541                 reg = <0x7000d000 0x100>;
 542                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 546                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 547                 clock-names = "div-clk", "fast-clk";
 548                 resets = <&tegra_car 47>;
 549                 reset-names = "i2c";
 550                 dmas = <&apbdma 24>, <&apbdma 24>;
 551                 dma-names = "rx", "tx";
 552                 status = "disabled";
 553         };
 554
 555         spi@7000d400 {
 556                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 557                 reg = <0x7000d400 0x200>;
 558                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 562                 resets = <&tegra_car 41>;
 563                 reset-names = "spi";
 564                 dmas = <&apbdma 15>, <&apbdma 15>;
 565                 dma-names = "rx", "tx";
 566                 status = "disabled";
 567         };
 568
 569         spi@7000d600 {
 570                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 571                 reg = <0x7000d600 0x200>;
 572                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 576                 resets = <&tegra_car 44>;
 577                 reset-names = "spi";
 578                 dmas = <&apbdma 16>, <&apbdma 16>;
 579                 dma-names = "rx", "tx";
 580                 status = "disabled";
 581         };
 582
 583         spi@7000d800 {
 584                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 585                 reg = <0x7000d800 0x200>;
 586                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 590                 resets = <&tegra_car 46>;
 591                 reset-names = "spi";
 592                 dmas = <&apbdma 17>, <&apbdma 17>;
 593                 dma-names = "rx", "tx";
 594                 status = "disabled";
 595         };
 596
 597         spi@7000da00 {
 598                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 599                 reg = <0x7000da00 0x200>;
 600                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 604                 resets = <&tegra_car 68>;
 605                 reset-names = "spi";
 606                 dmas = <&apbdma 18>, <&apbdma 18>;
 607                 dma-names = "rx", "tx";
 608                 status = "disabled";
 609         };
 610
 611         spi@7000dc00 {
 612                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 613                 reg = <0x7000dc00 0x200>;
 614                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 618                 resets = <&tegra_car 104>;
 619                 reset-names = "spi";
 620                 dmas = <&apbdma 27>, <&apbdma 27>;
 621                 dma-names = "rx", "tx";
 622                 status = "disabled";
 623         };
 624
 625         spi@7000de00 {
 626                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 627                 reg = <0x7000de00 0x200>;
 628                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 632                 resets = <&tegra_car 106>;
 633                 reset-names = "spi";
 634                 dmas = <&apbdma 28>, <&apbdma 28>;
 635                 dma-names = "rx", "tx";
 636                 status = "disabled";
 637         };
 638
 639         kbc@7000e200 {
 640                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 641                 reg = <0x7000e200 0x100>;
 642                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 643                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 644                 resets = <&tegra_car 36>;
 645                 reset-names = "kbc";
 646                 status = "disabled";
 647         };
 648
 649         pmc@7000e400 {
 650                 compatible = "nvidia,tegra30-pmc";
 651                 reg = <0x7000e400 0x400>;
 652                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 653                 clock-names = "pclk", "clk32k_in";
 654         };
 655
 656         mc: memory-controller@7000f000 {
 657                 compatible = "nvidia,tegra30-mc";
 658                 reg = <0x7000f000 0x400>;
 659                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 660                 clock-names = "mc";
 661
 662                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 663
 664                 #iommu-cells = <1>;
 665         };
 666
 667         fuse@7000f800 {
 668                 compatible = "nvidia,tegra30-efuse";
 669                 reg = <0x7000f800 0x400>;
 670                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 671                 clock-names = "fuse";
 672                 resets = <&tegra_car 39>;
 673                 reset-names = "fuse";
 674         };
 675
 676         hda@70030000 {
 677                 compatible = "nvidia,tegra30-hda";
 678                 reg = <0x70030000 0x10000>;
 679                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 680                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 681                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 682                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 683                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 684                 resets = <&tegra_car 125>, /* hda */
 685                          <&tegra_car 128>, /* hda2hdmi */
 686                          <&tegra_car 111>; /* hda2codec_2x */
 687                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 688                 status = "disabled";
 689         };
 690
 691         ahub@70080000 {
 692                 compatible = "nvidia,tegra30-ahub";
 693                 reg = <0x70080000 0x200
 694                        0x70080200 0x100>;
 695                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 697                          <&tegra_car TEGRA30_CLK_APBIF>;
 698                 clock-names = "d_audio", "apbif";
 699                 resets = <&tegra_car 106>, /* d_audio */
 700                          <&tegra_car 107>, /* apbif */
 701                          <&tegra_car 30>,  /* i2s0 */
 702                          <&tegra_car 11>,  /* i2s1 */
 703                          <&tegra_car 18>,  /* i2s2 */
 704                          <&tegra_car 101>, /* i2s3 */
 705                          <&tegra_car 102>, /* i2s4 */
 706                          <&tegra_car 108>, /* dam0 */
 707                          <&tegra_car 109>, /* dam1 */
 708                          <&tegra_car 110>, /* dam2 */
 709                          <&tegra_car 10>;  /* spdif */
 710                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 711                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 712                               "spdif";
 713                 dmas = <&apbdma 1>, <&apbdma 1>,
 714                        <&apbdma 2>, <&apbdma 2>,
 715                        <&apbdma 3>, <&apbdma 3>,
 716                        <&apbdma 4>, <&apbdma 4>;
 717                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 718                             "rx3", "tx3";
 719                 ranges;
 720                 #address-cells = <1>;
 721                 #size-cells = <1>;
 722
 723                 tegra_i2s0: i2s@70080300 {
 724                         compatible = "nvidia,tegra30-i2s";
 725                         reg = <0x70080300 0x100>;
 726                         nvidia,ahub-cif-ids = <4 4>;
 727                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 728                         resets = <&tegra_car 30>;
 729                         reset-names = "i2s";
 730                         status = "disabled";
 731                 };
 732
 733                 tegra_i2s1: i2s@70080400 {
 734                         compatible = "nvidia,tegra30-i2s";
 735                         reg = <0x70080400 0x100>;
 736                         nvidia,ahub-cif-ids = <5 5>;
 737                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 738                         resets = <&tegra_car 11>;
 739                         reset-names = "i2s";
 740                         status = "disabled";
 741                 };
 742
 743                 tegra_i2s2: i2s@70080500 {
 744                         compatible = "nvidia,tegra30-i2s";
 745                         reg = <0x70080500 0x100>;
 746                         nvidia,ahub-cif-ids = <6 6>;
 747                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 748                         resets = <&tegra_car 18>;
 749                         reset-names = "i2s";
 750                         status = "disabled";
 751                 };
 752
 753                 tegra_i2s3: i2s@70080600 {
 754                         compatible = "nvidia,tegra30-i2s";
 755                         reg = <0x70080600 0x100>;
 756                         nvidia,ahub-cif-ids = <7 7>;
 757                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 758                         resets = <&tegra_car 101>;
 759                         reset-names = "i2s";
 760                         status = "disabled";
 761                 };
 762
 763                 tegra_i2s4: i2s@70080700 {
 764                         compatible = "nvidia,tegra30-i2s";
 765                         reg = <0x70080700 0x100>;
 766                         nvidia,ahub-cif-ids = <8 8>;
 767                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 768                         resets = <&tegra_car 102>;
 769                         reset-names = "i2s";
 770                         status = "disabled";
 771                 };
 772         };
 773
 774         sdhci@78000000 {
 775                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 776                 reg = <0x78000000 0x200>;
 777                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 779                 resets = <&tegra_car 14>;
 780                 reset-names = "sdhci";
 781                 status = "disabled";
 782         };
 783
 784         sdhci@78000200 {
 785                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 786                 reg = <0x78000200 0x200>;
 787                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 788                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 789                 resets = <&tegra_car 9>;
 790                 reset-names = "sdhci";
 791                 status = "disabled";
 792         };
 793
 794         sdhci@78000400 {
 795                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 796                 reg = <0x78000400 0x200>;
 797                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 798                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 799                 resets = <&tegra_car 69>;
 800                 reset-names = "sdhci";
 801                 status = "disabled";
 802         };
 803
 804         sdhci@78000600 {
 805                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 806                 reg = <0x78000600 0x200>;
 807                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 809                 resets = <&tegra_car 15>;
 810                 reset-names = "sdhci";
 811                 status = "disabled";
 812         };
 813
 814         usb@7d000000 {
 815                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 816                 reg = <0x7d000000 0x4000>;
 817                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 818                 phy_type = "utmi";
 819                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 820                 resets = <&tegra_car 22>;
 821                 reset-names = "usb";
 822                 nvidia,needs-double-reset;
 823                 nvidia,phy = <&phy1>;
 824                 status = "disabled";
 825         };
 826
 827         phy1: usb-phy@7d000000 {
 828                 compatible = "nvidia,tegra30-usb-phy";
 829                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 830                 phy_type = "utmi";
 831                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 832                          <&tegra_car TEGRA30_CLK_PLL_U>,
 833                          <&tegra_car TEGRA30_CLK_USBD>;
 834                 clock-names = "reg", "pll_u", "utmi-pads";
 835                 resets = <&tegra_car 22>, <&tegra_car 22>;
 836                 reset-names = "usb", "utmi-pads";
 837                 nvidia,hssync-start-delay = <9>;
 838                 nvidia,idle-wait-delay = <17>;
 839                 nvidia,elastic-limit = <16>;
 840                 nvidia,term-range-adj = <6>;
 841                 nvidia,xcvr-setup = <51>;
 842                 nvidia.xcvr-setup-use-fuses;
 843                 nvidia,xcvr-lsfslew = <1>;
 844                 nvidia,xcvr-lsrslew = <1>;
 845                 nvidia,xcvr-hsslew = <32>;
 846                 nvidia,hssquelch-level = <2>;
 847                 nvidia,hsdiscon-level = <5>;
 848                 nvidia,has-utmi-pad-registers;
 849                 status = "disabled";
 850         };
 851
 852         usb@7d004000 {
 853                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 854                 reg = <0x7d004000 0x4000>;
 855                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 856                 phy_type = "utmi";
 857                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 858                 resets = <&tegra_car 58>;
 859                 reset-names = "usb";
 860                 nvidia,phy = <&phy2>;
 861                 status = "disabled";
 862         };
 863
 864         phy2: usb-phy@7d004000 {
 865                 compatible = "nvidia,tegra30-usb-phy";
 866                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 867                 phy_type = "utmi";
 868                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 869                          <&tegra_car TEGRA30_CLK_PLL_U>,
 870                          <&tegra_car TEGRA30_CLK_USBD>;
 871                 clock-names = "reg", "pll_u", "utmi-pads";
 872                 resets = <&tegra_car 58>, <&tegra_car 22>;
 873                 reset-names = "usb", "utmi-pads";
 874                 nvidia,hssync-start-delay = <9>;
 875                 nvidia,idle-wait-delay = <17>;
 876                 nvidia,elastic-limit = <16>;
 877                 nvidia,term-range-adj = <6>;
 878                 nvidia,xcvr-setup = <51>;
 879                 nvidia.xcvr-setup-use-fuses;
 880                 nvidia,xcvr-lsfslew = <2>;
 881                 nvidia,xcvr-lsrslew = <2>;
 882                 nvidia,xcvr-hsslew = <32>;
 883                 nvidia,hssquelch-level = <2>;
 884                 nvidia,hsdiscon-level = <5>;
 885                 status = "disabled";
 886         };
 887
 888         usb@7d008000 {
 889                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 890                 reg = <0x7d008000 0x4000>;
 891                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 892                 phy_type = "utmi";
 893                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 894                 resets = <&tegra_car 59>;
 895                 reset-names = "usb";
 896                 nvidia,phy = <&phy3>;
 897                 status = "disabled";
 898         };
 899
 900         phy3: usb-phy@7d008000 {
 901                 compatible = "nvidia,tegra30-usb-phy";
 902                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 903                 phy_type = "utmi";
 904                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 905                          <&tegra_car TEGRA30_CLK_PLL_U>,
 906                          <&tegra_car TEGRA30_CLK_USBD>;
 907                 clock-names = "reg", "pll_u", "utmi-pads";
 908                 resets = <&tegra_car 59>, <&tegra_car 22>;
 909                 reset-names = "usb", "utmi-pads";
 910                 nvidia,hssync-start-delay = <0>;
 911                 nvidia,idle-wait-delay = <17>;
 912                 nvidia,elastic-limit = <16>;
 913                 nvidia,term-range-adj = <6>;
 914                 nvidia,xcvr-setup = <51>;
 915                 nvidia.xcvr-setup-use-fuses;
 916                 nvidia,xcvr-lsfslew = <2>;
 917                 nvidia,xcvr-lsrslew = <2>;
 918                 nvidia,xcvr-hsslew = <32>;
 919                 nvidia,hssquelch-level = <2>;
 920                 nvidia,hsdiscon-level = <5>;
 921                 status = "disabled";
 922         };
 923
 924         cpus {
 925                 #address-cells = <1>;
 926                 #size-cells = <0>;
 927
 928                 cpu@0 {
 929                         device_type = "cpu";
 930                         compatible = "arm,cortex-a9";
 931                         reg = <0>;
 932                 };
 933
 934                 cpu@1 {
 935                         device_type = "cpu";
 936                         compatible = "arm,cortex-a9";
 937                         reg = <1>;
 938                 };
 939
 940                 cpu@2 {
 941                         device_type = "cpu";
 942                         compatible = "arm,cortex-a9";
 943                         reg = <2>;
 944                 };
 945
 946                 cpu@3 {
 947                         device_type = "cpu";
 948                         compatible = "arm,cortex-a9";
 949                         reg = <3>;
 950                 };
 951         };
 952
 953         pmu {
 954                 compatible = "arm,cortex-a9-pmu";
 955                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 956                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 957                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 958                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 959         };
 960 };