arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev B";
  50         compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 24 GPIO_ACTIVE_HIGH
  59                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  60                 mdio-parent-bus = <&mdio1>;
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 mdio_mux_1: mdio@1 {
  65                         reg = <1>;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68
  69                         switch0: switch@0 {
  70                                 compatible = "marvell,mv88e6085";
  71                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  72                                 pinctrl-names = "default";
  73                                 #address-cells = <1>;
  74                                 #size-cells = <0>;
  75                                 reg = <0>;
  76                                 dsa,member = <0 0>;
  77                                 interrupt-parent = <&gpio0>;
  78                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  79                                 interrupt-controller;
  80                                 #interrupt-cells = <2>;
  81                                 eeprom-length = <512>;
  82
  83                                 ports {
  84                                         #address-cells = <1>;
  85                                         #size-cells = <0>;
  86
  87                                         port@0 {
  88                                                 reg = <0>;
  89                                                 label = "lan0";
  90                                                 phy-handle = <&switch0phy0>;
  91                                         };
  92
  93                                         port@1 {
  94                                                 reg = <1>;
  95                                                 label = "lan1";
  96                                                 phy-handle = <&switch0phy1>;
  97                                         };
  98
  99                                         port@2 {
 100                                                 reg = <2>;
 101                                                 label = "lan2";
 102                                                 phy-handle = <&switch0phy2>;
 103                                         };
 104
 105                                         switch0port5: port@5 {
 106                                                 reg = <5>;
 107                                                 label = "dsa";
 108                                                 phy-mode = "rgmii-txid";
 109                                                 link = <&switch1port6
 110                                                         &switch2port9>;
 111                                                 fixed-link {
 112                                                         speed = <1000>;
 113                                                         full-duplex;
 114                                                 };
 115                                         };
 116
 117                                         port@6 {
 118                                                 reg = <6>;
 119                                                 label = "cpu";
 120                                                 ethernet = <&fec1>;
 121
 122                                                 fixed-link {
 123                                                         speed = <100>;
 124                                                         full-duplex;
 125                                                 };
 126                                         };
 127                                 };
 128                                 mdio {
 129                                         #address-cells = <1>;
 130                                         #size-cells = <0>;
 131                                         switch0phy0: switch0phy0@0 {
 132                                                 reg = <0>;
 133                                                 interrupt-parent = <&switch0>;
 134                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 135                                         };
 136                                         switch0phy1: switch1phy0@1 {
 137                                                 reg = <1>;
 138                                                 interrupt-parent = <&switch0>;
 139                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 140                                         };
 141                                         switch0phy2: switch1phy0@2 {
 142                                                 reg = <2>;
 143                                                 interrupt-parent = <&switch0>;
 144                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 145                                         };
 146                                 };
 147                         };
 148                 };
 149
 150                 mdio_mux_2: mdio@2 {
 151                         reg = <2>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154
 155                         switch1: switch@0 {
 156                                 compatible = "marvell,mv88e6085";
 157                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 158                                 pinctrl-names = "default";
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 reg = <0>;
 162                                 dsa,member = <0 1>;
 163                                 interrupt-parent = <&gpio0>;
 164                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 165                                 interrupt-controller;
 166                                 #interrupt-cells = <2>;
 167                                 eeprom-length = <512>;
 168
 169                                 ports {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172
 173                                         port@0 {
 174                                                 reg = <0>;
 175                                                 label = "lan3";
 176                                                 phy-handle = <&switch1phy0>;
 177                                         };
 178
 179                                         port@1 {
 180                                                 reg = <1>;
 181                                                 label = "lan4";
 182                                                 phy-handle = <&switch1phy1>;
 183                                         };
 184
 185                                         port@2 {
 186                                                 reg = <2>;
 187                                                 label = "lan5";
 188                                                 phy-handle = <&switch1phy2>;
 189                                         };
 190
 191                                         switch1port5: port@5 {
 192                                                 reg = <5>;
 193                                                 label = "dsa";
 194                                                 link = <&switch2port9>;
 195                                                 phy-mode = "rgmii-txid";
 196
 197                                                 fixed-link {
 198                                                         speed = <1000>;
 199                                                         full-duplex;
 200                                                 };
 201                                         };
 202
 203                                         switch1port6: port@6 {
 204                                                 reg = <6>;
 205                                                 label = "dsa";
 206                                                 phy-mode = "rgmii-txid";
 207                                                 link = <&switch0port5>;
 208                                                 fixed-link {
 209                                                         speed = <1000>;
 210                                                         full-duplex;
 211                                                 };
 212                                         };
 213                                 };
 214                                 mdio {
 215                                         #address-cells = <1>;
 216                                         #size-cells = <0>;
 217
 218                                         switch1phy0: switch1phy0@0 {
 219                                                 reg = <0>;
 220                                                 interrupt-parent = <&switch1>;
 221                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 222                                         };
 223
 224                                         switch1phy1: switch1phy0@1 {
 225                                                 reg = <1>;
 226                                                 interrupt-parent = <&switch1>;
 227                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 228                                         };
 229
 230                                         switch1phy2: switch1phy0@2 {
 231                                                 reg = <2>;
 232                                                 interrupt-parent = <&switch1>;
 233                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 234                                         };
 235                                 };
 236                         };
 237                 };
 238
 239                 mdio_mux_4: mdio@4 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         reg = <4>;
 243
 244                         switch2: switch@0 {
 245                                 compatible = "marvell,mv88e6085";
 246                                 #address-cells = <1>;
 247                                 #size-cells = <0>;
 248                                 reg = <0>;
 249                                 dsa,member = <0 2>;
 250
 251                                 ports {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254
 255                                         port@0 {
 256                                                 reg = <0>;
 257                                                 label = "lan6";
 258                                         };
 259
 260                                         port@1 {
 261                                                 reg = <1>;
 262                                                 label = "lan7";
 263                                         };
 264
 265                                         port@2 {
 266                                                 reg = <2>;
 267                                                 label = "lan8";
 268                                         };
 269
 270                                         port@3 {
 271                                                 reg = <3>;
 272                                                 label = "optical3";
 273
 274                                                 fixed-link {
 275                                                         speed = <1000>;
 276                                                         full-duplex;
 277                                                         link-gpios = <&gpio6 2
 278                                                               GPIO_ACTIVE_HIGH>;
 279                                                 };
 280                                         };
 281
 282                                         port@4 {
 283                                                 reg = <4>;
 284                                                 label = "optical4";
 285
 286                                                 fixed-link {
 287                                                         speed = <1000>;
 288                                                         full-duplex;
 289                                                         link-gpios = <&gpio6 3
 290                                                               GPIO_ACTIVE_HIGH>;
 291                                                 };
 292                                         };
 293
 294                                         switch2port9: port@9 {
 295                                                 reg = <9>;
 296                                                 label = "dsa";
 297                                                 phy-mode = "rgmii-txid";
 298                                                 link = <&switch1port5
 299                                                         &switch0port5>;
 300
 301                                                 fixed-link {
 302                                                         speed = <1000>;
 303                                                         full-duplex;
 304                                                 };
 305                                         };
 306                                 };
 307                         };
 308                 };
 309
 310                 mdio_mux_8: mdio@8 {
 311                         reg = <8>;
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                 };
 315         };
 316
 317         spi0 {
 318                 compatible = "spi-gpio";
 319                 pinctrl-0 = <&pinctrl_gpio_spi0>;
 320                 pinctrl-names = "default";
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 324                 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 325                 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 326                 cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
 327                              &gpio1  8 GPIO_ACTIVE_HIGH>;
 328                 num-chipselects = <2>;
 329
 330                 m25p128@0 {
 331                         compatible = "m25p128", "jedec,spi-nor";
 332                         #address-cells = <1>;
 333                         #size-cells = <1>;
 334                         reg = <0>;
 335                         spi-max-frequency = <1000000>;
 336                 };
 337
 338                 at93c46d@1 {
 339                         compatible = "atmel,at93c46d";
 340                         pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
 341                         pinctrl-names = "default";
 342                         #address-cells = <0>;
 343                         #size-cells = <0>;
 344                         reg = <1>;
 345                         spi-max-frequency = <500000>;
 346                         spi-cs-high;
 347                         data-size = <16>;
 348                         select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 349                 };
 350         };
 351 };
 352
 353 &i2c0 {
 354         clock-frequency = <100000>;
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_i2c0>;
 357         status = "okay";
 358
 359         gpio5: pca9554@20 {
 360                 compatible = "nxp,pca9554";
 361                 reg = <0x20>;
 362                 gpio-controller;
 363                 #gpio-cells = <2>;
 364
 365         };
 366
 367         gpio6: pca9554@22 {
 368                 compatible = "nxp,pca9554";
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&pinctrl_pca9554_22>;
 371                 reg = <0x22>;
 372                 gpio-controller;
 373                 #gpio-cells = <2>;
 374                 interrupt-parent = <&gpio2>;
 375                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 376         };
 377 };
 378
 379 &i2c2 {
 380         clock-frequency = <100000>;
 381         pinctrl-names = "default";
 382         pinctrl-0 = <&pinctrl_i2c2>;
 383         status = "okay";
 384
 385         tca9548@70 {
 386                 compatible = "nxp,pca9548";
 387                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 388                 pinctrl-names = "default";
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 reg = <0x70>;
 392                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 393
 394                 i2c@0 {
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         reg = <0>;
 398
 399                         sfp1: at24c04@50 {
 400                                 compatible = "atmel,24c02";
 401                                 reg = <0x50>;
 402                         };
 403                 };
 404
 405                 i2c@1 {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         reg = <1>;
 409
 410                         sfp2: at24c04@50 {
 411                                 compatible = "atmel,24c02";
 412                                 reg = <0x50>;
 413                         };
 414                 };
 415
 416                 i2c@2 {
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         reg = <2>;
 420
 421                         sfp3: at24c04@50 {
 422                                 compatible = "atmel,24c02";
 423                                 reg = <0x50>;
 424                         };
 425                 };
 426
 427                 i2c@3 {
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         reg = <3>;
 431
 432                         sfp4: at24c04@50 {
 433                                 compatible = "atmel,24c02";
 434                                 reg = <0x50>;
 435                         };
 436                 };
 437
 438                 i2c@4 {
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <4>;
 442                 };
 443         };
 444 };
 445
 446
 447 &iomuxc {
 448         pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
 449                 fsl,pins = <
 450                         VF610_PAD_PTE27__GPIO_132       0x33e2
 451                 >;
 452         };
 453
 454         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 455                 fsl,pins = <
 456                         VF610_PAD_PTB22__GPIO_44        0x33e2
 457                         VF610_PAD_PTB21__GPIO_43        0x33e2
 458                         VF610_PAD_PTB20__GPIO_42        0x33e1
 459                         VF610_PAD_PTB19__GPIO_41        0x33e2
 460                         VF610_PAD_PTB18__GPIO_40        0x33e2
 461                 >;
 462         };
 463
 464         pinctrl_mdio_mux: pinctrl-mdio-mux {
 465                 fsl,pins = <
 466                         VF610_PAD_PTA18__GPIO_8         0x31c2
 467                         VF610_PAD_PTA19__GPIO_9         0x31c2
 468                         VF610_PAD_PTB2__GPIO_24         0x31c2
 469                         VF610_PAD_PTB3__GPIO_25         0x31c2
 470                 >;
 471         };
 472
 473         pinctrl_pca9554_22: pinctrl-pca95540-22 {
 474                 fsl,pins = <
 475                         VF610_PAD_PTB28__GPIO_98        0x219d
 476                 >;
 477         };
 478 };