arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13
  14 #ifdef CONFIG_CPU_V7M
  15 #define CPUID_EXT_PFR0  0x40
  16 #define CPUID_EXT_PFR1  0x44
  17 #define CPUID_EXT_DFR0  0x48
  18 #define CPUID_EXT_AFR0  0x4c
  19 #define CPUID_EXT_MMFR0 0x50
  20 #define CPUID_EXT_MMFR1 0x54
  21 #define CPUID_EXT_MMFR2 0x58
  22 #define CPUID_EXT_MMFR3 0x5c
  23 #define CPUID_EXT_ISAR0 0x60
  24 #define CPUID_EXT_ISAR1 0x64
  25 #define CPUID_EXT_ISAR2 0x68
  26 #define CPUID_EXT_ISAR3 0x6c
  27 #define CPUID_EXT_ISAR4 0x70
  28 #define CPUID_EXT_ISAR5 0x74
  29 #else
  30 #define CPUID_EXT_PFR0  "c1, 0"
  31 #define CPUID_EXT_PFR1  "c1, 1"
  32 #define CPUID_EXT_DFR0  "c1, 2"
  33 #define CPUID_EXT_AFR0  "c1, 3"
  34 #define CPUID_EXT_MMFR0 "c1, 4"
  35 #define CPUID_EXT_MMFR1 "c1, 5"
  36 #define CPUID_EXT_MMFR2 "c1, 6"
  37 #define CPUID_EXT_MMFR3 "c1, 7"
  38 #define CPUID_EXT_ISAR0 "c2, 0"
  39 #define CPUID_EXT_ISAR1 "c2, 1"
  40 #define CPUID_EXT_ISAR2 "c2, 2"
  41 #define CPUID_EXT_ISAR3 "c2, 3"
  42 #define CPUID_EXT_ISAR4 "c2, 4"
  43 #define CPUID_EXT_ISAR5 "c2, 5"
  44 #endif
  45
  46 #define MPIDR_SMP_BITMASK (0x3 << 30)
  47 #define MPIDR_SMP_VALUE (0x2 << 30)
  48
  49 #define MPIDR_MT_BITMASK (0x1 << 24)
  50
  51 #define MPIDR_HWID_BITMASK 0xFFFFFF
  52
  53 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  54
  55 #define MPIDR_LEVEL_BITS 8
  56 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  57
  58 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  59         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  60
  61 #define ARM_CPU_IMP_ARM                 0x41
  62 #define ARM_CPU_IMP_INTEL               0x69
  63
  64 #define ARM_CPU_PART_ARM1136            0xB360
  65 #define ARM_CPU_PART_ARM1156            0xB560
  66 #define ARM_CPU_PART_ARM1176            0xB760
  67 #define ARM_CPU_PART_ARM11MPCORE        0xB020
  68 #define ARM_CPU_PART_CORTEX_A8          0xC080
  69 #define ARM_CPU_PART_CORTEX_A9          0xC090
  70 #define ARM_CPU_PART_CORTEX_A5          0xC050
  71 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
  72 #define ARM_CPU_PART_CORTEX_A7          0xC070
  73
  74 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  75 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  76 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  77 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  78
  79 extern unsigned int processor_id;
  80
  81 #ifdef CONFIG_CPU_CP15
  82 #define read_cpuid(reg)                                                 \
  83         ({                                                              \
  84                 unsigned int __val;                                     \
  85                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  86                     : "=r" (__val)                                      \
  87                     :                                                   \
  88                     : "cc");                                            \
  89                 __val;                                                  \
  90         })
  91
  92 /*
  93  * The memory clobber prevents gcc 4.5 from reordering the mrc before
  94  * any is_smp() tests, which can cause undefined instruction aborts on
  95  * ARM1136 r0 due to the missing extended CP15 registers.
  96  */
  97 #define read_cpuid_ext(ext_reg)                                         \
  98         ({                                                              \
  99                 unsigned int __val;                                     \
 100                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 101                     : "=r" (__val)                                      \
 102                     :                                                   \
 103                     : "memory");                                        \
 104                 __val;                                                  \
 105         })
 106
 107 #elif defined(CONFIG_CPU_V7M)
 108
 109 #include <asm/io.h>
 110 #include <asm/v7m.h>
 111
 112 #define read_cpuid(reg)                                                 \
 113         ({                                                              \
 114                 WARN_ON_ONCE(1);                                        \
 115                 0;                                                      \
 116         })
 117
 118 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 119 {
 120         return readl(BASEADDR_V7M_SCB + offset);
 121 }
 122
 123 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 124
 125 /*
 126  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 127  * have cp15 so warn on other usages.
 128  */
 129 #define read_cpuid(reg)                                                 \
 130         ({                                                              \
 131                 WARN_ON_ONCE(1);                                        \
 132                 0;                                                      \
 133         })
 134
 135 #define read_cpuid_ext(reg) read_cpuid(reg)
 136
 137 #endif /* ifdef CONFIG_CPU_CP15 / else */
 138
 139 #ifdef CONFIG_CPU_CP15
 140 /*
 141  * The CPU ID never changes at run time, so we might as well tell the
 142  * compiler that it's constant.  Use this function to read the CPU ID
 143  * rather than directly reading processor_id or read_cpuid() directly.
 144  */
 145 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 146 {
 147         return read_cpuid(CPUID_ID);
 148 }
 149
 150 #elif defined(CONFIG_CPU_V7M)
 151
 152 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 153 {
 154         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 155 }
 156
 157 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 158
 159 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 160 {
 161         return processor_id;
 162 }
 163
 164 #endif /* ifdef CONFIG_CPU_CP15 / else */
 165
 166 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 167 {
 168         return (read_cpuid_id() & 0xFF000000) >> 24;
 169 }
 170
 171 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 172 {
 173         return read_cpuid_id() & 0xFFF0;
 174 }
 175
 176 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 177 {
 178         return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 179 }
 180
 181 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 182 {
 183         return read_cpuid(CPUID_CACHETYPE);
 184 }
 185
 186 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 187 {
 188         return read_cpuid(CPUID_TCM);
 189 }
 190
 191 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 192 {
 193         return read_cpuid(CPUID_MPIDR);
 194 }
 195
 196 /*
 197  * Intel's XScale3 core supports some v6 features (supersections, L2)
 198  * but advertises itself as v5 as it does not support the v6 ISA.  For
 199  * this reason, we need a way to explicitly test for this type of CPU.
 200  */
 201 #ifndef CONFIG_CPU_XSC3
 202 #define cpu_is_xsc3()   0
 203 #else
 204 static inline int cpu_is_xsc3(void)
 205 {
 206         unsigned int id;
 207         id = read_cpuid_id() & 0xffffe000;
 208         /* It covers both Intel ID and Marvell ID */
 209         if ((id == 0x69056000) || (id == 0x56056000))
 210                 return 1;
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 217 #define cpu_is_xscale() 0
 218 #else
 219 #define cpu_is_xscale() 1
 220 #endif
 221
 222 #endif