arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/iommu-omap.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "soc.h"
  32 #include "omap_hwmod.h"
  33 #include "omap_hwmod_common_data.h"
  34 #include "prm-regbits-34xx.h"
  35 #include "cm-regbits-34xx.h"
  36
  37 #include "i2c.h"
  38 #include "wd_timer.h"
  39 #include "serial.h"
  40
  41 /*
  42  * OMAP3xxx hardware module integration data
  43  *
  44  * All of the data in this section should be autogeneratable from the
  45  * TI hardware database or other technical documentation.  Data that
  46  * is driver-specific or driver-kernel integration-specific belongs
  47  * elsewhere.
  48  */
  49
  50 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  51
  52 /*
  53  * IP blocks
  54  */
  55
  56 /* L3 */
  57 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  58         { .irq = 9 + OMAP_INTC_START, },
  59         { .irq = 10 + OMAP_INTC_START, },
  60         { .irq = -1 },
  61 };
  62
  63 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  64         .name           = "l3_main",
  65         .class          = &l3_hwmod_class,
  66         .mpu_irqs       = omap3xxx_l3_main_irqs,
  67         .flags          = HWMOD_NO_IDLEST,
  68 };
  69
  70 /* L4 CORE */
  71 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  72         .name           = "l4_core",
  73         .class          = &l4_hwmod_class,
  74         .flags          = HWMOD_NO_IDLEST,
  75 };
  76
  77 /* L4 PER */
  78 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  79         .name           = "l4_per",
  80         .class          = &l4_hwmod_class,
  81         .flags          = HWMOD_NO_IDLEST,
  82 };
  83
  84 /* L4 WKUP */
  85 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  86         .name           = "l4_wkup",
  87         .class          = &l4_hwmod_class,
  88         .flags          = HWMOD_NO_IDLEST,
  89 };
  90
  91 /* L4 SEC */
  92 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  93         .name           = "l4_sec",
  94         .class          = &l4_hwmod_class,
  95         .flags          = HWMOD_NO_IDLEST,
  96 };
  97
  98 /* MPU */
  99 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 100         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 101         { .irq = -1 }
 102 };
 103
 104 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 105         .name           = "mpu",
 106         .mpu_irqs       = omap3xxx_mpu_irqs,
 107         .class          = &mpu_hwmod_class,
 108         .main_clk       = "arm_fck",
 109 };
 110
 111 /* IVA2 (IVA2) */
 112 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 113         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 114         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 115         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 116 };
 117
 118 static struct omap_hwmod omap3xxx_iva_hwmod = {
 119         .name           = "iva",
 120         .class          = &iva_hwmod_class,
 121         .clkdm_name     = "iva2_clkdm",
 122         .rst_lines      = omap3xxx_iva_resets,
 123         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 124         .main_clk       = "iva2_ck",
 125         .prcm = {
 126                 .omap2 = {
 127                         .module_offs = OMAP3430_IVA2_MOD,
 128                         .prcm_reg_id = 1,
 129                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 130                         .idlest_reg_id = 1,
 131                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 132                 }
 133         },
 134 };
 135
 136 /*
 137  * 'debugss' class
 138  * debug and emulation sub system
 139  */
 140
 141 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 142         .name   = "debugss",
 143 };
 144
 145 /* debugss */
 146 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 147         .name           = "debugss",
 148         .class          = &omap3xxx_debugss_hwmod_class,
 149         .clkdm_name     = "emu_clkdm",
 150         .main_clk       = "emu_src_ck",
 151         .flags          = HWMOD_NO_IDLEST,
 152 };
 153
 154 /* timer class */
 155 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 156         .rev_offs       = 0x0000,
 157         .sysc_offs      = 0x0010,
 158         .syss_offs      = 0x0014,
 159         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 160                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 161                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 162                            SYSS_HAS_RESET_STATUS),
 163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 164         .clockact       = CLOCKACT_TEST_ICLK,
 165         .sysc_fields    = &omap_hwmod_sysc_type1,
 166 };
 167
 168 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 169         .name = "timer",
 170         .sysc = &omap3xxx_timer_sysc,
 171 };
 172
 173 /* secure timers dev attribute */
 174 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 175         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 176 };
 177
 178 /* always-on timers dev attribute */
 179 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 180         .timer_capability       = OMAP_TIMER_ALWON,
 181 };
 182
 183 /* pwm timers dev attribute */
 184 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 185         .timer_capability       = OMAP_TIMER_HAS_PWM,
 186 };
 187
 188 /* timers with DSP interrupt dev attribute */
 189 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 190         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 191 };
 192
 193 /* pwm timers with DSP interrupt dev attribute */
 194 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 195         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 196 };
 197
 198 /* timer1 */
 199 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 200         .name           = "timer1",
 201         .mpu_irqs       = omap2_timer1_mpu_irqs,
 202         .main_clk       = "gpt1_fck",
 203         .prcm           = {
 204                 .omap2 = {
 205                         .prcm_reg_id = 1,
 206                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 207                         .module_offs = WKUP_MOD,
 208                         .idlest_reg_id = 1,
 209                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 210                 },
 211         },
 212         .dev_attr       = &capability_alwon_dev_attr,
 213         .class          = &omap3xxx_timer_hwmod_class,
 214         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 215 };
 216
 217 /* timer2 */
 218 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 219         .name           = "timer2",
 220         .mpu_irqs       = omap2_timer2_mpu_irqs,
 221         .main_clk       = "gpt2_fck",
 222         .prcm           = {
 223                 .omap2 = {
 224                         .prcm_reg_id = 1,
 225                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 226                         .module_offs = OMAP3430_PER_MOD,
 227                         .idlest_reg_id = 1,
 228                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 229                 },
 230         },
 231         .class          = &omap3xxx_timer_hwmod_class,
 232         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 233 };
 234
 235 /* timer3 */
 236 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 237         .name           = "timer3",
 238         .mpu_irqs       = omap2_timer3_mpu_irqs,
 239         .main_clk       = "gpt3_fck",
 240         .prcm           = {
 241                 .omap2 = {
 242                         .prcm_reg_id = 1,
 243                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 244                         .module_offs = OMAP3430_PER_MOD,
 245                         .idlest_reg_id = 1,
 246                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 247                 },
 248         },
 249         .class          = &omap3xxx_timer_hwmod_class,
 250         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 251 };
 252
 253 /* timer4 */
 254 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 255         .name           = "timer4",
 256         .mpu_irqs       = omap2_timer4_mpu_irqs,
 257         .main_clk       = "gpt4_fck",
 258         .prcm           = {
 259                 .omap2 = {
 260                         .prcm_reg_id = 1,
 261                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 262                         .module_offs = OMAP3430_PER_MOD,
 263                         .idlest_reg_id = 1,
 264                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 265                 },
 266         },
 267         .class          = &omap3xxx_timer_hwmod_class,
 268         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 269 };
 270
 271 /* timer5 */
 272 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 273         .name           = "timer5",
 274         .mpu_irqs       = omap2_timer5_mpu_irqs,
 275         .main_clk       = "gpt5_fck",
 276         .prcm           = {
 277                 .omap2 = {
 278                         .prcm_reg_id = 1,
 279                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 280                         .module_offs = OMAP3430_PER_MOD,
 281                         .idlest_reg_id = 1,
 282                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 283                 },
 284         },
 285         .dev_attr       = &capability_dsp_dev_attr,
 286         .class          = &omap3xxx_timer_hwmod_class,
 287         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 288 };
 289
 290 /* timer6 */
 291 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 292         .name           = "timer6",
 293         .mpu_irqs       = omap2_timer6_mpu_irqs,
 294         .main_clk       = "gpt6_fck",
 295         .prcm           = {
 296                 .omap2 = {
 297                         .prcm_reg_id = 1,
 298                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 299                         .module_offs = OMAP3430_PER_MOD,
 300                         .idlest_reg_id = 1,
 301                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 302                 },
 303         },
 304         .dev_attr       = &capability_dsp_dev_attr,
 305         .class          = &omap3xxx_timer_hwmod_class,
 306         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 307 };
 308
 309 /* timer7 */
 310 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 311         .name           = "timer7",
 312         .mpu_irqs       = omap2_timer7_mpu_irqs,
 313         .main_clk       = "gpt7_fck",
 314         .prcm           = {
 315                 .omap2 = {
 316                         .prcm_reg_id = 1,
 317                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 318                         .module_offs = OMAP3430_PER_MOD,
 319                         .idlest_reg_id = 1,
 320                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 321                 },
 322         },
 323         .dev_attr       = &capability_dsp_dev_attr,
 324         .class          = &omap3xxx_timer_hwmod_class,
 325         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 326 };
 327
 328 /* timer8 */
 329 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 330         .name           = "timer8",
 331         .mpu_irqs       = omap2_timer8_mpu_irqs,
 332         .main_clk       = "gpt8_fck",
 333         .prcm           = {
 334                 .omap2 = {
 335                         .prcm_reg_id = 1,
 336                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 337                         .module_offs = OMAP3430_PER_MOD,
 338                         .idlest_reg_id = 1,
 339                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 340                 },
 341         },
 342         .dev_attr       = &capability_dsp_pwm_dev_attr,
 343         .class          = &omap3xxx_timer_hwmod_class,
 344         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 345 };
 346
 347 /* timer9 */
 348 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 349         .name           = "timer9",
 350         .mpu_irqs       = omap2_timer9_mpu_irqs,
 351         .main_clk       = "gpt9_fck",
 352         .prcm           = {
 353                 .omap2 = {
 354                         .prcm_reg_id = 1,
 355                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 356                         .module_offs = OMAP3430_PER_MOD,
 357                         .idlest_reg_id = 1,
 358                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 359                 },
 360         },
 361         .dev_attr       = &capability_pwm_dev_attr,
 362         .class          = &omap3xxx_timer_hwmod_class,
 363         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 364 };
 365
 366 /* timer10 */
 367 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 368         .name           = "timer10",
 369         .mpu_irqs       = omap2_timer10_mpu_irqs,
 370         .main_clk       = "gpt10_fck",
 371         .prcm           = {
 372                 .omap2 = {
 373                         .prcm_reg_id = 1,
 374                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 375                         .module_offs = CORE_MOD,
 376                         .idlest_reg_id = 1,
 377                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 378                 },
 379         },
 380         .dev_attr       = &capability_pwm_dev_attr,
 381         .class          = &omap3xxx_timer_hwmod_class,
 382         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 383 };
 384
 385 /* timer11 */
 386 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 387         .name           = "timer11",
 388         .mpu_irqs       = omap2_timer11_mpu_irqs,
 389         .main_clk       = "gpt11_fck",
 390         .prcm           = {
 391                 .omap2 = {
 392                         .prcm_reg_id = 1,
 393                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 394                         .module_offs = CORE_MOD,
 395                         .idlest_reg_id = 1,
 396                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 397                 },
 398         },
 399         .dev_attr       = &capability_pwm_dev_attr,
 400         .class          = &omap3xxx_timer_hwmod_class,
 401         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 402 };
 403
 404 /* timer12 */
 405 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 406         { .irq = 95 + OMAP_INTC_START, },
 407         { .irq = -1 },
 408 };
 409
 410 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 411         .name           = "timer12",
 412         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 413         .main_clk       = "gpt12_fck",
 414         .prcm           = {
 415                 .omap2 = {
 416                         .prcm_reg_id = 1,
 417                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 418                         .module_offs = WKUP_MOD,
 419                         .idlest_reg_id = 1,
 420                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 421                 },
 422         },
 423         .dev_attr       = &capability_secure_dev_attr,
 424         .class          = &omap3xxx_timer_hwmod_class,
 425         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 426 };
 427
 428 /*
 429  * 'wd_timer' class
 430  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 431  * overflow condition
 432  */
 433
 434 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 435         .rev_offs       = 0x0000,
 436         .sysc_offs      = 0x0010,
 437         .syss_offs      = 0x0014,
 438         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 439                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 440                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 441                            SYSS_HAS_RESET_STATUS),
 442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 443         .sysc_fields    = &omap_hwmod_sysc_type1,
 444 };
 445
 446 /* I2C common */
 447 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 448         .rev_offs       = 0x00,
 449         .sysc_offs      = 0x20,
 450         .syss_offs      = 0x10,
 451         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 452                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 453                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 454         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 455         .clockact       = CLOCKACT_TEST_ICLK,
 456         .sysc_fields    = &omap_hwmod_sysc_type1,
 457 };
 458
 459 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 460         .name           = "wd_timer",
 461         .sysc           = &omap3xxx_wd_timer_sysc,
 462         .pre_shutdown   = &omap2_wd_timer_disable,
 463         .reset          = &omap2_wd_timer_reset,
 464 };
 465
 466 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 467         .name           = "wd_timer2",
 468         .class          = &omap3xxx_wd_timer_hwmod_class,
 469         .main_clk       = "wdt2_fck",
 470         .prcm           = {
 471                 .omap2 = {
 472                         .prcm_reg_id = 1,
 473                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 474                         .module_offs = WKUP_MOD,
 475                         .idlest_reg_id = 1,
 476                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 477                 },
 478         },
 479         /*
 480          * XXX: Use software supervised mode, HW supervised smartidle seems to
 481          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 482          */
 483         .flags          = HWMOD_SWSUP_SIDLE,
 484 };
 485
 486 /* UART1 */
 487 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 488         .name           = "uart1",
 489         .mpu_irqs       = omap2_uart1_mpu_irqs,
 490         .sdma_reqs      = omap2_uart1_sdma_reqs,
 491         .main_clk       = "uart1_fck",
 492         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 493         .prcm           = {
 494                 .omap2 = {
 495                         .module_offs = CORE_MOD,
 496                         .prcm_reg_id = 1,
 497                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 498                         .idlest_reg_id = 1,
 499                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 500                 },
 501         },
 502         .class          = &omap2_uart_class,
 503 };
 504
 505 /* UART2 */
 506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 507         .name           = "uart2",
 508         .mpu_irqs       = omap2_uart2_mpu_irqs,
 509         .sdma_reqs      = omap2_uart2_sdma_reqs,
 510         .main_clk       = "uart2_fck",
 511         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 512         .prcm           = {
 513                 .omap2 = {
 514                         .module_offs = CORE_MOD,
 515                         .prcm_reg_id = 1,
 516                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 517                         .idlest_reg_id = 1,
 518                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 519                 },
 520         },
 521         .class          = &omap2_uart_class,
 522 };
 523
 524 /* UART3 */
 525 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 526         .name           = "uart3",
 527         .mpu_irqs       = omap2_uart3_mpu_irqs,
 528         .sdma_reqs      = omap2_uart3_sdma_reqs,
 529         .main_clk       = "uart3_fck",
 530         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 531                                 HWMOD_SWSUP_SIDLE,
 532         .prcm           = {
 533                 .omap2 = {
 534                         .module_offs = OMAP3430_PER_MOD,
 535                         .prcm_reg_id = 1,
 536                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 537                         .idlest_reg_id = 1,
 538                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 539                 },
 540         },
 541         .class          = &omap2_uart_class,
 542 };
 543
 544 /* UART4 */
 545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 546         { .irq = 80 + OMAP_INTC_START, },
 547         { .irq = -1 },
 548 };
 549
 550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 551         { .name = "rx", .dma_req = 82, },
 552         { .name = "tx", .dma_req = 81, },
 553         { .dma_req = -1 }
 554 };
 555
 556 static struct omap_hwmod omap36xx_uart4_hwmod = {
 557         .name           = "uart4",
 558         .mpu_irqs       = uart4_mpu_irqs,
 559         .sdma_reqs      = uart4_sdma_reqs,
 560         .main_clk       = "uart4_fck",
 561         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 562         .prcm           = {
 563                 .omap2 = {
 564                         .module_offs = OMAP3430_PER_MOD,
 565                         .prcm_reg_id = 1,
 566                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 567                         .idlest_reg_id = 1,
 568                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 569                 },
 570         },
 571         .class          = &omap2_uart_class,
 572 };
 573
 574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 575         { .irq = 84 + OMAP_INTC_START, },
 576         { .irq = -1 },
 577 };
 578
 579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 580         { .name = "rx", .dma_req = 55, },
 581         { .name = "tx", .dma_req = 54, },
 582         { .dma_req = -1 }
 583 };
 584
 585 /*
 586  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 587  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 588  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 589  * should not be needed.  The functional clock structure of the AM35xx
 590  * UART4 is extremely unclear and opaque; it is unclear what the role
 591  * of uart1/2_fck is for the UART4.  Any clarification from either
 592  * empirical testing or the AM3505/3517 hardware designers would be
 593  * most welcome.
 594  */
 595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 596         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 597 };
 598
 599 static struct omap_hwmod am35xx_uart4_hwmod = {
 600         .name           = "uart4",
 601         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 602         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 603         .main_clk       = "uart4_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .module_offs = CORE_MOD,
 607                         .prcm_reg_id = 1,
 608                         .module_bit = AM35XX_EN_UART4_SHIFT,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 611                 },
 612         },
 613         .opt_clks       = am35xx_uart4_opt_clks,
 614         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 615         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 616         .class          = &omap2_uart_class,
 617 };
 618
 619 static struct omap_hwmod_class i2c_class = {
 620         .name   = "i2c",
 621         .sysc   = &i2c_sysc,
 622         .rev    = OMAP_I2C_IP_VERSION_1,
 623         .reset  = &omap_i2c_reset,
 624 };
 625
 626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 627         { .name = "dispc", .dma_req = 5 },
 628         { .name = "dsi1", .dma_req = 74 },
 629         { .dma_req = -1 }
 630 };
 631
 632 /* dss */
 633 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 634         /*
 635          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 636          * driver does not use these clocks.
 637          */
 638         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 639         { .role = "tv_clk", .clk = "dss_tv_fck" },
 640         /* required only on OMAP3430 */
 641         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 642 };
 643
 644 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 645         .name           = "dss_core",
 646         .class          = &omap2_dss_hwmod_class,
 647         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 648         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 649         .prcm           = {
 650                 .omap2 = {
 651                         .prcm_reg_id = 1,
 652                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 653                         .module_offs = OMAP3430_DSS_MOD,
 654                         .idlest_reg_id = 1,
 655                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 656                 },
 657         },
 658         .opt_clks       = dss_opt_clks,
 659         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 660         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 661 };
 662
 663 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 664         .name           = "dss_core",
 665         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 666         .class          = &omap2_dss_hwmod_class,
 667         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 668         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 669         .prcm           = {
 670                 .omap2 = {
 671                         .prcm_reg_id = 1,
 672                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 673                         .module_offs = OMAP3430_DSS_MOD,
 674                         .idlest_reg_id = 1,
 675                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 676                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 677                 },
 678         },
 679         .opt_clks       = dss_opt_clks,
 680         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 681 };
 682
 683 /*
 684  * 'dispc' class
 685  * display controller
 686  */
 687
 688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 689         .rev_offs       = 0x0000,
 690         .sysc_offs      = 0x0010,
 691         .syss_offs      = 0x0014,
 692         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 693                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 694                            SYSC_HAS_ENAWAKEUP),
 695         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 696                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 697         .sysc_fields    = &omap_hwmod_sysc_type1,
 698 };
 699
 700 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 701         .name   = "dispc",
 702         .sysc   = &omap3_dispc_sysc,
 703 };
 704
 705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 706         .name           = "dss_dispc",
 707         .class          = &omap3_dispc_hwmod_class,
 708         .mpu_irqs       = omap2_dispc_irqs,
 709         .main_clk       = "dss1_alwon_fck",
 710         .prcm           = {
 711                 .omap2 = {
 712                         .prcm_reg_id = 1,
 713                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 714                         .module_offs = OMAP3430_DSS_MOD,
 715                 },
 716         },
 717         .flags          = HWMOD_NO_IDLEST,
 718         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 719 };
 720
 721 /*
 722  * 'dsi' class
 723  * display serial interface controller
 724  */
 725
 726 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 727         .name = "dsi",
 728 };
 729
 730 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 731         { .irq = 25 + OMAP_INTC_START, },
 732         { .irq = -1 },
 733 };
 734
 735 /* dss_dsi1 */
 736 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 737         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 738 };
 739
 740 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 741         .name           = "dss_dsi1",
 742         .class          = &omap3xxx_dsi_hwmod_class,
 743         .mpu_irqs       = omap3xxx_dsi1_irqs,
 744         .main_clk       = "dss1_alwon_fck",
 745         .prcm           = {
 746                 .omap2 = {
 747                         .prcm_reg_id = 1,
 748                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 749                         .module_offs = OMAP3430_DSS_MOD,
 750                 },
 751         },
 752         .opt_clks       = dss_dsi1_opt_clks,
 753         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 754         .flags          = HWMOD_NO_IDLEST,
 755 };
 756
 757 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 758         { .role = "ick", .clk = "dss_ick" },
 759 };
 760
 761 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 762         .name           = "dss_rfbi",
 763         .class          = &omap2_rfbi_hwmod_class,
 764         .main_clk       = "dss1_alwon_fck",
 765         .prcm           = {
 766                 .omap2 = {
 767                         .prcm_reg_id = 1,
 768                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 769                         .module_offs = OMAP3430_DSS_MOD,
 770                 },
 771         },
 772         .opt_clks       = dss_rfbi_opt_clks,
 773         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 774         .flags          = HWMOD_NO_IDLEST,
 775 };
 776
 777 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 778         /* required only on OMAP3430 */
 779         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 780 };
 781
 782 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 783         .name           = "dss_venc",
 784         .class          = &omap2_venc_hwmod_class,
 785         .main_clk       = "dss_tv_fck",
 786         .prcm           = {
 787                 .omap2 = {
 788                         .prcm_reg_id = 1,
 789                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 790                         .module_offs = OMAP3430_DSS_MOD,
 791                 },
 792         },
 793         .opt_clks       = dss_venc_opt_clks,
 794         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 795         .flags          = HWMOD_NO_IDLEST,
 796 };
 797
 798 /* I2C1 */
 799 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 800         .fifo_depth     = 8, /* bytes */
 801         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 802 };
 803
 804 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 805         .name           = "i2c1",
 806         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 807         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 808         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 809         .main_clk       = "i2c1_fck",
 810         .prcm           = {
 811                 .omap2 = {
 812                         .module_offs = CORE_MOD,
 813                         .prcm_reg_id = 1,
 814                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 815                         .idlest_reg_id = 1,
 816                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 817                 },
 818         },
 819         .class          = &i2c_class,
 820         .dev_attr       = &i2c1_dev_attr,
 821 };
 822
 823 /* I2C2 */
 824 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 825         .fifo_depth     = 8, /* bytes */
 826         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 827 };
 828
 829 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 830         .name           = "i2c2",
 831         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 832         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 833         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 834         .main_clk       = "i2c2_fck",
 835         .prcm           = {
 836                 .omap2 = {
 837                         .module_offs = CORE_MOD,
 838                         .prcm_reg_id = 1,
 839                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 840                         .idlest_reg_id = 1,
 841                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 842                 },
 843         },
 844         .class          = &i2c_class,
 845         .dev_attr       = &i2c2_dev_attr,
 846 };
 847
 848 /* I2C3 */
 849 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 850         .fifo_depth     = 64, /* bytes */
 851         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 852 };
 853
 854 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 855         { .irq = 61 + OMAP_INTC_START, },
 856         { .irq = -1 },
 857 };
 858
 859 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 860         { .name = "tx", .dma_req = 25 },
 861         { .name = "rx", .dma_req = 26 },
 862         { .dma_req = -1 }
 863 };
 864
 865 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 866         .name           = "i2c3",
 867         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 868         .mpu_irqs       = i2c3_mpu_irqs,
 869         .sdma_reqs      = i2c3_sdma_reqs,
 870         .main_clk       = "i2c3_fck",
 871         .prcm           = {
 872                 .omap2 = {
 873                         .module_offs = CORE_MOD,
 874                         .prcm_reg_id = 1,
 875                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 876                         .idlest_reg_id = 1,
 877                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 878                 },
 879         },
 880         .class          = &i2c_class,
 881         .dev_attr       = &i2c3_dev_attr,
 882 };
 883
 884 /*
 885  * 'gpio' class
 886  * general purpose io module
 887  */
 888
 889 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 890         .rev_offs       = 0x0000,
 891         .sysc_offs      = 0x0010,
 892         .syss_offs      = 0x0014,
 893         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 894                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 895                            SYSS_HAS_RESET_STATUS),
 896         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 897         .sysc_fields    = &omap_hwmod_sysc_type1,
 898 };
 899
 900 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 901         .name = "gpio",
 902         .sysc = &omap3xxx_gpio_sysc,
 903         .rev = 1,
 904 };
 905
 906 /* gpio_dev_attr */
 907 static struct omap_gpio_dev_attr gpio_dev_attr = {
 908         .bank_width = 32,
 909         .dbck_flag = true,
 910 };
 911
 912 /* gpio1 */
 913 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 914         { .role = "dbclk", .clk = "gpio1_dbck", },
 915 };
 916
 917 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 918         .name           = "gpio1",
 919         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 920         .mpu_irqs       = omap2_gpio1_irqs,
 921         .main_clk       = "gpio1_ick",
 922         .opt_clks       = gpio1_opt_clks,
 923         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 924         .prcm           = {
 925                 .omap2 = {
 926                         .prcm_reg_id = 1,
 927                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 928                         .module_offs = WKUP_MOD,
 929                         .idlest_reg_id = 1,
 930                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 931                 },
 932         },
 933         .class          = &omap3xxx_gpio_hwmod_class,
 934         .dev_attr       = &gpio_dev_attr,
 935 };
 936
 937 /* gpio2 */
 938 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 939         { .role = "dbclk", .clk = "gpio2_dbck", },
 940 };
 941
 942 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 943         .name           = "gpio2",
 944         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 945         .mpu_irqs       = omap2_gpio2_irqs,
 946         .main_clk       = "gpio2_ick",
 947         .opt_clks       = gpio2_opt_clks,
 948         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 949         .prcm           = {
 950                 .omap2 = {
 951                         .prcm_reg_id = 1,
 952                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 953                         .module_offs = OMAP3430_PER_MOD,
 954                         .idlest_reg_id = 1,
 955                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 956                 },
 957         },
 958         .class          = &omap3xxx_gpio_hwmod_class,
 959         .dev_attr       = &gpio_dev_attr,
 960 };
 961
 962 /* gpio3 */
 963 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 964         { .role = "dbclk", .clk = "gpio3_dbck", },
 965 };
 966
 967 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 968         .name           = "gpio3",
 969         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 970         .mpu_irqs       = omap2_gpio3_irqs,
 971         .main_clk       = "gpio3_ick",
 972         .opt_clks       = gpio3_opt_clks,
 973         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 974         .prcm           = {
 975                 .omap2 = {
 976                         .prcm_reg_id = 1,
 977                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 978                         .module_offs = OMAP3430_PER_MOD,
 979                         .idlest_reg_id = 1,
 980                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 981                 },
 982         },
 983         .class          = &omap3xxx_gpio_hwmod_class,
 984         .dev_attr       = &gpio_dev_attr,
 985 };
 986
 987 /* gpio4 */
 988 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 989         { .role = "dbclk", .clk = "gpio4_dbck", },
 990 };
 991
 992 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 993         .name           = "gpio4",
 994         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 995         .mpu_irqs       = omap2_gpio4_irqs,
 996         .main_clk       = "gpio4_ick",
 997         .opt_clks       = gpio4_opt_clks,
 998         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 999         .prcm           = {
1000                 .omap2 = {
1001                         .prcm_reg_id = 1,
1002                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1003                         .module_offs = OMAP3430_PER_MOD,
1004                         .idlest_reg_id = 1,
1005                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1006                 },
1007         },
1008         .class          = &omap3xxx_gpio_hwmod_class,
1009         .dev_attr       = &gpio_dev_attr,
1010 };
1011
1012 /* gpio5 */
1013 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1014         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1015         { .irq = -1 },
1016 };
1017
1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1019         { .role = "dbclk", .clk = "gpio5_dbck", },
1020 };
1021
1022 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1023         .name           = "gpio5",
1024         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1025         .mpu_irqs       = omap3xxx_gpio5_irqs,
1026         .main_clk       = "gpio5_ick",
1027         .opt_clks       = gpio5_opt_clks,
1028         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1029         .prcm           = {
1030                 .omap2 = {
1031                         .prcm_reg_id = 1,
1032                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1033                         .module_offs = OMAP3430_PER_MOD,
1034                         .idlest_reg_id = 1,
1035                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1036                 },
1037         },
1038         .class          = &omap3xxx_gpio_hwmod_class,
1039         .dev_attr       = &gpio_dev_attr,
1040 };
1041
1042 /* gpio6 */
1043 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1044         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1045         { .irq = -1 },
1046 };
1047
1048 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1049         { .role = "dbclk", .clk = "gpio6_dbck", },
1050 };
1051
1052 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1053         .name           = "gpio6",
1054         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1055         .mpu_irqs       = omap3xxx_gpio6_irqs,
1056         .main_clk       = "gpio6_ick",
1057         .opt_clks       = gpio6_opt_clks,
1058         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1059         .prcm           = {
1060                 .omap2 = {
1061                         .prcm_reg_id = 1,
1062                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1063                         .module_offs = OMAP3430_PER_MOD,
1064                         .idlest_reg_id = 1,
1065                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1066                 },
1067         },
1068         .class          = &omap3xxx_gpio_hwmod_class,
1069         .dev_attr       = &gpio_dev_attr,
1070 };
1071
1072 /* dma attributes */
1073 static struct omap_dma_dev_attr dma_dev_attr = {
1074         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1075                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1076         .lch_count = 32,
1077 };
1078
1079 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1080         .rev_offs       = 0x0000,
1081         .sysc_offs      = 0x002c,
1082         .syss_offs      = 0x0028,
1083         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1084                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1085                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1086                            SYSS_HAS_RESET_STATUS),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type1,
1090 };
1091
1092 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1093         .name = "dma",
1094         .sysc = &omap3xxx_dma_sysc,
1095 };
1096
1097 /* dma_system */
1098 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1099         .name           = "dma",
1100         .class          = &omap3xxx_dma_hwmod_class,
1101         .mpu_irqs       = omap2_dma_system_irqs,
1102         .main_clk       = "core_l3_ick",
1103         .prcm = {
1104                 .omap2 = {
1105                         .module_offs            = CORE_MOD,
1106                         .prcm_reg_id            = 1,
1107                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1108                         .idlest_reg_id          = 1,
1109                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1110                 },
1111         },
1112         .dev_attr       = &dma_dev_attr,
1113         .flags          = HWMOD_NO_IDLEST,
1114 };
1115
1116 /*
1117  * 'mcbsp' class
1118  * multi channel buffered serial port controller
1119  */
1120
1121 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1122         .sysc_offs      = 0x008c,
1123         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1124                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126         .sysc_fields    = &omap_hwmod_sysc_type1,
1127         .clockact       = 0x2,
1128 };
1129
1130 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1131         .name = "mcbsp",
1132         .sysc = &omap3xxx_mcbsp_sysc,
1133         .rev  = MCBSP_CONFIG_TYPE3,
1134 };
1135
1136 /* McBSP functional clock mapping */
1137 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1138         { .role = "pad_fck", .clk = "mcbsp_clks" },
1139         { .role = "prcm_fck", .clk = "core_96m_fck" },
1140 };
1141
1142 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1143         { .role = "pad_fck", .clk = "mcbsp_clks" },
1144         { .role = "prcm_fck", .clk = "per_96m_fck" },
1145 };
1146
1147 /* mcbsp1 */
1148 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1149         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1150         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1151         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1152         { .irq = -1 },
1153 };
1154
1155 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1156         .name           = "mcbsp1",
1157         .class          = &omap3xxx_mcbsp_hwmod_class,
1158         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1159         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1160         .main_clk       = "mcbsp1_fck",
1161         .prcm           = {
1162                 .omap2 = {
1163                         .prcm_reg_id = 1,
1164                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1165                         .module_offs = CORE_MOD,
1166                         .idlest_reg_id = 1,
1167                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1168                 },
1169         },
1170         .opt_clks       = mcbsp15_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1172 };
1173
1174 /* mcbsp2 */
1175 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1176         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1177         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1178         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1179         { .irq = -1 },
1180 };
1181
1182 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1183         .sidetone       = "mcbsp2_sidetone",
1184 };
1185
1186 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1187         .name           = "mcbsp2",
1188         .class          = &omap3xxx_mcbsp_hwmod_class,
1189         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1190         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1191         .main_clk       = "mcbsp2_fck",
1192         .prcm           = {
1193                 .omap2 = {
1194                         .prcm_reg_id = 1,
1195                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1196                         .module_offs = OMAP3430_PER_MOD,
1197                         .idlest_reg_id = 1,
1198                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1199                 },
1200         },
1201         .opt_clks       = mcbsp234_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1203         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1204 };
1205
1206 /* mcbsp3 */
1207 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1208         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1209         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1210         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1211         { .irq = -1 },
1212 };
1213
1214 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1215         .sidetone       = "mcbsp3_sidetone",
1216 };
1217
1218 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1219         .name           = "mcbsp3",
1220         .class          = &omap3xxx_mcbsp_hwmod_class,
1221         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1222         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1223         .main_clk       = "mcbsp3_fck",
1224         .prcm           = {
1225                 .omap2 = {
1226                         .prcm_reg_id = 1,
1227                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1228                         .module_offs = OMAP3430_PER_MOD,
1229                         .idlest_reg_id = 1,
1230                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1231                 },
1232         },
1233         .opt_clks       = mcbsp234_opt_clks,
1234         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1235         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1236 };
1237
1238 /* mcbsp4 */
1239 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1240         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1241         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1242         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1243         { .irq = -1 },
1244 };
1245
1246 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1247         { .name = "rx", .dma_req = 20 },
1248         { .name = "tx", .dma_req = 19 },
1249         { .dma_req = -1 }
1250 };
1251
1252 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1253         .name           = "mcbsp4",
1254         .class          = &omap3xxx_mcbsp_hwmod_class,
1255         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1256         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1257         .main_clk       = "mcbsp4_fck",
1258         .prcm           = {
1259                 .omap2 = {
1260                         .prcm_reg_id = 1,
1261                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1262                         .module_offs = OMAP3430_PER_MOD,
1263                         .idlest_reg_id = 1,
1264                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1265                 },
1266         },
1267         .opt_clks       = mcbsp234_opt_clks,
1268         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1269 };
1270
1271 /* mcbsp5 */
1272 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1273         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1274         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1275         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1276         { .irq = -1 },
1277 };
1278
1279 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1280         { .name = "rx", .dma_req = 22 },
1281         { .name = "tx", .dma_req = 21 },
1282         { .dma_req = -1 }
1283 };
1284
1285 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1286         .name           = "mcbsp5",
1287         .class          = &omap3xxx_mcbsp_hwmod_class,
1288         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1289         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1290         .main_clk       = "mcbsp5_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .prcm_reg_id = 1,
1294                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1295                         .module_offs = CORE_MOD,
1296                         .idlest_reg_id = 1,
1297                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1298                 },
1299         },
1300         .opt_clks       = mcbsp15_opt_clks,
1301         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1302 };
1303
1304 /* 'mcbsp sidetone' class */
1305 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1306         .sysc_offs      = 0x0010,
1307         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1308         .sysc_fields    = &omap_hwmod_sysc_type1,
1309 };
1310
1311 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1312         .name = "mcbsp_sidetone",
1313         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1314 };
1315
1316 /* mcbsp2_sidetone */
1317 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1318         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1319         { .irq = -1 },
1320 };
1321
1322 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1323         .name           = "mcbsp2_sidetone",
1324         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1325         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1326         .main_clk       = "mcbsp2_fck",
1327         .prcm           = {
1328                 .omap2 = {
1329                         .prcm_reg_id = 1,
1330                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1331                         .module_offs = OMAP3430_PER_MOD,
1332                         .idlest_reg_id = 1,
1333                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1334                 },
1335         },
1336 };
1337
1338 /* mcbsp3_sidetone */
1339 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1340         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1341         { .irq = -1 },
1342 };
1343
1344 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1345         .name           = "mcbsp3_sidetone",
1346         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1347         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1348         .main_clk       = "mcbsp3_fck",
1349         .prcm           = {
1350                 .omap2 = {
1351                         .prcm_reg_id = 1,
1352                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1353                         .module_offs = OMAP3430_PER_MOD,
1354                         .idlest_reg_id = 1,
1355                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1356                 },
1357         },
1358 };
1359
1360 /* SR common */
1361 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1362         .clkact_shift   = 20,
1363 };
1364
1365 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1366         .sysc_offs      = 0x24,
1367         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1368         .clockact       = CLOCKACT_TEST_ICLK,
1369         .sysc_fields    = &omap34xx_sr_sysc_fields,
1370 };
1371
1372 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1373         .name = "smartreflex",
1374         .sysc = &omap34xx_sr_sysc,
1375         .rev  = 1,
1376 };
1377
1378 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1379         .sidle_shift    = 24,
1380         .enwkup_shift   = 26,
1381 };
1382
1383 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1384         .sysc_offs      = 0x38,
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1387                         SYSC_NO_CACHE),
1388         .sysc_fields    = &omap36xx_sr_sysc_fields,
1389 };
1390
1391 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1392         .name = "smartreflex",
1393         .sysc = &omap36xx_sr_sysc,
1394         .rev  = 2,
1395 };
1396
1397 /* SR1 */
1398 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1399         .sensor_voltdm_name   = "mpu_iva",
1400 };
1401
1402 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1403         { .irq = 18 + OMAP_INTC_START, },
1404         { .irq = -1 },
1405 };
1406
1407 static struct omap_hwmod omap34xx_sr1_hwmod = {
1408         .name           = "smartreflex_mpu_iva",
1409         .class          = &omap34xx_smartreflex_hwmod_class,
1410         .main_clk       = "sr1_fck",
1411         .prcm           = {
1412                 .omap2 = {
1413                         .prcm_reg_id = 1,
1414                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1415                         .module_offs = WKUP_MOD,
1416                         .idlest_reg_id = 1,
1417                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1418                 },
1419         },
1420         .dev_attr       = &sr1_dev_attr,
1421         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1422         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1423 };
1424
1425 static struct omap_hwmod omap36xx_sr1_hwmod = {
1426         .name           = "smartreflex_mpu_iva",
1427         .class          = &omap36xx_smartreflex_hwmod_class,
1428         .main_clk       = "sr1_fck",
1429         .prcm           = {
1430                 .omap2 = {
1431                         .prcm_reg_id = 1,
1432                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1433                         .module_offs = WKUP_MOD,
1434                         .idlest_reg_id = 1,
1435                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1436                 },
1437         },
1438         .dev_attr       = &sr1_dev_attr,
1439         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1440 };
1441
1442 /* SR2 */
1443 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1444         .sensor_voltdm_name     = "core",
1445 };
1446
1447 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1448         { .irq = 19 + OMAP_INTC_START, },
1449         { .irq = -1 },
1450 };
1451
1452 static struct omap_hwmod omap34xx_sr2_hwmod = {
1453         .name           = "smartreflex_core",
1454         .class          = &omap34xx_smartreflex_hwmod_class,
1455         .main_clk       = "sr2_fck",
1456         .prcm           = {
1457                 .omap2 = {
1458                         .prcm_reg_id = 1,
1459                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1460                         .module_offs = WKUP_MOD,
1461                         .idlest_reg_id = 1,
1462                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1463                 },
1464         },
1465         .dev_attr       = &sr2_dev_attr,
1466         .mpu_irqs       = omap3_smartreflex_core_irqs,
1467         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1468 };
1469
1470 static struct omap_hwmod omap36xx_sr2_hwmod = {
1471         .name           = "smartreflex_core",
1472         .class          = &omap36xx_smartreflex_hwmod_class,
1473         .main_clk       = "sr2_fck",
1474         .prcm           = {
1475                 .omap2 = {
1476                         .prcm_reg_id = 1,
1477                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1478                         .module_offs = WKUP_MOD,
1479                         .idlest_reg_id = 1,
1480                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1481                 },
1482         },
1483         .dev_attr       = &sr2_dev_attr,
1484         .mpu_irqs       = omap3_smartreflex_core_irqs,
1485 };
1486
1487 /*
1488  * 'mailbox' class
1489  * mailbox module allowing communication between the on-chip processors
1490  * using a queued mailbox-interrupt mechanism.
1491  */
1492
1493 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1494         .rev_offs       = 0x000,
1495         .sysc_offs      = 0x010,
1496         .syss_offs      = 0x014,
1497         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1498                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1499         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1500         .sysc_fields    = &omap_hwmod_sysc_type1,
1501 };
1502
1503 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1504         .name = "mailbox",
1505         .sysc = &omap3xxx_mailbox_sysc,
1506 };
1507
1508 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1509         .name           = "mailbox",
1510         .class          = &omap3xxx_mailbox_hwmod_class,
1511         .main_clk       = "mailboxes_ick",
1512         .prcm           = {
1513                 .omap2 = {
1514                         .prcm_reg_id = 1,
1515                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1516                         .module_offs = CORE_MOD,
1517                         .idlest_reg_id = 1,
1518                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1519                 },
1520         },
1521 };
1522
1523 /*
1524  * 'mcspi' class
1525  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1526  * bus
1527  */
1528
1529 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1530         .rev_offs       = 0x0000,
1531         .sysc_offs      = 0x0010,
1532         .syss_offs      = 0x0014,
1533         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1534                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1535                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1536         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1537         .sysc_fields    = &omap_hwmod_sysc_type1,
1538 };
1539
1540 static struct omap_hwmod_class omap34xx_mcspi_class = {
1541         .name = "mcspi",
1542         .sysc = &omap34xx_mcspi_sysc,
1543         .rev = OMAP3_MCSPI_REV,
1544 };
1545
1546 /* mcspi1 */
1547 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1548         .num_chipselect = 4,
1549 };
1550
1551 static struct omap_hwmod omap34xx_mcspi1 = {
1552         .name           = "mcspi1",
1553         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1554         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1555         .main_clk       = "mcspi1_fck",
1556         .prcm           = {
1557                 .omap2 = {
1558                         .module_offs = CORE_MOD,
1559                         .prcm_reg_id = 1,
1560                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1561                         .idlest_reg_id = 1,
1562                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1563                 },
1564         },
1565         .class          = &omap34xx_mcspi_class,
1566         .dev_attr       = &omap_mcspi1_dev_attr,
1567 };
1568
1569 /* mcspi2 */
1570 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1571         .num_chipselect = 2,
1572 };
1573
1574 static struct omap_hwmod omap34xx_mcspi2 = {
1575         .name           = "mcspi2",
1576         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1577         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1578         .main_clk       = "mcspi2_fck",
1579         .prcm           = {
1580                 .omap2 = {
1581                         .module_offs = CORE_MOD,
1582                         .prcm_reg_id = 1,
1583                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1584                         .idlest_reg_id = 1,
1585                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1586                 },
1587         },
1588         .class          = &omap34xx_mcspi_class,
1589         .dev_attr       = &omap_mcspi2_dev_attr,
1590 };
1591
1592 /* mcspi3 */
1593 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1594         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1595         { .irq = -1 },
1596 };
1597
1598 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1599         { .name = "tx0", .dma_req = 15 },
1600         { .name = "rx0", .dma_req = 16 },
1601         { .name = "tx1", .dma_req = 23 },
1602         { .name = "rx1", .dma_req = 24 },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1607         .num_chipselect = 2,
1608 };
1609
1610 static struct omap_hwmod omap34xx_mcspi3 = {
1611         .name           = "mcspi3",
1612         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1613         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1614         .main_clk       = "mcspi3_fck",
1615         .prcm           = {
1616                 .omap2 = {
1617                         .module_offs = CORE_MOD,
1618                         .prcm_reg_id = 1,
1619                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1620                         .idlest_reg_id = 1,
1621                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1622                 },
1623         },
1624         .class          = &omap34xx_mcspi_class,
1625         .dev_attr       = &omap_mcspi3_dev_attr,
1626 };
1627
1628 /* mcspi4 */
1629 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1630         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1631         { .irq = -1 },
1632 };
1633
1634 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1635         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1636         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1637         { .dma_req = -1 }
1638 };
1639
1640 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1641         .num_chipselect = 1,
1642 };
1643
1644 static struct omap_hwmod omap34xx_mcspi4 = {
1645         .name           = "mcspi4",
1646         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1647         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1648         .main_clk       = "mcspi4_fck",
1649         .prcm           = {
1650                 .omap2 = {
1651                         .module_offs = CORE_MOD,
1652                         .prcm_reg_id = 1,
1653                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1654                         .idlest_reg_id = 1,
1655                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1656                 },
1657         },
1658         .class          = &omap34xx_mcspi_class,
1659         .dev_attr       = &omap_mcspi4_dev_attr,
1660 };
1661
1662 /* usbhsotg */
1663 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1664         .rev_offs       = 0x0400,
1665         .sysc_offs      = 0x0404,
1666         .syss_offs      = 0x0408,
1667         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1668                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1669                           SYSC_HAS_AUTOIDLE),
1670         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1671                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1672         .sysc_fields    = &omap_hwmod_sysc_type1,
1673 };
1674
1675 static struct omap_hwmod_class usbotg_class = {
1676         .name = "usbotg",
1677         .sysc = &omap3xxx_usbhsotg_sysc,
1678 };
1679
1680 /* usb_otg_hs */
1681 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1682
1683         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1684         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1685         { .irq = -1 },
1686 };
1687
1688 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1689         .name           = "usb_otg_hs",
1690         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1691         .main_clk       = "hsotgusb_ick",
1692         .prcm           = {
1693                 .omap2 = {
1694                         .prcm_reg_id = 1,
1695                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1696                         .module_offs = CORE_MOD,
1697                         .idlest_reg_id = 1,
1698                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1699                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1700                 },
1701         },
1702         .class          = &usbotg_class,
1703
1704         /*
1705          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1706          * broken when autoidle is enabled
1707          * workaround is to disable the autoidle bit at module level.
1708          *
1709          * Enabling the device in any other MIDLEMODE setting but force-idle
1710          * causes core_pwrdm not enter idle states at least on OMAP3630.
1711          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1712          * signal when MIDLEMODE is set to force-idle.
1713          */
1714         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1715                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1716 };
1717
1718 /* usb_otg_hs */
1719 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1720         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1721         { .irq = -1 },
1722 };
1723
1724 static struct omap_hwmod_class am35xx_usbotg_class = {
1725         .name = "am35xx_usbotg",
1726 };
1727
1728 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1729         .name           = "am35x_otg_hs",
1730         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1731         .main_clk       = "hsotgusb_fck",
1732         .class          = &am35xx_usbotg_class,
1733         .flags          = HWMOD_NO_IDLEST,
1734 };
1735
1736 /* MMC/SD/SDIO common */
1737 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1738         .rev_offs       = 0x1fc,
1739         .sysc_offs      = 0x10,
1740         .syss_offs      = 0x14,
1741         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1742                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1743                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1744         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1745         .sysc_fields    = &omap_hwmod_sysc_type1,
1746 };
1747
1748 static struct omap_hwmod_class omap34xx_mmc_class = {
1749         .name = "mmc",
1750         .sysc = &omap34xx_mmc_sysc,
1751 };
1752
1753 /* MMC/SD/SDIO1 */
1754
1755 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1756         { .irq = 83 + OMAP_INTC_START, },
1757         { .irq = -1 },
1758 };
1759
1760 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1761         { .name = "tx", .dma_req = 61, },
1762         { .name = "rx", .dma_req = 62, },
1763         { .dma_req = -1 }
1764 };
1765
1766 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1767         { .role = "dbck", .clk = "omap_32k_fck", },
1768 };
1769
1770 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1771         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1772 };
1773
1774 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1775 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1776         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1777                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1778 };
1779
1780 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1781         .name           = "mmc1",
1782         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1783         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1784         .opt_clks       = omap34xx_mmc1_opt_clks,
1785         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1786         .main_clk       = "mmchs1_fck",
1787         .prcm           = {
1788                 .omap2 = {
1789                         .module_offs = CORE_MOD,
1790                         .prcm_reg_id = 1,
1791                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1792                         .idlest_reg_id = 1,
1793                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1794                 },
1795         },
1796         .dev_attr       = &mmc1_pre_es3_dev_attr,
1797         .class          = &omap34xx_mmc_class,
1798 };
1799
1800 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1801         .name           = "mmc1",
1802         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1803         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1804         .opt_clks       = omap34xx_mmc1_opt_clks,
1805         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1806         .main_clk       = "mmchs1_fck",
1807         .prcm           = {
1808                 .omap2 = {
1809                         .module_offs = CORE_MOD,
1810                         .prcm_reg_id = 1,
1811                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1812                         .idlest_reg_id = 1,
1813                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1814                 },
1815         },
1816         .dev_attr       = &mmc1_dev_attr,
1817         .class          = &omap34xx_mmc_class,
1818 };
1819
1820 /* MMC/SD/SDIO2 */
1821
1822 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1823         { .irq = 86 + OMAP_INTC_START, },
1824         { .irq = -1 },
1825 };
1826
1827 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1828         { .name = "tx", .dma_req = 47, },
1829         { .name = "rx", .dma_req = 48, },
1830         { .dma_req = -1 }
1831 };
1832
1833 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1834         { .role = "dbck", .clk = "omap_32k_fck", },
1835 };
1836
1837 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1838 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1839         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1840 };
1841
1842 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1843         .name           = "mmc2",
1844         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1845         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1846         .opt_clks       = omap34xx_mmc2_opt_clks,
1847         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1848         .main_clk       = "mmchs2_fck",
1849         .prcm           = {
1850                 .omap2 = {
1851                         .module_offs = CORE_MOD,
1852                         .prcm_reg_id = 1,
1853                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1854                         .idlest_reg_id = 1,
1855                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1856                 },
1857         },
1858         .dev_attr       = &mmc2_pre_es3_dev_attr,
1859         .class          = &omap34xx_mmc_class,
1860 };
1861
1862 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1863         .name           = "mmc2",
1864         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1865         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1866         .opt_clks       = omap34xx_mmc2_opt_clks,
1867         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1868         .main_clk       = "mmchs2_fck",
1869         .prcm           = {
1870                 .omap2 = {
1871                         .module_offs = CORE_MOD,
1872                         .prcm_reg_id = 1,
1873                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1874                         .idlest_reg_id = 1,
1875                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1876                 },
1877         },
1878         .class          = &omap34xx_mmc_class,
1879 };
1880
1881 /* MMC/SD/SDIO3 */
1882
1883 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1884         { .irq = 94 + OMAP_INTC_START, },
1885         { .irq = -1 },
1886 };
1887
1888 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1889         { .name = "tx", .dma_req = 77, },
1890         { .name = "rx", .dma_req = 78, },
1891         { .dma_req = -1 }
1892 };
1893
1894 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1895         { .role = "dbck", .clk = "omap_32k_fck", },
1896 };
1897
1898 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1899         .name           = "mmc3",
1900         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1901         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1902         .opt_clks       = omap34xx_mmc3_opt_clks,
1903         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1904         .main_clk       = "mmchs3_fck",
1905         .prcm           = {
1906                 .omap2 = {
1907                         .prcm_reg_id = 1,
1908                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1909                         .idlest_reg_id = 1,
1910                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1911                 },
1912         },
1913         .class          = &omap34xx_mmc_class,
1914 };
1915
1916 /*
1917  * 'usb_host_hs' class
1918  * high-speed multi-port usb host controller
1919  */
1920
1921 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1922         .rev_offs       = 0x0000,
1923         .sysc_offs      = 0x0010,
1924         .syss_offs      = 0x0014,
1925         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1926                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1927                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1928                            SYSS_HAS_RESET_STATUS),
1929         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1930                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1931         .sysc_fields    = &omap_hwmod_sysc_type1,
1932 };
1933
1934 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1935         .name = "usb_host_hs",
1936         .sysc = &omap3xxx_usb_host_hs_sysc,
1937 };
1938
1939 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1940         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1941         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1942         { .irq = -1 },
1943 };
1944
1945 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1946         .name           = "usb_host_hs",
1947         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1948         .clkdm_name     = "usbhost_clkdm",
1949         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1950         .main_clk       = "usbhost_48m_fck",
1951         .prcm = {
1952                 .omap2 = {
1953                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1954                         .prcm_reg_id = 1,
1955                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1956                         .idlest_reg_id = 1,
1957                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1958                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1959                 },
1960         },
1961
1962         /*
1963          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1964          * id: i660
1965          *
1966          * Description:
1967          * In the following configuration :
1968          * - USBHOST module is set to smart-idle mode
1969          * - PRCM asserts idle_req to the USBHOST module ( This typically
1970          *   happens when the system is going to a low power mode : all ports
1971          *   have been suspended, the master part of the USBHOST module has
1972          *   entered the standby state, and SW has cut the functional clocks)
1973          * - an USBHOST interrupt occurs before the module is able to answer
1974          *   idle_ack, typically a remote wakeup IRQ.
1975          * Then the USB HOST module will enter a deadlock situation where it
1976          * is no more accessible nor functional.
1977          *
1978          * Workaround:
1979          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1980          */
1981
1982         /*
1983          * Errata: USB host EHCI may stall when entering smart-standby mode
1984          * Id: i571
1985          *
1986          * Description:
1987          * When the USBHOST module is set to smart-standby mode, and when it is
1988          * ready to enter the standby state (i.e. all ports are suspended and
1989          * all attached devices are in suspend mode), then it can wrongly assert
1990          * the Mstandby signal too early while there are still some residual OCP
1991          * transactions ongoing. If this condition occurs, the internal state
1992          * machine may go to an undefined state and the USB link may be stuck
1993          * upon the next resume.
1994          *
1995          * Workaround:
1996          * Don't use smart standby; use only force standby,
1997          * hence HWMOD_SWSUP_MSTANDBY
1998          */
1999
2000         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2001 };
2002
2003 /*
2004  * 'usb_tll_hs' class
2005  * usb_tll_hs module is the adapter on the usb_host_hs ports
2006  */
2007 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2008         .rev_offs       = 0x0000,
2009         .sysc_offs      = 0x0010,
2010         .syss_offs      = 0x0014,
2011         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2012                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2013                            SYSC_HAS_AUTOIDLE),
2014         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2015         .sysc_fields    = &omap_hwmod_sysc_type1,
2016 };
2017
2018 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2019         .name = "usb_tll_hs",
2020         .sysc = &omap3xxx_usb_tll_hs_sysc,
2021 };
2022
2023 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2024         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2025         { .irq = -1 },
2026 };
2027
2028 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2029         .name           = "usb_tll_hs",
2030         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2031         .clkdm_name     = "core_l4_clkdm",
2032         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2033         .main_clk       = "usbtll_fck",
2034         .prcm = {
2035                 .omap2 = {
2036                         .module_offs = CORE_MOD,
2037                         .prcm_reg_id = 3,
2038                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2039                         .idlest_reg_id = 3,
2040                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2041                 },
2042         },
2043 };
2044
2045 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2046         .name           = "hdq1w",
2047         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2048         .main_clk       = "hdq_fck",
2049         .prcm           = {
2050                 .omap2 = {
2051                         .module_offs = CORE_MOD,
2052                         .prcm_reg_id = 1,
2053                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2054                         .idlest_reg_id = 1,
2055                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2056                 },
2057         },
2058         .class          = &omap2_hdq1w_class,
2059 };
2060
2061 /* SAD2D */
2062 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2063         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2064         { .name = "rst_modem_sw", .rst_shift = 1 },
2065 };
2066
2067 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2068         .name                   = "sad2d",
2069 };
2070
2071 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2072         .name           = "sad2d",
2073         .rst_lines      = omap3xxx_sad2d_resets,
2074         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2075         .main_clk       = "sad2d_ick",
2076         .prcm           = {
2077                 .omap2 = {
2078                         .module_offs = CORE_MOD,
2079                         .prcm_reg_id = 1,
2080                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2081                         .idlest_reg_id = 1,
2082                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2083                 },
2084         },
2085         .class          = &omap3xxx_sad2d_class,
2086 };
2087
2088 /*
2089  * '32K sync counter' class
2090  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2091  */
2092 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2093         .rev_offs       = 0x0000,
2094         .sysc_offs      = 0x0004,
2095         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2096         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2097         .sysc_fields    = &omap_hwmod_sysc_type1,
2098 };
2099
2100 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2101         .name   = "counter",
2102         .sysc   = &omap3xxx_counter_sysc,
2103 };
2104
2105 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2106         .name           = "counter_32k",
2107         .class          = &omap3xxx_counter_hwmod_class,
2108         .clkdm_name     = "wkup_clkdm",
2109         .flags          = HWMOD_SWSUP_SIDLE,
2110         .main_clk       = "wkup_32k_fck",
2111         .prcm           = {
2112                 .omap2  = {
2113                         .module_offs = WKUP_MOD,
2114                         .prcm_reg_id = 1,
2115                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2116                         .idlest_reg_id = 1,
2117                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2118                 },
2119         },
2120 };
2121
2122 /*
2123  * 'gpmc' class
2124  * general purpose memory controller
2125  */
2126
2127 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2128         .rev_offs       = 0x0000,
2129         .sysc_offs      = 0x0010,
2130         .syss_offs      = 0x0014,
2131         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2132                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2134         .sysc_fields    = &omap_hwmod_sysc_type1,
2135 };
2136
2137 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2138         .name   = "gpmc",
2139         .sysc   = &omap3xxx_gpmc_sysc,
2140 };
2141
2142 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2143         { .irq = 20 + OMAP_INTC_START, },
2144         { .irq = -1 }
2145 };
2146
2147 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2148         .name           = "gpmc",
2149         .class          = &omap3xxx_gpmc_hwmod_class,
2150         .clkdm_name     = "core_l3_clkdm",
2151         .mpu_irqs       = omap3xxx_gpmc_irqs,
2152         .main_clk       = "gpmc_fck",
2153         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2154         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2155 };
2156
2157 /*
2158  * interfaces
2159  */
2160
2161 /* L3 -> L4_CORE interface */
2162 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2163         .master = &omap3xxx_l3_main_hwmod,
2164         .slave  = &omap3xxx_l4_core_hwmod,
2165         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2166 };
2167
2168 /* L3 -> L4_PER interface */
2169 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2170         .master = &omap3xxx_l3_main_hwmod,
2171         .slave  = &omap3xxx_l4_per_hwmod,
2172         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2173 };
2174
2175 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2176         {
2177                 .pa_start       = 0x68000000,
2178                 .pa_end         = 0x6800ffff,
2179                 .flags          = ADDR_TYPE_RT,
2180         },
2181         { }
2182 };
2183
2184 /* MPU -> L3 interface */
2185 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2186         .master   = &omap3xxx_mpu_hwmod,
2187         .slave    = &omap3xxx_l3_main_hwmod,
2188         .addr     = omap3xxx_l3_main_addrs,
2189         .user   = OCP_USER_MPU,
2190 };
2191
2192 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2193         {
2194                 .pa_start       = 0x54000000,
2195                 .pa_end         = 0x547fffff,
2196                 .flags          = ADDR_TYPE_RT,
2197         },
2198         { }
2199 };
2200
2201 /* l3 -> debugss */
2202 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2203         .master         = &omap3xxx_l3_main_hwmod,
2204         .slave          = &omap3xxx_debugss_hwmod,
2205         .addr           = omap3xxx_l4_emu_addrs,
2206         .user           = OCP_USER_MPU,
2207 };
2208
2209 /* DSS -> l3 */
2210 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2211         .master         = &omap3430es1_dss_core_hwmod,
2212         .slave          = &omap3xxx_l3_main_hwmod,
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2217         .master         = &omap3xxx_dss_core_hwmod,
2218         .slave          = &omap3xxx_l3_main_hwmod,
2219         .fw = {
2220                 .omap2 = {
2221                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2222                         .flags  = OMAP_FIREWALL_L3,
2223                 }
2224         },
2225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2226 };
2227
2228 /* l3_core -> usbhsotg interface */
2229 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2230         .master         = &omap3xxx_usbhsotg_hwmod,
2231         .slave          = &omap3xxx_l3_main_hwmod,
2232         .clk            = "core_l3_ick",
2233         .user           = OCP_USER_MPU,
2234 };
2235
2236 /* l3_core -> am35xx_usbhsotg interface */
2237 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2238         .master         = &am35xx_usbhsotg_hwmod,
2239         .slave          = &omap3xxx_l3_main_hwmod,
2240         .clk            = "hsotgusb_ick",
2241         .user           = OCP_USER_MPU,
2242 };
2243
2244 /* l3_core -> sad2d interface */
2245 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2246         .master         = &omap3xxx_sad2d_hwmod,
2247         .slave          = &omap3xxx_l3_main_hwmod,
2248         .clk            = "core_l3_ick",
2249         .user           = OCP_USER_MPU,
2250 };
2251
2252 /* L4_CORE -> L4_WKUP interface */
2253 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2254         .master = &omap3xxx_l4_core_hwmod,
2255         .slave  = &omap3xxx_l4_wkup_hwmod,
2256         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2257 };
2258
2259 /* L4 CORE -> MMC1 interface */
2260 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2261         .master         = &omap3xxx_l4_core_hwmod,
2262         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2263         .clk            = "mmchs1_ick",
2264         .addr           = omap2430_mmc1_addr_space,
2265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2266         .flags          = OMAP_FIREWALL_L4
2267 };
2268
2269 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2270         .master         = &omap3xxx_l4_core_hwmod,
2271         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2272         .clk            = "mmchs1_ick",
2273         .addr           = omap2430_mmc1_addr_space,
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275         .flags          = OMAP_FIREWALL_L4
2276 };
2277
2278 /* L4 CORE -> MMC2 interface */
2279 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2280         .master         = &omap3xxx_l4_core_hwmod,
2281         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2282         .clk            = "mmchs2_ick",
2283         .addr           = omap2430_mmc2_addr_space,
2284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2285         .flags          = OMAP_FIREWALL_L4
2286 };
2287
2288 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2289         .master         = &omap3xxx_l4_core_hwmod,
2290         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2291         .clk            = "mmchs2_ick",
2292         .addr           = omap2430_mmc2_addr_space,
2293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2294         .flags          = OMAP_FIREWALL_L4
2295 };
2296
2297 /* L4 CORE -> MMC3 interface */
2298 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2299         {
2300                 .pa_start       = 0x480ad000,
2301                 .pa_end         = 0x480ad1ff,
2302                 .flags          = ADDR_TYPE_RT,
2303         },
2304         { }
2305 };
2306
2307 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2308         .master         = &omap3xxx_l4_core_hwmod,
2309         .slave          = &omap3xxx_mmc3_hwmod,
2310         .clk            = "mmchs3_ick",
2311         .addr           = omap3xxx_mmc3_addr_space,
2312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2313         .flags          = OMAP_FIREWALL_L4
2314 };
2315
2316 /* L4 CORE -> UART1 interface */
2317 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2318         {
2319                 .pa_start       = OMAP3_UART1_BASE,
2320                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2321                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2322         },
2323         { }
2324 };
2325
2326 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2327         .master         = &omap3xxx_l4_core_hwmod,
2328         .slave          = &omap3xxx_uart1_hwmod,
2329         .clk            = "uart1_ick",
2330         .addr           = omap3xxx_uart1_addr_space,
2331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2332 };
2333
2334 /* L4 CORE -> UART2 interface */
2335 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2336         {
2337                 .pa_start       = OMAP3_UART2_BASE,
2338                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2339                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2340         },
2341         { }
2342 };
2343
2344 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2345         .master         = &omap3xxx_l4_core_hwmod,
2346         .slave          = &omap3xxx_uart2_hwmod,
2347         .clk            = "uart2_ick",
2348         .addr           = omap3xxx_uart2_addr_space,
2349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2350 };
2351
2352 /* L4 PER -> UART3 interface */
2353 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2354         {
2355                 .pa_start       = OMAP3_UART3_BASE,
2356                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2357                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2358         },
2359         { }
2360 };
2361
2362 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2363         .master         = &omap3xxx_l4_per_hwmod,
2364         .slave          = &omap3xxx_uart3_hwmod,
2365         .clk            = "uart3_ick",
2366         .addr           = omap3xxx_uart3_addr_space,
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* L4 PER -> UART4 interface */
2371 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2372         {
2373                 .pa_start       = OMAP3_UART4_BASE,
2374                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2375                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2376         },
2377         { }
2378 };
2379
2380 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2381         .master         = &omap3xxx_l4_per_hwmod,
2382         .slave          = &omap36xx_uart4_hwmod,
2383         .clk            = "uart4_ick",
2384         .addr           = omap36xx_uart4_addr_space,
2385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2386 };
2387
2388 /* AM35xx: L4 CORE -> UART4 interface */
2389 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2390         {
2391                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2392                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2393                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2394         },
2395         { }
2396 };
2397
2398 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2399         .master         = &omap3xxx_l4_core_hwmod,
2400         .slave          = &am35xx_uart4_hwmod,
2401         .clk            = "uart4_ick",
2402         .addr           = am35xx_uart4_addr_space,
2403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2404 };
2405
2406 /* L4 CORE -> I2C1 interface */
2407 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2408         .master         = &omap3xxx_l4_core_hwmod,
2409         .slave          = &omap3xxx_i2c1_hwmod,
2410         .clk            = "i2c1_ick",
2411         .addr           = omap2_i2c1_addr_space,
2412         .fw = {
2413                 .omap2 = {
2414                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2415                         .l4_prot_group = 7,
2416                         .flags  = OMAP_FIREWALL_L4,
2417                 }
2418         },
2419         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2420 };
2421
2422 /* L4 CORE -> I2C2 interface */
2423 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2424         .master         = &omap3xxx_l4_core_hwmod,
2425         .slave          = &omap3xxx_i2c2_hwmod,
2426         .clk            = "i2c2_ick",
2427         .addr           = omap2_i2c2_addr_space,
2428         .fw = {
2429                 .omap2 = {
2430                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2431                         .l4_prot_group = 7,
2432                         .flags = OMAP_FIREWALL_L4,
2433                 }
2434         },
2435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2436 };
2437
2438 /* L4 CORE -> I2C3 interface */
2439 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2440         {
2441                 .pa_start       = 0x48060000,
2442                 .pa_end         = 0x48060000 + SZ_128 - 1,
2443                 .flags          = ADDR_TYPE_RT,
2444         },
2445         { }
2446 };
2447
2448 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2449         .master         = &omap3xxx_l4_core_hwmod,
2450         .slave          = &omap3xxx_i2c3_hwmod,
2451         .clk            = "i2c3_ick",
2452         .addr           = omap3xxx_i2c3_addr_space,
2453         .fw = {
2454                 .omap2 = {
2455                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2456                         .l4_prot_group = 7,
2457                         .flags = OMAP_FIREWALL_L4,
2458                 }
2459         },
2460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462
2463 /* L4 CORE -> SR1 interface */
2464 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2465         {
2466                 .pa_start       = OMAP34XX_SR1_BASE,
2467                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2468                 .flags          = ADDR_TYPE_RT,
2469         },
2470         { }
2471 };
2472
2473 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2474         .master         = &omap3xxx_l4_core_hwmod,
2475         .slave          = &omap34xx_sr1_hwmod,
2476         .clk            = "sr_l4_ick",
2477         .addr           = omap3_sr1_addr_space,
2478         .user           = OCP_USER_MPU,
2479 };
2480
2481 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2482         .master         = &omap3xxx_l4_core_hwmod,
2483         .slave          = &omap36xx_sr1_hwmod,
2484         .clk            = "sr_l4_ick",
2485         .addr           = omap3_sr1_addr_space,
2486         .user           = OCP_USER_MPU,
2487 };
2488
2489 /* L4 CORE -> SR1 interface */
2490 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2491         {
2492                 .pa_start       = OMAP34XX_SR2_BASE,
2493                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2494                 .flags          = ADDR_TYPE_RT,
2495         },
2496         { }
2497 };
2498
2499 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2500         .master         = &omap3xxx_l4_core_hwmod,
2501         .slave          = &omap34xx_sr2_hwmod,
2502         .clk            = "sr_l4_ick",
2503         .addr           = omap3_sr2_addr_space,
2504         .user           = OCP_USER_MPU,
2505 };
2506
2507 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2508         .master         = &omap3xxx_l4_core_hwmod,
2509         .slave          = &omap36xx_sr2_hwmod,
2510         .clk            = "sr_l4_ick",
2511         .addr           = omap3_sr2_addr_space,
2512         .user           = OCP_USER_MPU,
2513 };
2514
2515 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2516         {
2517                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2518                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2519                 .flags          = ADDR_TYPE_RT
2520         },
2521         { }
2522 };
2523
2524 /* l4_core -> usbhsotg  */
2525 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2526         .master         = &omap3xxx_l4_core_hwmod,
2527         .slave          = &omap3xxx_usbhsotg_hwmod,
2528         .clk            = "l4_ick",
2529         .addr           = omap3xxx_usbhsotg_addrs,
2530         .user           = OCP_USER_MPU,
2531 };
2532
2533 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2534         {
2535                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2536                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2537                 .flags          = ADDR_TYPE_RT
2538         },
2539         { }
2540 };
2541
2542 /* l4_core -> usbhsotg  */
2543 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2544         .master         = &omap3xxx_l4_core_hwmod,
2545         .slave          = &am35xx_usbhsotg_hwmod,
2546         .clk            = "hsotgusb_ick",
2547         .addr           = am35xx_usbhsotg_addrs,
2548         .user           = OCP_USER_MPU,
2549 };
2550
2551 /* L4_WKUP -> L4_SEC interface */
2552 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2553         .master = &omap3xxx_l4_wkup_hwmod,
2554         .slave  = &omap3xxx_l4_sec_hwmod,
2555         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2556 };
2557
2558 /* IVA2 <- L3 interface */
2559 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2560         .master         = &omap3xxx_l3_main_hwmod,
2561         .slave          = &omap3xxx_iva_hwmod,
2562         .clk            = "core_l3_ick",
2563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2564 };
2565
2566 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2567         {
2568                 .pa_start       = 0x48318000,
2569                 .pa_end         = 0x48318000 + SZ_1K - 1,
2570                 .flags          = ADDR_TYPE_RT
2571         },
2572         { }
2573 };
2574
2575 /* l4_wkup -> timer1 */
2576 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2577         .master         = &omap3xxx_l4_wkup_hwmod,
2578         .slave          = &omap3xxx_timer1_hwmod,
2579         .clk            = "gpt1_ick",
2580         .addr           = omap3xxx_timer1_addrs,
2581         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2582 };
2583
2584 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2585         {
2586                 .pa_start       = 0x49032000,
2587                 .pa_end         = 0x49032000 + SZ_1K - 1,
2588                 .flags          = ADDR_TYPE_RT
2589         },
2590         { }
2591 };
2592
2593 /* l4_per -> timer2 */
2594 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2595         .master         = &omap3xxx_l4_per_hwmod,
2596         .slave          = &omap3xxx_timer2_hwmod,
2597         .clk            = "gpt2_ick",
2598         .addr           = omap3xxx_timer2_addrs,
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2603         {
2604                 .pa_start       = 0x49034000,
2605                 .pa_end         = 0x49034000 + SZ_1K - 1,
2606                 .flags          = ADDR_TYPE_RT
2607         },
2608         { }
2609 };
2610
2611 /* l4_per -> timer3 */
2612 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2613         .master         = &omap3xxx_l4_per_hwmod,
2614         .slave          = &omap3xxx_timer3_hwmod,
2615         .clk            = "gpt3_ick",
2616         .addr           = omap3xxx_timer3_addrs,
2617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2619
2620 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2621         {
2622                 .pa_start       = 0x49036000,
2623                 .pa_end         = 0x49036000 + SZ_1K - 1,
2624                 .flags          = ADDR_TYPE_RT
2625         },
2626         { }
2627 };
2628
2629 /* l4_per -> timer4 */
2630 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2631         .master         = &omap3xxx_l4_per_hwmod,
2632         .slave          = &omap3xxx_timer4_hwmod,
2633         .clk            = "gpt4_ick",
2634         .addr           = omap3xxx_timer4_addrs,
2635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2636 };
2637
2638 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2639         {
2640                 .pa_start       = 0x49038000,
2641                 .pa_end         = 0x49038000 + SZ_1K - 1,
2642                 .flags          = ADDR_TYPE_RT
2643         },
2644         { }
2645 };
2646
2647 /* l4_per -> timer5 */
2648 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2649         .master         = &omap3xxx_l4_per_hwmod,
2650         .slave          = &omap3xxx_timer5_hwmod,
2651         .clk            = "gpt5_ick",
2652         .addr           = omap3xxx_timer5_addrs,
2653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2655
2656 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2657         {
2658                 .pa_start       = 0x4903A000,
2659                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2660                 .flags          = ADDR_TYPE_RT
2661         },
2662         { }
2663 };
2664
2665 /* l4_per -> timer6 */
2666 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2667         .master         = &omap3xxx_l4_per_hwmod,
2668         .slave          = &omap3xxx_timer6_hwmod,
2669         .clk            = "gpt6_ick",
2670         .addr           = omap3xxx_timer6_addrs,
2671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2672 };
2673
2674 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2675         {
2676                 .pa_start       = 0x4903C000,
2677                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2678                 .flags          = ADDR_TYPE_RT
2679         },
2680         { }
2681 };
2682
2683 /* l4_per -> timer7 */
2684 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2685         .master         = &omap3xxx_l4_per_hwmod,
2686         .slave          = &omap3xxx_timer7_hwmod,
2687         .clk            = "gpt7_ick",
2688         .addr           = omap3xxx_timer7_addrs,
2689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2690 };
2691
2692 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2693         {
2694                 .pa_start       = 0x4903E000,
2695                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2696                 .flags          = ADDR_TYPE_RT
2697         },
2698         { }
2699 };
2700
2701 /* l4_per -> timer8 */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2703         .master         = &omap3xxx_l4_per_hwmod,
2704         .slave          = &omap3xxx_timer8_hwmod,
2705         .clk            = "gpt8_ick",
2706         .addr           = omap3xxx_timer8_addrs,
2707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2708 };
2709
2710 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2711         {
2712                 .pa_start       = 0x49040000,
2713                 .pa_end         = 0x49040000 + SZ_1K - 1,
2714                 .flags          = ADDR_TYPE_RT
2715         },
2716         { }
2717 };
2718
2719 /* l4_per -> timer9 */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2721         .master         = &omap3xxx_l4_per_hwmod,
2722         .slave          = &omap3xxx_timer9_hwmod,
2723         .clk            = "gpt9_ick",
2724         .addr           = omap3xxx_timer9_addrs,
2725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 /* l4_core -> timer10 */
2729 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2730         .master         = &omap3xxx_l4_core_hwmod,
2731         .slave          = &omap3xxx_timer10_hwmod,
2732         .clk            = "gpt10_ick",
2733         .addr           = omap2_timer10_addrs,
2734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2735 };
2736
2737 /* l4_core -> timer11 */
2738 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2739         .master         = &omap3xxx_l4_core_hwmod,
2740         .slave          = &omap3xxx_timer11_hwmod,
2741         .clk            = "gpt11_ick",
2742         .addr           = omap2_timer11_addrs,
2743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2747         {
2748                 .pa_start       = 0x48304000,
2749                 .pa_end         = 0x48304000 + SZ_1K - 1,
2750                 .flags          = ADDR_TYPE_RT
2751         },
2752         { }
2753 };
2754
2755 /* l4_core -> timer12 */
2756 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2757         .master         = &omap3xxx_l4_sec_hwmod,
2758         .slave          = &omap3xxx_timer12_hwmod,
2759         .clk            = "gpt12_ick",
2760         .addr           = omap3xxx_timer12_addrs,
2761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2762 };
2763
2764 /* l4_wkup -> wd_timer2 */
2765 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2766         {
2767                 .pa_start       = 0x48314000,
2768                 .pa_end         = 0x4831407f,
2769                 .flags          = ADDR_TYPE_RT
2770         },
2771         { }
2772 };
2773
2774 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2775         .master         = &omap3xxx_l4_wkup_hwmod,
2776         .slave          = &omap3xxx_wd_timer2_hwmod,
2777         .clk            = "wdt2_ick",
2778         .addr           = omap3xxx_wd_timer2_addrs,
2779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2780 };
2781
2782 /* l4_core -> dss */
2783 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2784         .master         = &omap3xxx_l4_core_hwmod,
2785         .slave          = &omap3430es1_dss_core_hwmod,
2786         .clk            = "dss_ick",
2787         .addr           = omap2_dss_addrs,
2788         .fw = {
2789                 .omap2 = {
2790                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2791                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2792                         .flags  = OMAP_FIREWALL_L4,
2793                 }
2794         },
2795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2796 };
2797
2798 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2799         .master         = &omap3xxx_l4_core_hwmod,
2800         .slave          = &omap3xxx_dss_core_hwmod,
2801         .clk            = "dss_ick",
2802         .addr           = omap2_dss_addrs,
2803         .fw = {
2804                 .omap2 = {
2805                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2806                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2807                         .flags  = OMAP_FIREWALL_L4,
2808                 }
2809         },
2810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2811 };
2812
2813 /* l4_core -> dss_dispc */
2814 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2815         .master         = &omap3xxx_l4_core_hwmod,
2816         .slave          = &omap3xxx_dss_dispc_hwmod,
2817         .clk            = "dss_ick",
2818         .addr           = omap2_dss_dispc_addrs,
2819         .fw = {
2820                 .omap2 = {
2821                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2822                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2823                         .flags  = OMAP_FIREWALL_L4,
2824                 }
2825         },
2826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2827 };
2828
2829 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2830         {
2831                 .pa_start       = 0x4804FC00,
2832                 .pa_end         = 0x4804FFFF,
2833                 .flags          = ADDR_TYPE_RT
2834         },
2835         { }
2836 };
2837
2838 /* l4_core -> dss_dsi1 */
2839 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2840         .master         = &omap3xxx_l4_core_hwmod,
2841         .slave          = &omap3xxx_dss_dsi1_hwmod,
2842         .clk            = "dss_ick",
2843         .addr           = omap3xxx_dss_dsi1_addrs,
2844         .fw = {
2845                 .omap2 = {
2846                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2847                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2848                         .flags  = OMAP_FIREWALL_L4,
2849                 }
2850         },
2851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2852 };
2853
2854 /* l4_core -> dss_rfbi */
2855 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2856         .master         = &omap3xxx_l4_core_hwmod,
2857         .slave          = &omap3xxx_dss_rfbi_hwmod,
2858         .clk            = "dss_ick",
2859         .addr           = omap2_dss_rfbi_addrs,
2860         .fw = {
2861                 .omap2 = {
2862                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2863                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2864                         .flags  = OMAP_FIREWALL_L4,
2865                 }
2866         },
2867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2868 };
2869
2870 /* l4_core -> dss_venc */
2871 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2872         .master         = &omap3xxx_l4_core_hwmod,
2873         .slave          = &omap3xxx_dss_venc_hwmod,
2874         .clk            = "dss_ick",
2875         .addr           = omap2_dss_venc_addrs,
2876         .fw = {
2877                 .omap2 = {
2878                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2879                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2880                         .flags  = OMAP_FIREWALL_L4,
2881                 }
2882         },
2883         .flags          = OCPIF_SWSUP_IDLE,
2884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l4_wkup -> gpio1 */
2888 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2889         {
2890                 .pa_start       = 0x48310000,
2891                 .pa_end         = 0x483101ff,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894         { }
2895 };
2896
2897 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2898         .master         = &omap3xxx_l4_wkup_hwmod,
2899         .slave          = &omap3xxx_gpio1_hwmod,
2900         .addr           = omap3xxx_gpio1_addrs,
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_per -> gpio2 */
2905 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2906         {
2907                 .pa_start       = 0x49050000,
2908                 .pa_end         = 0x490501ff,
2909                 .flags          = ADDR_TYPE_RT
2910         },
2911         { }
2912 };
2913
2914 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2915         .master         = &omap3xxx_l4_per_hwmod,
2916         .slave          = &omap3xxx_gpio2_hwmod,
2917         .addr           = omap3xxx_gpio2_addrs,
2918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 /* l4_per -> gpio3 */
2922 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2923         {
2924                 .pa_start       = 0x49052000,
2925                 .pa_end         = 0x490521ff,
2926                 .flags          = ADDR_TYPE_RT
2927         },
2928         { }
2929 };
2930
2931 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2932         .master         = &omap3xxx_l4_per_hwmod,
2933         .slave          = &omap3xxx_gpio3_hwmod,
2934         .addr           = omap3xxx_gpio3_addrs,
2935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2936 };
2937
2938 /*
2939  * 'mmu' class
2940  * The memory management unit performs virtual to physical address translation
2941  * for its requestors.
2942  */
2943
2944 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2945         .rev_offs       = 0x000,
2946         .sysc_offs      = 0x010,
2947         .syss_offs      = 0x014,
2948         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2949                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2951         .sysc_fields    = &omap_hwmod_sysc_type1,
2952 };
2953
2954 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2955         .name = "mmu",
2956         .sysc = &mmu_sysc,
2957 };
2958
2959 /* mmu isp */
2960
2961 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2962         .nr_tlb_entries = 8,
2963 };
2964
2965 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2966 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2967         { .irq = 24 + OMAP_INTC_START, },
2968         { .irq = -1 }
2969 };
2970
2971 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2972         {
2973                 .pa_start       = 0x480bd400,
2974                 .pa_end         = 0x480bd47f,
2975                 .flags          = ADDR_TYPE_RT,
2976         },
2977         { }
2978 };
2979
2980 /* l4_core -> mmu isp */
2981 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2982         .master         = &omap3xxx_l4_core_hwmod,
2983         .slave          = &omap3xxx_mmu_isp_hwmod,
2984         .addr           = omap3xxx_mmu_isp_addrs,
2985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2986 };
2987
2988 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2989         .name           = "mmu_isp",
2990         .class          = &omap3xxx_mmu_hwmod_class,
2991         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
2992         .main_clk       = "cam_ick",
2993         .dev_attr       = &mmu_isp_dev_attr,
2994         .flags          = HWMOD_NO_IDLEST,
2995 };
2996
2997 /* mmu iva */
2998
2999 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3000         .nr_tlb_entries = 32,
3001 };
3002
3003 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3004 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3005         { .irq = 28 + OMAP_INTC_START, },
3006         { .irq = -1 }
3007 };
3008
3009 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3010         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3011 };
3012
3013 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3014         {
3015                 .pa_start       = 0x5d000000,
3016                 .pa_end         = 0x5d00007f,
3017                 .flags          = ADDR_TYPE_RT,
3018         },
3019         { }
3020 };
3021
3022 /* l3_main -> iva mmu */
3023 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3024         .master         = &omap3xxx_l3_main_hwmod,
3025         .slave          = &omap3xxx_mmu_iva_hwmod,
3026         .addr           = omap3xxx_mmu_iva_addrs,
3027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3028 };
3029
3030 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3031         .name           = "mmu_iva",
3032         .class          = &omap3xxx_mmu_hwmod_class,
3033         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3034         .clkdm_name     = "iva2_clkdm",
3035         .rst_lines      = omap3xxx_mmu_iva_resets,
3036         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3037         .main_clk       = "iva2_ck",
3038         .prcm = {
3039                 .omap2 = {
3040                         .module_offs = OMAP3430_IVA2_MOD,
3041                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3042                         .idlest_reg_id = 1,
3043                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
3044                 },
3045         },
3046         .dev_attr       = &mmu_iva_dev_attr,
3047         .flags          = HWMOD_NO_IDLEST,
3048 };
3049
3050 /* l4_per -> gpio4 */
3051 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3052         {
3053                 .pa_start       = 0x49054000,
3054                 .pa_end         = 0x490541ff,
3055                 .flags          = ADDR_TYPE_RT
3056         },
3057         { }
3058 };
3059
3060 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3061         .master         = &omap3xxx_l4_per_hwmod,
3062         .slave          = &omap3xxx_gpio4_hwmod,
3063         .addr           = omap3xxx_gpio4_addrs,
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 /* l4_per -> gpio5 */
3068 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3069         {
3070                 .pa_start       = 0x49056000,
3071                 .pa_end         = 0x490561ff,
3072                 .flags          = ADDR_TYPE_RT
3073         },
3074         { }
3075 };
3076
3077 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3078         .master         = &omap3xxx_l4_per_hwmod,
3079         .slave          = &omap3xxx_gpio5_hwmod,
3080         .addr           = omap3xxx_gpio5_addrs,
3081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3082 };
3083
3084 /* l4_per -> gpio6 */
3085 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3086         {
3087                 .pa_start       = 0x49058000,
3088                 .pa_end         = 0x490581ff,
3089                 .flags          = ADDR_TYPE_RT
3090         },
3091         { }
3092 };
3093
3094 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3095         .master         = &omap3xxx_l4_per_hwmod,
3096         .slave          = &omap3xxx_gpio6_hwmod,
3097         .addr           = omap3xxx_gpio6_addrs,
3098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3099 };
3100
3101 /* dma_system -> L3 */
3102 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3103         .master         = &omap3xxx_dma_system_hwmod,
3104         .slave          = &omap3xxx_l3_main_hwmod,
3105         .clk            = "core_l3_ick",
3106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3107 };
3108
3109 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3110         {
3111                 .pa_start       = 0x48056000,
3112                 .pa_end         = 0x48056fff,
3113                 .flags          = ADDR_TYPE_RT
3114         },
3115         { }
3116 };
3117
3118 /* l4_cfg -> dma_system */
3119 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3120         .master         = &omap3xxx_l4_core_hwmod,
3121         .slave          = &omap3xxx_dma_system_hwmod,
3122         .clk            = "core_l4_ick",
3123         .addr           = omap3xxx_dma_system_addrs,
3124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3126
3127 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3128         {
3129                 .name           = "mpu",
3130                 .pa_start       = 0x48074000,
3131                 .pa_end         = 0x480740ff,
3132                 .flags          = ADDR_TYPE_RT
3133         },
3134         { }
3135 };
3136
3137 /* l4_core -> mcbsp1 */
3138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3139         .master         = &omap3xxx_l4_core_hwmod,
3140         .slave          = &omap3xxx_mcbsp1_hwmod,
3141         .clk            = "mcbsp1_ick",
3142         .addr           = omap3xxx_mcbsp1_addrs,
3143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3147         {
3148                 .name           = "mpu",
3149                 .pa_start       = 0x49022000,
3150                 .pa_end         = 0x490220ff,
3151                 .flags          = ADDR_TYPE_RT
3152         },
3153         { }
3154 };
3155
3156 /* l4_per -> mcbsp2 */
3157 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3158         .master         = &omap3xxx_l4_per_hwmod,
3159         .slave          = &omap3xxx_mcbsp2_hwmod,
3160         .clk            = "mcbsp2_ick",
3161         .addr           = omap3xxx_mcbsp2_addrs,
3162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164
3165 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3166         {
3167                 .name           = "mpu",
3168                 .pa_start       = 0x49024000,
3169                 .pa_end         = 0x490240ff,
3170                 .flags          = ADDR_TYPE_RT
3171         },
3172         { }
3173 };
3174
3175 /* l4_per -> mcbsp3 */
3176 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3177         .master         = &omap3xxx_l4_per_hwmod,
3178         .slave          = &omap3xxx_mcbsp3_hwmod,
3179         .clk            = "mcbsp3_ick",
3180         .addr           = omap3xxx_mcbsp3_addrs,
3181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3182 };
3183
3184 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3185         {
3186                 .name           = "mpu",
3187                 .pa_start       = 0x49026000,
3188                 .pa_end         = 0x490260ff,
3189                 .flags          = ADDR_TYPE_RT
3190         },
3191         { }
3192 };
3193
3194 /* l4_per -> mcbsp4 */
3195 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3196         .master         = &omap3xxx_l4_per_hwmod,
3197         .slave          = &omap3xxx_mcbsp4_hwmod,
3198         .clk            = "mcbsp4_ick",
3199         .addr           = omap3xxx_mcbsp4_addrs,
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3204         {
3205                 .name           = "mpu",
3206                 .pa_start       = 0x48096000,
3207                 .pa_end         = 0x480960ff,
3208                 .flags          = ADDR_TYPE_RT
3209         },
3210         { }
3211 };
3212
3213 /* l4_core -> mcbsp5 */
3214 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3215         .master         = &omap3xxx_l4_core_hwmod,
3216         .slave          = &omap3xxx_mcbsp5_hwmod,
3217         .clk            = "mcbsp5_ick",
3218         .addr           = omap3xxx_mcbsp5_addrs,
3219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3220 };
3221
3222 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3223         {
3224                 .name           = "sidetone",
3225                 .pa_start       = 0x49028000,
3226                 .pa_end         = 0x490280ff,
3227                 .flags          = ADDR_TYPE_RT
3228         },
3229         { }
3230 };
3231
3232 /* l4_per -> mcbsp2_sidetone */
3233 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3234         .master         = &omap3xxx_l4_per_hwmod,
3235         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3236         .clk            = "mcbsp2_ick",
3237         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3238         .user           = OCP_USER_MPU,
3239 };
3240
3241 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3242         {
3243                 .name           = "sidetone",
3244                 .pa_start       = 0x4902A000,
3245                 .pa_end         = 0x4902A0ff,
3246                 .flags          = ADDR_TYPE_RT
3247         },
3248         { }
3249 };
3250
3251 /* l4_per -> mcbsp3_sidetone */
3252 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3253         .master         = &omap3xxx_l4_per_hwmod,
3254         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3255         .clk            = "mcbsp3_ick",
3256         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3257         .user           = OCP_USER_MPU,
3258 };
3259
3260 /* l4_core -> mailbox */
3261 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3262         .master         = &omap3xxx_l4_core_hwmod,
3263         .slave          = &omap3xxx_mailbox_hwmod,
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* l4 core -> mcspi1 interface */
3268 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3269         .master         = &omap3xxx_l4_core_hwmod,
3270         .slave          = &omap34xx_mcspi1,
3271         .clk            = "mcspi1_ick",
3272         .addr           = omap2_mcspi1_addr_space,
3273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3274 };
3275
3276 /* l4 core -> mcspi2 interface */
3277 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3278         .master         = &omap3xxx_l4_core_hwmod,
3279         .slave          = &omap34xx_mcspi2,
3280         .clk            = "mcspi2_ick",
3281         .addr           = omap2_mcspi2_addr_space,
3282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* l4 core -> mcspi3 interface */
3286 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3287         .master         = &omap3xxx_l4_core_hwmod,
3288         .slave          = &omap34xx_mcspi3,
3289         .clk            = "mcspi3_ick",
3290         .addr           = omap2430_mcspi3_addr_space,
3291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3292 };
3293
3294 /* l4 core -> mcspi4 interface */
3295 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3296         {
3297                 .pa_start       = 0x480ba000,
3298                 .pa_end         = 0x480ba0ff,
3299                 .flags          = ADDR_TYPE_RT,
3300         },
3301         { }
3302 };
3303
3304 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3305         .master         = &omap3xxx_l4_core_hwmod,
3306         .slave          = &omap34xx_mcspi4,
3307         .clk            = "mcspi4_ick",
3308         .addr           = omap34xx_mcspi4_addr_space,
3309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3310 };
3311
3312 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3313         .master         = &omap3xxx_usb_host_hs_hwmod,
3314         .slave          = &omap3xxx_l3_main_hwmod,
3315         .clk            = "core_l3_ick",
3316         .user           = OCP_USER_MPU,
3317 };
3318
3319 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3320         {
3321                 .name           = "uhh",
3322                 .pa_start       = 0x48064000,
3323                 .pa_end         = 0x480643ff,
3324                 .flags          = ADDR_TYPE_RT
3325         },
3326         {
3327                 .name           = "ohci",
3328                 .pa_start       = 0x48064400,
3329                 .pa_end         = 0x480647ff,
3330         },
3331         {
3332                 .name           = "ehci",
3333                 .pa_start       = 0x48064800,
3334                 .pa_end         = 0x48064cff,
3335         },
3336         {}
3337 };
3338
3339 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3340         .master         = &omap3xxx_l4_core_hwmod,
3341         .slave          = &omap3xxx_usb_host_hs_hwmod,
3342         .clk            = "usbhost_ick",
3343         .addr           = omap3xxx_usb_host_hs_addrs,
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3348         {
3349                 .name           = "tll",
3350                 .pa_start       = 0x48062000,
3351                 .pa_end         = 0x48062fff,
3352                 .flags          = ADDR_TYPE_RT
3353         },
3354         {}
3355 };
3356
3357 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3358         .master         = &omap3xxx_l4_core_hwmod,
3359         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3360         .clk            = "usbtll_ick",
3361         .addr           = omap3xxx_usb_tll_hs_addrs,
3362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 /* l4_core -> hdq1w interface */
3366 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3367         .master         = &omap3xxx_l4_core_hwmod,
3368         .slave          = &omap3xxx_hdq1w_hwmod,
3369         .clk            = "hdq_ick",
3370         .addr           = omap2_hdq1w_addr_space,
3371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3372         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3373 };
3374
3375 /* l4_wkup -> 32ksync_counter */
3376 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3377         {
3378                 .pa_start       = 0x48320000,
3379                 .pa_end         = 0x4832001f,
3380                 .flags          = ADDR_TYPE_RT
3381         },
3382         { }
3383 };
3384
3385 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3386         {
3387                 .pa_start       = 0x6e000000,
3388                 .pa_end         = 0x6e000fff,
3389                 .flags          = ADDR_TYPE_RT
3390         },
3391         { }
3392 };
3393
3394 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3395         .master         = &omap3xxx_l4_wkup_hwmod,
3396         .slave          = &omap3xxx_counter_32k_hwmod,
3397         .clk            = "omap_32ksync_ick",
3398         .addr           = omap3xxx_counter_32k_addrs,
3399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* am35xx has Davinci MDIO & EMAC */
3403 static struct omap_hwmod_class am35xx_mdio_class = {
3404         .name = "davinci_mdio",
3405 };
3406
3407 static struct omap_hwmod am35xx_mdio_hwmod = {
3408         .name           = "davinci_mdio",
3409         .class          = &am35xx_mdio_class,
3410         .flags          = HWMOD_NO_IDLEST,
3411 };
3412
3413 /*
3414  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3415  * but this will probably require some additional hwmod core support,
3416  * so is left as a future to-do item.
3417  */
3418 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3419         .master         = &am35xx_mdio_hwmod,
3420         .slave          = &omap3xxx_l3_main_hwmod,
3421         .clk            = "emac_fck",
3422         .user           = OCP_USER_MPU,
3423 };
3424
3425 /* l4_core -> davinci mdio  */
3426 /*
3427  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3428  * but this will probably require some additional hwmod core support,
3429  * so is left as a future to-do item.
3430  */
3431 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3432         .master         = &omap3xxx_l4_core_hwmod,
3433         .slave          = &am35xx_mdio_hwmod,
3434         .clk            = "emac_fck",
3435         .user           = OCP_USER_MPU,
3436 };
3437
3438 static struct omap_hwmod_class am35xx_emac_class = {
3439         .name = "davinci_emac",
3440 };
3441
3442 static struct omap_hwmod am35xx_emac_hwmod = {
3443         .name           = "davinci_emac",
3444         .class          = &am35xx_emac_class,
3445         /*
3446          * According to Mark Greer, the MPU will not return from WFI
3447          * when the EMAC signals an interrupt.
3448          * http://www.spinics.net/lists/arm-kernel/msg174734.html
3449          */
3450         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3451 };
3452
3453 /* l3_core -> davinci emac interface */
3454 /*
3455  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3456  * but this will probably require some additional hwmod core support,
3457  * so is left as a future to-do item.
3458  */
3459 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3460         .master         = &am35xx_emac_hwmod,
3461         .slave          = &omap3xxx_l3_main_hwmod,
3462         .clk            = "emac_ick",
3463         .user           = OCP_USER_MPU,
3464 };
3465
3466 /* l4_core -> davinci emac  */
3467 /*
3468  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3469  * but this will probably require some additional hwmod core support,
3470  * so is left as a future to-do item.
3471  */
3472 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3473         .master         = &omap3xxx_l4_core_hwmod,
3474         .slave          = &am35xx_emac_hwmod,
3475         .clk            = "emac_ick",
3476         .user           = OCP_USER_MPU,
3477 };
3478
3479 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3480         .master         = &omap3xxx_l3_main_hwmod,
3481         .slave          = &omap3xxx_gpmc_hwmod,
3482         .clk            = "core_l3_ick",
3483         .addr           = omap3xxx_gpmc_addrs,
3484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3485 };
3486
3487 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3488 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3489         .sidle_shift    = 4,
3490         .srst_shift     = 1,
3491         .autoidle_shift = 0,
3492 };
3493
3494 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3495         .rev_offs       = 0x5c,
3496         .sysc_offs      = 0x60,
3497         .syss_offs      = 0x64,
3498         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3499                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3500         .sysc_fields    = &omap3_sham_sysc_fields,
3501 };
3502
3503 static struct omap_hwmod_class omap3xxx_sham_class = {
3504         .name   = "sham",
3505         .sysc   = &omap3_sham_sysc,
3506 };
3507
3508 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3509         { .irq = 49 + OMAP_INTC_START, },
3510         { .irq = -1 }
3511 };
3512
3513 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3514         { .name = "rx", .dma_req = 69, },
3515         { .dma_req = -1 }
3516 };
3517
3518 static struct omap_hwmod omap3xxx_sham_hwmod = {
3519         .name           = "sham",
3520         .mpu_irqs       = omap3_sham_mpu_irqs,
3521         .sdma_reqs      = omap3_sham_sdma_reqs,
3522         .main_clk       = "sha12_ick",
3523         .prcm           = {
3524                 .omap2 = {
3525                         .module_offs = CORE_MOD,
3526                         .prcm_reg_id = 1,
3527                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
3528                         .idlest_reg_id = 1,
3529                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3530                 },
3531         },
3532         .class          = &omap3xxx_sham_class,
3533 };
3534
3535 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3536         {
3537                 .pa_start       = 0x480c3000,
3538                 .pa_end         = 0x480c3000 + 0x64 - 1,
3539                 .flags          = ADDR_TYPE_RT
3540         },
3541         { }
3542 };
3543
3544 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3545         .master         = &omap3xxx_l4_core_hwmod,
3546         .slave          = &omap3xxx_sham_hwmod,
3547         .clk            = "sha12_ick",
3548         .addr           = omap3xxx_sham_addrs,
3549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3550 };
3551
3552 /* l4_core -> AES */
3553 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3554         .sidle_shift    = 6,
3555         .srst_shift     = 1,
3556         .autoidle_shift = 0,
3557 };
3558
3559 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3560         .rev_offs       = 0x44,
3561         .sysc_offs      = 0x48,
3562         .syss_offs      = 0x4c,
3563         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3564                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3565         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3566         .sysc_fields    = &omap3xxx_aes_sysc_fields,
3567 };
3568
3569 static struct omap_hwmod_class omap3xxx_aes_class = {
3570         .name   = "aes",
3571         .sysc   = &omap3_aes_sysc,
3572 };
3573
3574 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3575         { .name = "tx", .dma_req = 65, },
3576         { .name = "rx", .dma_req = 66, },
3577         { .dma_req = -1 }
3578 };
3579
3580 static struct omap_hwmod omap3xxx_aes_hwmod = {
3581         .name           = "aes",
3582         .sdma_reqs      = omap3_aes_sdma_reqs,
3583         .main_clk       = "aes2_ick",
3584         .prcm           = {
3585                 .omap2 = {
3586                         .module_offs = CORE_MOD,
3587                         .prcm_reg_id = 1,
3588                         .module_bit = OMAP3430_EN_AES2_SHIFT,
3589                         .idlest_reg_id = 1,
3590                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3591                 },
3592         },
3593         .class          = &omap3xxx_aes_class,
3594 };
3595
3596 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3597         {
3598                 .pa_start       = 0x480c5000,
3599                 .pa_end         = 0x480c5000 + 0x50 - 1,
3600                 .flags          = ADDR_TYPE_RT
3601         },
3602         { }
3603 };
3604
3605 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3606         .master         = &omap3xxx_l4_core_hwmod,
3607         .slave          = &omap3xxx_aes_hwmod,
3608         .clk            = "aes2_ick",
3609         .addr           = omap3xxx_aes_addrs,
3610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3611 };
3612
3613 /*
3614  * 'ssi' class
3615  * synchronous serial interface (multichannel and full-duplex serial if)
3616  */
3617
3618 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3619         .rev_offs       = 0x0000,
3620         .sysc_offs      = 0x0010,
3621         .syss_offs      = 0x0014,
3622         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3623                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3625         .sysc_fields    = &omap_hwmod_sysc_type1,
3626 };
3627
3628 static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
3629         .name   = "ssi",
3630         .sysc   = &omap34xx_ssi_sysc,
3631 };
3632
3633 static struct omap_hwmod omap34xx_ssi_hwmod = {
3634         .name           = "ssi",
3635         .class          = &omap34xx_ssi_hwmod_class,
3636         .clkdm_name     = "core_l4_clkdm",
3637         .main_clk       = "ssi_ssr_fck",
3638         .prcm           = {
3639                 .omap2 = {
3640                         .prcm_reg_id            = 1,
3641                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
3642                         .module_offs            = CORE_MOD,
3643                         .idlest_reg_id          = 1,
3644                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3645                 },
3646         },
3647 };
3648
3649 /* L4 CORE -> SSI */
3650 static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
3651         .master         = &omap3xxx_l4_core_hwmod,
3652         .slave          = &omap34xx_ssi_hwmod,
3653         .clk            = "ssi_ick",
3654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3656
3657 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3658         &omap3xxx_l3_main__l4_core,
3659         &omap3xxx_l3_main__l4_per,
3660         &omap3xxx_mpu__l3_main,
3661         &omap3xxx_l3_main__l4_debugss,
3662         &omap3xxx_l4_core__l4_wkup,
3663         &omap3xxx_l4_core__mmc3,
3664         &omap3_l4_core__uart1,
3665         &omap3_l4_core__uart2,
3666         &omap3_l4_per__uart3,
3667         &omap3_l4_core__i2c1,
3668         &omap3_l4_core__i2c2,
3669         &omap3_l4_core__i2c3,
3670         &omap3xxx_l4_wkup__l4_sec,
3671         &omap3xxx_l4_wkup__timer1,
3672         &omap3xxx_l4_per__timer2,
3673         &omap3xxx_l4_per__timer3,
3674         &omap3xxx_l4_per__timer4,
3675         &omap3xxx_l4_per__timer5,
3676         &omap3xxx_l4_per__timer6,
3677         &omap3xxx_l4_per__timer7,
3678         &omap3xxx_l4_per__timer8,
3679         &omap3xxx_l4_per__timer9,
3680         &omap3xxx_l4_core__timer10,
3681         &omap3xxx_l4_core__timer11,
3682         &omap3xxx_l4_wkup__wd_timer2,
3683         &omap3xxx_l4_wkup__gpio1,
3684         &omap3xxx_l4_per__gpio2,
3685         &omap3xxx_l4_per__gpio3,
3686         &omap3xxx_l4_per__gpio4,
3687         &omap3xxx_l4_per__gpio5,
3688         &omap3xxx_l4_per__gpio6,
3689         &omap3xxx_dma_system__l3,
3690         &omap3xxx_l4_core__dma_system,
3691         &omap3xxx_l4_core__mcbsp1,
3692         &omap3xxx_l4_per__mcbsp2,
3693         &omap3xxx_l4_per__mcbsp3,
3694         &omap3xxx_l4_per__mcbsp4,
3695         &omap3xxx_l4_core__mcbsp5,
3696         &omap3xxx_l4_per__mcbsp2_sidetone,
3697         &omap3xxx_l4_per__mcbsp3_sidetone,
3698         &omap34xx_l4_core__mcspi1,
3699         &omap34xx_l4_core__mcspi2,
3700         &omap34xx_l4_core__mcspi3,
3701         &omap34xx_l4_core__mcspi4,
3702         &omap3xxx_l4_wkup__counter_32k,
3703         &omap3xxx_l3_main__gpmc,
3704         NULL,
3705 };
3706
3707 /* GP-only hwmod links */
3708 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3709         &omap3xxx_l4_sec__timer12,
3710         NULL
3711 };
3712
3713 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3714         &omap3xxx_l4_sec__timer12,
3715         NULL
3716 };
3717
3718 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3719         &omap3xxx_l4_sec__timer12,
3720         NULL
3721 };
3722
3723 /* crypto hwmod links */
3724 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3725         &omap3xxx_l4_core__sham,
3726         NULL
3727 };
3728
3729 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3730         &omap3xxx_l4_core__aes,
3731         NULL
3732 };
3733
3734 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3735         &omap3xxx_l4_core__sham,
3736         NULL
3737 };
3738
3739 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3740         &omap3xxx_l4_core__aes,
3741         NULL
3742 };
3743
3744 /*
3745  * Apparently the SHA/MD5 and AES accelerator IP blocks are
3746  * only present on some AM35xx chips, and no one knows which
3747  * ones.  See
3748  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3749  * if you need these IP blocks on an AM35xx, try uncommenting
3750  * the following lines.
3751  */
3752 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3753         /* &omap3xxx_l4_core__sham, */
3754         NULL
3755 };
3756
3757 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3758         /* &omap3xxx_l4_core__aes, */
3759         NULL
3760 };
3761
3762 /* 3430ES1-only hwmod links */
3763 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3764         &omap3430es1_dss__l3,
3765         &omap3430es1_l4_core__dss,
3766         NULL
3767 };
3768
3769 /* 3430ES2+-only hwmod links */
3770 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3771         &omap3xxx_dss__l3,
3772         &omap3xxx_l4_core__dss,
3773         &omap3xxx_usbhsotg__l3,
3774         &omap3xxx_l4_core__usbhsotg,
3775         &omap3xxx_usb_host_hs__l3_main_2,
3776         &omap3xxx_l4_core__usb_host_hs,
3777         &omap3xxx_l4_core__usb_tll_hs,
3778         NULL
3779 };
3780
3781 /* <= 3430ES3-only hwmod links */
3782 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3783         &omap3xxx_l4_core__pre_es3_mmc1,
3784         &omap3xxx_l4_core__pre_es3_mmc2,
3785         NULL
3786 };
3787
3788 /* 3430ES3+-only hwmod links */
3789 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3790         &omap3xxx_l4_core__es3plus_mmc1,
3791         &omap3xxx_l4_core__es3plus_mmc2,
3792         NULL
3793 };
3794
3795 /* 34xx-only hwmod links (all ES revisions) */
3796 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3797         &omap3xxx_l3__iva,
3798         &omap34xx_l4_core__sr1,
3799         &omap34xx_l4_core__sr2,
3800         &omap3xxx_l4_core__mailbox,
3801         &omap3xxx_l4_core__hdq1w,
3802         &omap3xxx_sad2d__l3,
3803         &omap3xxx_l4_core__mmu_isp,
3804         &omap3xxx_l3_main__mmu_iva,
3805         &omap34xx_l4_core__ssi,
3806         NULL
3807 };
3808
3809 /* 36xx-only hwmod links (all ES revisions) */
3810 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3811         &omap3xxx_l3__iva,
3812         &omap36xx_l4_per__uart4,
3813         &omap3xxx_dss__l3,
3814         &omap3xxx_l4_core__dss,
3815         &omap36xx_l4_core__sr1,
3816         &omap36xx_l4_core__sr2,
3817         &omap3xxx_usbhsotg__l3,
3818         &omap3xxx_l4_core__usbhsotg,
3819         &omap3xxx_l4_core__mailbox,
3820         &omap3xxx_usb_host_hs__l3_main_2,
3821         &omap3xxx_l4_core__usb_host_hs,
3822         &omap3xxx_l4_core__usb_tll_hs,
3823         &omap3xxx_l4_core__es3plus_mmc1,
3824         &omap3xxx_l4_core__es3plus_mmc2,
3825         &omap3xxx_l4_core__hdq1w,
3826         &omap3xxx_sad2d__l3,
3827         &omap3xxx_l4_core__mmu_isp,
3828         &omap3xxx_l3_main__mmu_iva,
3829         NULL
3830 };
3831
3832 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3833         &omap3xxx_dss__l3,
3834         &omap3xxx_l4_core__dss,
3835         &am35xx_usbhsotg__l3,
3836         &am35xx_l4_core__usbhsotg,
3837         &am35xx_l4_core__uart4,
3838         &omap3xxx_usb_host_hs__l3_main_2,
3839         &omap3xxx_l4_core__usb_host_hs,
3840         &omap3xxx_l4_core__usb_tll_hs,
3841         &omap3xxx_l4_core__es3plus_mmc1,
3842         &omap3xxx_l4_core__es3plus_mmc2,
3843         &omap3xxx_l4_core__hdq1w,
3844         &am35xx_mdio__l3,
3845         &am35xx_l4_core__mdio,
3846         &am35xx_emac__l3,
3847         &am35xx_l4_core__emac,
3848         NULL
3849 };
3850
3851 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3852         &omap3xxx_l4_core__dss_dispc,
3853         &omap3xxx_l4_core__dss_dsi1,
3854         &omap3xxx_l4_core__dss_rfbi,
3855         &omap3xxx_l4_core__dss_venc,
3856         NULL
3857 };
3858
3859 /**
3860  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3861  * @bus: struct device_node * for the top-level OMAP DT data
3862  * @dev_name: device name used in the DT file
3863  *
3864  * Determine whether a "secure" IP block @dev_name is usable by Linux.
3865  * There doesn't appear to be a 100% reliable way to determine this,
3866  * so we rely on heuristics.  If @bus is null, meaning there's no DT
3867  * data, then we only assume the IP block is accessible if the OMAP is
3868  * fused as a 'general-purpose' SoC.  If however DT data is present,
3869  * test to see if the IP block is described in the DT data and set to
3870  * 'status = "okay"'.  If so then we assume the ODM has configured the
3871  * OMAP firewalls to allow access to the IP block.
3872  *
3873  * Return: 0 if device named @dev_name is not likely to be accessible,
3874  * or 1 if it is likely to be accessible.
3875  */
3876 static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3877                                                        const char *dev_name)
3878 {
3879         if (!bus)
3880                 return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
3881
3882         if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
3883                 return 1;
3884
3885         return 0;
3886 }
3887
3888 int __init omap3xxx_hwmod_init(void)
3889 {
3890         int r;
3891         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3892         struct omap_hwmod_ocp_if **h_aes = NULL;
3893         struct device_node *bus = NULL;
3894         unsigned int rev;
3895
3896         omap_hwmod_init();
3897
3898         /* Register hwmod links common to all OMAP3 */
3899         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3900         if (r < 0)
3901                 return r;
3902
3903         rev = omap_rev();
3904
3905         /*
3906          * Register hwmod links common to individual OMAP3 families, all
3907          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3908          * All possible revisions should be included in this conditional.
3909          */
3910         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3911             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3912             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3913                 h = omap34xx_hwmod_ocp_ifs;
3914                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3915                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3916                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3917         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3918                 h = am35xx_hwmod_ocp_ifs;
3919                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3920                 h_sham = am35xx_sham_hwmod_ocp_ifs;
3921                 h_aes = am35xx_aes_hwmod_ocp_ifs;
3922         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3923                    rev == OMAP3630_REV_ES1_2) {
3924                 h = omap36xx_hwmod_ocp_ifs;
3925                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3926                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3927                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3928         } else {
3929                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3930                 return -EINVAL;
3931         }
3932
3933         r = omap_hwmod_register_links(h);
3934         if (r < 0)
3935                 return r;
3936
3937         /* Register GP-only hwmod links. */
3938         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3939                 r = omap_hwmod_register_links(h_gp);
3940                 if (r < 0)
3941                         return r;
3942         }
3943
3944         /*
3945          * Register crypto hwmod links only if they are not disabled in DT.
3946          * If DT information is missing, enable them only for GP devices.
3947          */
3948
3949         if (of_have_populated_dt())
3950                 bus = of_find_node_by_name(NULL, "ocp");
3951
3952         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3953                 r = omap_hwmod_register_links(h_sham);
3954                 if (r < 0)
3955                         return r;
3956         }
3957
3958         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3959                 r = omap_hwmod_register_links(h_aes);
3960                 if (r < 0)
3961                         return r;
3962         }
3963
3964         /*
3965          * Register hwmod links specific to certain ES levels of a
3966          * particular family of silicon (e.g., 34xx ES1.0)
3967          */
3968         h = NULL;
3969         if (rev == OMAP3430_REV_ES1_0) {
3970                 h = omap3430es1_hwmod_ocp_ifs;
3971         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3972                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3973                    rev == OMAP3430_REV_ES3_1_2) {
3974                 h = omap3430es2plus_hwmod_ocp_ifs;
3975         }
3976
3977         if (h) {
3978                 r = omap_hwmod_register_links(h);
3979                 if (r < 0)
3980                         return r;
3981         }
3982
3983         h = NULL;
3984         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3985             rev == OMAP3430_REV_ES2_1) {
3986                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3987         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3988                    rev == OMAP3430_REV_ES3_1_2) {
3989                 h = omap3430_es3plus_hwmod_ocp_ifs;
3990         }
3991
3992         if (h)
3993                 r = omap_hwmod_register_links(h);
3994         if (r < 0)
3995                 return r;
3996
3997         /*
3998          * DSS code presumes that dss_core hwmod is handled first,
3999          * _before_ any other DSS related hwmods so register common
4000          * DSS hwmod links last to ensure that dss_core is already
4001          * registered.  Otherwise some change things may happen, for
4002          * ex. if dispc is handled before dss_core and DSS is enabled
4003          * in bootloader DISPC will be reset with outputs enabled
4004          * which sometimes leads to unrecoverable L3 error.  XXX The
4005          * long-term fix to this is to ensure hwmods are set up in
4006          * dependency order in the hwmod core code.
4007          */
4008         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
4009
4010         return r;
4011 }