arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "soc.h"
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "serial.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /* L3 */
  56
  57 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  58         .name           = "l3_main",
  59         .class          = &l3_hwmod_class,
  60         .flags          = HWMOD_NO_IDLEST,
  61 };
  62
  63 /* L4 CORE */
  64 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  65         .name           = "l4_core",
  66         .class          = &l4_hwmod_class,
  67         .flags          = HWMOD_NO_IDLEST,
  68 };
  69
  70 /* L4 PER */
  71 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  72         .name           = "l4_per",
  73         .class          = &l4_hwmod_class,
  74         .flags          = HWMOD_NO_IDLEST,
  75 };
  76
  77 /* L4 WKUP */
  78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  79         .name           = "l4_wkup",
  80         .class          = &l4_hwmod_class,
  81         .flags          = HWMOD_NO_IDLEST,
  82 };
  83
  84 /* L4 SEC */
  85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  86         .name           = "l4_sec",
  87         .class          = &l4_hwmod_class,
  88         .flags          = HWMOD_NO_IDLEST,
  89 };
  90
  91 /* MPU */
  92
  93 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  94         .name           = "mpu",
  95         .class          = &mpu_hwmod_class,
  96         .main_clk       = "arm_fck",
  97 };
  98
  99 /* IVA2 (IVA2) */
 100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 101         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 102         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 103         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 104 };
 105
 106 static struct omap_hwmod omap3xxx_iva_hwmod = {
 107         .name           = "iva",
 108         .class          = &iva_hwmod_class,
 109         .clkdm_name     = "iva2_clkdm",
 110         .rst_lines      = omap3xxx_iva_resets,
 111         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 112         .main_clk       = "iva2_ck",
 113         .prcm = {
 114                 .omap2 = {
 115                         .module_offs = OMAP3430_IVA2_MOD,
 116                         .prcm_reg_id = 1,
 117                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 118                         .idlest_reg_id = 1,
 119                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 120                 },
 121         },
 122 };
 123
 124 /*
 125  * 'debugss' class
 126  * debug and emulation sub system
 127  */
 128
 129 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 130         .name   = "debugss",
 131 };
 132
 133 /* debugss */
 134 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 135         .name           = "debugss",
 136         .class          = &omap3xxx_debugss_hwmod_class,
 137         .clkdm_name     = "emu_clkdm",
 138         .main_clk       = "emu_src_ck",
 139         .flags          = HWMOD_NO_IDLEST,
 140 };
 141
 142 /* timer class */
 143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 144         .rev_offs       = 0x0000,
 145         .sysc_offs      = 0x0010,
 146         .syss_offs      = 0x0014,
 147         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 148                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 149                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 150                            SYSS_HAS_RESET_STATUS),
 151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 152         .sysc_fields    = &omap_hwmod_sysc_type1,
 153 };
 154
 155 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 156         .name = "timer",
 157         .sysc = &omap3xxx_timer_sysc,
 158 };
 159
 160 /* secure timers dev attribute */
 161 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 162         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 163 };
 164
 165 /* always-on timers dev attribute */
 166 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 167         .timer_capability       = OMAP_TIMER_ALWON,
 168 };
 169
 170 /* pwm timers dev attribute */
 171 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 172         .timer_capability       = OMAP_TIMER_HAS_PWM,
 173 };
 174
 175 /* timers with DSP interrupt dev attribute */
 176 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 177         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 178 };
 179
 180 /* pwm timers with DSP interrupt dev attribute */
 181 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 182         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 183 };
 184
 185 /* timer1 */
 186 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 187         .name           = "timer1",
 188         .main_clk       = "gpt1_fck",
 189         .prcm           = {
 190                 .omap2 = {
 191                         .prcm_reg_id = 1,
 192                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 193                         .module_offs = WKUP_MOD,
 194                         .idlest_reg_id = 1,
 195                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 196                 },
 197         },
 198         .dev_attr       = &capability_alwon_dev_attr,
 199         .class          = &omap3xxx_timer_hwmod_class,
 200         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 201 };
 202
 203 /* timer2 */
 204 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 205         .name           = "timer2",
 206         .main_clk       = "gpt2_fck",
 207         .prcm           = {
 208                 .omap2 = {
 209                         .prcm_reg_id = 1,
 210                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 211                         .module_offs = OMAP3430_PER_MOD,
 212                         .idlest_reg_id = 1,
 213                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 214                 },
 215         },
 216         .class          = &omap3xxx_timer_hwmod_class,
 217         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 218 };
 219
 220 /* timer3 */
 221 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 222         .name           = "timer3",
 223         .main_clk       = "gpt3_fck",
 224         .prcm           = {
 225                 .omap2 = {
 226                         .prcm_reg_id = 1,
 227                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 228                         .module_offs = OMAP3430_PER_MOD,
 229                         .idlest_reg_id = 1,
 230                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 231                 },
 232         },
 233         .class          = &omap3xxx_timer_hwmod_class,
 234         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 235 };
 236
 237 /* timer4 */
 238 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 239         .name           = "timer4",
 240         .main_clk       = "gpt4_fck",
 241         .prcm           = {
 242                 .omap2 = {
 243                         .prcm_reg_id = 1,
 244                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 245                         .module_offs = OMAP3430_PER_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 248                 },
 249         },
 250         .class          = &omap3xxx_timer_hwmod_class,
 251         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 252 };
 253
 254 /* timer5 */
 255 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 256         .name           = "timer5",
 257         .main_clk       = "gpt5_fck",
 258         .prcm           = {
 259                 .omap2 = {
 260                         .prcm_reg_id = 1,
 261                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 262                         .module_offs = OMAP3430_PER_MOD,
 263                         .idlest_reg_id = 1,
 264                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 265                 },
 266         },
 267         .dev_attr       = &capability_dsp_dev_attr,
 268         .class          = &omap3xxx_timer_hwmod_class,
 269         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 270 };
 271
 272 /* timer6 */
 273 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 274         .name           = "timer6",
 275         .main_clk       = "gpt6_fck",
 276         .prcm           = {
 277                 .omap2 = {
 278                         .prcm_reg_id = 1,
 279                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 280                         .module_offs = OMAP3430_PER_MOD,
 281                         .idlest_reg_id = 1,
 282                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 283                 },
 284         },
 285         .dev_attr       = &capability_dsp_dev_attr,
 286         .class          = &omap3xxx_timer_hwmod_class,
 287         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 288 };
 289
 290 /* timer7 */
 291 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 292         .name           = "timer7",
 293         .main_clk       = "gpt7_fck",
 294         .prcm           = {
 295                 .omap2 = {
 296                         .prcm_reg_id = 1,
 297                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 298                         .module_offs = OMAP3430_PER_MOD,
 299                         .idlest_reg_id = 1,
 300                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 301                 },
 302         },
 303         .dev_attr       = &capability_dsp_dev_attr,
 304         .class          = &omap3xxx_timer_hwmod_class,
 305         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 306 };
 307
 308 /* timer8 */
 309 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 310         .name           = "timer8",
 311         .main_clk       = "gpt8_fck",
 312         .prcm           = {
 313                 .omap2 = {
 314                         .prcm_reg_id = 1,
 315                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 316                         .module_offs = OMAP3430_PER_MOD,
 317                         .idlest_reg_id = 1,
 318                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 319                 },
 320         },
 321         .dev_attr       = &capability_dsp_pwm_dev_attr,
 322         .class          = &omap3xxx_timer_hwmod_class,
 323         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 324 };
 325
 326 /* timer9 */
 327 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 328         .name           = "timer9",
 329         .main_clk       = "gpt9_fck",
 330         .prcm           = {
 331                 .omap2 = {
 332                         .prcm_reg_id = 1,
 333                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 334                         .module_offs = OMAP3430_PER_MOD,
 335                         .idlest_reg_id = 1,
 336                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 337                 },
 338         },
 339         .dev_attr       = &capability_pwm_dev_attr,
 340         .class          = &omap3xxx_timer_hwmod_class,
 341         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 342 };
 343
 344 /* timer10 */
 345 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 346         .name           = "timer10",
 347         .main_clk       = "gpt10_fck",
 348         .prcm           = {
 349                 .omap2 = {
 350                         .prcm_reg_id = 1,
 351                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 352                         .module_offs = CORE_MOD,
 353                         .idlest_reg_id = 1,
 354                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 355                 },
 356         },
 357         .dev_attr       = &capability_pwm_dev_attr,
 358         .class          = &omap3xxx_timer_hwmod_class,
 359         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 360 };
 361
 362 /* timer11 */
 363 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 364         .name           = "timer11",
 365         .main_clk       = "gpt11_fck",
 366         .prcm           = {
 367                 .omap2 = {
 368                         .prcm_reg_id = 1,
 369                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 370                         .module_offs = CORE_MOD,
 371                         .idlest_reg_id = 1,
 372                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 373                 },
 374         },
 375         .dev_attr       = &capability_pwm_dev_attr,
 376         .class          = &omap3xxx_timer_hwmod_class,
 377         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 378 };
 379
 380 /* timer12 */
 381
 382 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 383         .name           = "timer12",
 384         .main_clk       = "gpt12_fck",
 385         .prcm           = {
 386                 .omap2 = {
 387                         .prcm_reg_id = 1,
 388                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 389                         .module_offs = WKUP_MOD,
 390                         .idlest_reg_id = 1,
 391                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 392                 },
 393         },
 394         .dev_attr       = &capability_secure_dev_attr,
 395         .class          = &omap3xxx_timer_hwmod_class,
 396         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 397 };
 398
 399 /*
 400  * 'wd_timer' class
 401  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 402  * overflow condition
 403  */
 404
 405 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 406         .rev_offs       = 0x0000,
 407         .sysc_offs      = 0x0010,
 408         .syss_offs      = 0x0014,
 409         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 410                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 411                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 412                            SYSS_HAS_RESET_STATUS),
 413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 414         .sysc_fields    = &omap_hwmod_sysc_type1,
 415 };
 416
 417 /* I2C common */
 418 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 419         .rev_offs       = 0x00,
 420         .sysc_offs      = 0x20,
 421         .syss_offs      = 0x10,
 422         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 423                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 424                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 425         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 426         .sysc_fields    = &omap_hwmod_sysc_type1,
 427 };
 428
 429 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 430         .name           = "wd_timer",
 431         .sysc           = &omap3xxx_wd_timer_sysc,
 432         .pre_shutdown   = &omap2_wd_timer_disable,
 433         .reset          = &omap2_wd_timer_reset,
 434 };
 435
 436 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 437         .name           = "wd_timer2",
 438         .class          = &omap3xxx_wd_timer_hwmod_class,
 439         .main_clk       = "wdt2_fck",
 440         .prcm           = {
 441                 .omap2 = {
 442                         .prcm_reg_id = 1,
 443                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 444                         .module_offs = WKUP_MOD,
 445                         .idlest_reg_id = 1,
 446                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 447                 },
 448         },
 449         /*
 450          * XXX: Use software supervised mode, HW supervised smartidle seems to
 451          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 452          */
 453         .flags          = HWMOD_SWSUP_SIDLE,
 454 };
 455
 456 /* UART1 */
 457 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 458         .name           = "uart1",
 459         .main_clk       = "uart1_fck",
 460         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 461         .prcm           = {
 462                 .omap2 = {
 463                         .module_offs = CORE_MOD,
 464                         .prcm_reg_id = 1,
 465                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 466                         .idlest_reg_id = 1,
 467                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 468                 },
 469         },
 470         .class          = &omap2_uart_class,
 471 };
 472
 473 /* UART2 */
 474 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 475         .name           = "uart2",
 476         .main_clk       = "uart2_fck",
 477         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 478         .prcm           = {
 479                 .omap2 = {
 480                         .module_offs = CORE_MOD,
 481                         .prcm_reg_id = 1,
 482                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 483                         .idlest_reg_id = 1,
 484                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 485                 },
 486         },
 487         .class          = &omap2_uart_class,
 488 };
 489
 490 /* UART3 */
 491 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 492         .name           = "uart3",
 493         .main_clk       = "uart3_fck",
 494         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 495                                 HWMOD_SWSUP_SIDLE,
 496         .prcm           = {
 497                 .omap2 = {
 498                         .module_offs = OMAP3430_PER_MOD,
 499                         .prcm_reg_id = 1,
 500                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 501                         .idlest_reg_id = 1,
 502                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 503                 },
 504         },
 505         .class          = &omap2_uart_class,
 506 };
 507
 508 /* UART4 */
 509
 510
 511 static struct omap_hwmod omap36xx_uart4_hwmod = {
 512         .name           = "uart4",
 513         .main_clk       = "uart4_fck",
 514         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 515         .prcm           = {
 516                 .omap2 = {
 517                         .module_offs = OMAP3430_PER_MOD,
 518                         .prcm_reg_id = 1,
 519                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 520                         .idlest_reg_id = 1,
 521                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 522                 },
 523         },
 524         .class          = &omap2_uart_class,
 525 };
 526
 527
 528
 529 /*
 530  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 531  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 532  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 533  * should not be needed.  The functional clock structure of the AM35xx
 534  * UART4 is extremely unclear and opaque; it is unclear what the role
 535  * of uart1/2_fck is for the UART4.  Any clarification from either
 536  * empirical testing or the AM3505/3517 hardware designers would be
 537  * most welcome.
 538  */
 539 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 540         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 541 };
 542
 543 static struct omap_hwmod am35xx_uart4_hwmod = {
 544         .name           = "uart4",
 545         .main_clk       = "uart4_fck",
 546         .prcm           = {
 547                 .omap2 = {
 548                         .module_offs = CORE_MOD,
 549                         .prcm_reg_id = 1,
 550                         .module_bit = AM35XX_EN_UART4_SHIFT,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 553                 },
 554         },
 555         .opt_clks       = am35xx_uart4_opt_clks,
 556         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 557         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 558         .class          = &omap2_uart_class,
 559 };
 560
 561 static struct omap_hwmod_class i2c_class = {
 562         .name   = "i2c",
 563         .sysc   = &i2c_sysc,
 564         .rev    = OMAP_I2C_IP_VERSION_1,
 565         .reset  = &omap_i2c_reset,
 566 };
 567
 568 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 569         { .name = "dispc", .dma_req = 5 },
 570         { .name = "dsi1", .dma_req = 74 },
 571         { .dma_req = -1, },
 572 };
 573
 574 /* dss */
 575 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 576         /*
 577          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 578          * driver does not use these clocks.
 579          */
 580         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 581         { .role = "tv_clk", .clk = "dss_tv_fck" },
 582         /* required only on OMAP3430 */
 583         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 584 };
 585
 586 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 587         .name           = "dss_core",
 588         .class          = &omap2_dss_hwmod_class,
 589         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 590         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 591         .prcm           = {
 592                 .omap2 = {
 593                         .prcm_reg_id = 1,
 594                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 595                         .module_offs = OMAP3430_DSS_MOD,
 596                         .idlest_reg_id = 1,
 597                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 598                 },
 599         },
 600         .opt_clks       = dss_opt_clks,
 601         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 602         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 603 };
 604
 605 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 606         .name           = "dss_core",
 607         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 608         .class          = &omap2_dss_hwmod_class,
 609         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 610         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 611         .prcm           = {
 612                 .omap2 = {
 613                         .prcm_reg_id = 1,
 614                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 615                         .module_offs = OMAP3430_DSS_MOD,
 616                         .idlest_reg_id = 1,
 617                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 618                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 619                 },
 620         },
 621         .opt_clks       = dss_opt_clks,
 622         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 623 };
 624
 625 /*
 626  * 'dispc' class
 627  * display controller
 628  */
 629
 630 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 631         .rev_offs       = 0x0000,
 632         .sysc_offs      = 0x0010,
 633         .syss_offs      = 0x0014,
 634         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 635                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 636                            SYSC_HAS_ENAWAKEUP),
 637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 638                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 639         .sysc_fields    = &omap_hwmod_sysc_type1,
 640 };
 641
 642 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 643         .name   = "dispc",
 644         .sysc   = &omap3_dispc_sysc,
 645 };
 646
 647 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 648         .name           = "dss_dispc",
 649         .class          = &omap3_dispc_hwmod_class,
 650         .mpu_irqs       = omap2_dispc_irqs,
 651         .main_clk       = "dss1_alwon_fck",
 652         .prcm           = {
 653                 .omap2 = {
 654                         .prcm_reg_id = 1,
 655                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 656                         .module_offs = OMAP3430_DSS_MOD,
 657                 },
 658         },
 659         .flags          = HWMOD_NO_IDLEST,
 660         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 661 };
 662
 663 /*
 664  * 'dsi' class
 665  * display serial interface controller
 666  */
 667
 668 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
 669         .rev_offs       = 0x0000,
 670         .sysc_offs      = 0x0010,
 671         .syss_offs      = 0x0014,
 672         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 673                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 674                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 675         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 676         .sysc_fields    = &omap_hwmod_sysc_type1,
 677 };
 678
 679 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 680         .name = "dsi",
 681         .sysc   = &omap3xxx_dsi_sysc,
 682 };
 683
 684 /* dss_dsi1 */
 685 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 687 };
 688
 689 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 690         .name           = "dss_dsi1",
 691         .class          = &omap3xxx_dsi_hwmod_class,
 692         .main_clk       = "dss1_alwon_fck",
 693         .prcm           = {
 694                 .omap2 = {
 695                         .prcm_reg_id = 1,
 696                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 697                         .module_offs = OMAP3430_DSS_MOD,
 698                 },
 699         },
 700         .opt_clks       = dss_dsi1_opt_clks,
 701         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 702         .flags          = HWMOD_NO_IDLEST,
 703 };
 704
 705 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 706         { .role = "ick", .clk = "dss_ick" },
 707 };
 708
 709 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 710         .name           = "dss_rfbi",
 711         .class          = &omap2_rfbi_hwmod_class,
 712         .main_clk       = "dss1_alwon_fck",
 713         .prcm           = {
 714                 .omap2 = {
 715                         .prcm_reg_id = 1,
 716                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 717                         .module_offs = OMAP3430_DSS_MOD,
 718                 },
 719         },
 720         .opt_clks       = dss_rfbi_opt_clks,
 721         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 722         .flags          = HWMOD_NO_IDLEST,
 723 };
 724
 725 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 726         /* required only on OMAP3430 */
 727         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 728 };
 729
 730 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 731         .name           = "dss_venc",
 732         .class          = &omap2_venc_hwmod_class,
 733         .main_clk       = "dss_tv_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .prcm_reg_id = 1,
 737                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 738                         .module_offs = OMAP3430_DSS_MOD,
 739                 },
 740         },
 741         .opt_clks       = dss_venc_opt_clks,
 742         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 743         .flags          = HWMOD_NO_IDLEST,
 744 };
 745
 746 /* I2C1 */
 747 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 748         .fifo_depth     = 8, /* bytes */
 749         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 750 };
 751
 752 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 753         .name           = "i2c1",
 754         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 755         .main_clk       = "i2c1_fck",
 756         .prcm           = {
 757                 .omap2 = {
 758                         .module_offs = CORE_MOD,
 759                         .prcm_reg_id = 1,
 760                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 761                         .idlest_reg_id = 1,
 762                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 763                 },
 764         },
 765         .class          = &i2c_class,
 766         .dev_attr       = &i2c1_dev_attr,
 767 };
 768
 769 /* I2C2 */
 770 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 771         .fifo_depth     = 8, /* bytes */
 772         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 773 };
 774
 775 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 776         .name           = "i2c2",
 777         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 778         .main_clk       = "i2c2_fck",
 779         .prcm           = {
 780                 .omap2 = {
 781                         .module_offs = CORE_MOD,
 782                         .prcm_reg_id = 1,
 783                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 784                         .idlest_reg_id = 1,
 785                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 786                 },
 787         },
 788         .class          = &i2c_class,
 789         .dev_attr       = &i2c2_dev_attr,
 790 };
 791
 792 /* I2C3 */
 793 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 794         .fifo_depth     = 64, /* bytes */
 795         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 796 };
 797
 798
 799
 800 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 801         .name           = "i2c3",
 802         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 803         .main_clk       = "i2c3_fck",
 804         .prcm           = {
 805                 .omap2 = {
 806                         .module_offs = CORE_MOD,
 807                         .prcm_reg_id = 1,
 808                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 809                         .idlest_reg_id = 1,
 810                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 811                 },
 812         },
 813         .class          = &i2c_class,
 814         .dev_attr       = &i2c3_dev_attr,
 815 };
 816
 817 /*
 818  * 'gpio' class
 819  * general purpose io module
 820  */
 821
 822 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 823         .rev_offs       = 0x0000,
 824         .sysc_offs      = 0x0010,
 825         .syss_offs      = 0x0014,
 826         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 827                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 828                            SYSS_HAS_RESET_STATUS),
 829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 830         .sysc_fields    = &omap_hwmod_sysc_type1,
 831 };
 832
 833 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 834         .name = "gpio",
 835         .sysc = &omap3xxx_gpio_sysc,
 836         .rev = 1,
 837 };
 838
 839 /* gpio_dev_attr */
 840 static struct omap_gpio_dev_attr gpio_dev_attr = {
 841         .bank_width = 32,
 842         .dbck_flag = true,
 843 };
 844
 845 /* gpio1 */
 846 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 847         { .role = "dbclk", .clk = "gpio1_dbck", },
 848 };
 849
 850 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 851         .name           = "gpio1",
 852         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 853         .main_clk       = "gpio1_ick",
 854         .opt_clks       = gpio1_opt_clks,
 855         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 856         .prcm           = {
 857                 .omap2 = {
 858                         .prcm_reg_id = 1,
 859                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 860                         .module_offs = WKUP_MOD,
 861                         .idlest_reg_id = 1,
 862                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 863                 },
 864         },
 865         .class          = &omap3xxx_gpio_hwmod_class,
 866         .dev_attr       = &gpio_dev_attr,
 867 };
 868
 869 /* gpio2 */
 870 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 871         { .role = "dbclk", .clk = "gpio2_dbck", },
 872 };
 873
 874 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 875         .name           = "gpio2",
 876         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 877         .main_clk       = "gpio2_ick",
 878         .opt_clks       = gpio2_opt_clks,
 879         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 880         .prcm           = {
 881                 .omap2 = {
 882                         .prcm_reg_id = 1,
 883                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 884                         .module_offs = OMAP3430_PER_MOD,
 885                         .idlest_reg_id = 1,
 886                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 887                 },
 888         },
 889         .class          = &omap3xxx_gpio_hwmod_class,
 890         .dev_attr       = &gpio_dev_attr,
 891 };
 892
 893 /* gpio3 */
 894 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 895         { .role = "dbclk", .clk = "gpio3_dbck", },
 896 };
 897
 898 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 899         .name           = "gpio3",
 900         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 901         .main_clk       = "gpio3_ick",
 902         .opt_clks       = gpio3_opt_clks,
 903         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 904         .prcm           = {
 905                 .omap2 = {
 906                         .prcm_reg_id = 1,
 907                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 908                         .module_offs = OMAP3430_PER_MOD,
 909                         .idlest_reg_id = 1,
 910                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 911                 },
 912         },
 913         .class          = &omap3xxx_gpio_hwmod_class,
 914         .dev_attr       = &gpio_dev_attr,
 915 };
 916
 917 /* gpio4 */
 918 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 919         { .role = "dbclk", .clk = "gpio4_dbck", },
 920 };
 921
 922 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 923         .name           = "gpio4",
 924         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 925         .main_clk       = "gpio4_ick",
 926         .opt_clks       = gpio4_opt_clks,
 927         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 928         .prcm           = {
 929                 .omap2 = {
 930                         .prcm_reg_id = 1,
 931                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 932                         .module_offs = OMAP3430_PER_MOD,
 933                         .idlest_reg_id = 1,
 934                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 935                 },
 936         },
 937         .class          = &omap3xxx_gpio_hwmod_class,
 938         .dev_attr       = &gpio_dev_attr,
 939 };
 940
 941 /* gpio5 */
 942
 943 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 944         { .role = "dbclk", .clk = "gpio5_dbck", },
 945 };
 946
 947 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 948         .name           = "gpio5",
 949         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 950         .main_clk       = "gpio5_ick",
 951         .opt_clks       = gpio5_opt_clks,
 952         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 953         .prcm           = {
 954                 .omap2 = {
 955                         .prcm_reg_id = 1,
 956                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 957                         .module_offs = OMAP3430_PER_MOD,
 958                         .idlest_reg_id = 1,
 959                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 960                 },
 961         },
 962         .class          = &omap3xxx_gpio_hwmod_class,
 963         .dev_attr       = &gpio_dev_attr,
 964 };
 965
 966 /* gpio6 */
 967
 968 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 969         { .role = "dbclk", .clk = "gpio6_dbck", },
 970 };
 971
 972 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 973         .name           = "gpio6",
 974         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 975         .main_clk       = "gpio6_ick",
 976         .opt_clks       = gpio6_opt_clks,
 977         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 978         .prcm           = {
 979                 .omap2 = {
 980                         .prcm_reg_id = 1,
 981                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
 982                         .module_offs = OMAP3430_PER_MOD,
 983                         .idlest_reg_id = 1,
 984                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
 985                 },
 986         },
 987         .class          = &omap3xxx_gpio_hwmod_class,
 988         .dev_attr       = &gpio_dev_attr,
 989 };
 990
 991 /* dma attributes */
 992 static struct omap_dma_dev_attr dma_dev_attr = {
 993         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 994                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 995         .lch_count = 32,
 996 };
 997
 998 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 999         .rev_offs       = 0x0000,
1000         .sysc_offs      = 0x002c,
1001         .syss_offs      = 0x0028,
1002         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1003                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1004                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1005                            SYSS_HAS_RESET_STATUS),
1006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1007                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1008         .sysc_fields    = &omap_hwmod_sysc_type1,
1009 };
1010
1011 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1012         .name = "dma",
1013         .sysc = &omap3xxx_dma_sysc,
1014 };
1015
1016 /* dma_system */
1017 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1018         .name           = "dma",
1019         .class          = &omap3xxx_dma_hwmod_class,
1020         .mpu_irqs       = omap2_dma_system_irqs,
1021         .main_clk       = "core_l3_ick",
1022         .prcm = {
1023                 .omap2 = {
1024                         .module_offs            = CORE_MOD,
1025                         .prcm_reg_id            = 1,
1026                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1027                         .idlest_reg_id          = 1,
1028                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1029                 },
1030         },
1031         .dev_attr       = &dma_dev_attr,
1032         .flags          = HWMOD_NO_IDLEST,
1033 };
1034
1035 /*
1036  * 'mcbsp' class
1037  * multi channel buffered serial port controller
1038  */
1039
1040 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1041         .sysc_offs      = 0x008c,
1042         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1043                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1044         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1045         .sysc_fields    = &omap_hwmod_sysc_type1,
1046 };
1047
1048 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1049         .name = "mcbsp",
1050         .sysc = &omap3xxx_mcbsp_sysc,
1051         .rev  = MCBSP_CONFIG_TYPE3,
1052 };
1053
1054 /* McBSP functional clock mapping */
1055 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1056         { .role = "pad_fck", .clk = "mcbsp_clks" },
1057         { .role = "prcm_fck", .clk = "core_96m_fck" },
1058 };
1059
1060 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1061         { .role = "pad_fck", .clk = "mcbsp_clks" },
1062         { .role = "prcm_fck", .clk = "per_96m_fck" },
1063 };
1064
1065 /* mcbsp1 */
1066
1067 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1068         .name           = "mcbsp1",
1069         .class          = &omap3xxx_mcbsp_hwmod_class,
1070         .main_clk       = "mcbsp1_fck",
1071         .prcm           = {
1072                 .omap2 = {
1073                         .prcm_reg_id = 1,
1074                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1075                         .module_offs = CORE_MOD,
1076                         .idlest_reg_id = 1,
1077                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1078                 },
1079         },
1080         .opt_clks       = mcbsp15_opt_clks,
1081         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1082 };
1083
1084 /* mcbsp2 */
1085
1086 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1087         .sidetone       = "mcbsp2_sidetone",
1088 };
1089
1090 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1091         .name           = "mcbsp2",
1092         .class          = &omap3xxx_mcbsp_hwmod_class,
1093         .main_clk       = "mcbsp2_fck",
1094         .prcm           = {
1095                 .omap2 = {
1096                         .prcm_reg_id = 1,
1097                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1098                         .module_offs = OMAP3430_PER_MOD,
1099                         .idlest_reg_id = 1,
1100                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1101                 },
1102         },
1103         .opt_clks       = mcbsp234_opt_clks,
1104         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1105         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1106 };
1107
1108 /* mcbsp3 */
1109
1110 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1111         .sidetone       = "mcbsp3_sidetone",
1112 };
1113
1114 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1115         .name           = "mcbsp3",
1116         .class          = &omap3xxx_mcbsp_hwmod_class,
1117         .main_clk       = "mcbsp3_fck",
1118         .prcm           = {
1119                 .omap2 = {
1120                         .prcm_reg_id = 1,
1121                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1122                         .module_offs = OMAP3430_PER_MOD,
1123                         .idlest_reg_id = 1,
1124                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1125                 },
1126         },
1127         .opt_clks       = mcbsp234_opt_clks,
1128         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1129         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1130 };
1131
1132 /* mcbsp4 */
1133
1134
1135 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1136         .name           = "mcbsp4",
1137         .class          = &omap3xxx_mcbsp_hwmod_class,
1138         .main_clk       = "mcbsp4_fck",
1139         .prcm           = {
1140                 .omap2 = {
1141                         .prcm_reg_id = 1,
1142                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1143                         .module_offs = OMAP3430_PER_MOD,
1144                         .idlest_reg_id = 1,
1145                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1146                 },
1147         },
1148         .opt_clks       = mcbsp234_opt_clks,
1149         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1150 };
1151
1152 /* mcbsp5 */
1153
1154
1155 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1156         .name           = "mcbsp5",
1157         .class          = &omap3xxx_mcbsp_hwmod_class,
1158         .main_clk       = "mcbsp5_fck",
1159         .prcm           = {
1160                 .omap2 = {
1161                         .prcm_reg_id = 1,
1162                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1163                         .module_offs = CORE_MOD,
1164                         .idlest_reg_id = 1,
1165                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1166                 },
1167         },
1168         .opt_clks       = mcbsp15_opt_clks,
1169         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1170 };
1171
1172 /* 'mcbsp sidetone' class */
1173 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1174         .sysc_offs      = 0x0010,
1175         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1176         .sysc_fields    = &omap_hwmod_sysc_type1,
1177 };
1178
1179 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1180         .name = "mcbsp_sidetone",
1181         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1182 };
1183
1184 /* mcbsp2_sidetone */
1185
1186 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1187         .name           = "mcbsp2_sidetone",
1188         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1189         .main_clk       = "mcbsp2_ick",
1190         .flags          = HWMOD_NO_IDLEST,
1191 };
1192
1193 /* mcbsp3_sidetone */
1194
1195 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1196         .name           = "mcbsp3_sidetone",
1197         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1198         .main_clk       = "mcbsp3_ick",
1199         .flags          = HWMOD_NO_IDLEST,
1200 };
1201
1202 /* SR common */
1203 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1204         .clkact_shift   = 20,
1205 };
1206
1207 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1208         .sysc_offs      = 0x24,
1209         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1210         .sysc_fields    = &omap34xx_sr_sysc_fields,
1211 };
1212
1213 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1214         .name = "smartreflex",
1215         .sysc = &omap34xx_sr_sysc,
1216         .rev  = 1,
1217 };
1218
1219 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1220         .sidle_shift    = 24,
1221         .enwkup_shift   = 26,
1222 };
1223
1224 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1225         .sysc_offs      = 0x38,
1226         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1227         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1228                         SYSC_NO_CACHE),
1229         .sysc_fields    = &omap36xx_sr_sysc_fields,
1230 };
1231
1232 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1233         .name = "smartreflex",
1234         .sysc = &omap36xx_sr_sysc,
1235         .rev  = 2,
1236 };
1237
1238 /* SR1 */
1239 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1240         .sensor_voltdm_name   = "mpu_iva",
1241 };
1242
1243
1244 static struct omap_hwmod omap34xx_sr1_hwmod = {
1245         .name           = "smartreflex_mpu_iva",
1246         .class          = &omap34xx_smartreflex_hwmod_class,
1247         .main_clk       = "sr1_fck",
1248         .prcm           = {
1249                 .omap2 = {
1250                         .prcm_reg_id = 1,
1251                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1252                         .module_offs = WKUP_MOD,
1253                         .idlest_reg_id = 1,
1254                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1255                 },
1256         },
1257         .dev_attr       = &sr1_dev_attr,
1258         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1259 };
1260
1261 static struct omap_hwmod omap36xx_sr1_hwmod = {
1262         .name           = "smartreflex_mpu_iva",
1263         .class          = &omap36xx_smartreflex_hwmod_class,
1264         .main_clk       = "sr1_fck",
1265         .prcm           = {
1266                 .omap2 = {
1267                         .prcm_reg_id = 1,
1268                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1269                         .module_offs = WKUP_MOD,
1270                         .idlest_reg_id = 1,
1271                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1272                 },
1273         },
1274         .dev_attr       = &sr1_dev_attr,
1275 };
1276
1277 /* SR2 */
1278 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1279         .sensor_voltdm_name     = "core",
1280 };
1281
1282
1283 static struct omap_hwmod omap34xx_sr2_hwmod = {
1284         .name           = "smartreflex_core",
1285         .class          = &omap34xx_smartreflex_hwmod_class,
1286         .main_clk       = "sr2_fck",
1287         .prcm           = {
1288                 .omap2 = {
1289                         .prcm_reg_id = 1,
1290                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1291                         .module_offs = WKUP_MOD,
1292                         .idlest_reg_id = 1,
1293                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1294                 },
1295         },
1296         .dev_attr       = &sr2_dev_attr,
1297         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1298 };
1299
1300 static struct omap_hwmod omap36xx_sr2_hwmod = {
1301         .name           = "smartreflex_core",
1302         .class          = &omap36xx_smartreflex_hwmod_class,
1303         .main_clk       = "sr2_fck",
1304         .prcm           = {
1305                 .omap2 = {
1306                         .prcm_reg_id = 1,
1307                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1308                         .module_offs = WKUP_MOD,
1309                         .idlest_reg_id = 1,
1310                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1311                 },
1312         },
1313         .dev_attr       = &sr2_dev_attr,
1314 };
1315
1316 /*
1317  * 'mailbox' class
1318  * mailbox module allowing communication between the on-chip processors
1319  * using a queued mailbox-interrupt mechanism.
1320  */
1321
1322 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1323         .rev_offs       = 0x000,
1324         .sysc_offs      = 0x010,
1325         .syss_offs      = 0x014,
1326         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1327                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1328         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1329         .sysc_fields    = &omap_hwmod_sysc_type1,
1330 };
1331
1332 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1333         .name = "mailbox",
1334         .sysc = &omap3xxx_mailbox_sysc,
1335 };
1336
1337 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1338         .name           = "mailbox",
1339         .class          = &omap3xxx_mailbox_hwmod_class,
1340         .main_clk       = "mailboxes_ick",
1341         .prcm           = {
1342                 .omap2 = {
1343                         .prcm_reg_id = 1,
1344                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1345                         .module_offs = CORE_MOD,
1346                         .idlest_reg_id = 1,
1347                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1348                 },
1349         },
1350 };
1351
1352 /*
1353  * 'mcspi' class
1354  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1355  * bus
1356  */
1357
1358 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1359         .rev_offs       = 0x0000,
1360         .sysc_offs      = 0x0010,
1361         .syss_offs      = 0x0014,
1362         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1363                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1364                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1365         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1366         .sysc_fields    = &omap_hwmod_sysc_type1,
1367 };
1368
1369 static struct omap_hwmod_class omap34xx_mcspi_class = {
1370         .name = "mcspi",
1371         .sysc = &omap34xx_mcspi_sysc,
1372         .rev = OMAP3_MCSPI_REV,
1373 };
1374
1375 /* mcspi1 */
1376 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1377         .num_chipselect = 4,
1378 };
1379
1380 static struct omap_hwmod omap34xx_mcspi1 = {
1381         .name           = "mcspi1",
1382         .main_clk       = "mcspi1_fck",
1383         .prcm           = {
1384                 .omap2 = {
1385                         .module_offs = CORE_MOD,
1386                         .prcm_reg_id = 1,
1387                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1388                         .idlest_reg_id = 1,
1389                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1390                 },
1391         },
1392         .class          = &omap34xx_mcspi_class,
1393         .dev_attr       = &omap_mcspi1_dev_attr,
1394 };
1395
1396 /* mcspi2 */
1397 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1398         .num_chipselect = 2,
1399 };
1400
1401 static struct omap_hwmod omap34xx_mcspi2 = {
1402         .name           = "mcspi2",
1403         .main_clk       = "mcspi2_fck",
1404         .prcm           = {
1405                 .omap2 = {
1406                         .module_offs = CORE_MOD,
1407                         .prcm_reg_id = 1,
1408                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1409                         .idlest_reg_id = 1,
1410                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1411                 },
1412         },
1413         .class          = &omap34xx_mcspi_class,
1414         .dev_attr       = &omap_mcspi2_dev_attr,
1415 };
1416
1417 /* mcspi3 */
1418
1419
1420 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1421         .num_chipselect = 2,
1422 };
1423
1424 static struct omap_hwmod omap34xx_mcspi3 = {
1425         .name           = "mcspi3",
1426         .main_clk       = "mcspi3_fck",
1427         .prcm           = {
1428                 .omap2 = {
1429                         .module_offs = CORE_MOD,
1430                         .prcm_reg_id = 1,
1431                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1432                         .idlest_reg_id = 1,
1433                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1434                 },
1435         },
1436         .class          = &omap34xx_mcspi_class,
1437         .dev_attr       = &omap_mcspi3_dev_attr,
1438 };
1439
1440 /* mcspi4 */
1441
1442
1443 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1444         .num_chipselect = 1,
1445 };
1446
1447 static struct omap_hwmod omap34xx_mcspi4 = {
1448         .name           = "mcspi4",
1449         .main_clk       = "mcspi4_fck",
1450         .prcm           = {
1451                 .omap2 = {
1452                         .module_offs = CORE_MOD,
1453                         .prcm_reg_id = 1,
1454                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1455                         .idlest_reg_id = 1,
1456                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1457                 },
1458         },
1459         .class          = &omap34xx_mcspi_class,
1460         .dev_attr       = &omap_mcspi4_dev_attr,
1461 };
1462
1463 /* usbhsotg */
1464 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1465         .rev_offs       = 0x0400,
1466         .sysc_offs      = 0x0404,
1467         .syss_offs      = 0x0408,
1468         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1469                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1470                           SYSC_HAS_AUTOIDLE),
1471         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1473         .sysc_fields    = &omap_hwmod_sysc_type1,
1474 };
1475
1476 static struct omap_hwmod_class usbotg_class = {
1477         .name = "usbotg",
1478         .sysc = &omap3xxx_usbhsotg_sysc,
1479 };
1480
1481 /* usb_otg_hs */
1482
1483 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1484         .name           = "usb_otg_hs",
1485         .main_clk       = "hsotgusb_ick",
1486         .prcm           = {
1487                 .omap2 = {
1488                         .prcm_reg_id = 1,
1489                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1490                         .module_offs = CORE_MOD,
1491                         .idlest_reg_id = 1,
1492                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1493                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
1494                 },
1495         },
1496         .class          = &usbotg_class,
1497
1498         /*
1499          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1500          * broken when autoidle is enabled
1501          * workaround is to disable the autoidle bit at module level.
1502          *
1503          * Enabling the device in any other MIDLEMODE setting but force-idle
1504          * causes core_pwrdm not enter idle states at least on OMAP3630.
1505          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1506          * signal when MIDLEMODE is set to force-idle.
1507          */
1508         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1509                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1510 };
1511
1512 /* usb_otg_hs */
1513
1514 static struct omap_hwmod_class am35xx_usbotg_class = {
1515         .name = "am35xx_usbotg",
1516 };
1517
1518 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1519         .name           = "am35x_otg_hs",
1520         .main_clk       = "hsotgusb_fck",
1521         .class          = &am35xx_usbotg_class,
1522         .flags          = HWMOD_NO_IDLEST,
1523 };
1524
1525 /* MMC/SD/SDIO common */
1526 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1527         .rev_offs       = 0x1fc,
1528         .sysc_offs      = 0x10,
1529         .syss_offs      = 0x14,
1530         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1531                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1532                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1533         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1534         .sysc_fields    = &omap_hwmod_sysc_type1,
1535 };
1536
1537 static struct omap_hwmod_class omap34xx_mmc_class = {
1538         .name = "mmc",
1539         .sysc = &omap34xx_mmc_sysc,
1540 };
1541
1542 /* MMC/SD/SDIO1 */
1543
1544
1545
1546 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1547         { .role = "dbck", .clk = "omap_32k_fck", },
1548 };
1549
1550 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1551         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1552 };
1553
1554 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1555 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1556         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1557                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1558 };
1559
1560 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1561         .name           = "mmc1",
1562         .opt_clks       = omap34xx_mmc1_opt_clks,
1563         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1564         .main_clk       = "mmchs1_fck",
1565         .prcm           = {
1566                 .omap2 = {
1567                         .module_offs = CORE_MOD,
1568                         .prcm_reg_id = 1,
1569                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1570                         .idlest_reg_id = 1,
1571                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1572                 },
1573         },
1574         .dev_attr       = &mmc1_pre_es3_dev_attr,
1575         .class          = &omap34xx_mmc_class,
1576 };
1577
1578 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1579         .name           = "mmc1",
1580         .opt_clks       = omap34xx_mmc1_opt_clks,
1581         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1582         .main_clk       = "mmchs1_fck",
1583         .prcm           = {
1584                 .omap2 = {
1585                         .module_offs = CORE_MOD,
1586                         .prcm_reg_id = 1,
1587                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1588                         .idlest_reg_id = 1,
1589                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1590                 },
1591         },
1592         .dev_attr       = &mmc1_dev_attr,
1593         .class          = &omap34xx_mmc_class,
1594 };
1595
1596 /* MMC/SD/SDIO2 */
1597
1598
1599
1600 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1601         { .role = "dbck", .clk = "omap_32k_fck", },
1602 };
1603
1604 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1605 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1606         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1607 };
1608
1609 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1610         .name           = "mmc2",
1611         .opt_clks       = omap34xx_mmc2_opt_clks,
1612         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1613         .main_clk       = "mmchs2_fck",
1614         .prcm           = {
1615                 .omap2 = {
1616                         .module_offs = CORE_MOD,
1617                         .prcm_reg_id = 1,
1618                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1619                         .idlest_reg_id = 1,
1620                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1621                 },
1622         },
1623         .dev_attr       = &mmc2_pre_es3_dev_attr,
1624         .class          = &omap34xx_mmc_class,
1625 };
1626
1627 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1628         .name           = "mmc2",
1629         .opt_clks       = omap34xx_mmc2_opt_clks,
1630         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1631         .main_clk       = "mmchs2_fck",
1632         .prcm           = {
1633                 .omap2 = {
1634                         .module_offs = CORE_MOD,
1635                         .prcm_reg_id = 1,
1636                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1637                         .idlest_reg_id = 1,
1638                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1639                 },
1640         },
1641         .class          = &omap34xx_mmc_class,
1642 };
1643
1644 /* MMC/SD/SDIO3 */
1645
1646
1647
1648 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1649         { .role = "dbck", .clk = "omap_32k_fck", },
1650 };
1651
1652 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1653         .name           = "mmc3",
1654         .opt_clks       = omap34xx_mmc3_opt_clks,
1655         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1656         .main_clk       = "mmchs3_fck",
1657         .prcm           = {
1658                 .omap2 = {
1659                         .prcm_reg_id = 1,
1660                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1661                         .idlest_reg_id = 1,
1662                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1663                 },
1664         },
1665         .class          = &omap34xx_mmc_class,
1666 };
1667
1668 /*
1669  * 'usb_host_hs' class
1670  * high-speed multi-port usb host controller
1671  */
1672
1673 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1674         .rev_offs       = 0x0000,
1675         .sysc_offs      = 0x0010,
1676         .syss_offs      = 0x0014,
1677         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1678                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1679                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1680                            SYSS_HAS_RESET_STATUS),
1681         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1682                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1683         .sysc_fields    = &omap_hwmod_sysc_type1,
1684 };
1685
1686 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1687         .name = "usb_host_hs",
1688         .sysc = &omap3xxx_usb_host_hs_sysc,
1689 };
1690
1691
1692 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1693         .name           = "usb_host_hs",
1694         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1695         .clkdm_name     = "usbhost_clkdm",
1696         .main_clk       = "usbhost_48m_fck",
1697         .prcm = {
1698                 .omap2 = {
1699                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1700                         .prcm_reg_id = 1,
1701                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1702                         .idlest_reg_id = 1,
1703                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1704                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1705                 },
1706         },
1707
1708         /*
1709          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1710          * id: i660
1711          *
1712          * Description:
1713          * In the following configuration :
1714          * - USBHOST module is set to smart-idle mode
1715          * - PRCM asserts idle_req to the USBHOST module ( This typically
1716          *   happens when the system is going to a low power mode : all ports
1717          *   have been suspended, the master part of the USBHOST module has
1718          *   entered the standby state, and SW has cut the functional clocks)
1719          * - an USBHOST interrupt occurs before the module is able to answer
1720          *   idle_ack, typically a remote wakeup IRQ.
1721          * Then the USB HOST module will enter a deadlock situation where it
1722          * is no more accessible nor functional.
1723          *
1724          * Workaround:
1725          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1726          */
1727
1728         /*
1729          * Errata: USB host EHCI may stall when entering smart-standby mode
1730          * Id: i571
1731          *
1732          * Description:
1733          * When the USBHOST module is set to smart-standby mode, and when it is
1734          * ready to enter the standby state (i.e. all ports are suspended and
1735          * all attached devices are in suspend mode), then it can wrongly assert
1736          * the Mstandby signal too early while there are still some residual OCP
1737          * transactions ongoing. If this condition occurs, the internal state
1738          * machine may go to an undefined state and the USB link may be stuck
1739          * upon the next resume.
1740          *
1741          * Workaround:
1742          * Don't use smart standby; use only force standby,
1743          * hence HWMOD_SWSUP_MSTANDBY
1744          */
1745
1746         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1747 };
1748
1749 /*
1750  * 'usb_tll_hs' class
1751  * usb_tll_hs module is the adapter on the usb_host_hs ports
1752  */
1753 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1754         .rev_offs       = 0x0000,
1755         .sysc_offs      = 0x0010,
1756         .syss_offs      = 0x0014,
1757         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1758                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1759                            SYSC_HAS_AUTOIDLE),
1760         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1761         .sysc_fields    = &omap_hwmod_sysc_type1,
1762 };
1763
1764 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1765         .name = "usb_tll_hs",
1766         .sysc = &omap3xxx_usb_tll_hs_sysc,
1767 };
1768
1769
1770 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1771         .name           = "usb_tll_hs",
1772         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1773         .clkdm_name     = "core_l4_clkdm",
1774         .main_clk       = "usbtll_fck",
1775         .prcm = {
1776                 .omap2 = {
1777                         .module_offs = CORE_MOD,
1778                         .prcm_reg_id = 3,
1779                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1780                         .idlest_reg_id = 3,
1781                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1782                 },
1783         },
1784 };
1785
1786 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1787         .name           = "hdq1w",
1788         .main_clk       = "hdq_fck",
1789         .prcm           = {
1790                 .omap2 = {
1791                         .module_offs = CORE_MOD,
1792                         .prcm_reg_id = 1,
1793                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
1794                         .idlest_reg_id = 1,
1795                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1796                 },
1797         },
1798         .class          = &omap2_hdq1w_class,
1799 };
1800
1801 /* SAD2D */
1802 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1803         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1804         { .name = "rst_modem_sw", .rst_shift = 1 },
1805 };
1806
1807 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1808         .name                   = "sad2d",
1809 };
1810
1811 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1812         .name           = "sad2d",
1813         .rst_lines      = omap3xxx_sad2d_resets,
1814         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
1815         .main_clk       = "sad2d_ick",
1816         .prcm           = {
1817                 .omap2 = {
1818                         .module_offs = CORE_MOD,
1819                         .prcm_reg_id = 1,
1820                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
1821                         .idlest_reg_id = 1,
1822                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1823                 },
1824         },
1825         .class          = &omap3xxx_sad2d_class,
1826 };
1827
1828 /*
1829  * '32K sync counter' class
1830  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1831  */
1832 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1833         .rev_offs       = 0x0000,
1834         .sysc_offs      = 0x0004,
1835         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1836         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
1837         .sysc_fields    = &omap_hwmod_sysc_type1,
1838 };
1839
1840 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1841         .name   = "counter",
1842         .sysc   = &omap3xxx_counter_sysc,
1843 };
1844
1845 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1846         .name           = "counter_32k",
1847         .class          = &omap3xxx_counter_hwmod_class,
1848         .clkdm_name     = "wkup_clkdm",
1849         .flags          = HWMOD_SWSUP_SIDLE,
1850         .main_clk       = "wkup_32k_fck",
1851         .prcm           = {
1852                 .omap2  = {
1853                         .module_offs = WKUP_MOD,
1854                         .prcm_reg_id = 1,
1855                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
1856                         .idlest_reg_id = 1,
1857                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1858                 },
1859         },
1860 };
1861
1862 /*
1863  * 'gpmc' class
1864  * general purpose memory controller
1865  */
1866
1867 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1868         .rev_offs       = 0x0000,
1869         .sysc_offs      = 0x0010,
1870         .syss_offs      = 0x0014,
1871         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1872                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1873         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1874         .sysc_fields    = &omap_hwmod_sysc_type1,
1875 };
1876
1877 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1878         .name   = "gpmc",
1879         .sysc   = &omap3xxx_gpmc_sysc,
1880 };
1881
1882 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1883         .name           = "gpmc",
1884         .class          = &omap3xxx_gpmc_hwmod_class,
1885         .clkdm_name     = "core_l3_clkdm",
1886         .main_clk       = "gpmc_fck",
1887         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1888         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1889 };
1890
1891 /*
1892  * interfaces
1893  */
1894
1895 /* L3 -> L4_CORE interface */
1896 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1897         .master = &omap3xxx_l3_main_hwmod,
1898         .slave  = &omap3xxx_l4_core_hwmod,
1899         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1900 };
1901
1902 /* L3 -> L4_PER interface */
1903 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1904         .master = &omap3xxx_l3_main_hwmod,
1905         .slave  = &omap3xxx_l4_per_hwmod,
1906         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1907 };
1908
1909
1910 /* MPU -> L3 interface */
1911 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1912         .master   = &omap3xxx_mpu_hwmod,
1913         .slave    = &omap3xxx_l3_main_hwmod,
1914         .user   = OCP_USER_MPU,
1915 };
1916
1917
1918 /* l3 -> debugss */
1919 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1920         .master         = &omap3xxx_l3_main_hwmod,
1921         .slave          = &omap3xxx_debugss_hwmod,
1922         .user           = OCP_USER_MPU,
1923 };
1924
1925 /* DSS -> l3 */
1926 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1927         .master         = &omap3430es1_dss_core_hwmod,
1928         .slave          = &omap3xxx_l3_main_hwmod,
1929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1930 };
1931
1932 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1933         .master         = &omap3xxx_dss_core_hwmod,
1934         .slave          = &omap3xxx_l3_main_hwmod,
1935         .fw = {
1936                 .omap2 = {
1937                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1938                         .flags  = OMAP_FIREWALL_L3,
1939                 },
1940         },
1941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1942 };
1943
1944 /* l3_core -> usbhsotg interface */
1945 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1946         .master         = &omap3xxx_usbhsotg_hwmod,
1947         .slave          = &omap3xxx_l3_main_hwmod,
1948         .clk            = "core_l3_ick",
1949         .user           = OCP_USER_MPU,
1950 };
1951
1952 /* l3_core -> am35xx_usbhsotg interface */
1953 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1954         .master         = &am35xx_usbhsotg_hwmod,
1955         .slave          = &omap3xxx_l3_main_hwmod,
1956         .clk            = "hsotgusb_ick",
1957         .user           = OCP_USER_MPU,
1958 };
1959
1960 /* l3_core -> sad2d interface */
1961 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1962         .master         = &omap3xxx_sad2d_hwmod,
1963         .slave          = &omap3xxx_l3_main_hwmod,
1964         .clk            = "core_l3_ick",
1965         .user           = OCP_USER_MPU,
1966 };
1967
1968 /* L4_CORE -> L4_WKUP interface */
1969 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1970         .master = &omap3xxx_l4_core_hwmod,
1971         .slave  = &omap3xxx_l4_wkup_hwmod,
1972         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1973 };
1974
1975 /* L4 CORE -> MMC1 interface */
1976 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1977         .master         = &omap3xxx_l4_core_hwmod,
1978         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
1979         .clk            = "mmchs1_ick",
1980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1981         .flags          = OMAP_FIREWALL_L4,
1982 };
1983
1984 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1985         .master         = &omap3xxx_l4_core_hwmod,
1986         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
1987         .clk            = "mmchs1_ick",
1988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1989         .flags          = OMAP_FIREWALL_L4,
1990 };
1991
1992 /* L4 CORE -> MMC2 interface */
1993 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1994         .master         = &omap3xxx_l4_core_hwmod,
1995         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
1996         .clk            = "mmchs2_ick",
1997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1998         .flags          = OMAP_FIREWALL_L4,
1999 };
2000
2001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2002         .master         = &omap3xxx_l4_core_hwmod,
2003         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2004         .clk            = "mmchs2_ick",
2005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2006         .flags          = OMAP_FIREWALL_L4,
2007 };
2008
2009 /* L4 CORE -> MMC3 interface */
2010
2011 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2012         .master         = &omap3xxx_l4_core_hwmod,
2013         .slave          = &omap3xxx_mmc3_hwmod,
2014         .clk            = "mmchs3_ick",
2015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2016         .flags          = OMAP_FIREWALL_L4,
2017 };
2018
2019 /* L4 CORE -> UART1 interface */
2020
2021 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2022         .master         = &omap3xxx_l4_core_hwmod,
2023         .slave          = &omap3xxx_uart1_hwmod,
2024         .clk            = "uart1_ick",
2025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2026 };
2027
2028 /* L4 CORE -> UART2 interface */
2029
2030 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2031         .master         = &omap3xxx_l4_core_hwmod,
2032         .slave          = &omap3xxx_uart2_hwmod,
2033         .clk            = "uart2_ick",
2034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036
2037 /* L4 PER -> UART3 interface */
2038
2039 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2040         .master         = &omap3xxx_l4_per_hwmod,
2041         .slave          = &omap3xxx_uart3_hwmod,
2042         .clk            = "uart3_ick",
2043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2044 };
2045
2046 /* L4 PER -> UART4 interface */
2047
2048 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2049         .master         = &omap3xxx_l4_per_hwmod,
2050         .slave          = &omap36xx_uart4_hwmod,
2051         .clk            = "uart4_ick",
2052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2053 };
2054
2055 /* AM35xx: L4 CORE -> UART4 interface */
2056
2057 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2058         .master         = &omap3xxx_l4_core_hwmod,
2059         .slave          = &am35xx_uart4_hwmod,
2060         .clk            = "uart4_ick",
2061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2062 };
2063
2064 /* L4 CORE -> I2C1 interface */
2065 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2066         .master         = &omap3xxx_l4_core_hwmod,
2067         .slave          = &omap3xxx_i2c1_hwmod,
2068         .clk            = "i2c1_ick",
2069         .fw = {
2070                 .omap2 = {
2071                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2072                         .l4_prot_group = 7,
2073                         .flags  = OMAP_FIREWALL_L4,
2074                 },
2075         },
2076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2077 };
2078
2079 /* L4 CORE -> I2C2 interface */
2080 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2081         .master         = &omap3xxx_l4_core_hwmod,
2082         .slave          = &omap3xxx_i2c2_hwmod,
2083         .clk            = "i2c2_ick",
2084         .fw = {
2085                 .omap2 = {
2086                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2087                         .l4_prot_group = 7,
2088                         .flags = OMAP_FIREWALL_L4,
2089                 },
2090         },
2091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2092 };
2093
2094 /* L4 CORE -> I2C3 interface */
2095
2096 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2097         .master         = &omap3xxx_l4_core_hwmod,
2098         .slave          = &omap3xxx_i2c3_hwmod,
2099         .clk            = "i2c3_ick",
2100         .fw = {
2101                 .omap2 = {
2102                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2103                         .l4_prot_group = 7,
2104                         .flags = OMAP_FIREWALL_L4,
2105                 },
2106         },
2107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2108 };
2109
2110 /* L4 CORE -> SR1 interface */
2111 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2112         {
2113                 .pa_start       = OMAP34XX_SR1_BASE,
2114                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2115                 .flags          = ADDR_TYPE_RT,
2116         },
2117         { },
2118 };
2119
2120 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2121         .master         = &omap3xxx_l4_core_hwmod,
2122         .slave          = &omap34xx_sr1_hwmod,
2123         .clk            = "sr_l4_ick",
2124         .addr           = omap3_sr1_addr_space,
2125         .user           = OCP_USER_MPU,
2126 };
2127
2128 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2129         .master         = &omap3xxx_l4_core_hwmod,
2130         .slave          = &omap36xx_sr1_hwmod,
2131         .clk            = "sr_l4_ick",
2132         .addr           = omap3_sr1_addr_space,
2133         .user           = OCP_USER_MPU,
2134 };
2135
2136 /* L4 CORE -> SR1 interface */
2137 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2138         {
2139                 .pa_start       = OMAP34XX_SR2_BASE,
2140                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2141                 .flags          = ADDR_TYPE_RT,
2142         },
2143         { },
2144 };
2145
2146 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2147         .master         = &omap3xxx_l4_core_hwmod,
2148         .slave          = &omap34xx_sr2_hwmod,
2149         .clk            = "sr_l4_ick",
2150         .addr           = omap3_sr2_addr_space,
2151         .user           = OCP_USER_MPU,
2152 };
2153
2154 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2155         .master         = &omap3xxx_l4_core_hwmod,
2156         .slave          = &omap36xx_sr2_hwmod,
2157         .clk            = "sr_l4_ick",
2158         .addr           = omap3_sr2_addr_space,
2159         .user           = OCP_USER_MPU,
2160 };
2161
2162
2163 /* l4_core -> usbhsotg  */
2164 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2165         .master         = &omap3xxx_l4_core_hwmod,
2166         .slave          = &omap3xxx_usbhsotg_hwmod,
2167         .clk            = "l4_ick",
2168         .user           = OCP_USER_MPU,
2169 };
2170
2171
2172 /* l4_core -> usbhsotg  */
2173 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2174         .master         = &omap3xxx_l4_core_hwmod,
2175         .slave          = &am35xx_usbhsotg_hwmod,
2176         .clk            = "hsotgusb_ick",
2177         .user           = OCP_USER_MPU,
2178 };
2179
2180 /* L4_WKUP -> L4_SEC interface */
2181 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2182         .master = &omap3xxx_l4_wkup_hwmod,
2183         .slave  = &omap3xxx_l4_sec_hwmod,
2184         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2185 };
2186
2187 /* IVA2 <- L3 interface */
2188 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2189         .master         = &omap3xxx_l3_main_hwmod,
2190         .slave          = &omap3xxx_iva_hwmod,
2191         .clk            = "core_l3_ick",
2192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2193 };
2194
2195
2196 /* l4_wkup -> timer1 */
2197 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2198         .master         = &omap3xxx_l4_wkup_hwmod,
2199         .slave          = &omap3xxx_timer1_hwmod,
2200         .clk            = "gpt1_ick",
2201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2202 };
2203
2204
2205 /* l4_per -> timer2 */
2206 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2207         .master         = &omap3xxx_l4_per_hwmod,
2208         .slave          = &omap3xxx_timer2_hwmod,
2209         .clk            = "gpt2_ick",
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213
2214 /* l4_per -> timer3 */
2215 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2216         .master         = &omap3xxx_l4_per_hwmod,
2217         .slave          = &omap3xxx_timer3_hwmod,
2218         .clk            = "gpt3_ick",
2219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2220 };
2221
2222
2223 /* l4_per -> timer4 */
2224 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2225         .master         = &omap3xxx_l4_per_hwmod,
2226         .slave          = &omap3xxx_timer4_hwmod,
2227         .clk            = "gpt4_ick",
2228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2229 };
2230
2231
2232 /* l4_per -> timer5 */
2233 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2234         .master         = &omap3xxx_l4_per_hwmod,
2235         .slave          = &omap3xxx_timer5_hwmod,
2236         .clk            = "gpt5_ick",
2237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240
2241 /* l4_per -> timer6 */
2242 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2243         .master         = &omap3xxx_l4_per_hwmod,
2244         .slave          = &omap3xxx_timer6_hwmod,
2245         .clk            = "gpt6_ick",
2246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248
2249
2250 /* l4_per -> timer7 */
2251 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2252         .master         = &omap3xxx_l4_per_hwmod,
2253         .slave          = &omap3xxx_timer7_hwmod,
2254         .clk            = "gpt7_ick",
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258
2259 /* l4_per -> timer8 */
2260 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2261         .master         = &omap3xxx_l4_per_hwmod,
2262         .slave          = &omap3xxx_timer8_hwmod,
2263         .clk            = "gpt8_ick",
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266
2267
2268 /* l4_per -> timer9 */
2269 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2270         .master         = &omap3xxx_l4_per_hwmod,
2271         .slave          = &omap3xxx_timer9_hwmod,
2272         .clk            = "gpt9_ick",
2273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2274 };
2275
2276 /* l4_core -> timer10 */
2277 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2278         .master         = &omap3xxx_l4_core_hwmod,
2279         .slave          = &omap3xxx_timer10_hwmod,
2280         .clk            = "gpt10_ick",
2281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2282 };
2283
2284 /* l4_core -> timer11 */
2285 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2286         .master         = &omap3xxx_l4_core_hwmod,
2287         .slave          = &omap3xxx_timer11_hwmod,
2288         .clk            = "gpt11_ick",
2289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2290 };
2291
2292
2293 /* l4_core -> timer12 */
2294 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2295         .master         = &omap3xxx_l4_sec_hwmod,
2296         .slave          = &omap3xxx_timer12_hwmod,
2297         .clk            = "gpt12_ick",
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* l4_wkup -> wd_timer2 */
2302
2303 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2304         .master         = &omap3xxx_l4_wkup_hwmod,
2305         .slave          = &omap3xxx_wd_timer2_hwmod,
2306         .clk            = "wdt2_ick",
2307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2308 };
2309
2310 /* l4_core -> dss */
2311 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2312         .master         = &omap3xxx_l4_core_hwmod,
2313         .slave          = &omap3430es1_dss_core_hwmod,
2314         .clk            = "dss_ick",
2315         .fw = {
2316                 .omap2 = {
2317                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2318                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2319                         .flags  = OMAP_FIREWALL_L4,
2320                 },
2321         },
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2326         .master         = &omap3xxx_l4_core_hwmod,
2327         .slave          = &omap3xxx_dss_core_hwmod,
2328         .clk            = "dss_ick",
2329         .fw = {
2330                 .omap2 = {
2331                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2332                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2333                         .flags  = OMAP_FIREWALL_L4,
2334                 },
2335         },
2336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2337 };
2338
2339 /* l4_core -> dss_dispc */
2340 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2341         .master         = &omap3xxx_l4_core_hwmod,
2342         .slave          = &omap3xxx_dss_dispc_hwmod,
2343         .clk            = "dss_ick",
2344         .fw = {
2345                 .omap2 = {
2346                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2347                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2348                         .flags  = OMAP_FIREWALL_L4,
2349                 },
2350         },
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* l4_core -> dss_dsi1 */
2355 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2356         .master         = &omap3xxx_l4_core_hwmod,
2357         .slave          = &omap3xxx_dss_dsi1_hwmod,
2358         .clk            = "dss_ick",
2359         .fw = {
2360                 .omap2 = {
2361                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2362                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2363                         .flags  = OMAP_FIREWALL_L4,
2364                 },
2365         },
2366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2367 };
2368
2369 /* l4_core -> dss_rfbi */
2370 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2371         .master         = &omap3xxx_l4_core_hwmod,
2372         .slave          = &omap3xxx_dss_rfbi_hwmod,
2373         .clk            = "dss_ick",
2374         .fw = {
2375                 .omap2 = {
2376                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2377                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2378                         .flags  = OMAP_FIREWALL_L4,
2379                 },
2380         },
2381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* l4_core -> dss_venc */
2385 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2386         .master         = &omap3xxx_l4_core_hwmod,
2387         .slave          = &omap3xxx_dss_venc_hwmod,
2388         .clk            = "dss_ick",
2389         .fw = {
2390                 .omap2 = {
2391                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2392                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2393                         .flags  = OMAP_FIREWALL_L4,
2394                 },
2395         },
2396         .flags          = OCPIF_SWSUP_IDLE,
2397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* l4_wkup -> gpio1 */
2401
2402 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2403         .master         = &omap3xxx_l4_wkup_hwmod,
2404         .slave          = &omap3xxx_gpio1_hwmod,
2405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2406 };
2407
2408 /* l4_per -> gpio2 */
2409
2410 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2411         .master         = &omap3xxx_l4_per_hwmod,
2412         .slave          = &omap3xxx_gpio2_hwmod,
2413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2414 };
2415
2416 /* l4_per -> gpio3 */
2417
2418 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2419         .master         = &omap3xxx_l4_per_hwmod,
2420         .slave          = &omap3xxx_gpio3_hwmod,
2421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2422 };
2423
2424 /*
2425  * 'mmu' class
2426  * The memory management unit performs virtual to physical address translation
2427  * for its requestors.
2428  */
2429
2430 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2431         .rev_offs       = 0x000,
2432         .sysc_offs      = 0x010,
2433         .syss_offs      = 0x014,
2434         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2435                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2436         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2437         .sysc_fields    = &omap_hwmod_sysc_type1,
2438 };
2439
2440 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2441         .name = "mmu",
2442         .sysc = &mmu_sysc,
2443 };
2444
2445 /* mmu isp */
2446 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2447
2448 /* l4_core -> mmu isp */
2449 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2450         .master         = &omap3xxx_l4_core_hwmod,
2451         .slave          = &omap3xxx_mmu_isp_hwmod,
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2456         .name           = "mmu_isp",
2457         .class          = &omap3xxx_mmu_hwmod_class,
2458         .main_clk       = "cam_ick",
2459         .flags          = HWMOD_NO_IDLEST,
2460 };
2461
2462 /* mmu iva */
2463
2464 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2465
2466 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2467         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2468 };
2469
2470 /* l3_main -> iva mmu */
2471 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2472         .master         = &omap3xxx_l3_main_hwmod,
2473         .slave          = &omap3xxx_mmu_iva_hwmod,
2474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2475 };
2476
2477 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2478         .name           = "mmu_iva",
2479         .class          = &omap3xxx_mmu_hwmod_class,
2480         .clkdm_name     = "iva2_clkdm",
2481         .rst_lines      = omap3xxx_mmu_iva_resets,
2482         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2483         .main_clk       = "iva2_ck",
2484         .prcm = {
2485                 .omap2 = {
2486                         .module_offs = OMAP3430_IVA2_MOD,
2487                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2488                         .idlest_reg_id = 1,
2489                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2490                 },
2491         },
2492         .flags          = HWMOD_NO_IDLEST,
2493 };
2494
2495 /* l4_per -> gpio4 */
2496
2497 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2498         .master         = &omap3xxx_l4_per_hwmod,
2499         .slave          = &omap3xxx_gpio4_hwmod,
2500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2501 };
2502
2503 /* l4_per -> gpio5 */
2504
2505 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2506         .master         = &omap3xxx_l4_per_hwmod,
2507         .slave          = &omap3xxx_gpio5_hwmod,
2508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 /* l4_per -> gpio6 */
2512
2513 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2514         .master         = &omap3xxx_l4_per_hwmod,
2515         .slave          = &omap3xxx_gpio6_hwmod,
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* dma_system -> L3 */
2520 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2521         .master         = &omap3xxx_dma_system_hwmod,
2522         .slave          = &omap3xxx_l3_main_hwmod,
2523         .clk            = "core_l3_ick",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2528         {
2529                 .pa_start       = 0x48056000,
2530                 .pa_end         = 0x48056fff,
2531                 .flags          = ADDR_TYPE_RT,
2532         },
2533         { },
2534 };
2535
2536 /* l4_cfg -> dma_system */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2538         .master         = &omap3xxx_l4_core_hwmod,
2539         .slave          = &omap3xxx_dma_system_hwmod,
2540         .clk            = "core_l4_ick",
2541         .addr           = omap3xxx_dma_system_addrs,
2542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545
2546 /* l4_core -> mcbsp1 */
2547 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2548         .master         = &omap3xxx_l4_core_hwmod,
2549         .slave          = &omap3xxx_mcbsp1_hwmod,
2550         .clk            = "mcbsp1_ick",
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554
2555 /* l4_per -> mcbsp2 */
2556 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2557         .master         = &omap3xxx_l4_per_hwmod,
2558         .slave          = &omap3xxx_mcbsp2_hwmod,
2559         .clk            = "mcbsp2_ick",
2560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2561 };
2562
2563
2564 /* l4_per -> mcbsp3 */
2565 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2566         .master         = &omap3xxx_l4_per_hwmod,
2567         .slave          = &omap3xxx_mcbsp3_hwmod,
2568         .clk            = "mcbsp3_ick",
2569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572
2573 /* l4_per -> mcbsp4 */
2574 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2575         .master         = &omap3xxx_l4_per_hwmod,
2576         .slave          = &omap3xxx_mcbsp4_hwmod,
2577         .clk            = "mcbsp4_ick",
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581
2582 /* l4_core -> mcbsp5 */
2583 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2584         .master         = &omap3xxx_l4_core_hwmod,
2585         .slave          = &omap3xxx_mcbsp5_hwmod,
2586         .clk            = "mcbsp5_ick",
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590
2591 /* l4_per -> mcbsp2_sidetone */
2592 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2593         .master         = &omap3xxx_l4_per_hwmod,
2594         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2595         .clk            = "mcbsp2_ick",
2596         .user           = OCP_USER_MPU,
2597 };
2598
2599
2600 /* l4_per -> mcbsp3_sidetone */
2601 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2602         .master         = &omap3xxx_l4_per_hwmod,
2603         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2604         .clk            = "mcbsp3_ick",
2605         .user           = OCP_USER_MPU,
2606 };
2607
2608 /* l4_core -> mailbox */
2609 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2610         .master         = &omap3xxx_l4_core_hwmod,
2611         .slave          = &omap3xxx_mailbox_hwmod,
2612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l4 core -> mcspi1 interface */
2616 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2617         .master         = &omap3xxx_l4_core_hwmod,
2618         .slave          = &omap34xx_mcspi1,
2619         .clk            = "mcspi1_ick",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4 core -> mcspi2 interface */
2624 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2625         .master         = &omap3xxx_l4_core_hwmod,
2626         .slave          = &omap34xx_mcspi2,
2627         .clk            = "mcspi2_ick",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4 core -> mcspi3 interface */
2632 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2633         .master         = &omap3xxx_l4_core_hwmod,
2634         .slave          = &omap34xx_mcspi3,
2635         .clk            = "mcspi3_ick",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* l4 core -> mcspi4 interface */
2640
2641 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2642         .master         = &omap3xxx_l4_core_hwmod,
2643         .slave          = &omap34xx_mcspi4,
2644         .clk            = "mcspi4_ick",
2645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2647
2648 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2649         .master         = &omap3xxx_usb_host_hs_hwmod,
2650         .slave          = &omap3xxx_l3_main_hwmod,
2651         .clk            = "core_l3_ick",
2652         .user           = OCP_USER_MPU,
2653 };
2654
2655
2656 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2657         .master         = &omap3xxx_l4_core_hwmod,
2658         .slave          = &omap3xxx_usb_host_hs_hwmod,
2659         .clk            = "usbhost_ick",
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663
2664 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2665         .master         = &omap3xxx_l4_core_hwmod,
2666         .slave          = &omap3xxx_usb_tll_hs_hwmod,
2667         .clk            = "usbtll_ick",
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* l4_core -> hdq1w interface */
2672 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2673         .master         = &omap3xxx_l4_core_hwmod,
2674         .slave          = &omap3xxx_hdq1w_hwmod,
2675         .clk            = "hdq_ick",
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2678 };
2679
2680 /* l4_wkup -> 32ksync_counter */
2681
2682
2683 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2684         .master         = &omap3xxx_l4_wkup_hwmod,
2685         .slave          = &omap3xxx_counter_32k_hwmod,
2686         .clk            = "omap_32ksync_ick",
2687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2688 };
2689
2690 /* am35xx has Davinci MDIO & EMAC */
2691 static struct omap_hwmod_class am35xx_mdio_class = {
2692         .name = "davinci_mdio",
2693 };
2694
2695 static struct omap_hwmod am35xx_mdio_hwmod = {
2696         .name           = "davinci_mdio",
2697         .class          = &am35xx_mdio_class,
2698         .flags          = HWMOD_NO_IDLEST,
2699 };
2700
2701 /*
2702  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2703  * but this will probably require some additional hwmod core support,
2704  * so is left as a future to-do item.
2705  */
2706 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2707         .master         = &am35xx_mdio_hwmod,
2708         .slave          = &omap3xxx_l3_main_hwmod,
2709         .clk            = "emac_fck",
2710         .user           = OCP_USER_MPU,
2711 };
2712
2713 /* l4_core -> davinci mdio  */
2714 /*
2715  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2716  * but this will probably require some additional hwmod core support,
2717  * so is left as a future to-do item.
2718  */
2719 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2720         .master         = &omap3xxx_l4_core_hwmod,
2721         .slave          = &am35xx_mdio_hwmod,
2722         .clk            = "emac_fck",
2723         .user           = OCP_USER_MPU,
2724 };
2725
2726 static struct omap_hwmod_class am35xx_emac_class = {
2727         .name = "davinci_emac",
2728 };
2729
2730 static struct omap_hwmod am35xx_emac_hwmod = {
2731         .name           = "davinci_emac",
2732         .class          = &am35xx_emac_class,
2733         /*
2734          * According to Mark Greer, the MPU will not return from WFI
2735          * when the EMAC signals an interrupt.
2736          * http://www.spinics.net/lists/arm-kernel/msg174734.html
2737          */
2738         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2739 };
2740
2741 /* l3_core -> davinci emac interface */
2742 /*
2743  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2744  * but this will probably require some additional hwmod core support,
2745  * so is left as a future to-do item.
2746  */
2747 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2748         .master         = &am35xx_emac_hwmod,
2749         .slave          = &omap3xxx_l3_main_hwmod,
2750         .clk            = "emac_ick",
2751         .user           = OCP_USER_MPU,
2752 };
2753
2754 /* l4_core -> davinci emac  */
2755 /*
2756  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2757  * but this will probably require some additional hwmod core support,
2758  * so is left as a future to-do item.
2759  */
2760 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2761         .master         = &omap3xxx_l4_core_hwmod,
2762         .slave          = &am35xx_emac_hwmod,
2763         .clk            = "emac_ick",
2764         .user           = OCP_USER_MPU,
2765 };
2766
2767 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2768         .master         = &omap3xxx_l3_main_hwmod,
2769         .slave          = &omap3xxx_gpmc_hwmod,
2770         .clk            = "core_l3_ick",
2771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2772 };
2773
2774 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2775 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
2776         .sidle_shift    = 4,
2777         .srst_shift     = 1,
2778         .autoidle_shift = 0,
2779 };
2780
2781 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2782         .rev_offs       = 0x5c,
2783         .sysc_offs      = 0x60,
2784         .syss_offs      = 0x64,
2785         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2786                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2787         .sysc_fields    = &omap3_sham_sysc_fields,
2788 };
2789
2790 static struct omap_hwmod_class omap3xxx_sham_class = {
2791         .name   = "sham",
2792         .sysc   = &omap3_sham_sysc,
2793 };
2794
2795
2796
2797 static struct omap_hwmod omap3xxx_sham_hwmod = {
2798         .name           = "sham",
2799         .main_clk       = "sha12_ick",
2800         .prcm           = {
2801                 .omap2 = {
2802                         .module_offs = CORE_MOD,
2803                         .prcm_reg_id = 1,
2804                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
2805                         .idlest_reg_id = 1,
2806                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2807                 },
2808         },
2809         .class          = &omap3xxx_sham_class,
2810 };
2811
2812
2813 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2814         .master         = &omap3xxx_l4_core_hwmod,
2815         .slave          = &omap3xxx_sham_hwmod,
2816         .clk            = "sha12_ick",
2817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2818 };
2819
2820 /* l4_core -> AES */
2821 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
2822         .sidle_shift    = 6,
2823         .srst_shift     = 1,
2824         .autoidle_shift = 0,
2825 };
2826
2827 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2828         .rev_offs       = 0x44,
2829         .sysc_offs      = 0x48,
2830         .syss_offs      = 0x4c,
2831         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2832                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2833         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2834         .sysc_fields    = &omap3xxx_aes_sysc_fields,
2835 };
2836
2837 static struct omap_hwmod_class omap3xxx_aes_class = {
2838         .name   = "aes",
2839         .sysc   = &omap3_aes_sysc,
2840 };
2841
2842
2843 static struct omap_hwmod omap3xxx_aes_hwmod = {
2844         .name           = "aes",
2845         .main_clk       = "aes2_ick",
2846         .prcm           = {
2847                 .omap2 = {
2848                         .module_offs = CORE_MOD,
2849                         .prcm_reg_id = 1,
2850                         .module_bit = OMAP3430_EN_AES2_SHIFT,
2851                         .idlest_reg_id = 1,
2852                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2853                 },
2854         },
2855         .class          = &omap3xxx_aes_class,
2856 };
2857
2858
2859 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2860         .master         = &omap3xxx_l4_core_hwmod,
2861         .slave          = &omap3xxx_aes_hwmod,
2862         .clk            = "aes2_ick",
2863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2864 };
2865
2866 /*
2867  * 'ssi' class
2868  * synchronous serial interface (multichannel and full-duplex serial if)
2869  */
2870
2871 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2872         .rev_offs       = 0x0000,
2873         .sysc_offs      = 0x0010,
2874         .syss_offs      = 0x0014,
2875         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2876                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2877         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2878         .sysc_fields    = &omap_hwmod_sysc_type1,
2879 };
2880
2881 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2882         .name   = "ssi",
2883         .sysc   = &omap34xx_ssi_sysc,
2884 };
2885
2886 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2887         .name           = "ssi",
2888         .class          = &omap3xxx_ssi_hwmod_class,
2889         .clkdm_name     = "core_l4_clkdm",
2890         .main_clk       = "ssi_ssr_fck",
2891         .prcm           = {
2892                 .omap2 = {
2893                         .prcm_reg_id            = 1,
2894                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
2895                         .module_offs            = CORE_MOD,
2896                         .idlest_reg_id          = 1,
2897                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2898                 },
2899         },
2900 };
2901
2902 /* L4 CORE -> SSI */
2903 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2904         .master         = &omap3xxx_l4_core_hwmod,
2905         .slave          = &omap3xxx_ssi_hwmod,
2906         .clk            = "ssi_ick",
2907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2908 };
2909
2910 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2911         &omap3xxx_l3_main__l4_core,
2912         &omap3xxx_l3_main__l4_per,
2913         &omap3xxx_mpu__l3_main,
2914         &omap3xxx_l3_main__l4_debugss,
2915         &omap3xxx_l4_core__l4_wkup,
2916         &omap3xxx_l4_core__mmc3,
2917         &omap3_l4_core__uart1,
2918         &omap3_l4_core__uart2,
2919         &omap3_l4_per__uart3,
2920         &omap3_l4_core__i2c1,
2921         &omap3_l4_core__i2c2,
2922         &omap3_l4_core__i2c3,
2923         &omap3xxx_l4_wkup__l4_sec,
2924         &omap3xxx_l4_wkup__timer1,
2925         &omap3xxx_l4_per__timer2,
2926         &omap3xxx_l4_per__timer3,
2927         &omap3xxx_l4_per__timer4,
2928         &omap3xxx_l4_per__timer5,
2929         &omap3xxx_l4_per__timer6,
2930         &omap3xxx_l4_per__timer7,
2931         &omap3xxx_l4_per__timer8,
2932         &omap3xxx_l4_per__timer9,
2933         &omap3xxx_l4_core__timer10,
2934         &omap3xxx_l4_core__timer11,
2935         &omap3xxx_l4_wkup__wd_timer2,
2936         &omap3xxx_l4_wkup__gpio1,
2937         &omap3xxx_l4_per__gpio2,
2938         &omap3xxx_l4_per__gpio3,
2939         &omap3xxx_l4_per__gpio4,
2940         &omap3xxx_l4_per__gpio5,
2941         &omap3xxx_l4_per__gpio6,
2942         &omap3xxx_dma_system__l3,
2943         &omap3xxx_l4_core__dma_system,
2944         &omap3xxx_l4_core__mcbsp1,
2945         &omap3xxx_l4_per__mcbsp2,
2946         &omap3xxx_l4_per__mcbsp3,
2947         &omap3xxx_l4_per__mcbsp4,
2948         &omap3xxx_l4_core__mcbsp5,
2949         &omap3xxx_l4_per__mcbsp2_sidetone,
2950         &omap3xxx_l4_per__mcbsp3_sidetone,
2951         &omap34xx_l4_core__mcspi1,
2952         &omap34xx_l4_core__mcspi2,
2953         &omap34xx_l4_core__mcspi3,
2954         &omap34xx_l4_core__mcspi4,
2955         &omap3xxx_l4_wkup__counter_32k,
2956         &omap3xxx_l3_main__gpmc,
2957         NULL,
2958 };
2959
2960 /* GP-only hwmod links */
2961 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2962         &omap3xxx_l4_sec__timer12,
2963         NULL,
2964 };
2965
2966 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2967         &omap3xxx_l4_sec__timer12,
2968         NULL,
2969 };
2970
2971 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2972         &omap3xxx_l4_sec__timer12,
2973         NULL,
2974 };
2975
2976 /* crypto hwmod links */
2977 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2978         &omap3xxx_l4_core__sham,
2979         NULL,
2980 };
2981
2982 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2983         &omap3xxx_l4_core__aes,
2984         NULL,
2985 };
2986
2987 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2988         &omap3xxx_l4_core__sham,
2989         NULL
2990 };
2991
2992 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2993         &omap3xxx_l4_core__aes,
2994         NULL
2995 };
2996
2997 /*
2998  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2999  * only present on some AM35xx chips, and no one knows which
3000  * ones.  See
3001  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3002  * if you need these IP blocks on an AM35xx, try uncommenting
3003  * the following lines.
3004  */
3005 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3006         /* &omap3xxx_l4_core__sham, */
3007         NULL
3008 };
3009
3010 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3011         /* &omap3xxx_l4_core__aes, */
3012         NULL,
3013 };
3014
3015 /* 3430ES1-only hwmod links */
3016 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3017         &omap3430es1_dss__l3,
3018         &omap3430es1_l4_core__dss,
3019         NULL,
3020 };
3021
3022 /* 3430ES2+-only hwmod links */
3023 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3024         &omap3xxx_dss__l3,
3025         &omap3xxx_l4_core__dss,
3026         &omap3xxx_usbhsotg__l3,
3027         &omap3xxx_l4_core__usbhsotg,
3028         &omap3xxx_usb_host_hs__l3_main_2,
3029         &omap3xxx_l4_core__usb_host_hs,
3030         &omap3xxx_l4_core__usb_tll_hs,
3031         NULL,
3032 };
3033
3034 /* <= 3430ES3-only hwmod links */
3035 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3036         &omap3xxx_l4_core__pre_es3_mmc1,
3037         &omap3xxx_l4_core__pre_es3_mmc2,
3038         NULL,
3039 };
3040
3041 /* 3430ES3+-only hwmod links */
3042 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3043         &omap3xxx_l4_core__es3plus_mmc1,
3044         &omap3xxx_l4_core__es3plus_mmc2,
3045         NULL,
3046 };
3047
3048 /* 34xx-only hwmod links (all ES revisions) */
3049 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3050         &omap3xxx_l3__iva,
3051         &omap34xx_l4_core__sr1,
3052         &omap34xx_l4_core__sr2,
3053         &omap3xxx_l4_core__mailbox,
3054         &omap3xxx_l4_core__hdq1w,
3055         &omap3xxx_sad2d__l3,
3056         &omap3xxx_l4_core__mmu_isp,
3057         &omap3xxx_l3_main__mmu_iva,
3058         &omap3xxx_l4_core__ssi,
3059         NULL,
3060 };
3061
3062 /* 36xx-only hwmod links (all ES revisions) */
3063 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3064         &omap3xxx_l3__iva,
3065         &omap36xx_l4_per__uart4,
3066         &omap3xxx_dss__l3,
3067         &omap3xxx_l4_core__dss,
3068         &omap36xx_l4_core__sr1,
3069         &omap36xx_l4_core__sr2,
3070         &omap3xxx_usbhsotg__l3,
3071         &omap3xxx_l4_core__usbhsotg,
3072         &omap3xxx_l4_core__mailbox,
3073         &omap3xxx_usb_host_hs__l3_main_2,
3074         &omap3xxx_l4_core__usb_host_hs,
3075         &omap3xxx_l4_core__usb_tll_hs,
3076         &omap3xxx_l4_core__es3plus_mmc1,
3077         &omap3xxx_l4_core__es3plus_mmc2,
3078         &omap3xxx_l4_core__hdq1w,
3079         &omap3xxx_sad2d__l3,
3080         &omap3xxx_l4_core__mmu_isp,
3081         &omap3xxx_l3_main__mmu_iva,
3082         &omap3xxx_l4_core__ssi,
3083         NULL,
3084 };
3085
3086 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3087         &omap3xxx_dss__l3,
3088         &omap3xxx_l4_core__dss,
3089         &am35xx_usbhsotg__l3,
3090         &am35xx_l4_core__usbhsotg,
3091         &am35xx_l4_core__uart4,
3092         &omap3xxx_usb_host_hs__l3_main_2,
3093         &omap3xxx_l4_core__usb_host_hs,
3094         &omap3xxx_l4_core__usb_tll_hs,
3095         &omap3xxx_l4_core__es3plus_mmc1,
3096         &omap3xxx_l4_core__es3plus_mmc2,
3097         &omap3xxx_l4_core__hdq1w,
3098         &am35xx_mdio__l3,
3099         &am35xx_l4_core__mdio,
3100         &am35xx_emac__l3,
3101         &am35xx_l4_core__emac,
3102         NULL,
3103 };
3104
3105 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3106         &omap3xxx_l4_core__dss_dispc,
3107         &omap3xxx_l4_core__dss_dsi1,
3108         &omap3xxx_l4_core__dss_rfbi,
3109         &omap3xxx_l4_core__dss_venc,
3110         NULL,
3111 };
3112
3113 /**
3114  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3115  * @bus: struct device_node * for the top-level OMAP DT data
3116  * @dev_name: device name used in the DT file
3117  *
3118  * Determine whether a "secure" IP block @dev_name is usable by Linux.
3119  * There doesn't appear to be a 100% reliable way to determine this,
3120  * so we rely on heuristics.  If @bus is null, meaning there's no DT
3121  * data, then we only assume the IP block is accessible if the OMAP is
3122  * fused as a 'general-purpose' SoC.  If however DT data is present,
3123  * test to see if the IP block is described in the DT data and set to
3124  * 'status = "okay"'.  If so then we assume the ODM has configured the
3125  * OMAP firewalls to allow access to the IP block.
3126  *
3127  * Return: 0 if device named @dev_name is not likely to be accessible,
3128  * or 1 if it is likely to be accessible.
3129  */
3130 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3131                                                         const char *dev_name)
3132 {
3133         struct device_node *node;
3134         bool available;
3135
3136         if (!bus)
3137                 return omap_type() == OMAP2_DEVICE_TYPE_GP;
3138
3139         node = of_get_child_by_name(bus, dev_name);
3140         available = of_device_is_available(node);
3141         of_node_put(node);
3142
3143         return available;
3144 }
3145
3146 int __init omap3xxx_hwmod_init(void)
3147 {
3148         int r;
3149         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3150         struct omap_hwmod_ocp_if **h_aes = NULL;
3151         struct device_node *bus = NULL;
3152         unsigned int rev;
3153
3154         omap_hwmod_init();
3155
3156         /* Register hwmod links common to all OMAP3 */
3157         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3158         if (r < 0)
3159                 return r;
3160
3161         rev = omap_rev();
3162
3163         /*
3164          * Register hwmod links common to individual OMAP3 families, all
3165          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3166          * All possible revisions should be included in this conditional.
3167          */
3168         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3169             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3170             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3171                 h = omap34xx_hwmod_ocp_ifs;
3172                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3173                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3174                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3175         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3176                 h = am35xx_hwmod_ocp_ifs;
3177                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3178                 h_sham = am35xx_sham_hwmod_ocp_ifs;
3179                 h_aes = am35xx_aes_hwmod_ocp_ifs;
3180         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3181                    rev == OMAP3630_REV_ES1_2) {
3182                 h = omap36xx_hwmod_ocp_ifs;
3183                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3184                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3185                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3186         } else {
3187                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3188                 return -EINVAL;
3189         }
3190
3191         r = omap_hwmod_register_links(h);
3192         if (r < 0)
3193                 return r;
3194
3195         /* Register GP-only hwmod links. */
3196         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3197                 r = omap_hwmod_register_links(h_gp);
3198                 if (r < 0)
3199                         return r;
3200         }
3201
3202         /*
3203          * Register crypto hwmod links only if they are not disabled in DT.
3204          * If DT information is missing, enable them only for GP devices.
3205          */
3206
3207         bus = of_find_node_by_name(NULL, "ocp");
3208
3209         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3210                 r = omap_hwmod_register_links(h_sham);
3211                 if (r < 0) {
3212                         of_node_put(bus);
3213                         return r;
3214                 }
3215         }
3216
3217         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3218                 r = omap_hwmod_register_links(h_aes);
3219                 if (r < 0) {
3220                         of_node_put(bus);
3221                         return r;
3222                 }
3223         }
3224         of_node_put(bus);
3225
3226         /*
3227          * Register hwmod links specific to certain ES levels of a
3228          * particular family of silicon (e.g., 34xx ES1.0)
3229          */
3230         h = NULL;
3231         if (rev == OMAP3430_REV_ES1_0) {
3232                 h = omap3430es1_hwmod_ocp_ifs;
3233         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3234                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3235                    rev == OMAP3430_REV_ES3_1_2) {
3236                 h = omap3430es2plus_hwmod_ocp_ifs;
3237         }
3238
3239         if (h) {
3240                 r = omap_hwmod_register_links(h);
3241                 if (r < 0)
3242                         return r;
3243         }
3244
3245         h = NULL;
3246         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3247             rev == OMAP3430_REV_ES2_1) {
3248                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3249         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3250                    rev == OMAP3430_REV_ES3_1_2) {
3251                 h = omap3430_es3plus_hwmod_ocp_ifs;
3252         }
3253
3254         if (h)
3255                 r = omap_hwmod_register_links(h);
3256         if (r < 0)
3257                 return r;
3258
3259         /*
3260          * DSS code presumes that dss_core hwmod is handled first,
3261          * _before_ any other DSS related hwmods so register common
3262          * DSS hwmod links last to ensure that dss_core is already
3263          * registered.  Otherwise some change things may happen, for
3264          * ex. if dispc is handled before dss_core and DSS is enabled
3265          * in bootloader DISPC will be reset with outputs enabled
3266          * which sometimes leads to unrecoverable L3 error.  XXX The
3267          * long-term fix to this is to ensure hwmods are set up in
3268          * dependency order in the hwmod core code.
3269          */
3270         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3271
3272         return r;
3273 }