arch/arm/mach-omap2/powerdomains7xx_data.c

   1 /*
   2  * DRA7xx Power domains framework
   3  *
   4  * Copyright (C) 2009-2013 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2011 Nokia Corporation
   6  *
   7  * Generated by code originally written by:
   8  * Abhijit Pagare (abhijitpagare@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  * Paul Walmsley (paul@pwsan.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25
  26 #include "powerdomain.h"
  27
  28 #include "prcm-common.h"
  29 #include "prcm44xx.h"
  30 #include "prm7xx.h"
  31 #include "prcm_mpu7xx.h"
  32
  33 /* iva_7xx_pwrdm: IVA-HD power domain */
  34 static struct powerdomain iva_7xx_pwrdm = {
  35         .name             = "iva_pwrdm",
  36         .prcm_offs        = DRA7XX_PRM_IVA_INST,
  37         .prcm_partition   = DRA7XX_PRM_PARTITION,
  38         .pwrsts           = PWRSTS_OFF_ON,
  39         .banks            = 4,
  40         .pwrsts_mem_on  = {
  41                 [0] = PWRSTS_ON,        /* hwa_mem */
  42                 [1] = PWRSTS_ON,        /* sl2_mem */
  43                 [2] = PWRSTS_ON,        /* tcm1_mem */
  44                 [3] = PWRSTS_ON,        /* tcm2_mem */
  45         },
  46         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  47 };
  48
  49 /* rtc_7xx_pwrdm:  */
  50 static struct powerdomain rtc_7xx_pwrdm = {
  51         .name             = "rtc_pwrdm",
  52         .prcm_offs        = DRA7XX_PRM_RTC_INST,
  53         .prcm_partition   = DRA7XX_PRM_PARTITION,
  54         .pwrsts           = PWRSTS_ON,
  55 };
  56
  57 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
  58 static struct powerdomain custefuse_7xx_pwrdm = {
  59         .name             = "custefuse_pwrdm",
  60         .prcm_offs        = DRA7XX_PRM_CUSTEFUSE_INST,
  61         .prcm_partition   = DRA7XX_PRM_PARTITION,
  62         .pwrsts           = PWRSTS_OFF_ON,
  63         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  64 };
  65
  66 /* ipu_7xx_pwrdm: Audio back end power domain */
  67 static struct powerdomain ipu_7xx_pwrdm = {
  68         .name             = "ipu_pwrdm",
  69         .prcm_offs        = DRA7XX_PRM_IPU_INST,
  70         .prcm_partition   = DRA7XX_PRM_PARTITION,
  71         .pwrsts           = PWRSTS_OFF_ON,
  72         .banks            = 2,
  73         .pwrsts_mem_on  = {
  74                 [0] = PWRSTS_ON,        /* aessmem */
  75                 [1] = PWRSTS_ON,        /* periphmem */
  76         },
  77         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  78 };
  79
  80 /* dss_7xx_pwrdm: Display subsystem power domain */
  81 static struct powerdomain dss_7xx_pwrdm = {
  82         .name             = "dss_pwrdm",
  83         .prcm_offs        = DRA7XX_PRM_DSS_INST,
  84         .prcm_partition   = DRA7XX_PRM_PARTITION,
  85         .pwrsts           = PWRSTS_OFF_ON,
  86         .banks            = 1,
  87         .pwrsts_mem_on  = {
  88                 [0] = PWRSTS_ON,        /* dss_mem */
  89         },
  90         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  91 };
  92
  93 /* l4per_7xx_pwrdm: Target peripherals power domain */
  94 static struct powerdomain l4per_7xx_pwrdm = {
  95         .name             = "l4per_pwrdm",
  96         .prcm_offs        = DRA7XX_PRM_L4PER_INST,
  97         .prcm_partition   = DRA7XX_PRM_PARTITION,
  98         .pwrsts           = PWRSTS_ON,
  99         .banks            = 2,
 100         .pwrsts_mem_on  = {
 101                 [0] = PWRSTS_ON,        /* nonretained_bank */
 102                 [1] = PWRSTS_ON,        /* retained_bank */
 103         },
 104         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 105 };
 106
 107 /* gpu_7xx_pwrdm: 3D accelerator power domain */
 108 static struct powerdomain gpu_7xx_pwrdm = {
 109         .name             = "gpu_pwrdm",
 110         .prcm_offs        = DRA7XX_PRM_GPU_INST,
 111         .prcm_partition   = DRA7XX_PRM_PARTITION,
 112         .pwrsts           = PWRSTS_OFF_ON,
 113         .banks            = 1,
 114         .pwrsts_mem_on  = {
 115                 [0] = PWRSTS_ON,        /* gpu_mem */
 116         },
 117         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 118 };
 119
 120 /* wkupaon_7xx_pwrdm: Wake-up power domain */
 121 static struct powerdomain wkupaon_7xx_pwrdm = {
 122         .name             = "wkupaon_pwrdm",
 123         .prcm_offs        = DRA7XX_PRM_WKUPAON_INST,
 124         .prcm_partition   = DRA7XX_PRM_PARTITION,
 125         .pwrsts           = PWRSTS_ON,
 126         .banks            = 1,
 127         .pwrsts_mem_on  = {
 128                 [0] = PWRSTS_ON,        /* wkup_bank */
 129         },
 130 };
 131
 132 /* core_7xx_pwrdm: CORE power domain */
 133 static struct powerdomain core_7xx_pwrdm = {
 134         .name             = "core_pwrdm",
 135         .prcm_offs        = DRA7XX_PRM_CORE_INST,
 136         .prcm_partition   = DRA7XX_PRM_PARTITION,
 137         .pwrsts           = PWRSTS_ON,
 138         .banks            = 5,
 139         .pwrsts_mem_on  = {
 140                 [0] = PWRSTS_ON,        /* core_nret_bank */
 141                 [1] = PWRSTS_ON,        /* core_ocmram */
 142                 [2] = PWRSTS_ON,        /* core_other_bank */
 143                 [3] = PWRSTS_ON,        /* ipu_l2ram */
 144                 [4] = PWRSTS_ON,        /* ipu_unicache */
 145         },
 146         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 147 };
 148
 149 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
 150 static struct powerdomain coreaon_7xx_pwrdm = {
 151         .name             = "coreaon_pwrdm",
 152         .prcm_offs        = DRA7XX_PRM_COREAON_INST,
 153         .prcm_partition   = DRA7XX_PRM_PARTITION,
 154         .pwrsts           = PWRSTS_ON,
 155 };
 156
 157 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 158 static struct powerdomain cpu0_7xx_pwrdm = {
 159         .name             = "cpu0_pwrdm",
 160         .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C0_INST,
 161         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
 162         .pwrsts           = PWRSTS_RET_ON,
 163         .pwrsts_logic_ret = PWRSTS_RET,
 164         .banks            = 1,
 165         .pwrsts_mem_ret = {
 166                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
 167         },
 168         .pwrsts_mem_on  = {
 169                 [0] = PWRSTS_ON,        /* cpu0_l1 */
 170         },
 171 };
 172
 173 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 174 static struct powerdomain cpu1_7xx_pwrdm = {
 175         .name             = "cpu1_pwrdm",
 176         .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C1_INST,
 177         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
 178         .pwrsts           = PWRSTS_RET_ON,
 179         .pwrsts_logic_ret = PWRSTS_RET,
 180         .banks            = 1,
 181         .pwrsts_mem_ret = {
 182                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
 183         },
 184         .pwrsts_mem_on  = {
 185                 [0] = PWRSTS_ON,        /* cpu1_l1 */
 186         },
 187 };
 188
 189 /* vpe_7xx_pwrdm:  */
 190 static struct powerdomain vpe_7xx_pwrdm = {
 191         .name             = "vpe_pwrdm",
 192         .prcm_offs        = DRA7XX_PRM_VPE_INST,
 193         .prcm_partition   = DRA7XX_PRM_PARTITION,
 194         .pwrsts           = PWRSTS_OFF_ON,
 195         .banks            = 1,
 196         .pwrsts_mem_on  = {
 197                 [0] = PWRSTS_ON,        /* vpe_bank */
 198         },
 199         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 200 };
 201
 202 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 203 static struct powerdomain mpu_7xx_pwrdm = {
 204         .name             = "mpu_pwrdm",
 205         .prcm_offs        = DRA7XX_PRM_MPU_INST,
 206         .prcm_partition   = DRA7XX_PRM_PARTITION,
 207         .pwrsts           = PWRSTS_RET_ON,
 208         .pwrsts_logic_ret = PWRSTS_RET,
 209         .banks            = 2,
 210         .pwrsts_mem_ret = {
 211                 [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
 212                 [1] = PWRSTS_RET,       /* mpu_ram */
 213         },
 214         .pwrsts_mem_on  = {
 215                 [0] = PWRSTS_ON,        /* mpu_l2 */
 216                 [1] = PWRSTS_ON,        /* mpu_ram */
 217         },
 218 };
 219
 220 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
 221 static struct powerdomain l3init_7xx_pwrdm = {
 222         .name             = "l3init_pwrdm",
 223         .prcm_offs        = DRA7XX_PRM_L3INIT_INST,
 224         .prcm_partition   = DRA7XX_PRM_PARTITION,
 225         .pwrsts           = PWRSTS_ON,
 226         .banks            = 3,
 227         .pwrsts_mem_on  = {
 228                 [0] = PWRSTS_ON,        /* gmac_bank */
 229                 [1] = PWRSTS_ON,        /* l3init_bank1 */
 230                 [2] = PWRSTS_ON,        /* l3init_bank2 */
 231         },
 232         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 233 };
 234
 235 /* eve3_7xx_pwrdm:  */
 236 static struct powerdomain eve3_7xx_pwrdm = {
 237         .name             = "eve3_pwrdm",
 238         .prcm_offs        = DRA7XX_PRM_EVE3_INST,
 239         .prcm_partition   = DRA7XX_PRM_PARTITION,
 240         .pwrsts           = PWRSTS_OFF_ON,
 241         .banks            = 1,
 242         .pwrsts_mem_on  = {
 243                 [0] = PWRSTS_ON,        /* eve3_bank */
 244         },
 245         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 246 };
 247
 248 /* emu_7xx_pwrdm: Emulation power domain */
 249 static struct powerdomain emu_7xx_pwrdm = {
 250         .name             = "emu_pwrdm",
 251         .prcm_offs        = DRA7XX_PRM_EMU_INST,
 252         .prcm_partition   = DRA7XX_PRM_PARTITION,
 253         .pwrsts           = PWRSTS_OFF_ON,
 254         .banks            = 1,
 255         .pwrsts_mem_on  = {
 256                 [0] = PWRSTS_ON,        /* emu_bank */
 257         },
 258 };
 259
 260 /* dsp2_7xx_pwrdm:  */
 261 static struct powerdomain dsp2_7xx_pwrdm = {
 262         .name             = "dsp2_pwrdm",
 263         .prcm_offs        = DRA7XX_PRM_DSP2_INST,
 264         .prcm_partition   = DRA7XX_PRM_PARTITION,
 265         .pwrsts           = PWRSTS_OFF_ON,
 266         .banks            = 3,
 267         .pwrsts_mem_on  = {
 268                 [0] = PWRSTS_ON,        /* dsp2_edma */
 269                 [1] = PWRSTS_ON,        /* dsp2_l1 */
 270                 [2] = PWRSTS_ON,        /* dsp2_l2 */
 271         },
 272         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 273 };
 274
 275 /* dsp1_7xx_pwrdm: Tesla processor power domain */
 276 static struct powerdomain dsp1_7xx_pwrdm = {
 277         .name             = "dsp1_pwrdm",
 278         .prcm_offs        = DRA7XX_PRM_DSP1_INST,
 279         .prcm_partition   = DRA7XX_PRM_PARTITION,
 280         .pwrsts           = PWRSTS_OFF_ON,
 281         .banks            = 3,
 282         .pwrsts_mem_on  = {
 283                 [0] = PWRSTS_ON,        /* dsp1_edma */
 284                 [1] = PWRSTS_ON,        /* dsp1_l1 */
 285                 [2] = PWRSTS_ON,        /* dsp1_l2 */
 286         },
 287         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 288 };
 289
 290 /* cam_7xx_pwrdm: Camera subsystem power domain */
 291 static struct powerdomain cam_7xx_pwrdm = {
 292         .name             = "cam_pwrdm",
 293         .prcm_offs        = DRA7XX_PRM_CAM_INST,
 294         .prcm_partition   = DRA7XX_PRM_PARTITION,
 295         .pwrsts           = PWRSTS_OFF_ON,
 296         .banks            = 1,
 297         .pwrsts_mem_on  = {
 298                 [0] = PWRSTS_ON,        /* vip_bank */
 299         },
 300         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 301 };
 302
 303 /* eve4_7xx_pwrdm:  */
 304 static struct powerdomain eve4_7xx_pwrdm = {
 305         .name             = "eve4_pwrdm",
 306         .prcm_offs        = DRA7XX_PRM_EVE4_INST,
 307         .prcm_partition   = DRA7XX_PRM_PARTITION,
 308         .pwrsts           = PWRSTS_OFF_ON,
 309         .banks            = 1,
 310         .pwrsts_mem_on  = {
 311                 [0] = PWRSTS_ON,        /* eve4_bank */
 312         },
 313         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 314 };
 315
 316 /* eve2_7xx_pwrdm:  */
 317 static struct powerdomain eve2_7xx_pwrdm = {
 318         .name             = "eve2_pwrdm",
 319         .prcm_offs        = DRA7XX_PRM_EVE2_INST,
 320         .prcm_partition   = DRA7XX_PRM_PARTITION,
 321         .pwrsts           = PWRSTS_OFF_ON,
 322         .banks            = 1,
 323         .pwrsts_mem_on  = {
 324                 [0] = PWRSTS_ON,        /* eve2_bank */
 325         },
 326         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 327 };
 328
 329 /* eve1_7xx_pwrdm:  */
 330 static struct powerdomain eve1_7xx_pwrdm = {
 331         .name             = "eve1_pwrdm",
 332         .prcm_offs        = DRA7XX_PRM_EVE1_INST,
 333         .prcm_partition   = DRA7XX_PRM_PARTITION,
 334         .pwrsts           = PWRSTS_OFF_ON,
 335         .banks            = 1,
 336         .pwrsts_mem_on  = {
 337                 [0] = PWRSTS_ON,        /* eve1_bank */
 338         },
 339         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 340 };
 341
 342 /*
 343  * The following power domains are not under SW control
 344  *
 345  * mpuaon
 346  * mmaon
 347  */
 348
 349 /* As powerdomains are added or removed above, this list must also be changed */
 350 static struct powerdomain *powerdomains_dra7xx[] __initdata = {
 351         &iva_7xx_pwrdm,
 352         &rtc_7xx_pwrdm,
 353         &custefuse_7xx_pwrdm,
 354         &ipu_7xx_pwrdm,
 355         &dss_7xx_pwrdm,
 356         &l4per_7xx_pwrdm,
 357         &gpu_7xx_pwrdm,
 358         &wkupaon_7xx_pwrdm,
 359         &core_7xx_pwrdm,
 360         &coreaon_7xx_pwrdm,
 361         &cpu0_7xx_pwrdm,
 362         &cpu1_7xx_pwrdm,
 363         &vpe_7xx_pwrdm,
 364         &mpu_7xx_pwrdm,
 365         &l3init_7xx_pwrdm,
 366         &eve3_7xx_pwrdm,
 367         &emu_7xx_pwrdm,
 368         &dsp2_7xx_pwrdm,
 369         &dsp1_7xx_pwrdm,
 370         &cam_7xx_pwrdm,
 371         &eve4_7xx_pwrdm,
 372         &eve2_7xx_pwrdm,
 373         &eve1_7xx_pwrdm,
 374         NULL
 375 };
 376
 377 void __init dra7xx_powerdomains_init(void)
 378 {
 379         pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
 380         pwrdm_register_pwrdms(powerdomains_dra7xx);
 381         pwrdm_complete_init();
 382 }