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[karo-tx-linux.git] / arch / arm / mach-spear / spear3xx.c
1 /*
2  * arch/arm/mach-spear3xx/spear3xx.c
3  *
4  * SPEAr3XX machines common source file
5  *
6  * Copyright (C) 2009-2012 ST Microelectronics
7  * Viresh Kumar <vireshk@kernel.org>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13
14 #define pr_fmt(fmt) "SPEAr3xx: " fmt
15
16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl080.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <asm/mach/map.h>
21 #include "pl080.h"
22 #include "generic.h"
23 #include <mach/spear.h>
24 #include <mach/misc_regs.h>
25
26 /* ssp device registration */
27 struct pl022_ssp_controller pl022_plat_data = {
28         .bus_id = 0,
29         .enable_dma = 1,
30         .dma_filter = pl08x_filter_id,
31         .dma_tx_param = "ssp0_tx",
32         .dma_rx_param = "ssp0_rx",
33         /*
34          * This is number of spi devices that can be connected to spi. There are
35          * two type of chipselects on which slave devices can work. One is chip
36          * select provided by spi masters other is controlled through external
37          * gpio's. We can't use chipselect provided from spi master (because as
38          * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39          * this number now depends on number of gpios available for spi. each
40          * slave on each master requires a separate gpio pin.
41          */
42         .num_chipselect = 2,
43 };
44
45 /* dmac device registration */
46 struct pl08x_platform_data pl080_plat_data = {
47         .memcpy_burst_size = PL08X_BURST_SZ_16,
48         .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
49         .memcpy_prot_buff = true,
50         .memcpy_prot_cache = true,
51         .lli_buses = PL08X_AHB1,
52         .mem_buses = PL08X_AHB1,
53         .get_xfer_signal = pl080_get_signal,
54         .put_xfer_signal = pl080_put_signal,
55 };
56
57 /*
58  * Following will create 16MB static virtual/physical mappings
59  * PHYSICAL             VIRTUAL
60  * 0xD0000000           0xFD000000
61  * 0xFC000000           0xFC000000
62  */
63 struct map_desc spear3xx_io_desc[] __initdata = {
64         {
65                 .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
66                 .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
67                 .length         = SZ_16M,
68                 .type           = MT_DEVICE
69         }, {
70                 .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
71                 .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
72                 .length         = SZ_16M,
73                 .type           = MT_DEVICE
74         },
75 };
76
77 /* This will create static memory mapping for selected devices */
78 void __init spear3xx_map_io(void)
79 {
80         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
81 }
82
83 void __init spear3xx_timer_init(void)
84 {
85         char pclk_name[] = "pll3_clk";
86         struct clk *gpt_clk, *pclk;
87
88         spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
89
90         /* get the system timer clock */
91         gpt_clk = clk_get_sys("gpt0", NULL);
92         if (IS_ERR(gpt_clk)) {
93                 pr_err("%s:couldn't get clk for gpt\n", __func__);
94                 BUG();
95         }
96
97         /* get the suitable parent clock for timer*/
98         pclk = clk_get(NULL, pclk_name);
99         if (IS_ERR(pclk)) {
100                 pr_err("%s:couldn't get %s as parent for gpt\n",
101                                 __func__, pclk_name);
102                 BUG();
103         }
104
105         clk_set_parent(gpt_clk, pclk);
106         clk_put(gpt_clk);
107         clk_put(pclk);
108
109         spear_setup_of_timer();
110 }