2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
45 struct arm_dma_alloc_args {
55 struct arm_dma_free_args {
66 struct arm_dma_allocator {
67 void *(*alloc)(struct arm_dma_alloc_args *args,
68 struct page **ret_page);
69 void (*free)(struct arm_dma_free_args *args);
72 struct arm_dma_buffer {
73 struct list_head list;
75 struct arm_dma_allocator *allocator;
78 static LIST_HEAD(arm_dma_bufs);
79 static DEFINE_SPINLOCK(arm_dma_bufs_lock);
81 static struct arm_dma_buffer *arm_dma_buffer_find(void *virt)
83 struct arm_dma_buffer *buf, *found = NULL;
86 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
87 list_for_each_entry(buf, &arm_dma_bufs, list) {
88 if (buf->virt == virt) {
94 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
99 * The DMA API is built upon the notion of "buffer ownership". A buffer
100 * is either exclusively owned by the CPU (and therefore may be accessed
101 * by it) or exclusively owned by the DMA device. These helper functions
102 * represent the transitions between these two ownership states.
104 * Note, however, that on later ARMs, this notion does not work due to
105 * speculative prefetches. We model our approach on the assumption that
106 * the CPU does do speculative prefetches, which means we clean caches
107 * before transfers and delay cache invalidation until transfer completion.
110 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
111 size_t, enum dma_data_direction);
112 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
113 size_t, enum dma_data_direction);
116 * arm_dma_map_page - map a portion of a page for streaming DMA
117 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
118 * @page: page that buffer resides in
119 * @offset: offset into page for start of buffer
120 * @size: size of buffer to map
121 * @dir: DMA transfer direction
123 * Ensure that any data held in the cache is appropriately discarded
126 * The device owns this memory once this call has completed. The CPU
127 * can regain ownership by calling dma_unmap_page().
129 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
130 unsigned long offset, size_t size, enum dma_data_direction dir,
133 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
134 __dma_page_cpu_to_dev(page, offset, size, dir);
135 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
138 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
139 unsigned long offset, size_t size, enum dma_data_direction dir,
142 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
146 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
147 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
148 * @handle: DMA address of buffer
149 * @size: size of buffer (same as passed to dma_map_page)
150 * @dir: DMA transfer direction (same as passed to dma_map_page)
152 * Unmap a page streaming mode DMA translation. The handle and size
153 * must match what was provided in the previous dma_map_page() call.
154 * All other usages are undefined.
156 * After this call, reads by the CPU to the buffer are guaranteed to see
157 * whatever the device wrote there.
159 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
160 size_t size, enum dma_data_direction dir, unsigned long attrs)
162 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
163 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
164 handle & ~PAGE_MASK, size, dir);
167 static void arm_dma_sync_single_for_cpu(struct device *dev,
168 dma_addr_t handle, size_t size, enum dma_data_direction dir)
170 unsigned int offset = handle & (PAGE_SIZE - 1);
171 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
172 __dma_page_dev_to_cpu(page, offset, size, dir);
175 static void arm_dma_sync_single_for_device(struct device *dev,
176 dma_addr_t handle, size_t size, enum dma_data_direction dir)
178 unsigned int offset = handle & (PAGE_SIZE - 1);
179 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
180 __dma_page_cpu_to_dev(page, offset, size, dir);
183 const struct dma_map_ops arm_dma_ops = {
184 .alloc = arm_dma_alloc,
185 .free = arm_dma_free,
186 .mmap = arm_dma_mmap,
187 .get_sgtable = arm_dma_get_sgtable,
188 .map_page = arm_dma_map_page,
189 .unmap_page = arm_dma_unmap_page,
190 .map_sg = arm_dma_map_sg,
191 .unmap_sg = arm_dma_unmap_sg,
192 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
193 .sync_single_for_device = arm_dma_sync_single_for_device,
194 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
195 .sync_sg_for_device = arm_dma_sync_sg_for_device,
197 EXPORT_SYMBOL(arm_dma_ops);
199 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
200 dma_addr_t *handle, gfp_t gfp, unsigned long attrs);
201 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
202 dma_addr_t handle, unsigned long attrs);
203 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
204 void *cpu_addr, dma_addr_t dma_addr, size_t size,
205 unsigned long attrs);
207 const struct dma_map_ops arm_coherent_dma_ops = {
208 .alloc = arm_coherent_dma_alloc,
209 .free = arm_coherent_dma_free,
210 .mmap = arm_coherent_dma_mmap,
211 .get_sgtable = arm_dma_get_sgtable,
212 .map_page = arm_coherent_dma_map_page,
213 .map_sg = arm_dma_map_sg,
215 EXPORT_SYMBOL(arm_coherent_dma_ops);
217 static int __dma_supported(struct device *dev, u64 mask, bool warn)
219 unsigned long max_dma_pfn;
222 * If the mask allows for more memory than we can address,
223 * and we actually have that much memory, then we must
224 * indicate that DMA to this device is not supported.
226 if (sizeof(mask) != sizeof(dma_addr_t) &&
227 mask > (dma_addr_t)~0 &&
228 dma_to_pfn(dev, ~0) < max_pfn - 1) {
230 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
232 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
237 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
240 * Translate the device's DMA mask to a PFN limit. This
241 * PFN number includes the page which we can DMA to.
243 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
245 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
247 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
255 static u64 get_coherent_dma_mask(struct device *dev)
257 u64 mask = (u64)DMA_BIT_MASK(32);
260 mask = dev->coherent_dma_mask;
263 * Sanity check the DMA mask - it must be non-zero, and
264 * must be able to be satisfied by a DMA allocation.
267 dev_warn(dev, "coherent DMA mask is unset\n");
271 if (!__dma_supported(dev, mask, true))
278 static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
281 * Ensure that the allocated pages are zeroed, and that any data
282 * lurking in the kernel direct-mapped region is invalidated.
284 if (PageHighMem(page)) {
285 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
286 phys_addr_t end = base + size;
288 void *ptr = kmap_atomic(page);
289 memset(ptr, 0, PAGE_SIZE);
290 if (coherent_flag != COHERENT)
291 dmac_flush_range(ptr, ptr + PAGE_SIZE);
296 if (coherent_flag != COHERENT)
297 outer_flush_range(base, end);
299 void *ptr = page_address(page);
300 memset(ptr, 0, size);
301 if (coherent_flag != COHERENT) {
302 dmac_flush_range(ptr, ptr + size);
303 outer_flush_range(__pa(ptr), __pa(ptr) + size);
309 * Allocate a DMA buffer for 'dev' of size 'size' using the
310 * specified gfp mask. Note that 'size' must be page aligned.
312 static struct page *__dma_alloc_buffer(struct device *dev, size_t size,
313 gfp_t gfp, int coherent_flag)
315 unsigned long order = get_order(size);
316 struct page *page, *p, *e;
318 page = alloc_pages(gfp, order);
323 * Now split the huge page and free the excess pages
325 split_page(page, order);
326 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
329 __dma_clear_buffer(page, size, coherent_flag);
335 * Free a DMA buffer. 'size' must be page aligned.
337 static void __dma_free_buffer(struct page *page, size_t size)
339 struct page *e = page + (size >> PAGE_SHIFT);
349 static void *__alloc_from_contiguous(struct device *dev, size_t size,
350 pgprot_t prot, struct page **ret_page,
351 const void *caller, bool want_vaddr,
352 int coherent_flag, gfp_t gfp);
354 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
355 pgprot_t prot, struct page **ret_page,
356 const void *caller, bool want_vaddr);
359 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
363 * DMA allocation can be mapped to user space, so lets
364 * set VM_USERMAP flags too.
366 return dma_common_contiguous_remap(page, size,
367 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
371 static void __dma_free_remap(void *cpu_addr, size_t size)
373 dma_common_free_remap(cpu_addr, size,
374 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
377 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
378 static struct gen_pool *atomic_pool;
380 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
382 static int __init early_coherent_pool(char *p)
384 atomic_pool_size = memparse(p, &p);
387 early_param("coherent_pool", early_coherent_pool);
389 void __init init_dma_coherent_pool_size(unsigned long size)
392 * Catch any attempt to set the pool size too late.
397 * Set architecture specific coherent pool size only if
398 * it has not been changed by kernel command line parameter.
400 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
401 atomic_pool_size = size;
405 * Initialise the coherent pool for atomic allocations.
407 static int __init atomic_pool_init(void)
409 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
410 gfp_t gfp = GFP_KERNEL | GFP_DMA;
414 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
418 * The atomic pool is only used for non-coherent allocations
419 * so we must pass NORMAL for coherent_flag.
421 if (dev_get_cma_area(NULL))
422 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
423 &page, atomic_pool_init, true, NORMAL,
426 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
427 &page, atomic_pool_init, true);
431 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
433 atomic_pool_size, -1);
435 goto destroy_genpool;
437 gen_pool_set_algo(atomic_pool,
438 gen_pool_first_fit_order_align,
440 pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n",
441 atomic_pool_size / 1024);
446 gen_pool_destroy(atomic_pool);
449 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
450 atomic_pool_size / 1024);
454 * CMA is activated by core_initcall, so we must be called after it.
456 postcore_initcall(atomic_pool_init);
458 struct dma_contig_early_reserve {
463 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
465 static int dma_mmu_remap_num __initdata;
467 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
469 dma_mmu_remap[dma_mmu_remap_num].base = base;
470 dma_mmu_remap[dma_mmu_remap_num].size = size;
474 void __init dma_contiguous_remap(void)
477 for (i = 0; i < dma_mmu_remap_num; i++) {
478 phys_addr_t start = dma_mmu_remap[i].base;
479 phys_addr_t end = start + dma_mmu_remap[i].size;
483 if (end > arm_lowmem_limit)
484 end = arm_lowmem_limit;
488 map.pfn = __phys_to_pfn(start);
489 map.virtual = __phys_to_virt(start);
490 map.length = end - start;
491 map.type = MT_MEMORY_DMA_READY;
494 * Clear previous low-memory mapping to ensure that the
495 * TLB does not see any conflicting entries, then flush
496 * the TLB of the old entries before creating new mappings.
498 * This ensures that any speculatively loaded TLB entries
499 * (even though they may be rare) can not cause any problems,
500 * and ensures that this code is architecturally compliant.
502 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
504 pmd_clear(pmd_off_k(addr));
506 flush_tlb_kernel_range(__phys_to_virt(start),
507 __phys_to_virt(end));
509 iotable_init(&map, 1);
513 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
516 struct page *page = virt_to_page(addr);
517 pgprot_t prot = *(pgprot_t *)data;
519 set_pte_ext(pte, mk_pte(page, prot), 0);
523 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
525 unsigned long start = (unsigned long) page_address(page);
526 unsigned end = start + size;
528 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
529 flush_tlb_kernel_range(start, end);
532 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
533 pgprot_t prot, struct page **ret_page,
534 const void *caller, bool want_vaddr)
539 * __alloc_remap_buffer is only called when the device is
542 page = __dma_alloc_buffer(dev, size, gfp, NORMAL);
548 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
550 __dma_free_buffer(page, size);
559 static void *__alloc_from_pool(size_t size, struct page **ret_page)
565 WARN(1, "coherent pool not initialised!\n");
569 val = gen_pool_alloc(atomic_pool, size);
571 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
573 *ret_page = phys_to_page(phys);
580 static bool __in_atomic_pool(void *start, size_t size)
582 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
585 static int __free_from_pool(void *start, size_t size)
587 if (!__in_atomic_pool(start, size))
590 gen_pool_free(atomic_pool, (unsigned long)start, size);
595 static void *__alloc_from_contiguous(struct device *dev, size_t size,
596 pgprot_t prot, struct page **ret_page,
597 const void *caller, bool want_vaddr,
598 int coherent_flag, gfp_t gfp)
600 unsigned long order = get_order(size);
601 size_t count = size >> PAGE_SHIFT;
605 page = dma_alloc_from_contiguous(dev, count, order, gfp);
609 __dma_clear_buffer(page, size, coherent_flag);
614 if (PageHighMem(page)) {
615 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
617 dma_release_from_contiguous(dev, page, count);
621 __dma_remap(page, size, prot);
622 ptr = page_address(page);
630 static void __free_from_contiguous(struct device *dev, struct page *page,
631 void *cpu_addr, size_t size, bool want_vaddr)
634 if (PageHighMem(page))
635 __dma_free_remap(cpu_addr, size);
637 __dma_remap(page, size, PAGE_KERNEL);
639 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
642 static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot)
644 prot = (attrs & DMA_ATTR_WRITE_COMBINE) ?
645 pgprot_writecombine(prot) :
646 pgprot_dmacoherent(prot);
652 #else /* !CONFIG_MMU */
656 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
657 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
658 #define __alloc_from_pool(size, ret_page) NULL
659 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv, coherent_flag, gfp) NULL
660 #define __free_from_pool(cpu_addr, size) do { } while (0)
661 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
662 #define __dma_free_remap(cpu_addr, size) do { } while (0)
664 #endif /* CONFIG_MMU */
666 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
667 struct page **ret_page)
670 /* __alloc_simple_buffer is only called when the device is coherent */
671 page = __dma_alloc_buffer(dev, size, gfp, COHERENT);
676 return page_address(page);
679 static void *simple_allocator_alloc(struct arm_dma_alloc_args *args,
680 struct page **ret_page)
682 return __alloc_simple_buffer(args->dev, args->size, args->gfp,
686 static void simple_allocator_free(struct arm_dma_free_args *args)
688 __dma_free_buffer(args->page, args->size);
691 static struct arm_dma_allocator simple_allocator = {
692 .alloc = simple_allocator_alloc,
693 .free = simple_allocator_free,
696 static void *cma_allocator_alloc(struct arm_dma_alloc_args *args,
697 struct page **ret_page)
699 return __alloc_from_contiguous(args->dev, args->size, args->prot,
700 ret_page, args->caller,
701 args->want_vaddr, args->coherent_flag,
705 static void cma_allocator_free(struct arm_dma_free_args *args)
707 __free_from_contiguous(args->dev, args->page, args->cpu_addr,
708 args->size, args->want_vaddr);
711 static struct arm_dma_allocator cma_allocator = {
712 .alloc = cma_allocator_alloc,
713 .free = cma_allocator_free,
716 static void *pool_allocator_alloc(struct arm_dma_alloc_args *args,
717 struct page **ret_page)
719 return __alloc_from_pool(args->size, ret_page);
722 static void pool_allocator_free(struct arm_dma_free_args *args)
724 __free_from_pool(args->cpu_addr, args->size);
727 static struct arm_dma_allocator pool_allocator = {
728 .alloc = pool_allocator_alloc,
729 .free = pool_allocator_free,
732 static void *remap_allocator_alloc(struct arm_dma_alloc_args *args,
733 struct page **ret_page)
735 return __alloc_remap_buffer(args->dev, args->size, args->gfp,
736 args->prot, ret_page, args->caller,
740 static void remap_allocator_free(struct arm_dma_free_args *args)
742 if (args->want_vaddr)
743 __dma_free_remap(args->cpu_addr, args->size);
745 __dma_free_buffer(args->page, args->size);
748 static struct arm_dma_allocator remap_allocator = {
749 .alloc = remap_allocator_alloc,
750 .free = remap_allocator_free,
753 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
754 gfp_t gfp, pgprot_t prot, bool is_coherent,
755 unsigned long attrs, const void *caller)
757 u64 mask = get_coherent_dma_mask(dev);
758 struct page *page = NULL;
760 bool allowblock, cma;
761 struct arm_dma_buffer *buf;
762 struct arm_dma_alloc_args args = {
764 .size = PAGE_ALIGN(size),
768 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
769 .coherent_flag = is_coherent ? COHERENT : NORMAL,
772 #ifdef CONFIG_DMA_API_DEBUG
773 u64 limit = (mask + 1) & ~mask;
774 if (limit && size >= limit) {
775 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
784 buf = kzalloc(sizeof(*buf),
785 gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
789 if (mask < 0xffffffffULL)
793 * Following is a work-around (a.k.a. hack) to prevent pages
794 * with __GFP_COMP being passed to split_page() which cannot
795 * handle them. The real problem is that this flag probably
796 * should be 0 on ARM as it is not supported on this
797 * platform; see CONFIG_HUGETLBFS.
799 gfp &= ~(__GFP_COMP);
802 *handle = DMA_ERROR_CODE;
803 allowblock = gfpflags_allow_blocking(gfp);
804 cma = allowblock ? dev_get_cma_area(dev) : false;
807 buf->allocator = &cma_allocator;
808 else if (nommu() || is_coherent)
809 buf->allocator = &simple_allocator;
811 buf->allocator = &remap_allocator;
813 buf->allocator = &pool_allocator;
815 addr = buf->allocator->alloc(&args, &page);
820 *handle = pfn_to_dma(dev, page_to_pfn(page));
821 buf->virt = args.want_vaddr ? addr : page;
823 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
824 list_add(&buf->list, &arm_dma_bufs);
825 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
830 return args.want_vaddr ? addr : page;
834 * Allocate DMA-coherent memory space and return both the kernel remapped
835 * virtual and bus address for that space.
837 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
838 gfp_t gfp, unsigned long attrs)
840 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
842 return __dma_alloc(dev, size, handle, gfp, prot, false,
843 attrs, __builtin_return_address(0));
846 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
847 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
849 return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true,
850 attrs, __builtin_return_address(0));
853 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
854 void *cpu_addr, dma_addr_t dma_addr, size_t size,
859 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
860 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
861 unsigned long pfn = dma_to_pfn(dev, dma_addr);
862 unsigned long off = vma->vm_pgoff;
864 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
867 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
868 ret = remap_pfn_range(vma, vma->vm_start,
870 vma->vm_end - vma->vm_start,
874 ret = vm_iomap_memory(vma, vma->vm_start,
875 (vma->vm_end - vma->vm_start));
876 #endif /* CONFIG_MMU */
882 * Create userspace mapping for the DMA-coherent memory.
884 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
885 void *cpu_addr, dma_addr_t dma_addr, size_t size,
888 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
891 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
892 void *cpu_addr, dma_addr_t dma_addr, size_t size,
896 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
897 #endif /* CONFIG_MMU */
898 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
902 * Free a buffer as defined by the above mapping.
904 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
905 dma_addr_t handle, unsigned long attrs,
908 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
909 struct arm_dma_buffer *buf;
910 struct arm_dma_free_args args = {
912 .size = PAGE_ALIGN(size),
913 .cpu_addr = cpu_addr,
915 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
918 buf = arm_dma_buffer_find(cpu_addr);
919 if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr))
922 buf->allocator->free(&args);
926 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
927 dma_addr_t handle, unsigned long attrs)
929 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
932 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
933 dma_addr_t handle, unsigned long attrs)
935 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
938 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
939 void *cpu_addr, dma_addr_t handle, size_t size,
942 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
945 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
949 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
953 static void dma_cache_maint_page(struct page *page, unsigned long offset,
954 size_t size, enum dma_data_direction dir,
955 void (*op)(const void *, size_t, int))
960 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
964 * A single sg entry may refer to multiple physically contiguous
965 * pages. But we still need to process highmem pages individually.
966 * If highmem is not configured then the bulk of this loop gets
973 page = pfn_to_page(pfn);
975 if (PageHighMem(page)) {
976 if (len + offset > PAGE_SIZE)
977 len = PAGE_SIZE - offset;
979 if (cache_is_vipt_nonaliasing()) {
980 vaddr = kmap_atomic(page);
981 op(vaddr + offset, len, dir);
982 kunmap_atomic(vaddr);
984 vaddr = kmap_high_get(page);
986 op(vaddr + offset, len, dir);
991 vaddr = page_address(page) + offset;
1001 * Make an area consistent for devices.
1002 * Note: Drivers should NOT use this function directly, as it will break
1003 * platforms with CONFIG_DMABOUNCE.
1004 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
1006 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
1007 size_t size, enum dma_data_direction dir)
1011 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
1013 paddr = page_to_phys(page) + off;
1014 if (dir == DMA_FROM_DEVICE) {
1015 outer_inv_range(paddr, paddr + size);
1017 outer_clean_range(paddr, paddr + size);
1019 /* FIXME: non-speculating: flush on bidirectional mappings? */
1022 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
1023 size_t size, enum dma_data_direction dir)
1025 phys_addr_t paddr = page_to_phys(page) + off;
1027 /* FIXME: non-speculating: not required */
1028 /* in any case, don't bother invalidating if DMA to device */
1029 if (dir != DMA_TO_DEVICE) {
1030 outer_inv_range(paddr, paddr + size);
1032 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
1036 * Mark the D-cache clean for these pages to avoid extra flushing.
1038 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
1042 pfn = page_to_pfn(page) + off / PAGE_SIZE;
1046 left -= PAGE_SIZE - off;
1048 while (left >= PAGE_SIZE) {
1049 page = pfn_to_page(pfn++);
1050 set_bit(PG_dcache_clean, &page->flags);
1057 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
1058 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1059 * @sg: list of buffers
1060 * @nents: number of buffers to map
1061 * @dir: DMA transfer direction
1063 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1064 * This is the scatter-gather version of the dma_map_single interface.
1065 * Here the scatter gather list elements are each tagged with the
1066 * appropriate dma address and length. They are obtained via
1067 * sg_dma_{address,length}.
1069 * Device ownership issues as mentioned for dma_map_single are the same
1072 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1073 enum dma_data_direction dir, unsigned long attrs)
1075 const struct dma_map_ops *ops = get_dma_ops(dev);
1076 struct scatterlist *s;
1079 for_each_sg(sg, s, nents, i) {
1080 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1081 s->dma_length = s->length;
1083 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
1084 s->length, dir, attrs);
1085 if (dma_mapping_error(dev, s->dma_address))
1091 for_each_sg(sg, s, i, j)
1092 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1097 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1098 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1099 * @sg: list of buffers
1100 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1101 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1103 * Unmap a set of streaming mode DMA translations. Again, CPU access
1104 * rules concerning calls here are the same as for dma_unmap_single().
1106 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1107 enum dma_data_direction dir, unsigned long attrs)
1109 const struct dma_map_ops *ops = get_dma_ops(dev);
1110 struct scatterlist *s;
1114 for_each_sg(sg, s, nents, i)
1115 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1119 * arm_dma_sync_sg_for_cpu
1120 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1121 * @sg: list of buffers
1122 * @nents: number of buffers to map (returned from dma_map_sg)
1123 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1125 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1126 int nents, enum dma_data_direction dir)
1128 const struct dma_map_ops *ops = get_dma_ops(dev);
1129 struct scatterlist *s;
1132 for_each_sg(sg, s, nents, i)
1133 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1138 * arm_dma_sync_sg_for_device
1139 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1140 * @sg: list of buffers
1141 * @nents: number of buffers to map (returned from dma_map_sg)
1142 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1144 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1145 int nents, enum dma_data_direction dir)
1147 const struct dma_map_ops *ops = get_dma_ops(dev);
1148 struct scatterlist *s;
1151 for_each_sg(sg, s, nents, i)
1152 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1157 * Return whether the given device DMA address mask can be supported
1158 * properly. For example, if your device can only drive the low 24-bits
1159 * during bus mastering, then you would pass 0x00ffffff as the mask
1162 int dma_supported(struct device *dev, u64 mask)
1164 return __dma_supported(dev, mask, false);
1166 EXPORT_SYMBOL(dma_supported);
1168 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1170 static int __init dma_debug_do_init(void)
1172 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1175 core_initcall(dma_debug_do_init);
1177 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1179 static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs)
1183 if (attrs & DMA_ATTR_PRIVILEGED)
1187 case DMA_BIDIRECTIONAL:
1188 return prot | IOMMU_READ | IOMMU_WRITE;
1190 return prot | IOMMU_READ;
1191 case DMA_FROM_DEVICE:
1192 return prot | IOMMU_WRITE;
1200 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1202 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1205 unsigned int order = get_order(size);
1206 unsigned int align = 0;
1207 unsigned int count, start;
1208 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1209 unsigned long flags;
1213 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1214 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1216 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1217 align = (1 << order) - 1;
1219 spin_lock_irqsave(&mapping->lock, flags);
1220 for (i = 0; i < mapping->nr_bitmaps; i++) {
1221 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1222 mapping->bits, 0, count, align);
1224 if (start > mapping->bits)
1227 bitmap_set(mapping->bitmaps[i], start, count);
1232 * No unused range found. Try to extend the existing mapping
1233 * and perform a second attempt to reserve an IO virtual
1234 * address range of size bytes.
1236 if (i == mapping->nr_bitmaps) {
1237 if (extend_iommu_mapping(mapping)) {
1238 spin_unlock_irqrestore(&mapping->lock, flags);
1239 return DMA_ERROR_CODE;
1242 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1243 mapping->bits, 0, count, align);
1245 if (start > mapping->bits) {
1246 spin_unlock_irqrestore(&mapping->lock, flags);
1247 return DMA_ERROR_CODE;
1250 bitmap_set(mapping->bitmaps[i], start, count);
1252 spin_unlock_irqrestore(&mapping->lock, flags);
1254 iova = mapping->base + (mapping_size * i);
1255 iova += start << PAGE_SHIFT;
1260 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1261 dma_addr_t addr, size_t size)
1263 unsigned int start, count;
1264 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1265 unsigned long flags;
1266 dma_addr_t bitmap_base;
1272 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1273 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1275 bitmap_base = mapping->base + mapping_size * bitmap_index;
1277 start = (addr - bitmap_base) >> PAGE_SHIFT;
1279 if (addr + size > bitmap_base + mapping_size) {
1281 * The address range to be freed reaches into the iova
1282 * range of the next bitmap. This should not happen as
1283 * we don't allow this in __alloc_iova (at the
1288 count = size >> PAGE_SHIFT;
1290 spin_lock_irqsave(&mapping->lock, flags);
1291 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1292 spin_unlock_irqrestore(&mapping->lock, flags);
1295 /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */
1296 static const int iommu_order_array[] = { 9, 8, 4, 0 };
1298 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1299 gfp_t gfp, unsigned long attrs,
1302 struct page **pages;
1303 int count = size >> PAGE_SHIFT;
1304 int array_size = count * sizeof(struct page *);
1308 if (array_size <= PAGE_SIZE)
1309 pages = kzalloc(array_size, GFP_KERNEL);
1311 pages = vzalloc(array_size);
1315 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS)
1317 unsigned long order = get_order(size);
1320 page = dma_alloc_from_contiguous(dev, count, order, gfp);
1324 __dma_clear_buffer(page, size, coherent_flag);
1326 for (i = 0; i < count; i++)
1327 pages[i] = page + i;
1332 /* Go straight to 4K chunks if caller says it's OK. */
1333 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
1334 order_idx = ARRAY_SIZE(iommu_order_array) - 1;
1337 * IOMMU can map any pages, so himem can also be used here
1339 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1344 order = iommu_order_array[order_idx];
1346 /* Drop down when we get small */
1347 if (__fls(count) < order) {
1353 /* See if it's easy to allocate a high-order chunk */
1354 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1356 /* Go down a notch at first sign of pressure */
1362 pages[i] = alloc_pages(gfp, 0);
1368 split_page(pages[i], order);
1371 pages[i + j] = pages[i] + j;
1374 __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag);
1376 count -= 1 << order;
1383 __free_pages(pages[i], 0);
1388 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1389 size_t size, unsigned long attrs)
1391 int count = size >> PAGE_SHIFT;
1394 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
1395 dma_release_from_contiguous(dev, pages[0], count);
1397 for (i = 0; i < count; i++)
1399 __free_pages(pages[i], 0);
1407 * Create a CPU mapping for a specified pages
1410 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1413 return dma_common_pages_remap(pages, size,
1414 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1418 * Create a mapping in device IO address space for specified pages
1421 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size,
1422 unsigned long attrs)
1424 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1425 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1426 dma_addr_t dma_addr, iova;
1429 dma_addr = __alloc_iova(mapping, size);
1430 if (dma_addr == DMA_ERROR_CODE)
1434 for (i = 0; i < count; ) {
1437 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1438 phys_addr_t phys = page_to_phys(pages[i]);
1439 unsigned int len, j;
1441 for (j = i + 1; j < count; j++, next_pfn++)
1442 if (page_to_pfn(pages[j]) != next_pfn)
1445 len = (j - i) << PAGE_SHIFT;
1446 ret = iommu_map(mapping->domain, iova, phys, len,
1447 __dma_info_to_prot(DMA_BIDIRECTIONAL, attrs));
1455 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1456 __free_iova(mapping, dma_addr, size);
1457 return DMA_ERROR_CODE;
1460 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1462 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1465 * add optional in-page offset from iova to size and align
1466 * result to page size
1468 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1471 iommu_unmap(mapping->domain, iova, size);
1472 __free_iova(mapping, iova, size);
1476 static struct page **__atomic_get_pages(void *addr)
1481 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1482 page = phys_to_page(phys);
1484 return (struct page **)page;
1487 static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs)
1489 struct vm_struct *area;
1491 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1492 return __atomic_get_pages(cpu_addr);
1494 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1497 area = find_vm_area(cpu_addr);
1498 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1503 static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
1504 dma_addr_t *handle, int coherent_flag,
1505 unsigned long attrs)
1510 if (coherent_flag == COHERENT)
1511 addr = __alloc_simple_buffer(dev, size, gfp, &page);
1513 addr = __alloc_from_pool(size, &page);
1517 *handle = __iommu_create_mapping(dev, &page, size, attrs);
1518 if (*handle == DMA_ERROR_CODE)
1524 __free_from_pool(addr, size);
1528 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1529 dma_addr_t handle, size_t size, int coherent_flag)
1531 __iommu_remove_mapping(dev, handle, size);
1532 if (coherent_flag == COHERENT)
1533 __dma_free_buffer(virt_to_page(cpu_addr), size);
1535 __free_from_pool(cpu_addr, size);
1538 static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size,
1539 dma_addr_t *handle, gfp_t gfp, unsigned long attrs,
1542 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1543 struct page **pages;
1546 *handle = DMA_ERROR_CODE;
1547 size = PAGE_ALIGN(size);
1549 if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp))
1550 return __iommu_alloc_simple(dev, size, gfp, handle,
1551 coherent_flag, attrs);
1554 * Following is a work-around (a.k.a. hack) to prevent pages
1555 * with __GFP_COMP being passed to split_page() which cannot
1556 * handle them. The real problem is that this flag probably
1557 * should be 0 on ARM as it is not supported on this
1558 * platform; see CONFIG_HUGETLBFS.
1560 gfp &= ~(__GFP_COMP);
1562 pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag);
1566 *handle = __iommu_create_mapping(dev, pages, size, attrs);
1567 if (*handle == DMA_ERROR_CODE)
1570 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1573 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1574 __builtin_return_address(0));
1581 __iommu_remove_mapping(dev, *handle, size);
1583 __iommu_free_buffer(dev, pages, size, attrs);
1587 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1588 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1590 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL);
1593 static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size,
1594 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1596 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT);
1599 static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1600 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1601 unsigned long attrs)
1603 unsigned long uaddr = vma->vm_start;
1604 unsigned long usize = vma->vm_end - vma->vm_start;
1605 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1606 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1607 unsigned long off = vma->vm_pgoff;
1612 if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off)
1618 int ret = vm_insert_page(vma, uaddr, *pages++);
1620 pr_err("Remapping memory failed: %d\n", ret);
1625 } while (usize > 0);
1629 static int arm_iommu_mmap_attrs(struct device *dev,
1630 struct vm_area_struct *vma, void *cpu_addr,
1631 dma_addr_t dma_addr, size_t size, unsigned long attrs)
1633 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1635 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1638 static int arm_coherent_iommu_mmap_attrs(struct device *dev,
1639 struct vm_area_struct *vma, void *cpu_addr,
1640 dma_addr_t dma_addr, size_t size, unsigned long attrs)
1642 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1646 * free a page as defined by the above mapping.
1647 * Must not be called with IRQs disabled.
1649 void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1650 dma_addr_t handle, unsigned long attrs, int coherent_flag)
1652 struct page **pages;
1653 size = PAGE_ALIGN(size);
1655 if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) {
1656 __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag);
1660 pages = __iommu_get_pages(cpu_addr, attrs);
1662 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1666 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) {
1667 dma_common_free_remap(cpu_addr, size,
1668 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1671 __iommu_remove_mapping(dev, handle, size);
1672 __iommu_free_buffer(dev, pages, size, attrs);
1675 void arm_iommu_free_attrs(struct device *dev, size_t size,
1676 void *cpu_addr, dma_addr_t handle, unsigned long attrs)
1678 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL);
1681 void arm_coherent_iommu_free_attrs(struct device *dev, size_t size,
1682 void *cpu_addr, dma_addr_t handle, unsigned long attrs)
1684 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT);
1687 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1688 void *cpu_addr, dma_addr_t dma_addr,
1689 size_t size, unsigned long attrs)
1691 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1692 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1697 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1702 * Map a part of the scatter-gather list into contiguous io address space
1704 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1705 size_t size, dma_addr_t *handle,
1706 enum dma_data_direction dir, unsigned long attrs,
1709 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1710 dma_addr_t iova, iova_base;
1713 struct scatterlist *s;
1716 size = PAGE_ALIGN(size);
1717 *handle = DMA_ERROR_CODE;
1719 iova_base = iova = __alloc_iova(mapping, size);
1720 if (iova == DMA_ERROR_CODE)
1723 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1724 phys_addr_t phys = page_to_phys(sg_page(s));
1725 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1727 if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1728 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1730 prot = __dma_info_to_prot(dir, attrs);
1732 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1735 count += len >> PAGE_SHIFT;
1738 *handle = iova_base;
1742 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1743 __free_iova(mapping, iova_base, size);
1747 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1748 enum dma_data_direction dir, unsigned long attrs,
1751 struct scatterlist *s = sg, *dma = sg, *start = sg;
1753 unsigned int offset = s->offset;
1754 unsigned int size = s->offset + s->length;
1755 unsigned int max = dma_get_max_seg_size(dev);
1757 for (i = 1; i < nents; i++) {
1760 s->dma_address = DMA_ERROR_CODE;
1763 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1764 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1765 dir, attrs, is_coherent) < 0)
1768 dma->dma_address += offset;
1769 dma->dma_length = size - offset;
1771 size = offset = s->offset;
1778 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1782 dma->dma_address += offset;
1783 dma->dma_length = size - offset;
1788 for_each_sg(sg, s, count, i)
1789 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1794 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1795 * @dev: valid struct device pointer
1796 * @sg: list of buffers
1797 * @nents: number of buffers to map
1798 * @dir: DMA transfer direction
1800 * Map a set of i/o coherent buffers described by scatterlist in streaming
1801 * mode for DMA. The scatter gather list elements are merged together (if
1802 * possible) and tagged with the appropriate dma address and length. They are
1803 * obtained via sg_dma_{address,length}.
1805 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1806 int nents, enum dma_data_direction dir, unsigned long attrs)
1808 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1812 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1813 * @dev: valid struct device pointer
1814 * @sg: list of buffers
1815 * @nents: number of buffers to map
1816 * @dir: DMA transfer direction
1818 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1819 * The scatter gather list elements are merged together (if possible) and
1820 * tagged with the appropriate dma address and length. They are obtained via
1821 * sg_dma_{address,length}.
1823 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1824 int nents, enum dma_data_direction dir, unsigned long attrs)
1826 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1829 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1830 int nents, enum dma_data_direction dir,
1831 unsigned long attrs, bool is_coherent)
1833 struct scatterlist *s;
1836 for_each_sg(sg, s, nents, i) {
1838 __iommu_remove_mapping(dev, sg_dma_address(s),
1840 if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1841 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1847 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1848 * @dev: valid struct device pointer
1849 * @sg: list of buffers
1850 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1851 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1853 * Unmap a set of streaming mode DMA translations. Again, CPU access
1854 * rules concerning calls here are the same as for dma_unmap_single().
1856 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1857 int nents, enum dma_data_direction dir,
1858 unsigned long attrs)
1860 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1864 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1865 * @dev: valid struct device pointer
1866 * @sg: list of buffers
1867 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1868 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1870 * Unmap a set of streaming mode DMA translations. Again, CPU access
1871 * rules concerning calls here are the same as for dma_unmap_single().
1873 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1874 enum dma_data_direction dir,
1875 unsigned long attrs)
1877 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1881 * arm_iommu_sync_sg_for_cpu
1882 * @dev: valid struct device pointer
1883 * @sg: list of buffers
1884 * @nents: number of buffers to map (returned from dma_map_sg)
1885 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1887 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1888 int nents, enum dma_data_direction dir)
1890 struct scatterlist *s;
1893 for_each_sg(sg, s, nents, i)
1894 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1899 * arm_iommu_sync_sg_for_device
1900 * @dev: valid struct device pointer
1901 * @sg: list of buffers
1902 * @nents: number of buffers to map (returned from dma_map_sg)
1903 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1905 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1906 int nents, enum dma_data_direction dir)
1908 struct scatterlist *s;
1911 for_each_sg(sg, s, nents, i)
1912 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1917 * arm_coherent_iommu_map_page
1918 * @dev: valid struct device pointer
1919 * @page: page that buffer resides in
1920 * @offset: offset into page for start of buffer
1921 * @size: size of buffer to map
1922 * @dir: DMA transfer direction
1924 * Coherent IOMMU aware version of arm_dma_map_page()
1926 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1927 unsigned long offset, size_t size, enum dma_data_direction dir,
1928 unsigned long attrs)
1930 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1931 dma_addr_t dma_addr;
1932 int ret, prot, len = PAGE_ALIGN(size + offset);
1934 dma_addr = __alloc_iova(mapping, len);
1935 if (dma_addr == DMA_ERROR_CODE)
1938 prot = __dma_info_to_prot(dir, attrs);
1940 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1944 return dma_addr + offset;
1946 __free_iova(mapping, dma_addr, len);
1947 return DMA_ERROR_CODE;
1951 * arm_iommu_map_page
1952 * @dev: valid struct device pointer
1953 * @page: page that buffer resides in
1954 * @offset: offset into page for start of buffer
1955 * @size: size of buffer to map
1956 * @dir: DMA transfer direction
1958 * IOMMU aware version of arm_dma_map_page()
1960 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1961 unsigned long offset, size_t size, enum dma_data_direction dir,
1962 unsigned long attrs)
1964 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1965 __dma_page_cpu_to_dev(page, offset, size, dir);
1967 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1971 * arm_coherent_iommu_unmap_page
1972 * @dev: valid struct device pointer
1973 * @handle: DMA address of buffer
1974 * @size: size of buffer (same as passed to dma_map_page)
1975 * @dir: DMA transfer direction (same as passed to dma_map_page)
1977 * Coherent IOMMU aware version of arm_dma_unmap_page()
1979 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1980 size_t size, enum dma_data_direction dir, unsigned long attrs)
1982 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1983 dma_addr_t iova = handle & PAGE_MASK;
1984 int offset = handle & ~PAGE_MASK;
1985 int len = PAGE_ALIGN(size + offset);
1990 iommu_unmap(mapping->domain, iova, len);
1991 __free_iova(mapping, iova, len);
1995 * arm_iommu_unmap_page
1996 * @dev: valid struct device pointer
1997 * @handle: DMA address of buffer
1998 * @size: size of buffer (same as passed to dma_map_page)
1999 * @dir: DMA transfer direction (same as passed to dma_map_page)
2001 * IOMMU aware version of arm_dma_unmap_page()
2003 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
2004 size_t size, enum dma_data_direction dir, unsigned long attrs)
2006 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2007 dma_addr_t iova = handle & PAGE_MASK;
2008 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2009 int offset = handle & ~PAGE_MASK;
2010 int len = PAGE_ALIGN(size + offset);
2015 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
2016 __dma_page_dev_to_cpu(page, offset, size, dir);
2018 iommu_unmap(mapping->domain, iova, len);
2019 __free_iova(mapping, iova, len);
2023 * arm_iommu_map_resource - map a device resource for DMA
2024 * @dev: valid struct device pointer
2025 * @phys_addr: physical address of resource
2026 * @size: size of resource to map
2027 * @dir: DMA transfer direction
2029 static dma_addr_t arm_iommu_map_resource(struct device *dev,
2030 phys_addr_t phys_addr, size_t size,
2031 enum dma_data_direction dir, unsigned long attrs)
2033 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2034 dma_addr_t dma_addr;
2036 phys_addr_t addr = phys_addr & PAGE_MASK;
2037 unsigned int offset = phys_addr & ~PAGE_MASK;
2038 size_t len = PAGE_ALIGN(size + offset);
2040 dma_addr = __alloc_iova(mapping, len);
2041 if (dma_addr == DMA_ERROR_CODE)
2044 prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO;
2046 ret = iommu_map(mapping->domain, dma_addr, addr, len, prot);
2050 return dma_addr + offset;
2052 __free_iova(mapping, dma_addr, len);
2053 return DMA_ERROR_CODE;
2057 * arm_iommu_unmap_resource - unmap a device DMA resource
2058 * @dev: valid struct device pointer
2059 * @dma_handle: DMA address to resource
2060 * @size: size of resource to map
2061 * @dir: DMA transfer direction
2063 static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle,
2064 size_t size, enum dma_data_direction dir,
2065 unsigned long attrs)
2067 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2068 dma_addr_t iova = dma_handle & PAGE_MASK;
2069 unsigned int offset = dma_handle & ~PAGE_MASK;
2070 size_t len = PAGE_ALIGN(size + offset);
2075 iommu_unmap(mapping->domain, iova, len);
2076 __free_iova(mapping, iova, len);
2079 static void arm_iommu_sync_single_for_cpu(struct device *dev,
2080 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2082 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2083 dma_addr_t iova = handle & PAGE_MASK;
2084 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2085 unsigned int offset = handle & ~PAGE_MASK;
2090 __dma_page_dev_to_cpu(page, offset, size, dir);
2093 static void arm_iommu_sync_single_for_device(struct device *dev,
2094 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2096 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2097 dma_addr_t iova = handle & PAGE_MASK;
2098 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2099 unsigned int offset = handle & ~PAGE_MASK;
2104 __dma_page_cpu_to_dev(page, offset, size, dir);
2107 const struct dma_map_ops iommu_ops = {
2108 .alloc = arm_iommu_alloc_attrs,
2109 .free = arm_iommu_free_attrs,
2110 .mmap = arm_iommu_mmap_attrs,
2111 .get_sgtable = arm_iommu_get_sgtable,
2113 .map_page = arm_iommu_map_page,
2114 .unmap_page = arm_iommu_unmap_page,
2115 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
2116 .sync_single_for_device = arm_iommu_sync_single_for_device,
2118 .map_sg = arm_iommu_map_sg,
2119 .unmap_sg = arm_iommu_unmap_sg,
2120 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
2121 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
2123 .map_resource = arm_iommu_map_resource,
2124 .unmap_resource = arm_iommu_unmap_resource,
2127 const struct dma_map_ops iommu_coherent_ops = {
2128 .alloc = arm_coherent_iommu_alloc_attrs,
2129 .free = arm_coherent_iommu_free_attrs,
2130 .mmap = arm_coherent_iommu_mmap_attrs,
2131 .get_sgtable = arm_iommu_get_sgtable,
2133 .map_page = arm_coherent_iommu_map_page,
2134 .unmap_page = arm_coherent_iommu_unmap_page,
2136 .map_sg = arm_coherent_iommu_map_sg,
2137 .unmap_sg = arm_coherent_iommu_unmap_sg,
2139 .map_resource = arm_iommu_map_resource,
2140 .unmap_resource = arm_iommu_unmap_resource,
2144 * arm_iommu_create_mapping
2145 * @bus: pointer to the bus holding the client device (for IOMMU calls)
2146 * @base: start address of the valid IO address space
2147 * @size: maximum size of the valid IO address space
2149 * Creates a mapping structure which holds information about used/unused
2150 * IO address ranges, which is required to perform memory allocation and
2151 * mapping with IOMMU aware functions.
2153 * The client device need to be attached to the mapping with
2154 * arm_iommu_attach_device function.
2156 struct dma_iommu_mapping *
2157 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
2159 unsigned int bits = size >> PAGE_SHIFT;
2160 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
2161 struct dma_iommu_mapping *mapping;
2165 /* currently only 32-bit DMA address space is supported */
2166 if (size > DMA_BIT_MASK(32) + 1)
2167 return ERR_PTR(-ERANGE);
2170 return ERR_PTR(-EINVAL);
2172 if (bitmap_size > PAGE_SIZE) {
2173 extensions = bitmap_size / PAGE_SIZE;
2174 bitmap_size = PAGE_SIZE;
2177 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
2181 mapping->bitmap_size = bitmap_size;
2182 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
2184 if (!mapping->bitmaps)
2187 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
2188 if (!mapping->bitmaps[0])
2191 mapping->nr_bitmaps = 1;
2192 mapping->extensions = extensions;
2193 mapping->base = base;
2194 mapping->bits = BITS_PER_BYTE * bitmap_size;
2196 spin_lock_init(&mapping->lock);
2198 mapping->domain = iommu_domain_alloc(bus);
2199 if (!mapping->domain)
2202 kref_init(&mapping->kref);
2205 kfree(mapping->bitmaps[0]);
2207 kfree(mapping->bitmaps);
2211 return ERR_PTR(err);
2213 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
2215 static void release_iommu_mapping(struct kref *kref)
2218 struct dma_iommu_mapping *mapping =
2219 container_of(kref, struct dma_iommu_mapping, kref);
2221 iommu_domain_free(mapping->domain);
2222 for (i = 0; i < mapping->nr_bitmaps; i++)
2223 kfree(mapping->bitmaps[i]);
2224 kfree(mapping->bitmaps);
2228 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
2232 if (mapping->nr_bitmaps >= mapping->extensions)
2235 next_bitmap = mapping->nr_bitmaps;
2236 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
2238 if (!mapping->bitmaps[next_bitmap])
2241 mapping->nr_bitmaps++;
2246 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
2249 kref_put(&mapping->kref, release_iommu_mapping);
2251 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2253 static int __arm_iommu_attach_device(struct device *dev,
2254 struct dma_iommu_mapping *mapping)
2258 err = iommu_attach_device(mapping->domain, dev);
2262 kref_get(&mapping->kref);
2263 to_dma_iommu_mapping(dev) = mapping;
2265 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2270 * arm_iommu_attach_device
2271 * @dev: valid struct device pointer
2272 * @mapping: io address space mapping structure (returned from
2273 * arm_iommu_create_mapping)
2275 * Attaches specified io address space mapping to the provided device.
2276 * This replaces the dma operations (dma_map_ops pointer) with the
2277 * IOMMU aware version.
2279 * More than one client might be attached to the same io address space
2282 int arm_iommu_attach_device(struct device *dev,
2283 struct dma_iommu_mapping *mapping)
2287 err = __arm_iommu_attach_device(dev, mapping);
2291 set_dma_ops(dev, &iommu_ops);
2294 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2296 static void __arm_iommu_detach_device(struct device *dev)
2298 struct dma_iommu_mapping *mapping;
2300 mapping = to_dma_iommu_mapping(dev);
2302 dev_warn(dev, "Not attached\n");
2306 iommu_detach_device(mapping->domain, dev);
2307 kref_put(&mapping->kref, release_iommu_mapping);
2308 to_dma_iommu_mapping(dev) = NULL;
2310 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2314 * arm_iommu_detach_device
2315 * @dev: valid struct device pointer
2317 * Detaches the provided device from a previously attached map.
2318 * This voids the dma operations (dma_map_ops pointer)
2320 void arm_iommu_detach_device(struct device *dev)
2322 __arm_iommu_detach_device(dev);
2323 set_dma_ops(dev, NULL);
2325 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2327 static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2329 return coherent ? &iommu_coherent_ops : &iommu_ops;
2332 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2333 const struct iommu_ops *iommu)
2335 struct dma_iommu_mapping *mapping;
2340 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2341 if (IS_ERR(mapping)) {
2342 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2343 size, dev_name(dev));
2347 if (__arm_iommu_attach_device(dev, mapping)) {
2348 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2350 arm_iommu_release_mapping(mapping);
2357 static void arm_teardown_iommu_dma_ops(struct device *dev)
2359 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2364 __arm_iommu_detach_device(dev);
2365 arm_iommu_release_mapping(mapping);
2370 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2371 const struct iommu_ops *iommu)
2376 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2378 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2380 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2382 static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2384 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2387 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2388 const struct iommu_ops *iommu, bool coherent)
2390 const struct dma_map_ops *dma_ops;
2392 dev->archdata.dma_coherent = coherent;
2393 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2394 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2396 dma_ops = arm_get_dma_map_ops(coherent);
2398 set_dma_ops(dev, dma_ops);
2401 void arch_teardown_dma_ops(struct device *dev)
2403 arm_teardown_iommu_dma_ops(dev);