arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0>;
  48                 };
  49
  50                 CPU1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x1>;
  54                 };
  55
  56                 CPU2: cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         reg = <0x2>;
  60                 };
  61
  62                 CPU3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x3>;
  66                 };
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  75         };
  76
  77         soc: soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0 0 0xffffffff>;
  81                 compatible = "simple-bus";
  82
  83                 restart@4ab000 {
  84                         compatible = "qcom,pshold";
  85                         reg = <0x4ab000 0x4>;
  86                 };
  87
  88                 msmgpio: pinctrl@1000000 {
  89                         compatible = "qcom,msm8916-pinctrl";
  90                         reg = <0x1000000 0x300000>;
  91                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  92                         gpio-controller;
  93                         #gpio-cells = <2>;
  94                         interrupt-controller;
  95                         #interrupt-cells = <2>;
  96                 };
  97
  98                 gcc: qcom,gcc@1800000 {
  99                         compatible = "qcom,gcc-msm8916";
 100                         #clock-cells = <1>;
 101                         #reset-cells = <1>;
 102                         #power-domain-cells = <1>;
 103                         reg = <0x1800000 0x80000>;
 104                 };
 105
 106                 blsp1_uart2: serial@78b0000 {
 107                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 108                         reg = <0x78b0000 0x200>;
 109                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 110                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 111                         clock-names = "core", "iface";
 112                         status = "disabled";
 113                 };
 114
 115                 blsp_dma: dma@7884000 {
 116                         compatible = "qcom,bam-v1.7.0";
 117                         reg = <0x07884000 0x23000>;
 118                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 120                         clock-names = "bam_clk";
 121                         #dma-cells = <1>;
 122                         qcom,ee = <0>;
 123                         status = "disabled";
 124                 };
 125
 126                 blsp_spi1: spi@78b5000 {
 127                         compatible = "qcom,spi-qup-v2.2.1";
 128                         reg = <0x078b5000 0x600>;
 129                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 130                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 131                                  <&gcc GCC_BLSP1_AHB_CLK>;
 132                         clock-names = "core", "iface";
 133                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 134                         dma-names = "rx", "tx";
 135                         pinctrl-names = "default", "sleep";
 136                         pinctrl-0 = <&spi1_default>;
 137                         pinctrl-1 = <&spi1_sleep>;
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         status = "disabled";
 141                 };
 142
 143                 blsp_spi2: spi@78b6000 {
 144                         compatible = "qcom,spi-qup-v2.2.1";
 145                         reg = <0x078b6000 0x600>;
 146                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 148                                  <&gcc GCC_BLSP1_AHB_CLK>;
 149                         clock-names = "core", "iface";
 150                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 151                         dma-names = "rx", "tx";
 152                         pinctrl-names = "default", "sleep";
 153                         pinctrl-0 = <&spi2_default>;
 154                         pinctrl-1 = <&spi2_sleep>;
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         status = "disabled";
 158                 };
 159
 160                 blsp_spi3: spi@78b7000 {
 161                         compatible = "qcom,spi-qup-v2.2.1";
 162                         reg = <0x078b7000 0x600>;
 163                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 165                                  <&gcc GCC_BLSP1_AHB_CLK>;
 166                         clock-names = "core", "iface";
 167                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 168                         dma-names = "rx", "tx";
 169                         pinctrl-names = "default", "sleep";
 170                         pinctrl-0 = <&spi3_default>;
 171                         pinctrl-1 = <&spi3_sleep>;
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         status = "disabled";
 175                 };
 176
 177                 blsp_spi4: spi@78b8000 {
 178                         compatible = "qcom,spi-qup-v2.2.1";
 179                         reg = <0x078b8000 0x600>;
 180                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 182                                  <&gcc GCC_BLSP1_AHB_CLK>;
 183                         clock-names = "core", "iface";
 184                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 185                         dma-names = "rx", "tx";
 186                         pinctrl-names = "default", "sleep";
 187                         pinctrl-0 = <&spi4_default>;
 188                         pinctrl-1 = <&spi4_sleep>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         status = "disabled";
 192                 };
 193
 194                 blsp_spi5: spi@78b9000 {
 195                         compatible = "qcom,spi-qup-v2.2.1";
 196                         reg = <0x078b9000 0x600>;
 197                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 199                                  <&gcc GCC_BLSP1_AHB_CLK>;
 200                         clock-names = "core", "iface";
 201                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 202                         dma-names = "rx", "tx";
 203                         pinctrl-names = "default", "sleep";
 204                         pinctrl-0 = <&spi5_default>;
 205                         pinctrl-1 = <&spi5_sleep>;
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         status = "disabled";
 209                 };
 210
 211                 blsp_spi6: spi@78ba000 {
 212                         compatible = "qcom,spi-qup-v2.2.1";
 213                         reg = <0x078ba000 0x600>;
 214                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 216                                  <&gcc GCC_BLSP1_AHB_CLK>;
 217                         clock-names = "core", "iface";
 218                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 219                         dma-names = "rx", "tx";
 220                         pinctrl-names = "default", "sleep";
 221                         pinctrl-0 = <&spi6_default>;
 222                         pinctrl-1 = <&spi6_sleep>;
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         status = "disabled";
 226                 };
 227
 228                 blsp_i2c4: i2c@78b8000 {
 229                         compatible = "qcom,i2c-qup-v2.2.1";
 230                         reg = <0x78b8000 0x1000>;
 231                         interrupts = <GIC_SPI 98 0>;
 232                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 233                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 234                         clock-names = "iface", "core";
 235                         pinctrl-names = "default", "sleep";
 236                         pinctrl-0 = <&i2c4_default>;
 237                         pinctrl-1 = <&i2c4_sleep>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241                 };
 242
 243                 sdhc_1: sdhci@07824000 {
 244                         compatible = "qcom,sdhci-msm-v4";
 245                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 246                         reg-names = "hc_mem", "core_mem";
 247
 248                         interrupts = <0 123 0>, <0 138 0>;
 249                         interrupt-names = "hc_irq", "pwr_irq";
 250                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 251                                  <&gcc GCC_SDCC1_AHB_CLK>;
 252                         clock-names = "core", "iface";
 253                         bus-width = <8>;
 254                         non-removable;
 255                         status = "disabled";
 256                 };
 257
 258                 sdhc_2: sdhci@07864000 {
 259                         compatible = "qcom,sdhci-msm-v4";
 260                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 261                         reg-names = "hc_mem", "core_mem";
 262
 263                         interrupts = <0 125 0>, <0 221 0>;
 264                         interrupt-names = "hc_irq", "pwr_irq";
 265                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 266                                  <&gcc GCC_SDCC2_AHB_CLK>;
 267                         clock-names = "core", "iface";
 268                         bus-width = <4>;
 269                         status = "disabled";
 270                 };
 271
 272                 usb_dev: usb@78d9000 {
 273                         compatible = "qcom,ci-hdrc";
 274                         reg = <0x78d9000 0x400>;
 275                         dr_mode = "peripheral";
 276                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 277                         usb-phy = <&usb_otg>;
 278                         status = "disabled";
 279                 };
 280
 281                 usb_host: ehci@78d9000 {
 282                         compatible = "qcom,ehci-host";
 283                         reg = <0x78d9000 0x400>;
 284                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 285                         usb-phy = <&usb_otg>;
 286                         status = "disabled";
 287                 };
 288
 289                 usb_otg: phy@78d9000 {
 290                         compatible = "qcom,usb-otg-snps";
 291                         reg = <0x78d9000 0x400>;
 292                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 293                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 294
 295                         qcom,vdd-levels = <1 5 7>;
 296                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 297                         dr_mode = "peripheral";
 298                         qcom,otg-control = <2>; // PMIC
 299
 300                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 301                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 302                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 303                         clock-names = "iface", "core", "sleep";
 304
 305                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 306                                  <&gcc GCC_USB_HS_BCR>;
 307                         reset-names = "phy", "link";
 308                         status = "disabled";
 309                 };
 310
 311                 intc: interrupt-controller@b000000 {
 312                         compatible = "qcom,msm-qgic2";
 313                         interrupt-controller;
 314                         #interrupt-cells = <3>;
 315                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 316                 };
 317
 318                 timer@b020000 {
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         ranges;
 322                         compatible = "arm,armv7-timer-mem";
 323                         reg = <0xb020000 0x1000>;
 324                         clock-frequency = <19200000>;
 325
 326                         frame@b021000 {
 327                                 frame-number = <0>;
 328                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 329                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 330                                 reg = <0xb021000 0x1000>,
 331                                       <0xb022000 0x1000>;
 332                         };
 333
 334                         frame@b023000 {
 335                                 frame-number = <1>;
 336                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 337                                 reg = <0xb023000 0x1000>;
 338                                 status = "disabled";
 339                         };
 340
 341                         frame@b024000 {
 342                                 frame-number = <2>;
 343                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 344                                 reg = <0xb024000 0x1000>;
 345                                 status = "disabled";
 346                         };
 347
 348                         frame@b025000 {
 349                                 frame-number = <3>;
 350                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 351                                 reg = <0xb025000 0x1000>;
 352                                 status = "disabled";
 353                         };
 354
 355                         frame@b026000 {
 356                                 frame-number = <4>;
 357                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 358                                 reg = <0xb026000 0x1000>;
 359                                 status = "disabled";
 360                         };
 361
 362                         frame@b027000 {
 363                                 frame-number = <5>;
 364                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 365                                 reg = <0xb027000 0x1000>;
 366                                 status = "disabled";
 367                         };
 368
 369                         frame@b028000 {
 370                                 frame-number = <6>;
 371                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 372                                 reg = <0xb028000 0x1000>;
 373                                 status = "disabled";
 374                         };
 375                 };
 376
 377                 spmi_bus: spmi@200f000 {
 378                         compatible = "qcom,spmi-pmic-arb";
 379                         reg = <0x200f000 0x001000>,
 380                               <0x2400000 0x400000>,
 381                               <0x2c00000 0x400000>,
 382                               <0x3800000 0x200000>,
 383                               <0x200a000 0x002100>;
 384                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 385                         interrupt-names = "periph_irq";
 386                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 387                         qcom,ee = <0>;
 388                         qcom,channel = <0>;
 389                         #address-cells = <2>;
 390                         #size-cells = <0>;
 391                         interrupt-controller;
 392                         #interrupt-cells = <4>;
 393                 };
 394         };
 395 };
 396
 397 #include "msm8916-pins.dtsi"