arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         pmu_a53 {
 157                 compatible = "arm,cortex-a53-pmu";
 158                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 159         };
 160
 161         pmu_a72 {
 162                 compatible = "arm,cortex-a72-pmu";
 163                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 174                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 175                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 176                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 177                 arm,no-tick-in-suspend;
 178         };
 179
 180         xin24m: xin24m {
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <24000000>;
 183                 clock-output-names = "xin24m";
 184                 #clock-cells = <0>;
 185         };
 186
 187         amba {
 188                 compatible = "simple-bus";
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192
 193                 dmac_bus: dma-controller@ff6d0000 {
 194                         compatible = "arm,pl330", "arm,primecell";
 195                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 196                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 197                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 198                         #dma-cells = <1>;
 199                         clocks = <&cru ACLK_DMAC0_PERILP>;
 200                         clock-names = "apb_pclk";
 201                 };
 202
 203                 dmac_peri: dma-controller@ff6e0000 {
 204                         compatible = "arm,pl330", "arm,primecell";
 205                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 206                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 207                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 208                         #dma-cells = <1>;
 209                         clocks = <&cru ACLK_DMAC1_PERILP>;
 210                         clock-names = "apb_pclk";
 211                 };
 212         };
 213
 214         gmac: ethernet@fe300000 {
 215                 compatible = "rockchip,rk3399-gmac";
 216                 reg = <0x0 0xfe300000 0x0 0x10000>;
 217                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 218                 interrupt-names = "macirq";
 219                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 220                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 221                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 222                          <&cru PCLK_GMAC>;
 223                 clock-names = "stmmaceth", "mac_clk_rx",
 224                               "mac_clk_tx", "clk_mac_ref",
 225                               "clk_mac_refout", "aclk_mac",
 226                               "pclk_mac";
 227                 power-domains = <&power RK3399_PD_GMAC>;
 228                 resets = <&cru SRST_A_GMAC>;
 229                 reset-names = "stmmaceth";
 230                 rockchip,grf = <&grf>;
 231                 status = "disabled";
 232         };
 233
 234         sdio0: dwmmc@fe310000 {
 235                 compatible = "rockchip,rk3399-dw-mshc",
 236                              "rockchip,rk3288-dw-mshc";
 237                 reg = <0x0 0xfe310000 0x0 0x4000>;
 238                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 clock-freq-min-max = <400000 150000000>;
 240                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 241                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 242                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 243                 fifo-depth = <0x100>;
 244                 status = "disabled";
 245         };
 246
 247         sdmmc: dwmmc@fe320000 {
 248                 compatible = "rockchip,rk3399-dw-mshc",
 249                              "rockchip,rk3288-dw-mshc";
 250                 reg = <0x0 0xfe320000 0x0 0x4000>;
 251                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 252                 clock-freq-min-max = <400000 150000000>;
 253                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 254                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 status = "disabled";
 258         };
 259
 260         sdhci: sdhci@fe330000 {
 261                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 262                 reg = <0x0 0xfe330000 0x0 0x10000>;
 263                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 264                 arasan,soc-ctl-syscon = <&grf>;
 265                 assigned-clocks = <&cru SCLK_EMMC>;
 266                 assigned-clock-rates = <200000000>;
 267                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 268                 clock-names = "clk_xin", "clk_ahb";
 269                 clock-output-names = "emmc_cardclock";
 270                 #clock-cells = <0>;
 271                 phys = <&emmc_phy>;
 272                 phy-names = "phy_arasan";
 273                 status = "disabled";
 274         };
 275
 276         pcie0: pcie@f8000000 {
 277                 compatible = "rockchip,rk3399-pcie";
 278                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 279                       <0x0 0xfd000000 0x0 0x1000000>;
 280                 reg-names = "axi-base", "apb-base";
 281                 #address-cells = <3>;
 282                 #size-cells = <2>;
 283                 #interrupt-cells = <1>;
 284                 bus-range = <0x0 0x1>;
 285                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 286                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 287                 clock-names = "aclk", "aclk-perf",
 288                               "hclk", "pm";
 289                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 290                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 291                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 292                 interrupt-names = "sys", "legacy", "client";
 293                 interrupt-map-mask = <0 0 0 7>;
 294                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 295                                 <0 0 0 2 &pcie0_intc 1>,
 296                                 <0 0 0 3 &pcie0_intc 2>,
 297                                 <0 0 0 4 &pcie0_intc 3>;
 298                 msi-map = <0x0 &its 0x0 0x1000>;
 299                 phys = <&pcie_phy>;
 300                 phy-names = "pcie-phy";
 301                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 302                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 303                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 304                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
 305                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
 306                 status = "disabled";
 307
 308                 pcie0_intc: interrupt-controller {
 309                         interrupt-controller;
 310                         #address-cells = <0>;
 311                         #interrupt-cells = <1>;
 312                 };
 313         };
 314
 315         usb_host0_ehci: usb@fe380000 {
 316                 compatible = "generic-ehci";
 317                 reg = <0x0 0xfe380000 0x0 0x20000>;
 318                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 319                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 320                 clock-names = "hclk_host0", "hclk_host0_arb";
 321                 phys = <&u2phy0_host>;
 322                 phy-names = "usb";
 323                 status = "disabled";
 324         };
 325
 326         usb_host0_ohci: usb@fe3a0000 {
 327                 compatible = "generic-ohci";
 328                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 329                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 330                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 331                 clock-names = "hclk_host0", "hclk_host0_arb";
 332                 status = "disabled";
 333         };
 334
 335         usb_host1_ehci: usb@fe3c0000 {
 336                 compatible = "generic-ehci";
 337                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 338                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 339                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 340                 clock-names = "hclk_host1", "hclk_host1_arb";
 341                 phys = <&u2phy1_host>;
 342                 phy-names = "usb";
 343                 status = "disabled";
 344         };
 345
 346         usb_host1_ohci: usb@fe3e0000 {
 347                 compatible = "generic-ohci";
 348                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 349                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 350                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 351                 clock-names = "hclk_host1", "hclk_host1_arb";
 352                 status = "disabled";
 353         };
 354
 355         gic: interrupt-controller@fee00000 {
 356                 compatible = "arm,gic-v3";
 357                 #interrupt-cells = <4>;
 358                 #address-cells = <2>;
 359                 #size-cells = <2>;
 360                 ranges;
 361                 interrupt-controller;
 362
 363                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 364                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 365                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 366                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 367                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 368                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 its: interrupt-controller@fee20000 {
 370                         compatible = "arm,gic-v3-its";
 371                         msi-controller;
 372                         reg = <0x0 0xfee20000 0x0 0x20000>;
 373                 };
 374
 375                 ppi-partitions {
 376                         ppi_cluster0: interrupt-partition-0 {
 377                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 378                         };
 379
 380                         ppi_cluster1: interrupt-partition-1 {
 381                                 affinity = <&cpu_b0 &cpu_b1>;
 382                         };
 383                 };
 384         };
 385
 386         saradc: saradc@ff100000 {
 387                 compatible = "rockchip,rk3399-saradc";
 388                 reg = <0x0 0xff100000 0x0 0x100>;
 389                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 390                 #io-channel-cells = <1>;
 391                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 392                 clock-names = "saradc", "apb_pclk";
 393                 resets = <&cru SRST_P_SARADC>;
 394                 reset-names = "saradc-apb";
 395                 status = "disabled";
 396         };
 397
 398         i2c1: i2c@ff110000 {
 399                 compatible = "rockchip,rk3399-i2c";
 400                 reg = <0x0 0xff110000 0x0 0x1000>;
 401                 assigned-clocks = <&cru SCLK_I2C1>;
 402                 assigned-clock-rates = <200000000>;
 403                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 404                 clock-names = "i2c", "pclk";
 405                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c1_xfer>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 status = "disabled";
 411         };
 412
 413         i2c2: i2c@ff120000 {
 414                 compatible = "rockchip,rk3399-i2c";
 415                 reg = <0x0 0xff120000 0x0 0x1000>;
 416                 assigned-clocks = <&cru SCLK_I2C2>;
 417                 assigned-clock-rates = <200000000>;
 418                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 419                 clock-names = "i2c", "pclk";
 420                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c2_xfer>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 status = "disabled";
 426         };
 427
 428         i2c3: i2c@ff130000 {
 429                 compatible = "rockchip,rk3399-i2c";
 430                 reg = <0x0 0xff130000 0x0 0x1000>;
 431                 assigned-clocks = <&cru SCLK_I2C3>;
 432                 assigned-clock-rates = <200000000>;
 433                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 434                 clock-names = "i2c", "pclk";
 435                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c3_xfer>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 status = "disabled";
 441         };
 442
 443         i2c5: i2c@ff140000 {
 444                 compatible = "rockchip,rk3399-i2c";
 445                 reg = <0x0 0xff140000 0x0 0x1000>;
 446                 assigned-clocks = <&cru SCLK_I2C5>;
 447                 assigned-clock-rates = <200000000>;
 448                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 449                 clock-names = "i2c", "pclk";
 450                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&i2c5_xfer>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 status = "disabled";
 456         };
 457
 458         i2c6: i2c@ff150000 {
 459                 compatible = "rockchip,rk3399-i2c";
 460                 reg = <0x0 0xff150000 0x0 0x1000>;
 461                 assigned-clocks = <&cru SCLK_I2C6>;
 462                 assigned-clock-rates = <200000000>;
 463                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 464                 clock-names = "i2c", "pclk";
 465                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&i2c6_xfer>;
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 status = "disabled";
 471         };
 472
 473         i2c7: i2c@ff160000 {
 474                 compatible = "rockchip,rk3399-i2c";
 475                 reg = <0x0 0xff160000 0x0 0x1000>;
 476                 assigned-clocks = <&cru SCLK_I2C7>;
 477                 assigned-clock-rates = <200000000>;
 478                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 479                 clock-names = "i2c", "pclk";
 480                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&i2c7_xfer>;
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 status = "disabled";
 486         };
 487
 488         uart0: serial@ff180000 {
 489                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 490                 reg = <0x0 0xff180000 0x0 0x100>;
 491                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 492                 clock-names = "baudclk", "apb_pclk";
 493                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 494                 reg-shift = <2>;
 495                 reg-io-width = <4>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&uart0_xfer>;
 498                 status = "disabled";
 499         };
 500
 501         uart1: serial@ff190000 {
 502                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 503                 reg = <0x0 0xff190000 0x0 0x100>;
 504                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 505                 clock-names = "baudclk", "apb_pclk";
 506                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 507                 reg-shift = <2>;
 508                 reg-io-width = <4>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&uart1_xfer>;
 511                 status = "disabled";
 512         };
 513
 514         uart2: serial@ff1a0000 {
 515                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 516                 reg = <0x0 0xff1a0000 0x0 0x100>;
 517                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 518                 clock-names = "baudclk", "apb_pclk";
 519                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 520                 reg-shift = <2>;
 521                 reg-io-width = <4>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&uart2c_xfer>;
 524                 status = "disabled";
 525         };
 526
 527         uart3: serial@ff1b0000 {
 528                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 529                 reg = <0x0 0xff1b0000 0x0 0x100>;
 530                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 531                 clock-names = "baudclk", "apb_pclk";
 532                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 533                 reg-shift = <2>;
 534                 reg-io-width = <4>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&uart3_xfer>;
 537                 status = "disabled";
 538         };
 539
 540         spi0: spi@ff1c0000 {
 541                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 542                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 544                 clock-names = "spiclk", "apb_pclk";
 545                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         spi1: spi@ff1d0000 {
 554                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 555                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 557                 clock-names = "spiclk", "apb_pclk";
 558                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         spi2: spi@ff1e0000 {
 567                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 568                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 570                 clock-names = "spiclk", "apb_pclk";
 571                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         spi4: spi@ff1f0000 {
 580                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 581                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 583                 clock-names = "spiclk", "apb_pclk";
 584                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         spi5: spi@ff200000 {
 593                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 594                 reg = <0x0 0xff200000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 596                 clock-names = "spiclk", "apb_pclk";
 597                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         thermal-zones {
 606                 cpu_thermal: cpu {
 607                         polling-delay-passive = <100>;
 608                         polling-delay = <1000>;
 609
 610                         thermal-sensors = <&tsadc 0>;
 611
 612                         trips {
 613                                 cpu_alert0: cpu_alert0 {
 614                                         temperature = <70000>;
 615                                         hysteresis = <2000>;
 616                                         type = "passive";
 617                                 };
 618                                 cpu_alert1: cpu_alert1 {
 619                                         temperature = <75000>;
 620                                         hysteresis = <2000>;
 621                                         type = "passive";
 622                                 };
 623                                 cpu_crit: cpu_crit {
 624                                         temperature = <95000>;
 625                                         hysteresis = <2000>;
 626                                         type = "critical";
 627                                 };
 628                         };
 629
 630                         cooling-maps {
 631                                 map0 {
 632                                         trip = <&cpu_alert0>;
 633                                         cooling-device =
 634                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 635                                 };
 636                                 map1 {
 637                                         trip = <&cpu_alert1>;
 638                                         cooling-device =
 639                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 640                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 641                                 };
 642                         };
 643                 };
 644
 645                 gpu_thermal: gpu {
 646                         polling-delay-passive = <100>;
 647                         polling-delay = <1000>;
 648
 649                         thermal-sensors = <&tsadc 1>;
 650
 651                         trips {
 652                                 gpu_alert0: gpu_alert0 {
 653                                         temperature = <75000>;
 654                                         hysteresis = <2000>;
 655                                         type = "passive";
 656                                 };
 657                                 gpu_crit: gpu_crit {
 658                                         temperature = <95000>;
 659                                         hysteresis = <2000>;
 660                                         type = "critical";
 661                                 };
 662                         };
 663
 664                         cooling-maps {
 665                                 map0 {
 666                                         trip = <&gpu_alert0>;
 667                                         cooling-device =
 668                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 669                                 };
 670                         };
 671                 };
 672         };
 673
 674         tsadc: tsadc@ff260000 {
 675                 compatible = "rockchip,rk3399-tsadc";
 676                 reg = <0x0 0xff260000 0x0 0x100>;
 677                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 678                 assigned-clocks = <&cru SCLK_TSADC>;
 679                 assigned-clock-rates = <750000>;
 680                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 681                 clock-names = "tsadc", "apb_pclk";
 682                 resets = <&cru SRST_TSADC>;
 683                 reset-names = "tsadc-apb";
 684                 rockchip,grf = <&grf>;
 685                 rockchip,hw-tshut-temp = <95000>;
 686                 pinctrl-names = "init", "default", "sleep";
 687                 pinctrl-0 = <&otp_gpio>;
 688                 pinctrl-1 = <&otp_out>;
 689                 pinctrl-2 = <&otp_gpio>;
 690                 #thermal-sensor-cells = <1>;
 691                 status = "disabled";
 692         };
 693
 694         qos_gmac: qos@ffa5c000 {
 695                 compatible = "syscon";
 696                 reg = <0x0 0xffa5c000 0x0 0x20>;
 697         };
 698
 699         qos_hdcp: qos@ffa90000 {
 700                 compatible = "syscon";
 701                 reg = <0x0 0xffa90000 0x0 0x20>;
 702         };
 703
 704         qos_iep: qos@ffa98000 {
 705                 compatible = "syscon";
 706                 reg = <0x0 0xffa98000 0x0 0x20>;
 707         };
 708
 709         qos_isp0_m0: qos@ffaa0000 {
 710                 compatible = "syscon";
 711                 reg = <0x0 0xffaa0000 0x0 0x20>;
 712         };
 713
 714         qos_isp0_m1: qos@ffaa0080 {
 715                 compatible = "syscon";
 716                 reg = <0x0 0xffaa0080 0x0 0x20>;
 717         };
 718
 719         qos_isp1_m0: qos@ffaa8000 {
 720                 compatible = "syscon";
 721                 reg = <0x0 0xffaa8000 0x0 0x20>;
 722         };
 723
 724         qos_isp1_m1: qos@ffaa8080 {
 725                 compatible = "syscon";
 726                 reg = <0x0 0xffaa8080 0x0 0x20>;
 727         };
 728
 729         qos_rga_r: qos@ffab0000 {
 730                 compatible = "syscon";
 731                 reg = <0x0 0xffab0000 0x0 0x20>;
 732         };
 733
 734         qos_rga_w: qos@ffab0080 {
 735                 compatible = "syscon";
 736                 reg = <0x0 0xffab0080 0x0 0x20>;
 737         };
 738
 739         qos_video_m0: qos@ffab8000 {
 740                 compatible = "syscon";
 741                 reg = <0x0 0xffab8000 0x0 0x20>;
 742         };
 743
 744         qos_video_m1_r: qos@ffac0000 {
 745                 compatible = "syscon";
 746                 reg = <0x0 0xffac0000 0x0 0x20>;
 747         };
 748
 749         qos_video_m1_w: qos@ffac0080 {
 750                 compatible = "syscon";
 751                 reg = <0x0 0xffac0080 0x0 0x20>;
 752         };
 753
 754         qos_vop_big_r: qos@ffac8000 {
 755                 compatible = "syscon";
 756                 reg = <0x0 0xffac8000 0x0 0x20>;
 757         };
 758
 759         qos_vop_big_w: qos@ffac8080 {
 760                 compatible = "syscon";
 761                 reg = <0x0 0xffac8080 0x0 0x20>;
 762         };
 763
 764         qos_vop_little: qos@ffad0000 {
 765                 compatible = "syscon";
 766                 reg = <0x0 0xffad0000 0x0 0x20>;
 767         };
 768
 769         qos_gpu: qos@ffae0000 {
 770                 compatible = "syscon";
 771                 reg = <0x0 0xffae0000 0x0 0x20>;
 772         };
 773
 774         pmu: power-management@ff310000 {
 775                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 776                 reg = <0x0 0xff310000 0x0 0x1000>;
 777
 778                 /*
 779                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 780                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 781                  * Some of the power domains are grouped together for every
 782                  * voltage domain.
 783                  * The detail contents as below.
 784                  */
 785                 power: power-controller {
 786                         compatible = "rockchip,rk3399-power-controller";
 787                         #power-domain-cells = <1>;
 788                         #address-cells = <1>;
 789                         #size-cells = <0>;
 790
 791                         /* These power domains are grouped by VD_CENTER */
 792                         pd_iep@RK3399_PD_IEP {
 793                                 reg = <RK3399_PD_IEP>;
 794                                 clocks = <&cru ACLK_IEP>,
 795                                          <&cru HCLK_IEP>;
 796                                 pm_qos = <&qos_iep>;
 797                         };
 798                         pd_rga@RK3399_PD_RGA {
 799                                 reg = <RK3399_PD_RGA>;
 800                                 clocks = <&cru ACLK_RGA>,
 801                                          <&cru HCLK_RGA>;
 802                                 pm_qos = <&qos_rga_r>,
 803                                          <&qos_rga_w>;
 804                         };
 805                         pd_vcodec@RK3399_PD_VCODEC {
 806                                 reg = <RK3399_PD_VCODEC>;
 807                                 clocks = <&cru ACLK_VCODEC>,
 808                                          <&cru HCLK_VCODEC>;
 809                                 pm_qos = <&qos_video_m0>;
 810                         };
 811                         pd_vdu@RK3399_PD_VDU {
 812                                 reg = <RK3399_PD_VDU>;
 813                                 clocks = <&cru ACLK_VDU>,
 814                                          <&cru HCLK_VDU>;
 815                                 pm_qos = <&qos_video_m1_r>,
 816                                          <&qos_video_m1_w>;
 817                         };
 818
 819                         /* These power domains are grouped by VD_GPU */
 820                         pd_gpu@RK3399_PD_GPU {
 821                                 reg = <RK3399_PD_GPU>;
 822                                 clocks = <&cru ACLK_GPU>;
 823                                 pm_qos = <&qos_gpu>;
 824                         };
 825
 826                         /* These power domains are grouped by VD_LOGIC */
 827                         pd_gmac@RK3399_PD_GMAC {
 828                                 reg = <RK3399_PD_GMAC>;
 829                                 clocks = <&cru ACLK_GMAC>;
 830                                 pm_qos = <&qos_gmac>;
 831                         };
 832                         pd_vio@RK3399_PD_VIO {
 833                                 reg = <RK3399_PD_VIO>;
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836
 837                                 pd_hdcp@RK3399_PD_HDCP {
 838                                         reg = <RK3399_PD_HDCP>;
 839                                         clocks = <&cru ACLK_HDCP>,
 840                                                  <&cru HCLK_HDCP>,
 841                                                  <&cru PCLK_HDCP>;
 842                                         pm_qos = <&qos_hdcp>;
 843                                 };
 844                                 pd_isp0@RK3399_PD_ISP0 {
 845                                         reg = <RK3399_PD_ISP0>;
 846                                         clocks = <&cru ACLK_ISP0>,
 847                                                  <&cru HCLK_ISP0>;
 848                                         pm_qos = <&qos_isp0_m0>,
 849                                                  <&qos_isp0_m1>;
 850                                 };
 851                                 pd_isp1@RK3399_PD_ISP1 {
 852                                         reg = <RK3399_PD_ISP1>;
 853                                         clocks = <&cru ACLK_ISP1>,
 854                                                  <&cru HCLK_ISP1>;
 855                                         pm_qos = <&qos_isp1_m0>,
 856                                                  <&qos_isp1_m1>;
 857                                 };
 858                                 pd_tcpc0@RK3399_PD_TCPC0 {
 859                                         reg = <RK3399_PD_TCPD0>;
 860                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 861                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 862                                 };
 863                                 pd_tcpc1@RK3399_PD_TCPC1 {
 864                                         reg = <RK3399_PD_TCPD1>;
 865                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 866                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 867                                 };
 868                                 pd_vo@RK3399_PD_VO {
 869                                         reg = <RK3399_PD_VO>;
 870                                         #address-cells = <1>;
 871                                         #size-cells = <0>;
 872
 873                                         pd_vopb@RK3399_PD_VOPB {
 874                                                 reg = <RK3399_PD_VOPB>;
 875                                                 clocks = <&cru ACLK_VOP0>,
 876                                                          <&cru HCLK_VOP0>;
 877                                                 pm_qos = <&qos_vop_big_r>,
 878                                                          <&qos_vop_big_w>;
 879                                         };
 880                                         pd_vopl@RK3399_PD_VOPL {
 881                                                 reg = <RK3399_PD_VOPL>;
 882                                                 clocks = <&cru ACLK_VOP1>,
 883                                                          <&cru HCLK_VOP1>;
 884                                                 pm_qos = <&qos_vop_little>;
 885                                         };
 886                                 };
 887                         };
 888                 };
 889         };
 890
 891         pmugrf: syscon@ff320000 {
 892                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 893                 reg = <0x0 0xff320000 0x0 0x1000>;
 894                 #address-cells = <1>;
 895                 #size-cells = <1>;
 896
 897                 pmu_io_domains: io-domains {
 898                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 899                         status = "disabled";
 900                 };
 901         };
 902
 903         spi3: spi@ff350000 {
 904                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 905                 reg = <0x0 0xff350000 0x0 0x1000>;
 906                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 907                 clock-names = "spiclk", "apb_pclk";
 908                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
 909                 pinctrl-names = "default";
 910                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 911                 #address-cells = <1>;
 912                 #size-cells = <0>;
 913                 status = "disabled";
 914         };
 915
 916         uart4: serial@ff370000 {
 917                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 918                 reg = <0x0 0xff370000 0x0 0x100>;
 919                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 920                 clock-names = "baudclk", "apb_pclk";
 921                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
 922                 reg-shift = <2>;
 923                 reg-io-width = <4>;
 924                 pinctrl-names = "default";
 925                 pinctrl-0 = <&uart4_xfer>;
 926                 status = "disabled";
 927         };
 928
 929         i2c0: i2c@ff3c0000 {
 930                 compatible = "rockchip,rk3399-i2c";
 931                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 932                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 933                 assigned-clock-rates = <200000000>;
 934                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 935                 clock-names = "i2c", "pclk";
 936                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 937                 pinctrl-names = "default";
 938                 pinctrl-0 = <&i2c0_xfer>;
 939                 #address-cells = <1>;
 940                 #size-cells = <0>;
 941                 status = "disabled";
 942         };
 943
 944         i2c4: i2c@ff3d0000 {
 945                 compatible = "rockchip,rk3399-i2c";
 946                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 947                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 948                 assigned-clock-rates = <200000000>;
 949                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 950                 clock-names = "i2c", "pclk";
 951                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
 952                 pinctrl-names = "default";
 953                 pinctrl-0 = <&i2c4_xfer>;
 954                 #address-cells = <1>;
 955                 #size-cells = <0>;
 956                 status = "disabled";
 957         };
 958
 959         i2c8: i2c@ff3e0000 {
 960                 compatible = "rockchip,rk3399-i2c";
 961                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 962                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 963                 assigned-clock-rates = <200000000>;
 964                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 965                 clock-names = "i2c", "pclk";
 966                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 967                 pinctrl-names = "default";
 968                 pinctrl-0 = <&i2c8_xfer>;
 969                 #address-cells = <1>;
 970                 #size-cells = <0>;
 971                 status = "disabled";
 972         };
 973
 974         pwm0: pwm@ff420000 {
 975                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 976                 reg = <0x0 0xff420000 0x0 0x10>;
 977                 #pwm-cells = <3>;
 978                 pinctrl-names = "default";
 979                 pinctrl-0 = <&pwm0_pin>;
 980                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 981                 clock-names = "pwm";
 982                 status = "disabled";
 983         };
 984
 985         pwm1: pwm@ff420010 {
 986                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 987                 reg = <0x0 0xff420010 0x0 0x10>;
 988                 #pwm-cells = <3>;
 989                 pinctrl-names = "default";
 990                 pinctrl-0 = <&pwm1_pin>;
 991                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 992                 clock-names = "pwm";
 993                 status = "disabled";
 994         };
 995
 996         pwm2: pwm@ff420020 {
 997                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 998                 reg = <0x0 0xff420020 0x0 0x10>;
 999                 #pwm-cells = <3>;
1000                 pinctrl-names = "default";
1001                 pinctrl-0 = <&pwm2_pin>;
1002                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1003                 clock-names = "pwm";
1004                 status = "disabled";
1005         };
1006
1007         pwm3: pwm@ff420030 {
1008                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1009                 reg = <0x0 0xff420030 0x0 0x10>;
1010                 #pwm-cells = <3>;
1011                 pinctrl-names = "default";
1012                 pinctrl-0 = <&pwm3a_pin>;
1013                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1014                 clock-names = "pwm";
1015                 status = "disabled";
1016         };
1017
1018         efuse0: efuse@ff690000 {
1019                 compatible = "rockchip,rk3399-efuse";
1020                 reg = <0x0 0xff690000 0x0 0x80>;
1021                 #address-cells = <1>;
1022                 #size-cells = <1>;
1023                 clocks = <&cru PCLK_EFUSE1024NS>;
1024                 clock-names = "pclk_efuse";
1025
1026                 /* Data cells */
1027                 cpub_leakage: cpu-leakage@17 {
1028                         reg = <0x17 0x1>;
1029                 };
1030                 gpu_leakage: gpu-leakage@18 {
1031                         reg = <0x18 0x1>;
1032                 };
1033                 center_leakage: center-leakage@19 {
1034                         reg = <0x19 0x1>;
1035                 };
1036                 cpul_leakage: cpu-leakage@1a {
1037                         reg = <0x1a 0x1>;
1038                 };
1039                 logic_leakage: logic-leakage@1b {
1040                         reg = <0x1b 0x1>;
1041                 };
1042                 wafer_info: wafer-info@1c {
1043                         reg = <0x1c 0x1>;
1044                 };
1045         };
1046
1047         pmucru: pmu-clock-controller@ff750000 {
1048                 compatible = "rockchip,rk3399-pmucru";
1049                 reg = <0x0 0xff750000 0x0 0x1000>;
1050                 #clock-cells = <1>;
1051                 #reset-cells = <1>;
1052                 assigned-clocks = <&pmucru PLL_PPLL>;
1053                 assigned-clock-rates = <676000000>;
1054         };
1055
1056         cru: clock-controller@ff760000 {
1057                 compatible = "rockchip,rk3399-cru";
1058                 reg = <0x0 0xff760000 0x0 0x1000>;
1059                 #clock-cells = <1>;
1060                 #reset-cells = <1>;
1061                 assigned-clocks =
1062                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1063                         <&cru PLL_NPLL>,
1064                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1065                         <&cru PCLK_PERIHP>,
1066                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1067                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1068                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1069                 assigned-clock-rates =
1070                          <594000000>,  <800000000>,
1071                         <1000000000>,
1072                          <150000000>,   <75000000>,
1073                           <37500000>,
1074                          <100000000>,  <100000000>,
1075                           <50000000>, <600000000>,
1076                          <100000000>,   <50000000>;
1077         };
1078
1079         grf: syscon@ff770000 {
1080                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1081                 reg = <0x0 0xff770000 0x0 0x10000>;
1082                 #address-cells = <1>;
1083                 #size-cells = <1>;
1084
1085                 io_domains: io-domains {
1086                         compatible = "rockchip,rk3399-io-voltage-domain";
1087                         status = "disabled";
1088                 };
1089
1090                 u2phy0: usb2-phy@e450 {
1091                         compatible = "rockchip,rk3399-usb2phy";
1092                         reg = <0xe450 0x10>;
1093                         clocks = <&cru SCLK_USB2PHY0_REF>;
1094                         clock-names = "phyclk";
1095                         #clock-cells = <0>;
1096                         clock-output-names = "clk_usbphy0_480m";
1097                         status = "disabled";
1098
1099                         u2phy0_host: host-port {
1100                                 #phy-cells = <0>;
1101                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1102                                 interrupt-names = "linestate";
1103                                 status = "disabled";
1104                         };
1105                 };
1106
1107                 u2phy1: usb2-phy@e460 {
1108                         compatible = "rockchip,rk3399-usb2phy";
1109                         reg = <0xe460 0x10>;
1110                         clocks = <&cru SCLK_USB2PHY1_REF>;
1111                         clock-names = "phyclk";
1112                         #clock-cells = <0>;
1113                         clock-output-names = "clk_usbphy1_480m";
1114                         status = "disabled";
1115
1116                         u2phy1_host: host-port {
1117                                 #phy-cells = <0>;
1118                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1119                                 interrupt-names = "linestate";
1120                                 status = "disabled";
1121                         };
1122                 };
1123
1124                 emmc_phy: phy@f780 {
1125                         compatible = "rockchip,rk3399-emmc-phy";
1126                         reg = <0xf780 0x24>;
1127                         clocks = <&sdhci>;
1128                         clock-names = "emmcclk";
1129                         #phy-cells = <0>;
1130                         status = "disabled";
1131                 };
1132
1133                 pcie_phy: pcie-phy {
1134                         compatible = "rockchip,rk3399-pcie-phy";
1135                         clocks = <&cru SCLK_PCIEPHY_REF>;
1136                         clock-names = "refclk";
1137                         #phy-cells = <0>;
1138                         resets = <&cru SRST_PCIEPHY>;
1139                         reset-names = "phy";
1140                         status = "disabled";
1141                 };
1142         };
1143
1144         tcphy0: phy@ff7c0000 {
1145                 compatible = "rockchip,rk3399-typec-phy";
1146                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1147                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1148                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1149                 clock-names = "tcpdcore", "tcpdphy-ref";
1150                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1151                 assigned-clock-rates = <50000000>;
1152                 resets = <&cru SRST_UPHY0>,
1153                          <&cru SRST_UPHY0_PIPE_L00>,
1154                          <&cru SRST_P_UPHY0_TCPHY>;
1155                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1156                 rockchip,grf = <&grf>;
1157                 rockchip,typec-conn-dir = <0xe580 0 16>;
1158                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1159                 rockchip,external-psm = <0xe588 14 30>;
1160                 rockchip,pipe-status = <0xe5c0 0 0>;
1161                 status = "disabled";
1162
1163                 tcphy0_dp: dp-port {
1164                         #phy-cells = <0>;
1165                 };
1166
1167                 tcphy0_usb3: usb3-port {
1168                         #phy-cells = <0>;
1169                 };
1170         };
1171
1172         tcphy1: phy@ff800000 {
1173                 compatible = "rockchip,rk3399-typec-phy";
1174                 reg = <0x0 0xff800000 0x0 0x40000>;
1175                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1176                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1177                 clock-names = "tcpdcore", "tcpdphy-ref";
1178                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1179                 assigned-clock-rates = <50000000>;
1180                 resets = <&cru SRST_UPHY1>,
1181                          <&cru SRST_UPHY1_PIPE_L00>,
1182                          <&cru SRST_P_UPHY1_TCPHY>;
1183                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1184                 rockchip,grf = <&grf>;
1185                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1186                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1187                 rockchip,external-psm = <0xe594 14 30>;
1188                 rockchip,pipe-status = <0xe5c0 16 16>;
1189                 status = "disabled";
1190
1191                 tcphy1_dp: dp-port {
1192                         #phy-cells = <0>;
1193                 };
1194
1195                 tcphy1_usb3: usb3-port {
1196                         #phy-cells = <0>;
1197                 };
1198         };
1199
1200         watchdog@ff848000 {
1201                 compatible = "snps,dw-wdt";
1202                 reg = <0x0 0xff848000 0x0 0x100>;
1203                 clocks = <&cru PCLK_WDT>;
1204                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1205         };
1206
1207         rktimer: rktimer@ff850000 {
1208                 compatible = "rockchip,rk3399-timer";
1209                 reg = <0x0 0xff850000 0x0 0x1000>;
1210                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1211                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1212                 clock-names = "pclk", "timer";
1213         };
1214
1215         spdif: spdif@ff870000 {
1216                 compatible = "rockchip,rk3399-spdif";
1217                 reg = <0x0 0xff870000 0x0 0x1000>;
1218                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1219                 dmas = <&dmac_bus 7>;
1220                 dma-names = "tx";
1221                 clock-names = "mclk", "hclk";
1222                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1223                 pinctrl-names = "default";
1224                 pinctrl-0 = <&spdif_bus>;
1225                 status = "disabled";
1226         };
1227
1228         i2s0: i2s@ff880000 {
1229                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1230                 reg = <0x0 0xff880000 0x0 0x1000>;
1231                 rockchip,grf = <&grf>;
1232                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1233                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1234                 dma-names = "tx", "rx";
1235                 clock-names = "i2s_clk", "i2s_hclk";
1236                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1237                 pinctrl-names = "default";
1238                 pinctrl-0 = <&i2s0_8ch_bus>;
1239                 status = "disabled";
1240         };
1241
1242         i2s1: i2s@ff890000 {
1243                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1244                 reg = <0x0 0xff890000 0x0 0x1000>;
1245                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1246                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1247                 dma-names = "tx", "rx";
1248                 clock-names = "i2s_clk", "i2s_hclk";
1249                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1250                 pinctrl-names = "default";
1251                 pinctrl-0 = <&i2s1_2ch_bus>;
1252                 status = "disabled";
1253         };
1254
1255         i2s2: i2s@ff8a0000 {
1256                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1257                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1258                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1259                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1260                 dma-names = "tx", "rx";
1261                 clock-names = "i2s_clk", "i2s_hclk";
1262                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1263                 status = "disabled";
1264         };
1265
1266         pinctrl: pinctrl {
1267                 compatible = "rockchip,rk3399-pinctrl";
1268                 rockchip,grf = <&grf>;
1269                 rockchip,pmu = <&pmugrf>;
1270                 #address-cells = <2>;
1271                 #size-cells = <2>;
1272                 ranges;
1273
1274                 gpio0: gpio0@ff720000 {
1275                         compatible = "rockchip,gpio-bank";
1276                         reg = <0x0 0xff720000 0x0 0x100>;
1277                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1278                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1279
1280                         gpio-controller;
1281                         #gpio-cells = <0x2>;
1282
1283                         interrupt-controller;
1284                         #interrupt-cells = <0x2>;
1285                 };
1286
1287                 gpio1: gpio1@ff730000 {
1288                         compatible = "rockchip,gpio-bank";
1289                         reg = <0x0 0xff730000 0x0 0x100>;
1290                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1291                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1292
1293                         gpio-controller;
1294                         #gpio-cells = <0x2>;
1295
1296                         interrupt-controller;
1297                         #interrupt-cells = <0x2>;
1298                 };
1299
1300                 gpio2: gpio2@ff780000 {
1301                         compatible = "rockchip,gpio-bank";
1302                         reg = <0x0 0xff780000 0x0 0x100>;
1303                         clocks = <&cru PCLK_GPIO2>;
1304                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1305
1306                         gpio-controller;
1307                         #gpio-cells = <0x2>;
1308
1309                         interrupt-controller;
1310                         #interrupt-cells = <0x2>;
1311                 };
1312
1313                 gpio3: gpio3@ff788000 {
1314                         compatible = "rockchip,gpio-bank";
1315                         reg = <0x0 0xff788000 0x0 0x100>;
1316                         clocks = <&cru PCLK_GPIO3>;
1317                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1318
1319                         gpio-controller;
1320                         #gpio-cells = <0x2>;
1321
1322                         interrupt-controller;
1323                         #interrupt-cells = <0x2>;
1324                 };
1325
1326                 gpio4: gpio4@ff790000 {
1327                         compatible = "rockchip,gpio-bank";
1328                         reg = <0x0 0xff790000 0x0 0x100>;
1329                         clocks = <&cru PCLK_GPIO4>;
1330                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1331
1332                         gpio-controller;
1333                         #gpio-cells = <0x2>;
1334
1335                         interrupt-controller;
1336                         #interrupt-cells = <0x2>;
1337                 };
1338
1339                 pcfg_pull_up: pcfg-pull-up {
1340                         bias-pull-up;
1341                 };
1342
1343                 pcfg_pull_down: pcfg-pull-down {
1344                         bias-pull-down;
1345                 };
1346
1347                 pcfg_pull_none: pcfg-pull-none {
1348                         bias-disable;
1349                 };
1350
1351                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1352                         bias-disable;
1353                         drive-strength = <12>;
1354                 };
1355
1356                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1357                         bias-pull-up;
1358                         drive-strength = <8>;
1359                 };
1360
1361                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1362                         bias-pull-down;
1363                         drive-strength = <4>;
1364                 };
1365
1366                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1367                         bias-pull-up;
1368                         drive-strength = <2>;
1369                 };
1370
1371                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1372                         bias-pull-down;
1373                         drive-strength = <12>;
1374                 };
1375
1376                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1377                         bias-disable;
1378                         drive-strength = <13>;
1379                 };
1380
1381                 clock {
1382                         clk_32k: clk-32k {
1383                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1384                         };
1385                 };
1386
1387                 gmac {
1388                         rgmii_pins: rgmii-pins {
1389                                 rockchip,pins =
1390                                         /* mac_txclk */
1391                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1392                                         /* mac_rxclk */
1393                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1394                                         /* mac_mdio */
1395                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1396                                         /* mac_txen */
1397                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1398                                         /* mac_clk */
1399                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1400                                         /* mac_rxdv */
1401                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1402                                         /* mac_mdc */
1403                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1404                                         /* mac_rxd1 */
1405                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1406                                         /* mac_rxd0 */
1407                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1408                                         /* mac_txd1 */
1409                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1410                                         /* mac_txd0 */
1411                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1412                                         /* mac_rxd3 */
1413                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1414                                         /* mac_rxd2 */
1415                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1416                                         /* mac_txd3 */
1417                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1418                                         /* mac_txd2 */
1419                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1420                         };
1421
1422                         rmii_pins: rmii-pins {
1423                                 rockchip,pins =
1424                                         /* mac_mdio */
1425                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1426                                         /* mac_txen */
1427                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1428                                         /* mac_clk */
1429                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1430                                         /* mac_rxer */
1431                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1432                                         /* mac_rxdv */
1433                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1434                                         /* mac_mdc */
1435                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1436                                         /* mac_rxd1 */
1437                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1438                                         /* mac_rxd0 */
1439                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1440                                         /* mac_txd1 */
1441                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1442                                         /* mac_txd0 */
1443                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1444                         };
1445                 };
1446
1447                 i2c0 {
1448                         i2c0_xfer: i2c0-xfer {
1449                                 rockchip,pins =
1450                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1451                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 i2c1 {
1456                         i2c1_xfer: i2c1-xfer {
1457                                 rockchip,pins =
1458                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1459                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461                 };
1462
1463                 i2c2 {
1464                         i2c2_xfer: i2c2-xfer {
1465                                 rockchip,pins =
1466                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1467                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1468                         };
1469                 };
1470
1471                 i2c3 {
1472                         i2c3_xfer: i2c3-xfer {
1473                                 rockchip,pins =
1474                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1475                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1476                         };
1477                 };
1478
1479                 i2c4 {
1480                         i2c4_xfer: i2c4-xfer {
1481                                 rockchip,pins =
1482                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1483                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1484                         };
1485                 };
1486
1487                 i2c5 {
1488                         i2c5_xfer: i2c5-xfer {
1489                                 rockchip,pins =
1490                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1491                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 i2c6 {
1496                         i2c6_xfer: i2c6-xfer {
1497                                 rockchip,pins =
1498                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1499                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1500                         };
1501                 };
1502
1503                 i2c7 {
1504                         i2c7_xfer: i2c7-xfer {
1505                                 rockchip,pins =
1506                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1507                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1508                         };
1509                 };
1510
1511                 i2c8 {
1512                         i2c8_xfer: i2c8-xfer {
1513                                 rockchip,pins =
1514                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1515                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1516                         };
1517                 };
1518
1519                 i2s0 {
1520                         i2s0_8ch_bus: i2s0-8ch-bus {
1521                                 rockchip,pins =
1522                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1523                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1524                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1525                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1526                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1527                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1528                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1529                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1530                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1531                         };
1532                 };
1533
1534                 i2s1 {
1535                         i2s1_2ch_bus: i2s1-2ch-bus {
1536                                 rockchip,pins =
1537                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1538                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1539                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1540                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1541                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 sleep {
1546                         ap_pwroff: ap-pwroff {
1547                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549
1550                         ddrio_pwroff: ddrio-pwroff {
1551                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 spdif {
1556                         spdif_bus: spdif-bus {
1557                                 rockchip,pins =
1558                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1559                         };
1560                 };
1561
1562                 spi0 {
1563                         spi0_clk: spi0-clk {
1564                                 rockchip,pins =
1565                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1566                         };
1567                         spi0_cs0: spi0-cs0 {
1568                                 rockchip,pins =
1569                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1570                         };
1571                         spi0_cs1: spi0-cs1 {
1572                                 rockchip,pins =
1573                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1574                         };
1575                         spi0_tx: spi0-tx {
1576                                 rockchip,pins =
1577                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1578                         };
1579                         spi0_rx: spi0-rx {
1580                                 rockchip,pins =
1581                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1582                         };
1583                 };
1584
1585                 spi1 {
1586                         spi1_clk: spi1-clk {
1587                                 rockchip,pins =
1588                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1589                         };
1590                         spi1_cs0: spi1-cs0 {
1591                                 rockchip,pins =
1592                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1593                         };
1594                         spi1_rx: spi1-rx {
1595                                 rockchip,pins =
1596                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1597                         };
1598                         spi1_tx: spi1-tx {
1599                                 rockchip,pins =
1600                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1601                         };
1602                 };
1603
1604                 spi2 {
1605                         spi2_clk: spi2-clk {
1606                                 rockchip,pins =
1607                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1608                         };
1609                         spi2_cs0: spi2-cs0 {
1610                                 rockchip,pins =
1611                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1612                         };
1613                         spi2_rx: spi2-rx {
1614                                 rockchip,pins =
1615                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1616                         };
1617                         spi2_tx: spi2-tx {
1618                                 rockchip,pins =
1619                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1620                         };
1621                 };
1622
1623                 spi3 {
1624                         spi3_clk: spi3-clk {
1625                                 rockchip,pins =
1626                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1627                         };
1628                         spi3_cs0: spi3-cs0 {
1629                                 rockchip,pins =
1630                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1631                         };
1632                         spi3_rx: spi3-rx {
1633                                 rockchip,pins =
1634                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1635                         };
1636                         spi3_tx: spi3-tx {
1637                                 rockchip,pins =
1638                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1639                         };
1640                 };
1641
1642                 spi4 {
1643                         spi4_clk: spi4-clk {
1644                                 rockchip,pins =
1645                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1646                         };
1647                         spi4_cs0: spi4-cs0 {
1648                                 rockchip,pins =
1649                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651                         spi4_rx: spi4-rx {
1652                                 rockchip,pins =
1653                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1654                         };
1655                         spi4_tx: spi4-tx {
1656                                 rockchip,pins =
1657                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1658                         };
1659                 };
1660
1661                 spi5 {
1662                         spi5_clk: spi5-clk {
1663                                 rockchip,pins =
1664                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1665                         };
1666                         spi5_cs0: spi5-cs0 {
1667                                 rockchip,pins =
1668                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1669                         };
1670                         spi5_rx: spi5-rx {
1671                                 rockchip,pins =
1672                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1673                         };
1674                         spi5_tx: spi5-tx {
1675                                 rockchip,pins =
1676                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1677                         };
1678                 };
1679
1680                 tsadc {
1681                         otp_gpio: otp-gpio {
1682                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1683                         };
1684
1685                         otp_out: otp-out {
1686                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1687                         };
1688                 };
1689
1690                 uart0 {
1691                         uart0_xfer: uart0-xfer {
1692                                 rockchip,pins =
1693                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1694                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1695                         };
1696
1697                         uart0_cts: uart0-cts {
1698                                 rockchip,pins =
1699                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1700                         };
1701
1702                         uart0_rts: uart0-rts {
1703                                 rockchip,pins =
1704                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1705                         };
1706                 };
1707
1708                 uart1 {
1709                         uart1_xfer: uart1-xfer {
1710                                 rockchip,pins =
1711                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1712                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1713                         };
1714                 };
1715
1716                 uart2a {
1717                         uart2a_xfer: uart2a-xfer {
1718                                 rockchip,pins =
1719                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1720                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1721                         };
1722                 };
1723
1724                 uart2b {
1725                         uart2b_xfer: uart2b-xfer {
1726                                 rockchip,pins =
1727                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1728                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1729                         };
1730                 };
1731
1732                 uart2c {
1733                         uart2c_xfer: uart2c-xfer {
1734                                 rockchip,pins =
1735                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1736                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1737                         };
1738                 };
1739
1740                 uart3 {
1741                         uart3_xfer: uart3-xfer {
1742                                 rockchip,pins =
1743                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1744                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1745                         };
1746
1747                         uart3_cts: uart3-cts {
1748                                 rockchip,pins =
1749                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1750                         };
1751
1752                         uart3_rts: uart3-rts {
1753                                 rockchip,pins =
1754                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1755                         };
1756                 };
1757
1758                 uart4 {
1759                         uart4_xfer: uart4-xfer {
1760                                 rockchip,pins =
1761                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1762                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 uarthdcp {
1767                         uarthdcp_xfer: uarthdcp-xfer {
1768                                 rockchip,pins =
1769                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1770                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1771                         };
1772                 };
1773
1774                 pwm0 {
1775                         pwm0_pin: pwm0-pin {
1776                                 rockchip,pins =
1777                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1778                         };
1779
1780                         vop0_pwm_pin: vop0-pwm-pin {
1781                                 rockchip,pins =
1782                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1783                         };
1784                 };
1785
1786                 pwm1 {
1787                         pwm1_pin: pwm1-pin {
1788                                 rockchip,pins =
1789                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1790                         };
1791
1792                         vop1_pwm_pin: vop1-pwm-pin {
1793                                 rockchip,pins =
1794                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1795                         };
1796                 };
1797
1798                 pwm2 {
1799                         pwm2_pin: pwm2-pin {
1800                                 rockchip,pins =
1801                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 pwm3a {
1806                         pwm3a_pin: pwm3a-pin {
1807                                 rockchip,pins =
1808                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1809                         };
1810                 };
1811
1812                 pwm3b {
1813                         pwm3b_pin: pwm3b-pin {
1814                                 rockchip,pins =
1815                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1816                         };
1817                 };
1818
1819                 pcie {
1820                         pcie_clkreqn: pci-clkreqn {
1821                                 rockchip,pins =
1822                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
1823                         };
1824
1825                         pcie_clkreqnb: pci-clkreqnb {
1826                                 rockchip,pins =
1827                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829                 };
1830
1831         };
1832 };