arch/arm64/boot/dts/zte/zx296718.dtsi

   1 /*
   2  * Copyright 2016 ZTE Corporation.
   3  * Copyright 2016 Linaro Ltd.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/input/input.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/clock/zx296718-clock.h>
  48
  49 / {
  50         compatible = "zte,zx296718";
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57         };
  58
  59         cpus {
  60                 #address-cells = <2>;
  61                 #size-cells = <0>;
  62
  63                 cpu-map {
  64                         cluster0 {
  65                                 core0 {
  66                                         cpu = <&cpu0>;
  67                                 };
  68                                 core1 {
  69                                         cpu = <&cpu1>;
  70                                 };
  71                                 core2 {
  72                                         cpu = <&cpu2>;
  73                                 };
  74                                 core3 {
  75                                         cpu = <&cpu3>;
  76                                 };
  77                         };
  78                 };
  79
  80                 cpu0: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53","arm,armv8";
  83                         reg = <0x0 0x0>;
  84                         enable-method = "psci";
  85                         clocks = <&topcrm A53_GATE>;
  86                         operating-points-v2 = <&cluster0_opp>;
  87                 };
  88
  89                 cpu1: cpu@1 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x1>;
  93                         enable-method = "psci";
  94                         clocks = <&topcrm A53_GATE>;
  95                         operating-points-v2 = <&cluster0_opp>;
  96                 };
  97
  98                 cpu2: cpu@2 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a53","arm,armv8";
 101                         reg = <0x0 0x2>;
 102                         enable-method = "psci";
 103                         clocks = <&topcrm A53_GATE>;
 104                         operating-points-v2 = <&cluster0_opp>;
 105                 };
 106
 107                 cpu3: cpu@3 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a53","arm,armv8";
 110                         reg = <0x0 0x3>;
 111                         enable-method = "psci";
 112                         clocks = <&topcrm A53_GATE>;
 113                         operating-points-v2 = <&cluster0_opp>;
 114                 };
 115         };
 116
 117         cluster0_opp: opp-table0 {
 118                 compatible = "operating-points-v2";
 119                 opp-shared;
 120
 121                 opp@500000000 {
 122                         opp-hz = /bits/ 64 <500000000>;
 123                         clock-latency-ns = <500000>;
 124                 };
 125
 126                 opp@648000000 {
 127                         opp-hz = /bits/ 64 <648000000>;
 128                         clock-latency-ns = <500000>;
 129                 };
 130
 131                 opp@800000000 {
 132                         opp-hz = /bits/ 64 <800000000>;
 133                         clock-latency-ns = <500000>;
 134                 };
 135
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         clock-latency-ns = <500000>;
 139                 };
 140
 141                 opp@1188000000 {
 142                         opp-hz = /bits/ 64 <1188000000>;
 143                         clock-latency-ns = <500000>;
 144                 };
 145         };
 146
 147         clk24k: clk-24k {
 148                 compatible = "fixed-clock";
 149                 #clock-cells = <0>;
 150                 clock-frequency = <24000>;
 151                 clock-output-names = "rtcclk";
 152         };
 153
 154         osc32k: clk-osc32k {
 155                 compatible = "fixed-clock";
 156                 #clock-cells = <0>;
 157                 clock-frequency = <32000>;
 158                 clock-output-names = "osc32k";
 159         };
 160
 161         osc12m: clk-osc12m {
 162                 compatible = "fixed-clock";
 163                 #clock-cells = <0>;
 164                 clock-frequency = <12000000>;
 165                 clock-output-names = "osc12m";
 166         };
 167
 168         osc24m: clk-osc24m {
 169                 compatible = "fixed-clock";
 170                 #clock-cells = <0>;
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "osc24m";
 173         };
 174
 175         osc25m: clk-osc25m {
 176                 compatible = "fixed-clock";
 177                 #clock-cells = <0>;
 178                 clock-frequency = <25000000>;
 179                 clock-output-names = "osc25m";
 180         };
 181
 182         osc60m: clk-osc60m {
 183                 compatible = "fixed-clock";
 184                 #clock-cells = <0>;
 185                 clock-frequency = <60000000>;
 186                 clock-output-names = "osc60m";
 187         };
 188
 189         osc99m: clk-osc99m {
 190                 compatible = "fixed-clock";
 191                 #clock-cells = <0>;
 192                 clock-frequency = <99000000>;
 193                 clock-output-names = "osc99m";
 194         };
 195
 196         osc125m: clk-osc125m {
 197                 compatible = "fixed-clock";
 198                 #clock-cells = <0>;
 199                 clock-frequency = <125000000>;
 200                 clock-output-names = "osc125m";
 201         };
 202
 203         osc198m: clk-osc198m {
 204                 compatible = "fixed-clock";
 205                 #clock-cells = <0>;
 206                 clock-frequency = <198000000>;
 207                 clock-output-names = "osc198m";
 208         };
 209
 210         pll_audio: clk-pll-884m {
 211                 compatible = "fixed-clock";
 212                 #clock-cells = <0>;
 213                 clock-frequency = <884000000>;
 214                 clock-output-names = "pll_audio";
 215         };
 216
 217         pll_ddr: clk-pll-932m {
 218                 compatible = "fixed-clock";
 219                 #clock-cells = <0>;
 220                 clock-frequency = <932000000>;
 221                 clock-output-names = "pll_ddr";
 222         };
 223
 224         pll_hsic: clk-pll-960m {
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <960000000>;
 228                 clock-output-names = "pll_hsic";
 229         };
 230
 231         pll_mac: clk-pll-1000m {
 232                 compatible = "fixed-clock";
 233                 #clock-cells = <0>;
 234                 clock-frequency = <1000000000>;
 235                 clock-output-names = "pll_mac";
 236         };
 237
 238         pll_mm0: clk-pll-1188m {
 239                 compatible = "fixed-clock";
 240                 #clock-cells = <0>;
 241                 clock-frequency = <1188000000>;
 242                 clock-output-names = "pll_mm0";
 243         };
 244
 245         pll_mm1: clk-pll-1296m {
 246                 compatible = "fixed-clock";
 247                 #clock-cells = <0>;
 248                 clock-frequency = <1296000000>;
 249                 clock-output-names = "pll_mm1";
 250         };
 251
 252         psci {
 253                 compatible = "arm,psci-1.0";
 254                 method = "smc";
 255         };
 256
 257         timer {
 258                 compatible = "arm,armv8-timer";
 259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 263         };
 264
 265         pmu {
 266                 compatible = "arm,cortex-a53-pmu";
 267                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 268         };
 269
 270         gic: interrupt-controller@2a00000 {
 271                 compatible = "arm,gic-v3";
 272                 #interrupt-cells = <3>;
 273                 #address-cells = <0>;
 274                 interrupt-controller;
 275                 reg = <0x02a00000 0x10000>,
 276                       <0x02b00000 0xc0000>;
 277                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 278         };
 279
 280         soc {
 281                 #address-cells = <1>;
 282                 #size-cells = <1>;
 283                 compatible = "simple-bus";
 284                 ranges;
 285
 286                 aon_sysctrl: aon-sysctrl@116000 {
 287                         compatible = "zte,zx296718-aon-sysctrl", "syscon";
 288                         reg = <0x116000 0x1000>;
 289                 };
 290
 291                 uart0: uart@11f000 {
 292                         compatible = "arm,pl011", "arm,primecell";
 293                         arm,primecell-periphid = <0x001feffe>;
 294                         reg = <0x11f000 0x1000>;
 295                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 296                         clocks = <&osc24m>;
 297                         clock-names = "apb_pclk";
 298                         status = "disabled";
 299                 };
 300
 301                 sd0: mmc@1110000 {
 302                         compatible = "zte,zx296718-dw-mshc";
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <0x01110000 0x1000>;
 306                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 307                         fifo-depth = <32>;
 308                         data-addr = <0x200>;
 309                         fifo-watermark-aligned;
 310                         bus-width = <4>;
 311                         clock-frequency = <50000000>;
 312                         clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
 313                         clock-names = "biu", "ciu";
 314                         num-slots = <1>;
 315                         max-frequency = <50000000>;
 316                         cap-sdio-irq;
 317                         cap-sd-highspeed;
 318                         sd-uhs-sdr12;
 319                         sd-uhs-sdr25;
 320                         sd-uhs-sdr50;
 321                         sd-uhs-sdr104;
 322                         sd-uhs-ddr50;
 323                         status = "disabled";
 324                 };
 325
 326                 sd1: mmc@1111000 {
 327                         compatible = "zte,zx296718-dw-mshc";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         reg = <0x01111000 0x1000>;
 331                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 332                         fifo-depth = <32>;
 333                         data-addr = <0x200>;
 334                         fifo-watermark-aligned;
 335                         bus-width = <4>;
 336                         clock-frequency = <167000000>;
 337                         clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
 338                         clock-names = "biu", "ciu";
 339                         num-slots = <1>;
 340                         max-frequency = <167000000>;
 341                         cap-sdio-irq;
 342                         cap-sd-highspeed;
 343                         status = "disabled";
 344                 };
 345
 346                 dma: dma-controller@1460000 {
 347                         compatible = "zte,zx296702-dma";
 348                         reg = <0x01460000 0x1000>;
 349                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 350                         clocks = <&osc24m>;
 351                         clock-names = "dmaclk";
 352                         #dma-cells = <1>;
 353                         dma-channels = <32>;
 354                         dma-requests = <32>;
 355                 };
 356
 357                 lsp0crm: clock-controller@1420000 {
 358                         compatible = "zte,zx296718-lsp0crm";
 359                         reg = <0x01420000 0x1000>;
 360                         #clock-cells = <1>;
 361                 };
 362
 363                 lsp1crm: clock-controller@1430000 {
 364                         compatible = "zte,zx296718-lsp1crm";
 365                         reg = <0x01430000 0x1000>;
 366                         #clock-cells = <1>;
 367                 };
 368
 369                 vou: vou@1440000 {
 370                         compatible = "zte,zx296718-vou";
 371                         #address-cells = <1>;
 372                         #size-cells = <1>;
 373                         ranges = <0 0x1440000 0x10000>;
 374
 375                         dpc: dpc@0 {
 376                                 compatible = "zte,zx296718-dpc";
 377                                 reg = <0x0000 0x1000>, <0x1000 0x1000>,
 378                                       <0x5000 0x1000>, <0x6000 0x1000>,
 379                                       <0xa000 0x1000>;
 380                                 reg-names = "osd", "timing_ctrl",
 381                                             "dtrc", "vou_ctrl",
 382                                             "otfppu";
 383                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
 385                                          <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
 386                                 clock-names = "aclk", "ppu_wclk",
 387                                               "main_wclk", "aux_wclk";
 388                         };
 389
 390                         hdmi: hdmi@c000 {
 391                                 compatible = "zte,zx296718-hdmi";
 392                                 reg = <0xc000 0x4000>;
 393                                 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
 394                                 clocks = <&topcrm HDMI_OSC_CEC>,
 395                                          <&topcrm HDMI_OSC_CLK>,
 396                                          <&topcrm HDMI_XCLK>;
 397                                 clock-names = "osc_cec", "osc_clk", "xclk";
 398                                 #sound-dai-cells = <0>;
 399                                 status = "disabled";
 400                         };
 401
 402                         tvenc: tvenc@2000 {
 403                                 compatible = "zte,zx296718-tvenc";
 404                                 reg = <0x2000 0x1000>;
 405                                 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
 406                                 status = "disabled";
 407                         };
 408                 };
 409
 410                 topcrm: clock-controller@1461000 {
 411                         compatible = "zte,zx296718-topcrm";
 412                         reg = <0x01461000 0x1000>;
 413                         #clock-cells = <1>;
 414                 };
 415
 416                 sysctrl: sysctrl@1463000 {
 417                         compatible = "zte,zx296718-sysctrl", "syscon";
 418                         reg = <0x1463000 0x1000>;
 419                 };
 420
 421                 emmc: mmc@1470000{
 422                         compatible = "zte,zx296718-dw-mshc";
 423                         reg = <0x01470000 0x1000>;
 424                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 425                         zte,aon-syscon = <&aon_sysctrl>;
 426                         bus-width = <8>;
 427                         fifo-depth = <128>;
 428                         data-addr = <0x200>;
 429                         fifo-watermark-aligned;
 430                         clock-frequency = <167000000>;
 431                         clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
 432                         clock-names = "biu", "ciu";
 433                         max-frequency = <167000000>;
 434                         cap-mmc-highspeed;
 435                         mmc-ddr-1_8v;
 436                         mmc-hs200-1_8v;
 437                         non-removable;
 438                         disable-wp;
 439                         status = "disabled";
 440                 };
 441
 442                 audiocrm: clock-controller@1480000 {
 443                         compatible = "zte,zx296718-audiocrm";
 444                         reg = <0x01480000 0x1000>;
 445                         #clock-cells = <1>;
 446                 };
 447
 448                 spdif0: spdif@1488000 {
 449                         compatible = "zte,zx296702-spdif";
 450                         reg = <0x1488000 0x1000>;
 451                         clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
 452                         clock-names = "tx";
 453                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 454                         #sound-dai-cells = <0>;
 455                         dmas = <&dma 30>;
 456                         dma-names = "tx";
 457                         status = "disabled";
 458                 };
 459         };
 460 };