arch/arm64/boot/dts/zte/zx296718.dtsi

   1 /*
   2  * Copyright 2016 ZTE Corporation.
   3  * Copyright 2016 Linaro Ltd.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/input/input.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/clock/zx296718-clock.h>
  48
  49 / {
  50         compatible = "zte,zx296718";
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57         };
  58
  59         cpus {
  60                 #address-cells = <2>;
  61                 #size-cells = <0>;
  62
  63                 cpu-map {
  64                         cluster0 {
  65                                 core0 {
  66                                         cpu = <&cpu0>;
  67                                 };
  68                                 core1 {
  69                                         cpu = <&cpu1>;
  70                                 };
  71                                 core2 {
  72                                         cpu = <&cpu2>;
  73                                 };
  74                                 core3 {
  75                                         cpu = <&cpu3>;
  76                                 };
  77                         };
  78                 };
  79
  80                 cpu0: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53","arm,armv8";
  83                         reg = <0x0 0x0>;
  84                         enable-method = "psci";
  85                         clocks = <&topcrm A53_GATE>;
  86                         operating-points-v2 = <&cluster0_opp>;
  87                 };
  88
  89                 cpu1: cpu@1 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x1>;
  93                         enable-method = "psci";
  94                         clocks = <&topcrm A53_GATE>;
  95                         operating-points-v2 = <&cluster0_opp>;
  96                 };
  97
  98                 cpu2: cpu@2 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a53","arm,armv8";
 101                         reg = <0x0 0x2>;
 102                         enable-method = "psci";
 103                         clocks = <&topcrm A53_GATE>;
 104                         operating-points-v2 = <&cluster0_opp>;
 105                 };
 106
 107                 cpu3: cpu@3 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a53","arm,armv8";
 110                         reg = <0x0 0x3>;
 111                         enable-method = "psci";
 112                         clocks = <&topcrm A53_GATE>;
 113                         operating-points-v2 = <&cluster0_opp>;
 114                 };
 115         };
 116
 117         cluster0_opp: opp-table0 {
 118                 compatible = "operating-points-v2";
 119                 opp-shared;
 120
 121                 opp@500000000 {
 122                         opp-hz = /bits/ 64 <500000000>;
 123                         clock-latency-ns = <500000>;
 124                 };
 125
 126                 opp@648000000 {
 127                         opp-hz = /bits/ 64 <648000000>;
 128                         clock-latency-ns = <500000>;
 129                 };
 130
 131                 opp@800000000 {
 132                         opp-hz = /bits/ 64 <800000000>;
 133                         clock-latency-ns = <500000>;
 134                 };
 135
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         clock-latency-ns = <500000>;
 139                 };
 140
 141                 opp@1188000000 {
 142                         opp-hz = /bits/ 64 <1188000000>;
 143                         clock-latency-ns = <500000>;
 144                 };
 145         };
 146
 147         clk24k: clk-24k {
 148                 compatible = "fixed-clock";
 149                 #clock-cells = <0>;
 150                 clock-frequency = <24000>;
 151                 clock-output-names = "rtcclk";
 152         };
 153
 154         osc32k: clk-osc32k {
 155                 compatible = "fixed-clock";
 156                 #clock-cells = <0>;
 157                 clock-frequency = <32000>;
 158                 clock-output-names = "osc32k";
 159         };
 160
 161         osc12m: clk-osc12m {
 162                 compatible = "fixed-clock";
 163                 #clock-cells = <0>;
 164                 clock-frequency = <12000000>;
 165                 clock-output-names = "osc12m";
 166         };
 167
 168         osc24m: clk-osc24m {
 169                 compatible = "fixed-clock";
 170                 #clock-cells = <0>;
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "osc24m";
 173         };
 174
 175         osc25m: clk-osc25m {
 176                 compatible = "fixed-clock";
 177                 #clock-cells = <0>;
 178                 clock-frequency = <25000000>;
 179                 clock-output-names = "osc25m";
 180         };
 181
 182         osc60m: clk-osc60m {
 183                 compatible = "fixed-clock";
 184                 #clock-cells = <0>;
 185                 clock-frequency = <60000000>;
 186                 clock-output-names = "osc60m";
 187         };
 188
 189         osc99m: clk-osc99m {
 190                 compatible = "fixed-clock";
 191                 #clock-cells = <0>;
 192                 clock-frequency = <99000000>;
 193                 clock-output-names = "osc99m";
 194         };
 195
 196         osc125m: clk-osc125m {
 197                 compatible = "fixed-clock";
 198                 #clock-cells = <0>;
 199                 clock-frequency = <125000000>;
 200                 clock-output-names = "osc125m";
 201         };
 202
 203         osc198m: clk-osc198m {
 204                 compatible = "fixed-clock";
 205                 #clock-cells = <0>;
 206                 clock-frequency = <198000000>;
 207                 clock-output-names = "osc198m";
 208         };
 209
 210         pll_audio: clk-pll-884m {
 211                 compatible = "fixed-clock";
 212                 #clock-cells = <0>;
 213                 clock-frequency = <884000000>;
 214                 clock-output-names = "pll_audio";
 215         };
 216
 217         pll_ddr: clk-pll-932m {
 218                 compatible = "fixed-clock";
 219                 #clock-cells = <0>;
 220                 clock-frequency = <932000000>;
 221                 clock-output-names = "pll_ddr";
 222         };
 223
 224         pll_hsic: clk-pll-960m {
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <960000000>;
 228                 clock-output-names = "pll_hsic";
 229         };
 230
 231         pll_mac: clk-pll-1000m {
 232                 compatible = "fixed-clock";
 233                 #clock-cells = <0>;
 234                 clock-frequency = <1000000000>;
 235                 clock-output-names = "pll_mac";
 236         };
 237
 238         pll_vga: clk-pll-1073m {
 239                 compatible = "fixed-clock";
 240                 #clock-cells = <0>;
 241                 clock-frequency = <1073000000>;
 242                 clock-output-names = "pll_vga";
 243         };
 244
 245         pll_mm0: clk-pll-1188m {
 246                 compatible = "fixed-clock";
 247                 #clock-cells = <0>;
 248                 clock-frequency = <1188000000>;
 249                 clock-output-names = "pll_mm0";
 250         };
 251
 252         pll_mm1: clk-pll-1296m {
 253                 compatible = "fixed-clock";
 254                 #clock-cells = <0>;
 255                 clock-frequency = <1296000000>;
 256                 clock-output-names = "pll_mm1";
 257         };
 258
 259         psci {
 260                 compatible = "arm,psci-1.0";
 261                 method = "smc";
 262         };
 263
 264         timer {
 265                 compatible = "arm,armv8-timer";
 266                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 267                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 268                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 269                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 270         };
 271
 272         pmu {
 273                 compatible = "arm,cortex-a53-pmu";
 274                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 275         };
 276
 277         gic: interrupt-controller@2a00000 {
 278                 compatible = "arm,gic-v3";
 279                 #interrupt-cells = <3>;
 280                 #address-cells = <0>;
 281                 interrupt-controller;
 282                 reg = <0x02a00000 0x10000>,
 283                       <0x02b00000 0xc0000>;
 284                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 285         };
 286
 287         soc {
 288                 #address-cells = <1>;
 289                 #size-cells = <1>;
 290                 compatible = "simple-bus";
 291                 ranges;
 292
 293                 aon_sysctrl: aon-sysctrl@116000 {
 294                         compatible = "zte,zx296718-aon-sysctrl", "syscon";
 295                         reg = <0x116000 0x1000>;
 296                 };
 297
 298                 uart0: uart@11f000 {
 299                         compatible = "arm,pl011", "arm,primecell";
 300                         arm,primecell-periphid = <0x001feffe>;
 301                         reg = <0x11f000 0x1000>;
 302                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&osc24m>;
 304                         clock-names = "apb_pclk";
 305                         status = "disabled";
 306                 };
 307
 308                 dma: dma-controller@1460000 {
 309                         compatible = "zte,zx296702-dma";
 310                         reg = <0x01460000 0x1000>;
 311                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&osc24m>;
 313                         clock-names = "dmaclk";
 314                         #dma-cells = <1>;
 315                         dma-channels = <32>;
 316                         dma-requests = <32>;
 317                 };
 318
 319                 lsp0crm: clock-controller@1420000 {
 320                         compatible = "zte,zx296718-lsp0crm";
 321                         reg = <0x01420000 0x1000>;
 322                         #clock-cells = <1>;
 323                 };
 324
 325                 lsp1crm: clock-controller@1430000 {
 326                         compatible = "zte,zx296718-lsp1crm";
 327                         reg = <0x01430000 0x1000>;
 328                         #clock-cells = <1>;
 329                 };
 330
 331                 topcrm: clock-controller@1461000 {
 332                         compatible = "zte,zx296718-topcrm";
 333                         reg = <0x01461000 0x1000>;
 334                         #clock-cells = <1>;
 335                 };
 336
 337                 sysctrl: sysctrl@1463000 {
 338                         compatible = "zte,zx296718-sysctrl", "syscon";
 339                         reg = <0x1463000 0x1000>;
 340                 };
 341
 342                 audiocrm: clock-controller@1480000 {
 343                         compatible = "zte,zx296718-audiocrm";
 344                         reg = <0x01480000 0x1000>;
 345                         #clock-cells = <1>;
 346                 };
 347         };
 348 };