2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
22 * For SMTC kernel, global IE should be left set, and interrupts
23 * controlled exclusively via IXMT.
25 #ifdef CONFIG_MIPS_MT_SMTC
27 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
33 #ifdef CONFIG_MIPS_MT_SMTC
34 #include <asm/mipsmtregs.h>
35 #endif /* CONFIG_MIPS_MT_SMTC */
45 #ifdef CONFIG_CPU_HAS_SMARTMIPS
59 LONG_S $10, PT_R10(sp)
60 LONG_S $11, PT_R11(sp)
61 LONG_S $12, PT_R12(sp)
62 #ifndef CONFIG_CPU_HAS_SMARTMIPS
66 LONG_S $13, PT_R13(sp)
67 LONG_S $14, PT_R14(sp)
68 LONG_S $15, PT_R15(sp)
69 LONG_S $24, PT_R24(sp)
70 #ifndef CONFIG_CPU_HAS_SMARTMIPS
73 #ifdef CONFIG_CPU_CAVIUM_OCTEON
75 * The Octeon multiplier state is affected by general
76 * multiply instructions. It must be saved before and
77 * kernel code might corrupt it
84 LONG_S $16, PT_R16(sp)
85 LONG_S $17, PT_R17(sp)
86 LONG_S $18, PT_R18(sp)
87 LONG_S $19, PT_R19(sp)
88 LONG_S $20, PT_R20(sp)
89 LONG_S $21, PT_R21(sp)
90 LONG_S $22, PT_R22(sp)
91 LONG_S $23, PT_R23(sp)
92 LONG_S $30, PT_R30(sp)
96 #ifdef CONFIG_MIPS_MT_SMTC
97 #define PTEBASE_SHIFT 19 /* TCBIND */
98 #define CPU_ID_REG CP0_TCBIND
99 #define CPU_ID_MFC0 mfc0
100 #elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
101 #define PTEBASE_SHIFT 48 /* XCONTEXT */
102 #define CPU_ID_REG CP0_XCONTEXT
103 #define CPU_ID_MFC0 MFC0
105 #define PTEBASE_SHIFT 23 /* CONTEXT */
106 #define CPU_ID_REG CP0_CONTEXT
107 #define CPU_ID_MFC0 MFC0
109 .macro get_saved_sp /* SMP variation */
110 CPU_ID_MFC0 k0, CPU_ID_REG
111 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
112 lui k1, %hi(kernelsp)
114 lui k1, %highest(kernelsp)
115 daddiu k1, %higher(kernelsp)
117 daddiu k1, %hi(kernelsp)
120 LONG_SRL k0, PTEBASE_SHIFT
122 LONG_L k1, %lo(kernelsp)(k1)
125 .macro set_saved_sp stackp temp temp2
126 CPU_ID_MFC0 \temp, CPU_ID_REG
127 LONG_SRL \temp, PTEBASE_SHIFT
128 LONG_S \stackp, kernelsp(\temp)
131 .macro get_saved_sp /* Uniprocessor variation */
132 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
134 * Clear BTB (branch target buffer), forbid RAS (return address
135 * stack) to workaround the Out-of-order Issue in Loongson2F
136 * via its diagnostic register.
150 #endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
151 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
152 lui k1, %hi(kernelsp)
154 lui k1, %highest(kernelsp)
155 daddiu k1, %higher(kernelsp)
157 daddiu k1, %hi(kernelsp)
160 LONG_L k1, %lo(kernelsp)(k1)
163 .macro set_saved_sp stackp temp temp2
164 LONG_S \stackp, kernelsp
173 sll k0, 3 /* extract cu0 bit */
178 /* Called from user mode, new stack. */
180 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
182 PTR_SUBU sp, k1, PT_SIZE
185 8: PTR_SUBU k1, PT_SIZE
190 LONG_S k0, PT_R29(sp)
193 * You might think that you don't need to save $0,
194 * but the FPU emulator and gdb remote debug stub
195 * need it to operate correctly
200 LONG_S v1, PT_STATUS(sp)
201 #ifdef CONFIG_MIPS_MT_SMTC
203 * Ideally, these instructions would be shuffled in
204 * to cover the pipeline delay.
207 mfc0 k0, CP0_TCSTATUS
209 LONG_S k0, PT_TCSTATUS(sp)
210 #endif /* CONFIG_MIPS_MT_SMTC */
214 LONG_S v1, PT_CAUSE(sp)
222 LONG_S v1, PT_EPC(sp)
223 LONG_S $25, PT_R25(sp)
224 LONG_S $28, PT_R28(sp)
225 LONG_S $31, PT_R31(sp)
226 ori $28, sp, _THREAD_MASK
227 xori $28, _THREAD_MASK
228 #ifdef CONFIG_CPU_CAVIUM_OCTEON
230 pref 0, 0($28) /* Prefetch the current pointer */
250 #ifdef CONFIG_CPU_CAVIUM_OCTEON
251 /* Restore the Octeon multiplier state */
252 jal octeon_mult_restore
254 #ifdef CONFIG_CPU_HAS_SMARTMIPS
255 LONG_L $24, PT_ACX(sp)
257 LONG_L $24, PT_HI(sp)
259 LONG_L $24, PT_LO(sp)
262 LONG_L $24, PT_LO(sp)
264 LONG_L $24, PT_HI(sp)
271 LONG_L $10, PT_R10(sp)
272 LONG_L $11, PT_R11(sp)
273 LONG_L $12, PT_R12(sp)
274 LONG_L $13, PT_R13(sp)
275 LONG_L $14, PT_R14(sp)
276 LONG_L $15, PT_R15(sp)
277 LONG_L $24, PT_R24(sp)
280 .macro RESTORE_STATIC
281 LONG_L $16, PT_R16(sp)
282 LONG_L $17, PT_R17(sp)
283 LONG_L $18, PT_R18(sp)
284 LONG_L $19, PT_R19(sp)
285 LONG_L $20, PT_R20(sp)
286 LONG_L $21, PT_R21(sp)
287 LONG_L $22, PT_R22(sp)
288 LONG_L $23, PT_R23(sp)
289 LONG_L $30, PT_R30(sp)
292 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
304 LONG_L v0, PT_STATUS(sp)
309 LONG_L $31, PT_R31(sp)
310 LONG_L $28, PT_R28(sp)
311 LONG_L $25, PT_R25(sp)
321 .macro RESTORE_SP_AND_RET
324 LONG_L k0, PT_EPC(sp)
325 LONG_L sp, PT_R29(sp)
336 #ifdef CONFIG_MIPS_MT_SMTC
339 * We need to make sure the read-modify-write
340 * of Status below isn't perturbed by an interrupt
341 * or cross-TC access, so we need to do at least a DMT,
342 * protected by an interrupt-inhibit. But setting IXMT
343 * also creates a few-cycle window where an IPI could
344 * be queued and not be detected before potentially
345 * returning to a WAIT or user-mode loop. It must be
348 * We're in the middle of a context switch, and
349 * we can't dispatch it directly without trashing
350 * some registers, so we'll try to detect this unlikely
351 * case and program a software interrupt in the VPE,
352 * as would be done for a cross-VPE IPI. To accommodate
353 * the handling of that case, we're doing a DVPE instead
354 * of just a DMT here to protect against other threads.
355 * This is a lot of cruft to cover a tiny window.
356 * If you can find a better design, implement it!
359 mfc0 v0, CP0_TCSTATUS
360 ori v0, TCSTATUS_IXMT
361 mtc0 v0, CP0_TCSTATUS
365 #endif /* CONFIG_MIPS_MT_SMTC */
372 LONG_L v0, PT_STATUS(sp)
377 #ifdef CONFIG_MIPS_MT_SMTC
379 * Only after EXL/ERL have been restored to status can we
380 * restore TCStatus.IXMT.
382 LONG_L v1, PT_TCSTATUS(sp)
384 mfc0 a0, CP0_TCSTATUS
385 andi v1, TCSTATUS_IXMT
389 * We'd like to detect any IPIs queued in the tiny window
390 * above and request an software interrupt to service them
393 * Computing the offset into the IPIQ array of the executing
394 * TC's IPI queue in-line would be tedious. We use part of
395 * the TCContext register to hold 16 bits of offset that we
396 * can add in-line to find the queue head.
398 mfc0 v0, CP0_TCCONTEXT
405 * If we have a queue, provoke dispatch within the VPE by setting C_SW1
412 * This test should really never branch but
413 * let's be prudent here. Having atomized
414 * the shared register modifications, we can
415 * now EVPE, and must do so before interrupts
416 * are potentially re-enabled.
418 andi a1, a1, MVPCONTROL_EVP
422 /* We know that TCStatua.IXMT should be set from above */
423 xori a0, a0, TCSTATUS_IXMT
425 mtc0 a0, CP0_TCSTATUS
429 #endif /* CONFIG_MIPS_MT_SMTC */
430 LONG_L v1, PT_EPC(sp)
432 LONG_L $31, PT_R31(sp)
433 LONG_L $28, PT_R28(sp)
434 LONG_L $25, PT_R25(sp)
448 .macro RESTORE_SP_AND_RET
449 LONG_L sp, PT_R29(sp)
458 LONG_L sp, PT_R29(sp)
469 .macro RESTORE_ALL_AND_RET
478 * Move to kernel mode and disable interrupts.
479 * Set cp0 enable bit as sign that we're running on the kernel stack
482 #if !defined(CONFIG_MIPS_MT_SMTC)
484 li t1, ST0_CU0 | STATMASK
488 #else /* CONFIG_MIPS_MT_SMTC */
490 * For SMTC, we need to set privilege
491 * and disable interrupts only for the
492 * current TC, using the TCStatus register.
494 mfc0 t0, CP0_TCSTATUS
495 /* Fortunately CU 0 is in the same place in both registers */
496 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
497 li t1, ST0_CU0 | 0x08001c00
499 /* Clear TKSU, leave IXMT */
501 mtc0 t0, CP0_TCSTATUS
503 /* We need to leave the global IE bit set, but clear EXL...*/
505 ori t0, ST0_EXL | ST0_ERL
506 xori t0, ST0_EXL | ST0_ERL
508 #endif /* CONFIG_MIPS_MT_SMTC */
513 * Move to kernel mode and enable interrupts.
514 * Set cp0 enable bit as sign that we're running on the kernel stack
517 #if !defined(CONFIG_MIPS_MT_SMTC)
519 li t1, ST0_CU0 | STATMASK
521 xori t0, STATMASK & ~1
523 #else /* CONFIG_MIPS_MT_SMTC */
525 * For SMTC, we need to set privilege
526 * and enable interrupts only for the
527 * current TC, using the TCStatus register.
530 mfc0 t0, CP0_TCSTATUS
531 /* Fortunately CU 0 is in the same place in both registers */
532 /* Set TCU0, TKSU (for later inversion) and IXMT */
533 li t1, ST0_CU0 | 0x08001c00
535 /* Clear TKSU *and* IXMT */
537 mtc0 t0, CP0_TCSTATUS
539 /* We need to leave the global IE bit set, but clear EXL...*/
544 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
545 #endif /* CONFIG_MIPS_MT_SMTC */
550 * Just move to kernel mode and leave interrupts as they are. Note
551 * for the R3000 this means copying the previous enable from IEp.
552 * Set cp0 enable bit as sign that we're running on the kernel stack
555 #ifdef CONFIG_MIPS_MT_SMTC
557 * This gets baroque in SMTC. We want to
558 * protect the non-atomic clearing of EXL
559 * with DMT/EMT, but we don't want to take
560 * an interrupt while DMT is still in effect.
563 /* KMODE gets invoked from both reorder and noreorder code */
567 mfc0 v0, CP0_TCSTATUS
568 andi v1, v0, TCSTATUS_IXMT
569 ori v0, TCSTATUS_IXMT
570 mtc0 v0, CP0_TCSTATUS
574 * We don't know a priori if ra is "live"
580 #endif /* CONFIG_MIPS_MT_SMTC */
582 li t1, ST0_CU0 | (STATMASK & ~1)
583 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
589 xori t0, STATMASK & ~1
591 #ifdef CONFIG_MIPS_MT_SMTC
593 andi v0, v0, VPECONTROL_TE
598 mfc0 v0, CP0_TCSTATUS
599 /* Clear IXMT, then OR in previous value */
600 ori v0, TCSTATUS_IXMT
601 xori v0, TCSTATUS_IXMT
603 mtc0 v0, CP0_TCSTATUS
605 * irq_disable_hazard below should expand to EHB
609 #endif /* CONFIG_MIPS_MT_SMTC */
613 #endif /* _ASM_STACKFRAME_H */