arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/stddef.h>
  26 #include <linux/unistd.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/slab.h>
  29 #include <linux/user.h>
  30 #include <linux/elf.h>
  31 #include <linux/prctl.h>
  32 #include <linux/init_task.h>
  33 #include <linux/export.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/mqueue.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/utsname.h>
  38 #include <linux/ftrace.h>
  39 #include <linux/kernel_stat.h>
  40 #include <linux/personality.h>
  41 #include <linux/random.h>
  42 #include <linux/hw_breakpoint.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/elf-randomize.h>
  45
  46 #include <asm/pgtable.h>
  47 #include <asm/io.h>
  48 #include <asm/processor.h>
  49 #include <asm/mmu.h>
  50 #include <asm/prom.h>
  51 #include <asm/machdep.h>
  52 #include <asm/time.h>
  53 #include <asm/runlatch.h>
  54 #include <asm/syscalls.h>
  55 #include <asm/switch_to.h>
  56 #include <asm/tm.h>
  57 #include <asm/debug.h>
  58 #ifdef CONFIG_PPC64
  59 #include <asm/firmware.h>
  60 #endif
  61 #include <asm/code-patching.h>
  62 #include <asm/exec.h>
  63 #include <asm/livepatch.h>
  64 #include <asm/cpu_has_feature.h>
  65 #include <asm/asm-prototypes.h>
  66
  67 #include <linux/kprobes.h>
  68 #include <linux/kdebug.h>
  69
  70 /* Transactional Memory debug */
  71 #ifdef TM_DEBUG_SW
  72 #define TM_DEBUG(x...) printk(KERN_INFO x)
  73 #else
  74 #define TM_DEBUG(x...) do { } while(0)
  75 #endif
  76
  77 extern unsigned long _get_SP(void);
  78
  79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  80 static void check_if_tm_restore_required(struct task_struct *tsk)
  81 {
  82         /*
  83          * If we are saving the current thread's registers, and the
  84          * thread is in a transactional state, set the TIF_RESTORE_TM
  85          * bit so that we know to restore the registers before
  86          * returning to userspace.
  87          */
  88         if (tsk == current && tsk->thread.regs &&
  89             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  90             !test_thread_flag(TIF_RESTORE_TM)) {
  91                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  92                 set_thread_flag(TIF_RESTORE_TM);
  93         }
  94 }
  95
  96 static inline bool msr_tm_active(unsigned long msr)
  97 {
  98         return MSR_TM_ACTIVE(msr);
  99 }
 100 #else
 101 static inline bool msr_tm_active(unsigned long msr) { return false; }
 102 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 103 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 104
 105 bool strict_msr_control;
 106 EXPORT_SYMBOL(strict_msr_control);
 107
 108 static int __init enable_strict_msr_control(char *str)
 109 {
 110         strict_msr_control = true;
 111         pr_info("Enabling strict facility control\n");
 112
 113         return 0;
 114 }
 115 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 116
 117 unsigned long msr_check_and_set(unsigned long bits)
 118 {
 119         unsigned long oldmsr = mfmsr();
 120         unsigned long newmsr;
 121
 122         newmsr = oldmsr | bits;
 123
 124 #ifdef CONFIG_VSX
 125         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 126                 newmsr |= MSR_VSX;
 127 #endif
 128
 129         if (oldmsr != newmsr)
 130                 mtmsr_isync(newmsr);
 131
 132         return newmsr;
 133 }
 134
 135 void __msr_check_and_clear(unsigned long bits)
 136 {
 137         unsigned long oldmsr = mfmsr();
 138         unsigned long newmsr;
 139
 140         newmsr = oldmsr & ~bits;
 141
 142 #ifdef CONFIG_VSX
 143         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 144                 newmsr &= ~MSR_VSX;
 145 #endif
 146
 147         if (oldmsr != newmsr)
 148                 mtmsr_isync(newmsr);
 149 }
 150 EXPORT_SYMBOL(__msr_check_and_clear);
 151
 152 #ifdef CONFIG_PPC_FPU
 153 void __giveup_fpu(struct task_struct *tsk)
 154 {
 155         unsigned long msr;
 156
 157         save_fpu(tsk);
 158         msr = tsk->thread.regs->msr;
 159         msr &= ~MSR_FP;
 160 #ifdef CONFIG_VSX
 161         if (cpu_has_feature(CPU_FTR_VSX))
 162                 msr &= ~MSR_VSX;
 163 #endif
 164         tsk->thread.regs->msr = msr;
 165 }
 166
 167 void giveup_fpu(struct task_struct *tsk)
 168 {
 169         check_if_tm_restore_required(tsk);
 170
 171         msr_check_and_set(MSR_FP);
 172         __giveup_fpu(tsk);
 173         msr_check_and_clear(MSR_FP);
 174 }
 175 EXPORT_SYMBOL(giveup_fpu);
 176
 177 /*
 178  * Make sure the floating-point register state in the
 179  * the thread_struct is up to date for task tsk.
 180  */
 181 void flush_fp_to_thread(struct task_struct *tsk)
 182 {
 183         if (tsk->thread.regs) {
 184                 /*
 185                  * We need to disable preemption here because if we didn't,
 186                  * another process could get scheduled after the regs->msr
 187                  * test but before we have finished saving the FP registers
 188                  * to the thread_struct.  That process could take over the
 189                  * FPU, and then when we get scheduled again we would store
 190                  * bogus values for the remaining FP registers.
 191                  */
 192                 preempt_disable();
 193                 if (tsk->thread.regs->msr & MSR_FP) {
 194                         /*
 195                          * This should only ever be called for current or
 196                          * for a stopped child process.  Since we save away
 197                          * the FP register state on context switch,
 198                          * there is something wrong if a stopped child appears
 199                          * to still have its FP state in the CPU registers.
 200                          */
 201                         BUG_ON(tsk != current);
 202                         giveup_fpu(tsk);
 203                 }
 204                 preempt_enable();
 205         }
 206 }
 207 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 208
 209 void enable_kernel_fp(void)
 210 {
 211         unsigned long cpumsr;
 212
 213         WARN_ON(preemptible());
 214
 215         cpumsr = msr_check_and_set(MSR_FP);
 216
 217         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 218                 check_if_tm_restore_required(current);
 219                 /*
 220                  * If a thread has already been reclaimed then the
 221                  * checkpointed registers are on the CPU but have definitely
 222                  * been saved by the reclaim code. Don't need to and *cannot*
 223                  * giveup as this would save  to the 'live' structure not the
 224                  * checkpointed structure.
 225                  */
 226                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 227                         return;
 228                 __giveup_fpu(current);
 229         }
 230 }
 231 EXPORT_SYMBOL(enable_kernel_fp);
 232
 233 static int restore_fp(struct task_struct *tsk) {
 234         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 235                 load_fp_state(&current->thread.fp_state);
 236                 current->thread.load_fp++;
 237                 return 1;
 238         }
 239         return 0;
 240 }
 241 #else
 242 static int restore_fp(struct task_struct *tsk) { return 0; }
 243 #endif /* CONFIG_PPC_FPU */
 244
 245 #ifdef CONFIG_ALTIVEC
 246 #define loadvec(thr) ((thr).load_vec)
 247
 248 static void __giveup_altivec(struct task_struct *tsk)
 249 {
 250         unsigned long msr;
 251
 252         save_altivec(tsk);
 253         msr = tsk->thread.regs->msr;
 254         msr &= ~MSR_VEC;
 255 #ifdef CONFIG_VSX
 256         if (cpu_has_feature(CPU_FTR_VSX))
 257                 msr &= ~MSR_VSX;
 258 #endif
 259         tsk->thread.regs->msr = msr;
 260 }
 261
 262 void giveup_altivec(struct task_struct *tsk)
 263 {
 264         check_if_tm_restore_required(tsk);
 265
 266         msr_check_and_set(MSR_VEC);
 267         __giveup_altivec(tsk);
 268         msr_check_and_clear(MSR_VEC);
 269 }
 270 EXPORT_SYMBOL(giveup_altivec);
 271
 272 void enable_kernel_altivec(void)
 273 {
 274         unsigned long cpumsr;
 275
 276         WARN_ON(preemptible());
 277
 278         cpumsr = msr_check_and_set(MSR_VEC);
 279
 280         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 281                 check_if_tm_restore_required(current);
 282                 /*
 283                  * If a thread has already been reclaimed then the
 284                  * checkpointed registers are on the CPU but have definitely
 285                  * been saved by the reclaim code. Don't need to and *cannot*
 286                  * giveup as this would save  to the 'live' structure not the
 287                  * checkpointed structure.
 288                  */
 289                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 290                         return;
 291                 __giveup_altivec(current);
 292         }
 293 }
 294 EXPORT_SYMBOL(enable_kernel_altivec);
 295
 296 /*
 297  * Make sure the VMX/Altivec register state in the
 298  * the thread_struct is up to date for task tsk.
 299  */
 300 void flush_altivec_to_thread(struct task_struct *tsk)
 301 {
 302         if (tsk->thread.regs) {
 303                 preempt_disable();
 304                 if (tsk->thread.regs->msr & MSR_VEC) {
 305                         BUG_ON(tsk != current);
 306                         giveup_altivec(tsk);
 307                 }
 308                 preempt_enable();
 309         }
 310 }
 311 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 312
 313 static int restore_altivec(struct task_struct *tsk)
 314 {
 315         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 316                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 317                 load_vr_state(&tsk->thread.vr_state);
 318                 tsk->thread.used_vr = 1;
 319                 tsk->thread.load_vec++;
 320
 321                 return 1;
 322         }
 323         return 0;
 324 }
 325 #else
 326 #define loadvec(thr) 0
 327 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 328 #endif /* CONFIG_ALTIVEC */
 329
 330 #ifdef CONFIG_VSX
 331 static void __giveup_vsx(struct task_struct *tsk)
 332 {
 333         if (tsk->thread.regs->msr & MSR_FP)
 334                 __giveup_fpu(tsk);
 335         if (tsk->thread.regs->msr & MSR_VEC)
 336                 __giveup_altivec(tsk);
 337         tsk->thread.regs->msr &= ~MSR_VSX;
 338 }
 339
 340 static void giveup_vsx(struct task_struct *tsk)
 341 {
 342         check_if_tm_restore_required(tsk);
 343
 344         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 345         __giveup_vsx(tsk);
 346         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 347 }
 348
 349 static void save_vsx(struct task_struct *tsk)
 350 {
 351         if (tsk->thread.regs->msr & MSR_FP)
 352                 save_fpu(tsk);
 353         if (tsk->thread.regs->msr & MSR_VEC)
 354                 save_altivec(tsk);
 355 }
 356
 357 void enable_kernel_vsx(void)
 358 {
 359         unsigned long cpumsr;
 360
 361         WARN_ON(preemptible());
 362
 363         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 364
 365         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 366                 check_if_tm_restore_required(current);
 367                 /*
 368                  * If a thread has already been reclaimed then the
 369                  * checkpointed registers are on the CPU but have definitely
 370                  * been saved by the reclaim code. Don't need to and *cannot*
 371                  * giveup as this would save  to the 'live' structure not the
 372                  * checkpointed structure.
 373                  */
 374                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 375                         return;
 376                 if (current->thread.regs->msr & MSR_FP)
 377                         __giveup_fpu(current);
 378                 if (current->thread.regs->msr & MSR_VEC)
 379                         __giveup_altivec(current);
 380                 __giveup_vsx(current);
 381         }
 382 }
 383 EXPORT_SYMBOL(enable_kernel_vsx);
 384
 385 void flush_vsx_to_thread(struct task_struct *tsk)
 386 {
 387         if (tsk->thread.regs) {
 388                 preempt_disable();
 389                 if (tsk->thread.regs->msr & MSR_VSX) {
 390                         BUG_ON(tsk != current);
 391                         giveup_vsx(tsk);
 392                 }
 393                 preempt_enable();
 394         }
 395 }
 396 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 397
 398 static int restore_vsx(struct task_struct *tsk)
 399 {
 400         if (cpu_has_feature(CPU_FTR_VSX)) {
 401                 tsk->thread.used_vsr = 1;
 402                 return 1;
 403         }
 404
 405         return 0;
 406 }
 407 #else
 408 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 409 static inline void save_vsx(struct task_struct *tsk) { }
 410 #endif /* CONFIG_VSX */
 411
 412 #ifdef CONFIG_SPE
 413 void giveup_spe(struct task_struct *tsk)
 414 {
 415         check_if_tm_restore_required(tsk);
 416
 417         msr_check_and_set(MSR_SPE);
 418         __giveup_spe(tsk);
 419         msr_check_and_clear(MSR_SPE);
 420 }
 421 EXPORT_SYMBOL(giveup_spe);
 422
 423 void enable_kernel_spe(void)
 424 {
 425         WARN_ON(preemptible());
 426
 427         msr_check_and_set(MSR_SPE);
 428
 429         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 430                 check_if_tm_restore_required(current);
 431                 __giveup_spe(current);
 432         }
 433 }
 434 EXPORT_SYMBOL(enable_kernel_spe);
 435
 436 void flush_spe_to_thread(struct task_struct *tsk)
 437 {
 438         if (tsk->thread.regs) {
 439                 preempt_disable();
 440                 if (tsk->thread.regs->msr & MSR_SPE) {
 441                         BUG_ON(tsk != current);
 442                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 443                         giveup_spe(tsk);
 444                 }
 445                 preempt_enable();
 446         }
 447 }
 448 #endif /* CONFIG_SPE */
 449
 450 static unsigned long msr_all_available;
 451
 452 static int __init init_msr_all_available(void)
 453 {
 454 #ifdef CONFIG_PPC_FPU
 455         msr_all_available |= MSR_FP;
 456 #endif
 457 #ifdef CONFIG_ALTIVEC
 458         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 459                 msr_all_available |= MSR_VEC;
 460 #endif
 461 #ifdef CONFIG_VSX
 462         if (cpu_has_feature(CPU_FTR_VSX))
 463                 msr_all_available |= MSR_VSX;
 464 #endif
 465 #ifdef CONFIG_SPE
 466         if (cpu_has_feature(CPU_FTR_SPE))
 467                 msr_all_available |= MSR_SPE;
 468 #endif
 469
 470         return 0;
 471 }
 472 early_initcall(init_msr_all_available);
 473
 474 void giveup_all(struct task_struct *tsk)
 475 {
 476         unsigned long usermsr;
 477
 478         if (!tsk->thread.regs)
 479                 return;
 480
 481         usermsr = tsk->thread.regs->msr;
 482
 483         if ((usermsr & msr_all_available) == 0)
 484                 return;
 485
 486         msr_check_and_set(msr_all_available);
 487         check_if_tm_restore_required(tsk);
 488
 489 #ifdef CONFIG_PPC_FPU
 490         if (usermsr & MSR_FP)
 491                 __giveup_fpu(tsk);
 492 #endif
 493 #ifdef CONFIG_ALTIVEC
 494         if (usermsr & MSR_VEC)
 495                 __giveup_altivec(tsk);
 496 #endif
 497 #ifdef CONFIG_VSX
 498         if (usermsr & MSR_VSX)
 499                 __giveup_vsx(tsk);
 500 #endif
 501 #ifdef CONFIG_SPE
 502         if (usermsr & MSR_SPE)
 503                 __giveup_spe(tsk);
 504 #endif
 505
 506         msr_check_and_clear(msr_all_available);
 507 }
 508 EXPORT_SYMBOL(giveup_all);
 509
 510 void restore_math(struct pt_regs *regs)
 511 {
 512         unsigned long msr;
 513
 514         if (!msr_tm_active(regs->msr) &&
 515                 !current->thread.load_fp && !loadvec(current->thread))
 516                 return;
 517
 518         msr = regs->msr;
 519         msr_check_and_set(msr_all_available);
 520
 521         /*
 522          * Only reload if the bit is not set in the user MSR, the bit BEING set
 523          * indicates that the registers are hot
 524          */
 525         if ((!(msr & MSR_FP)) && restore_fp(current))
 526                 msr |= MSR_FP | current->thread.fpexc_mode;
 527
 528         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 529                 msr |= MSR_VEC;
 530
 531         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 532                         restore_vsx(current)) {
 533                 msr |= MSR_VSX;
 534         }
 535
 536         msr_check_and_clear(msr_all_available);
 537
 538         regs->msr = msr;
 539 }
 540
 541 void save_all(struct task_struct *tsk)
 542 {
 543         unsigned long usermsr;
 544
 545         if (!tsk->thread.regs)
 546                 return;
 547
 548         usermsr = tsk->thread.regs->msr;
 549
 550         if ((usermsr & msr_all_available) == 0)
 551                 return;
 552
 553         msr_check_and_set(msr_all_available);
 554
 555         /*
 556          * Saving the way the register space is in hardware, save_vsx boils
 557          * down to a save_fpu() and save_altivec()
 558          */
 559         if (usermsr & MSR_VSX) {
 560                 save_vsx(tsk);
 561         } else {
 562                 if (usermsr & MSR_FP)
 563                         save_fpu(tsk);
 564
 565                 if (usermsr & MSR_VEC)
 566                         save_altivec(tsk);
 567         }
 568
 569         if (usermsr & MSR_SPE)
 570                 __giveup_spe(tsk);
 571
 572         msr_check_and_clear(msr_all_available);
 573 }
 574
 575 void flush_all_to_thread(struct task_struct *tsk)
 576 {
 577         if (tsk->thread.regs) {
 578                 preempt_disable();
 579                 BUG_ON(tsk != current);
 580                 save_all(tsk);
 581
 582 #ifdef CONFIG_SPE
 583                 if (tsk->thread.regs->msr & MSR_SPE)
 584                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 585 #endif
 586
 587                 preempt_enable();
 588         }
 589 }
 590 EXPORT_SYMBOL(flush_all_to_thread);
 591
 592 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 593 void do_send_trap(struct pt_regs *regs, unsigned long address,
 594                   unsigned long error_code, int signal_code, int breakpt)
 595 {
 596         siginfo_t info;
 597
 598         current->thread.trap_nr = signal_code;
 599         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 600                         11, SIGSEGV) == NOTIFY_STOP)
 601                 return;
 602
 603         /* Deliver the signal to userspace */
 604         info.si_signo = SIGTRAP;
 605         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 606         info.si_code = signal_code;
 607         info.si_addr = (void __user *)address;
 608         force_sig_info(SIGTRAP, &info, current);
 609 }
 610 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 611 void do_break (struct pt_regs *regs, unsigned long address,
 612                     unsigned long error_code)
 613 {
 614         siginfo_t info;
 615
 616         current->thread.trap_nr = TRAP_HWBKPT;
 617         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 618                         11, SIGSEGV) == NOTIFY_STOP)
 619                 return;
 620
 621         if (debugger_break_match(regs))
 622                 return;
 623
 624         /* Clear the breakpoint */
 625         hw_breakpoint_disable();
 626
 627         /* Deliver the signal to userspace */
 628         info.si_signo = SIGTRAP;
 629         info.si_errno = 0;
 630         info.si_code = TRAP_HWBKPT;
 631         info.si_addr = (void __user *)address;
 632         force_sig_info(SIGTRAP, &info, current);
 633 }
 634 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 635
 636 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 637
 638 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 639 /*
 640  * Set the debug registers back to their default "safe" values.
 641  */
 642 static void set_debug_reg_defaults(struct thread_struct *thread)
 643 {
 644         thread->debug.iac1 = thread->debug.iac2 = 0;
 645 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 646         thread->debug.iac3 = thread->debug.iac4 = 0;
 647 #endif
 648         thread->debug.dac1 = thread->debug.dac2 = 0;
 649 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 650         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 651 #endif
 652         thread->debug.dbcr0 = 0;
 653 #ifdef CONFIG_BOOKE
 654         /*
 655          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 656          */
 657         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 658                         DBCR1_IAC3US | DBCR1_IAC4US;
 659         /*
 660          * Force Data Address Compare User/Supervisor bits to be User-only
 661          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 662          */
 663         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 664 #else
 665         thread->debug.dbcr1 = 0;
 666 #endif
 667 }
 668
 669 static void prime_debug_regs(struct debug_reg *debug)
 670 {
 671         /*
 672          * We could have inherited MSR_DE from userspace, since
 673          * it doesn't get cleared on exception entry.  Make sure
 674          * MSR_DE is clear before we enable any debug events.
 675          */
 676         mtmsr(mfmsr() & ~MSR_DE);
 677
 678         mtspr(SPRN_IAC1, debug->iac1);
 679         mtspr(SPRN_IAC2, debug->iac2);
 680 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 681         mtspr(SPRN_IAC3, debug->iac3);
 682         mtspr(SPRN_IAC4, debug->iac4);
 683 #endif
 684         mtspr(SPRN_DAC1, debug->dac1);
 685         mtspr(SPRN_DAC2, debug->dac2);
 686 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 687         mtspr(SPRN_DVC1, debug->dvc1);
 688         mtspr(SPRN_DVC2, debug->dvc2);
 689 #endif
 690         mtspr(SPRN_DBCR0, debug->dbcr0);
 691         mtspr(SPRN_DBCR1, debug->dbcr1);
 692 #ifdef CONFIG_BOOKE
 693         mtspr(SPRN_DBCR2, debug->dbcr2);
 694 #endif
 695 }
 696 /*
 697  * Unless neither the old or new thread are making use of the
 698  * debug registers, set the debug registers from the values
 699  * stored in the new thread.
 700  */
 701 void switch_booke_debug_regs(struct debug_reg *new_debug)
 702 {
 703         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 704                 || (new_debug->dbcr0 & DBCR0_IDM))
 705                         prime_debug_regs(new_debug);
 706 }
 707 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 708 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 709 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 710 static void set_debug_reg_defaults(struct thread_struct *thread)
 711 {
 712         thread->hw_brk.address = 0;
 713         thread->hw_brk.type = 0;
 714         set_breakpoint(&thread->hw_brk);
 715 }
 716 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 717 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 718
 719 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 720 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 721 {
 722         mtspr(SPRN_DAC1, dabr);
 723 #ifdef CONFIG_PPC_47x
 724         isync();
 725 #endif
 726         return 0;
 727 }
 728 #elif defined(CONFIG_PPC_BOOK3S)
 729 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 730 {
 731         mtspr(SPRN_DABR, dabr);
 732         if (cpu_has_feature(CPU_FTR_DABRX))
 733                 mtspr(SPRN_DABRX, dabrx);
 734         return 0;
 735 }
 736 #elif defined(CONFIG_PPC_8xx)
 737 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 738 {
 739         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 740         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 741         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 742
 743         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 744                 lctrl1 |= 0xa0000;
 745         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 746                 lctrl1 |= 0xf0000;
 747         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 748                 lctrl2 = 0;
 749
 750         mtspr(SPRN_LCTRL2, 0);
 751         mtspr(SPRN_CMPE, addr);
 752         mtspr(SPRN_CMPF, addr + 4);
 753         mtspr(SPRN_LCTRL1, lctrl1);
 754         mtspr(SPRN_LCTRL2, lctrl2);
 755
 756         return 0;
 757 }
 758 #else
 759 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 760 {
 761         return -EINVAL;
 762 }
 763 #endif
 764
 765 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 766 {
 767         unsigned long dabr, dabrx;
 768
 769         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 770         dabrx = ((brk->type >> 3) & 0x7);
 771
 772         if (ppc_md.set_dabr)
 773                 return ppc_md.set_dabr(dabr, dabrx);
 774
 775         return __set_dabr(dabr, dabrx);
 776 }
 777
 778 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 779 {
 780         unsigned long dawr, dawrx, mrd;
 781
 782         dawr = brk->address;
 783
 784         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 785                                    << (63 - 58); //* read/write bits */
 786         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 787                                    << (63 - 59); //* translate */
 788         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 789                                    >> 3; //* PRIM bits */
 790         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 791            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 792            0b111111=64DW.
 793            brk->len is in bytes.
 794            This aligns up to double word size, shifts and does the bias.
 795         */
 796         mrd = ((brk->len + 7) >> 3) - 1;
 797         dawrx |= (mrd & 0x3f) << (63 - 53);
 798
 799         if (ppc_md.set_dawr)
 800                 return ppc_md.set_dawr(dawr, dawrx);
 801         mtspr(SPRN_DAWR, dawr);
 802         mtspr(SPRN_DAWRX, dawrx);
 803         return 0;
 804 }
 805
 806 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 807 {
 808         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 809
 810         if (cpu_has_feature(CPU_FTR_DAWR))
 811                 set_dawr(brk);
 812         else
 813                 set_dabr(brk);
 814 }
 815
 816 void set_breakpoint(struct arch_hw_breakpoint *brk)
 817 {
 818         preempt_disable();
 819         __set_breakpoint(brk);
 820         preempt_enable();
 821 }
 822
 823 #ifdef CONFIG_PPC64
 824 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 825 #endif
 826
 827 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 828                               struct arch_hw_breakpoint *b)
 829 {
 830         if (a->address != b->address)
 831                 return false;
 832         if (a->type != b->type)
 833                 return false;
 834         if (a->len != b->len)
 835                 return false;
 836         return true;
 837 }
 838
 839 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 840
 841 static inline bool tm_enabled(struct task_struct *tsk)
 842 {
 843         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 844 }
 845
 846 static void tm_reclaim_thread(struct thread_struct *thr,
 847                               struct thread_info *ti, uint8_t cause)
 848 {
 849         /*
 850          * Use the current MSR TM suspended bit to track if we have
 851          * checkpointed state outstanding.
 852          * On signal delivery, we'd normally reclaim the checkpointed
 853          * state to obtain stack pointer (see:get_tm_stackpointer()).
 854          * This will then directly return to userspace without going
 855          * through __switch_to(). However, if the stack frame is bad,
 856          * we need to exit this thread which calls __switch_to() which
 857          * will again attempt to reclaim the already saved tm state.
 858          * Hence we need to check that we've not already reclaimed
 859          * this state.
 860          * We do this using the current MSR, rather tracking it in
 861          * some specific thread_struct bit, as it has the additional
 862          * benefit of checking for a potential TM bad thing exception.
 863          */
 864         if (!MSR_TM_SUSPENDED(mfmsr()))
 865                 return;
 866
 867         /*
 868          * If we are in a transaction and FP is off then we can't have
 869          * used FP inside that transaction. Hence the checkpointed
 870          * state is the same as the live state. We need to copy the
 871          * live state to the checkpointed state so that when the
 872          * transaction is restored, the checkpointed state is correct
 873          * and the aborted transaction sees the correct state. We use
 874          * ckpt_regs.msr here as that's what tm_reclaim will use to
 875          * determine if it's going to write the checkpointed state or
 876          * not. So either this will write the checkpointed registers,
 877          * or reclaim will. Similarly for VMX.
 878          */
 879         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 880                 memcpy(&thr->ckfp_state, &thr->fp_state,
 881                        sizeof(struct thread_fp_state));
 882         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 883                 memcpy(&thr->ckvr_state, &thr->vr_state,
 884                        sizeof(struct thread_vr_state));
 885
 886         giveup_all(container_of(thr, struct task_struct, thread));
 887
 888         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 889 }
 890
 891 void tm_reclaim_current(uint8_t cause)
 892 {
 893         tm_enable();
 894         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 895 }
 896
 897 static inline void tm_reclaim_task(struct task_struct *tsk)
 898 {
 899         /* We have to work out if we're switching from/to a task that's in the
 900          * middle of a transaction.
 901          *
 902          * In switching we need to maintain a 2nd register state as
 903          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 904          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 905          * ckvr_state
 906          *
 907          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 908          */
 909         struct thread_struct *thr = &tsk->thread;
 910
 911         if (!thr->regs)
 912                 return;
 913
 914         if (!MSR_TM_ACTIVE(thr->regs->msr))
 915                 goto out_and_saveregs;
 916
 917         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 918                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 919                  tsk->pid, thr->regs->nip,
 920                  thr->regs->ccr, thr->regs->msr,
 921                  thr->regs->trap);
 922
 923         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 924
 925         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 926                  tsk->pid);
 927
 928 out_and_saveregs:
 929         /* Always save the regs here, even if a transaction's not active.
 930          * This context-switches a thread's TM info SPRs.  We do it here to
 931          * be consistent with the restore path (in recheckpoint) which
 932          * cannot happen later in _switch().
 933          */
 934         tm_save_sprs(thr);
 935 }
 936
 937 extern void __tm_recheckpoint(struct thread_struct *thread,
 938                               unsigned long orig_msr);
 939
 940 void tm_recheckpoint(struct thread_struct *thread,
 941                      unsigned long orig_msr)
 942 {
 943         unsigned long flags;
 944
 945         if (!(thread->regs->msr & MSR_TM))
 946                 return;
 947
 948         /* We really can't be interrupted here as the TEXASR registers can't
 949          * change and later in the trecheckpoint code, we have a userspace R1.
 950          * So let's hard disable over this region.
 951          */
 952         local_irq_save(flags);
 953         hard_irq_disable();
 954
 955         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 956          * before the trecheckpoint and no explosion occurs.
 957          */
 958         tm_restore_sprs(thread);
 959
 960         __tm_recheckpoint(thread, orig_msr);
 961
 962         local_irq_restore(flags);
 963 }
 964
 965 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 966 {
 967         unsigned long msr;
 968
 969         if (!cpu_has_feature(CPU_FTR_TM))
 970                 return;
 971
 972         /* Recheckpoint the registers of the thread we're about to switch to.
 973          *
 974          * If the task was using FP, we non-lazily reload both the original and
 975          * the speculative FP register states.  This is because the kernel
 976          * doesn't see if/when a TM rollback occurs, so if we take an FP
 977          * unavailable later, we are unable to determine which set of FP regs
 978          * need to be restored.
 979          */
 980         if (!tm_enabled(new))
 981                 return;
 982
 983         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 984                 tm_restore_sprs(&new->thread);
 985                 return;
 986         }
 987         msr = new->thread.ckpt_regs.msr;
 988         /* Recheckpoint to restore original checkpointed register state. */
 989         TM_DEBUG("*** tm_recheckpoint of pid %d "
 990                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 991                  new->pid, new->thread.regs->msr, msr);
 992
 993         tm_recheckpoint(&new->thread, msr);
 994
 995         /*
 996          * The checkpointed state has been restored but the live state has
 997          * not, ensure all the math functionality is turned off to trigger
 998          * restore_math() to reload.
 999          */
1000         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1001
1002         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1003                  "(kernel msr 0x%lx)\n",
1004                  new->pid, mfmsr());
1005 }
1006
1007 static inline void __switch_to_tm(struct task_struct *prev,
1008                 struct task_struct *new)
1009 {
1010         if (cpu_has_feature(CPU_FTR_TM)) {
1011                 if (tm_enabled(prev) || tm_enabled(new))
1012                         tm_enable();
1013
1014                 if (tm_enabled(prev)) {
1015                         prev->thread.load_tm++;
1016                         tm_reclaim_task(prev);
1017                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1018                                 prev->thread.regs->msr &= ~MSR_TM;
1019                 }
1020
1021                 tm_recheckpoint_new_task(new);
1022         }
1023 }
1024
1025 /*
1026  * This is called if we are on the way out to userspace and the
1027  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1028  * FP and/or vector state and does so if necessary.
1029  * If userspace is inside a transaction (whether active or
1030  * suspended) and FP/VMX/VSX instructions have ever been enabled
1031  * inside that transaction, then we have to keep them enabled
1032  * and keep the FP/VMX/VSX state loaded while ever the transaction
1033  * continues.  The reason is that if we didn't, and subsequently
1034  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1035  * we don't know whether it's the same transaction, and thus we
1036  * don't know which of the checkpointed state and the transactional
1037  * state to use.
1038  */
1039 void restore_tm_state(struct pt_regs *regs)
1040 {
1041         unsigned long msr_diff;
1042
1043         /*
1044          * This is the only moment we should clear TIF_RESTORE_TM as
1045          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1046          * again, anything else could lead to an incorrect ckpt_msr being
1047          * saved and therefore incorrect signal contexts.
1048          */
1049         clear_thread_flag(TIF_RESTORE_TM);
1050         if (!MSR_TM_ACTIVE(regs->msr))
1051                 return;
1052
1053         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1054         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1055
1056         /* Ensure that restore_math() will restore */
1057         if (msr_diff & MSR_FP)
1058                 current->thread.load_fp = 1;
1059 #ifdef CONFIG_ALTIVEC
1060         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1061                 current->thread.load_vec = 1;
1062 #endif
1063         restore_math(regs);
1064
1065         regs->msr |= msr_diff;
1066 }
1067
1068 #else
1069 #define tm_recheckpoint_new_task(new)
1070 #define __switch_to_tm(prev, new)
1071 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1072
1073 static inline void save_sprs(struct thread_struct *t)
1074 {
1075 #ifdef CONFIG_ALTIVEC
1076         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1077                 t->vrsave = mfspr(SPRN_VRSAVE);
1078 #endif
1079 #ifdef CONFIG_PPC_BOOK3S_64
1080         if (cpu_has_feature(CPU_FTR_DSCR))
1081                 t->dscr = mfspr(SPRN_DSCR);
1082
1083         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1084                 t->bescr = mfspr(SPRN_BESCR);
1085                 t->ebbhr = mfspr(SPRN_EBBHR);
1086                 t->ebbrr = mfspr(SPRN_EBBRR);
1087
1088                 t->fscr = mfspr(SPRN_FSCR);
1089
1090                 /*
1091                  * Note that the TAR is not available for use in the kernel.
1092                  * (To provide this, the TAR should be backed up/restored on
1093                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1094                  * this should be in pt_regs anyway (for debug).)
1095                  */
1096                 t->tar = mfspr(SPRN_TAR);
1097         }
1098 #endif
1099 }
1100
1101 static inline void restore_sprs(struct thread_struct *old_thread,
1102                                 struct thread_struct *new_thread)
1103 {
1104 #ifdef CONFIG_ALTIVEC
1105         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1106             old_thread->vrsave != new_thread->vrsave)
1107                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1108 #endif
1109 #ifdef CONFIG_PPC_BOOK3S_64
1110         if (cpu_has_feature(CPU_FTR_DSCR)) {
1111                 u64 dscr = get_paca()->dscr_default;
1112                 if (new_thread->dscr_inherit)
1113                         dscr = new_thread->dscr;
1114
1115                 if (old_thread->dscr != dscr)
1116                         mtspr(SPRN_DSCR, dscr);
1117         }
1118
1119         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1120                 if (old_thread->bescr != new_thread->bescr)
1121                         mtspr(SPRN_BESCR, new_thread->bescr);
1122                 if (old_thread->ebbhr != new_thread->ebbhr)
1123                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1124                 if (old_thread->ebbrr != new_thread->ebbrr)
1125                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1126
1127                 if (old_thread->fscr != new_thread->fscr)
1128                         mtspr(SPRN_FSCR, new_thread->fscr);
1129
1130                 if (old_thread->tar != new_thread->tar)
1131                         mtspr(SPRN_TAR, new_thread->tar);
1132         }
1133 #endif
1134 }
1135
1136 #ifdef CONFIG_PPC_BOOK3S_64
1137 #define CP_SIZE 128
1138 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1139 #endif
1140
1141 struct task_struct *__switch_to(struct task_struct *prev,
1142         struct task_struct *new)
1143 {
1144         struct thread_struct *new_thread, *old_thread;
1145         struct task_struct *last;
1146 #ifdef CONFIG_PPC_BOOK3S_64
1147         struct ppc64_tlb_batch *batch;
1148 #endif
1149
1150         new_thread = &new->thread;
1151         old_thread = &current->thread;
1152
1153         WARN_ON(!irqs_disabled());
1154
1155 #ifdef CONFIG_PPC64
1156         /*
1157          * Collect processor utilization data per process
1158          */
1159         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1160                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1161                 long unsigned start_tb, current_tb;
1162                 start_tb = old_thread->start_tb;
1163                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1164                 old_thread->accum_tb += (current_tb - start_tb);
1165                 new_thread->start_tb = current_tb;
1166         }
1167 #endif /* CONFIG_PPC64 */
1168
1169 #ifdef CONFIG_PPC_STD_MMU_64
1170         batch = this_cpu_ptr(&ppc64_tlb_batch);
1171         if (batch->active) {
1172                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1173                 if (batch->index)
1174                         __flush_tlb_pending(batch);
1175                 batch->active = 0;
1176         }
1177 #endif /* CONFIG_PPC_STD_MMU_64 */
1178
1179 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1180         switch_booke_debug_regs(&new->thread.debug);
1181 #else
1182 /*
1183  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1184  * schedule DABR
1185  */
1186 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1187         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1188                 __set_breakpoint(&new->thread.hw_brk);
1189 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1190 #endif
1191
1192         /*
1193          * We need to save SPRs before treclaim/trecheckpoint as these will
1194          * change a number of them.
1195          */
1196         save_sprs(&prev->thread);
1197
1198         /* Save FPU, Altivec, VSX and SPE state */
1199         giveup_all(prev);
1200
1201         __switch_to_tm(prev, new);
1202
1203         if (!radix_enabled()) {
1204                 /*
1205                  * We can't take a PMU exception inside _switch() since there
1206                  * is a window where the kernel stack SLB and the kernel stack
1207                  * are out of sync. Hard disable here.
1208                  */
1209                 hard_irq_disable();
1210         }
1211
1212         /*
1213          * Call restore_sprs() before calling _switch(). If we move it after
1214          * _switch() then we miss out on calling it for new tasks. The reason
1215          * for this is we manually create a stack frame for new tasks that
1216          * directly returns through ret_from_fork() or
1217          * ret_from_kernel_thread(). See copy_thread() for details.
1218          */
1219         restore_sprs(old_thread, new_thread);
1220
1221         last = _switch(old_thread, new_thread);
1222
1223 #ifdef CONFIG_PPC_STD_MMU_64
1224         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1225                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1226                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1227                 batch->active = 1;
1228         }
1229
1230         if (current_thread_info()->task->thread.regs) {
1231                 restore_math(current_thread_info()->task->thread.regs);
1232
1233                 /*
1234                  * The copy-paste buffer can only store into foreign real
1235                  * addresses, so unprivileged processes can not see the
1236                  * data or use it in any way unless they have foreign real
1237                  * mappings. We don't have a VAS driver that allocates those
1238                  * yet, so no cpabort is required.
1239                  */
1240                 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
1241                         /*
1242                          * DD1 allows paste into normal system memory, so we
1243                          * do an unpaired copy here to clear the buffer and
1244                          * prevent a covert channel being set up.
1245                          *
1246                          * cpabort is not used because it is quite expensive.
1247                          */
1248                         asm volatile(PPC_COPY(%0, %1)
1249                                         : : "r"(dummy_copy_buffer), "r"(0));
1250                 }
1251         }
1252 #endif /* CONFIG_PPC_STD_MMU_64 */
1253
1254         return last;
1255 }
1256
1257 static int instructions_to_print = 16;
1258
1259 static void show_instructions(struct pt_regs *regs)
1260 {
1261         int i;
1262         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1263                         sizeof(int));
1264
1265         printk("Instruction dump:");
1266
1267         for (i = 0; i < instructions_to_print; i++) {
1268                 int instr;
1269
1270                 if (!(i % 8))
1271                         pr_cont("\n");
1272
1273 #if !defined(CONFIG_BOOKE)
1274                 /* If executing with the IMMU off, adjust pc rather
1275                  * than print XXXXXXXX.
1276                  */
1277                 if (!(regs->msr & MSR_IR))
1278                         pc = (unsigned long)phys_to_virt(pc);
1279 #endif
1280
1281                 if (!__kernel_text_address(pc) ||
1282                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1283                         pr_cont("XXXXXXXX ");
1284                 } else {
1285                         if (regs->nip == pc)
1286                                 pr_cont("<%08x> ", instr);
1287                         else
1288                                 pr_cont("%08x ", instr);
1289                 }
1290
1291                 pc += sizeof(int);
1292         }
1293
1294         pr_cont("\n");
1295 }
1296
1297 struct regbit {
1298         unsigned long bit;
1299         const char *name;
1300 };
1301
1302 static struct regbit msr_bits[] = {
1303 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1304         {MSR_SF,        "SF"},
1305         {MSR_HV,        "HV"},
1306 #endif
1307         {MSR_VEC,       "VEC"},
1308         {MSR_VSX,       "VSX"},
1309 #ifdef CONFIG_BOOKE
1310         {MSR_CE,        "CE"},
1311 #endif
1312         {MSR_EE,        "EE"},
1313         {MSR_PR,        "PR"},
1314         {MSR_FP,        "FP"},
1315         {MSR_ME,        "ME"},
1316 #ifdef CONFIG_BOOKE
1317         {MSR_DE,        "DE"},
1318 #else
1319         {MSR_SE,        "SE"},
1320         {MSR_BE,        "BE"},
1321 #endif
1322         {MSR_IR,        "IR"},
1323         {MSR_DR,        "DR"},
1324         {MSR_PMM,       "PMM"},
1325 #ifndef CONFIG_BOOKE
1326         {MSR_RI,        "RI"},
1327         {MSR_LE,        "LE"},
1328 #endif
1329         {0,             NULL}
1330 };
1331
1332 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1333 {
1334         const char *s = "";
1335
1336         for (; bits->bit; ++bits)
1337                 if (val & bits->bit) {
1338                         pr_cont("%s%s", s, bits->name);
1339                         s = sep;
1340                 }
1341 }
1342
1343 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1344 static struct regbit msr_tm_bits[] = {
1345         {MSR_TS_T,      "T"},
1346         {MSR_TS_S,      "S"},
1347         {MSR_TM,        "E"},
1348         {0,             NULL}
1349 };
1350
1351 static void print_tm_bits(unsigned long val)
1352 {
1353 /*
1354  * This only prints something if at least one of the TM bit is set.
1355  * Inside the TM[], the output means:
1356  *   E: Enabled         (bit 32)
1357  *   S: Suspended       (bit 33)
1358  *   T: Transactional   (bit 34)
1359  */
1360         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1361                 pr_cont(",TM[");
1362                 print_bits(val, msr_tm_bits, "");
1363                 pr_cont("]");
1364         }
1365 }
1366 #else
1367 static void print_tm_bits(unsigned long val) {}
1368 #endif
1369
1370 static void print_msr_bits(unsigned long val)
1371 {
1372         pr_cont("<");
1373         print_bits(val, msr_bits, ",");
1374         print_tm_bits(val);
1375         pr_cont(">");
1376 }
1377
1378 #ifdef CONFIG_PPC64
1379 #define REG             "%016lx"
1380 #define REGS_PER_LINE   4
1381 #define LAST_VOLATILE   13
1382 #else
1383 #define REG             "%08lx"
1384 #define REGS_PER_LINE   8
1385 #define LAST_VOLATILE   12
1386 #endif
1387
1388 void show_regs(struct pt_regs * regs)
1389 {
1390         int i, trap;
1391
1392         show_regs_print_info(KERN_DEFAULT);
1393
1394         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1395                regs->nip, regs->link, regs->ctr);
1396         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1397                regs, regs->trap, print_tainted(), init_utsname()->release);
1398         printk("MSR: "REG" ", regs->msr);
1399         print_msr_bits(regs->msr);
1400         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1401         trap = TRAP(regs);
1402         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1403                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1404         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1405 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1406                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1407 #else
1408                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1409 #endif
1410 #ifdef CONFIG_PPC64
1411         pr_cont("SOFTE: %ld ", regs->softe);
1412 #endif
1413 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1414         if (MSR_TM_ACTIVE(regs->msr))
1415                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1416 #endif
1417
1418         for (i = 0;  i < 32;  i++) {
1419                 if ((i % REGS_PER_LINE) == 0)
1420                         pr_cont("\nGPR%02d: ", i);
1421                 pr_cont(REG " ", regs->gpr[i]);
1422                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1423                         break;
1424         }
1425         pr_cont("\n");
1426 #ifdef CONFIG_KALLSYMS
1427         /*
1428          * Lookup NIP late so we have the best change of getting the
1429          * above info out without failing
1430          */
1431         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1432         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1433 #endif
1434         show_stack(current, (unsigned long *) regs->gpr[1]);
1435         if (!user_mode(regs))
1436                 show_instructions(regs);
1437 }
1438
1439 void flush_thread(void)
1440 {
1441 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1442         flush_ptrace_hw_breakpoint(current);
1443 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1444         set_debug_reg_defaults(&current->thread);
1445 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1446 }
1447
1448 void
1449 release_thread(struct task_struct *t)
1450 {
1451 }
1452
1453 /*
1454  * this gets called so that we can store coprocessor state into memory and
1455  * copy the current task into the new thread.
1456  */
1457 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1458 {
1459         flush_all_to_thread(src);
1460         /*
1461          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1462          * flush but it removes the checkpointed state from the current CPU and
1463          * transitions the CPU out of TM mode.  Hence we need to call
1464          * tm_recheckpoint_new_task() (on the same task) to restore the
1465          * checkpointed state back and the TM mode.
1466          *
1467          * Can't pass dst because it isn't ready. Doesn't matter, passing
1468          * dst is only important for __switch_to()
1469          */
1470         __switch_to_tm(src, src);
1471
1472         *dst = *src;
1473
1474         clear_task_ebb(dst);
1475
1476         return 0;
1477 }
1478
1479 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1480 {
1481 #ifdef CONFIG_PPC_STD_MMU_64
1482         unsigned long sp_vsid;
1483         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1484
1485         if (radix_enabled())
1486                 return;
1487
1488         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1489                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1490                         << SLB_VSID_SHIFT_1T;
1491         else
1492                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1493                         << SLB_VSID_SHIFT;
1494         sp_vsid |= SLB_VSID_KERNEL | llp;
1495         p->thread.ksp_vsid = sp_vsid;
1496 #endif
1497 }
1498
1499 /*
1500  * Copy a thread..
1501  */
1502
1503 /*
1504  * Copy architecture-specific thread state
1505  */
1506 int copy_thread(unsigned long clone_flags, unsigned long usp,
1507                 unsigned long kthread_arg, struct task_struct *p)
1508 {
1509         struct pt_regs *childregs, *kregs;
1510         extern void ret_from_fork(void);
1511         extern void ret_from_kernel_thread(void);
1512         void (*f)(void);
1513         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1514         struct thread_info *ti = task_thread_info(p);
1515
1516         klp_init_thread_info(ti);
1517
1518         /* Copy registers */
1519         sp -= sizeof(struct pt_regs);
1520         childregs = (struct pt_regs *) sp;
1521         if (unlikely(p->flags & PF_KTHREAD)) {
1522                 /* kernel thread */
1523                 memset(childregs, 0, sizeof(struct pt_regs));
1524                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1525                 /* function */
1526                 if (usp)
1527                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1528 #ifdef CONFIG_PPC64
1529                 clear_tsk_thread_flag(p, TIF_32BIT);
1530                 childregs->softe = 1;
1531 #endif
1532                 childregs->gpr[15] = kthread_arg;
1533                 p->thread.regs = NULL;  /* no user register state */
1534                 ti->flags |= _TIF_RESTOREALL;
1535                 f = ret_from_kernel_thread;
1536         } else {
1537                 /* user thread */
1538                 struct pt_regs *regs = current_pt_regs();
1539                 CHECK_FULL_REGS(regs);
1540                 *childregs = *regs;
1541                 if (usp)
1542                         childregs->gpr[1] = usp;
1543                 p->thread.regs = childregs;
1544                 childregs->gpr[3] = 0;  /* Result from fork() */
1545                 if (clone_flags & CLONE_SETTLS) {
1546 #ifdef CONFIG_PPC64
1547                         if (!is_32bit_task())
1548                                 childregs->gpr[13] = childregs->gpr[6];
1549                         else
1550 #endif
1551                                 childregs->gpr[2] = childregs->gpr[6];
1552                 }
1553
1554                 f = ret_from_fork;
1555         }
1556         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1557         sp -= STACK_FRAME_OVERHEAD;
1558
1559         /*
1560          * The way this works is that at some point in the future
1561          * some task will call _switch to switch to the new task.
1562          * That will pop off the stack frame created below and start
1563          * the new task running at ret_from_fork.  The new task will
1564          * do some house keeping and then return from the fork or clone
1565          * system call, using the stack frame created above.
1566          */
1567         ((unsigned long *)sp)[0] = 0;
1568         sp -= sizeof(struct pt_regs);
1569         kregs = (struct pt_regs *) sp;
1570         sp -= STACK_FRAME_OVERHEAD;
1571         p->thread.ksp = sp;
1572 #ifdef CONFIG_PPC32
1573         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1574                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1575 #endif
1576 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1577         p->thread.ptrace_bps[0] = NULL;
1578 #endif
1579
1580         p->thread.fp_save_area = NULL;
1581 #ifdef CONFIG_ALTIVEC
1582         p->thread.vr_save_area = NULL;
1583 #endif
1584
1585         setup_ksp_vsid(p, sp);
1586
1587 #ifdef CONFIG_PPC64
1588         if (cpu_has_feature(CPU_FTR_DSCR)) {
1589                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1590                 p->thread.dscr = mfspr(SPRN_DSCR);
1591         }
1592         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1593                 p->thread.ppr = INIT_PPR;
1594 #endif
1595         kregs->nip = ppc_function_entry(f);
1596         return 0;
1597 }
1598
1599 /*
1600  * Set up a thread for executing a new program
1601  */
1602 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1603 {
1604 #ifdef CONFIG_PPC64
1605         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1606 #endif
1607
1608         /*
1609          * If we exec out of a kernel thread then thread.regs will not be
1610          * set.  Do it now.
1611          */
1612         if (!current->thread.regs) {
1613                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1614                 current->thread.regs = regs - 1;
1615         }
1616
1617 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1618         /*
1619          * Clear any transactional state, we're exec()ing. The cause is
1620          * not important as there will never be a recheckpoint so it's not
1621          * user visible.
1622          */
1623         if (MSR_TM_SUSPENDED(mfmsr()))
1624                 tm_reclaim_current(0);
1625 #endif
1626
1627         memset(regs->gpr, 0, sizeof(regs->gpr));
1628         regs->ctr = 0;
1629         regs->link = 0;
1630         regs->xer = 0;
1631         regs->ccr = 0;
1632         regs->gpr[1] = sp;
1633
1634         /*
1635          * We have just cleared all the nonvolatile GPRs, so make
1636          * FULL_REGS(regs) return true.  This is necessary to allow
1637          * ptrace to examine the thread immediately after exec.
1638          */
1639         regs->trap &= ~1UL;
1640
1641 #ifdef CONFIG_PPC32
1642         regs->mq = 0;
1643         regs->nip = start;
1644         regs->msr = MSR_USER;
1645 #else
1646         if (!is_32bit_task()) {
1647                 unsigned long entry;
1648
1649                 if (is_elf2_task()) {
1650                         /* Look ma, no function descriptors! */
1651                         entry = start;
1652
1653                         /*
1654                          * Ulrich says:
1655                          *   The latest iteration of the ABI requires that when
1656                          *   calling a function (at its global entry point),
1657                          *   the caller must ensure r12 holds the entry point
1658                          *   address (so that the function can quickly
1659                          *   establish addressability).
1660                          */
1661                         regs->gpr[12] = start;
1662                         /* Make sure that's restored on entry to userspace. */
1663                         set_thread_flag(TIF_RESTOREALL);
1664                 } else {
1665                         unsigned long toc;
1666
1667                         /* start is a relocated pointer to the function
1668                          * descriptor for the elf _start routine.  The first
1669                          * entry in the function descriptor is the entry
1670                          * address of _start and the second entry is the TOC
1671                          * value we need to use.
1672                          */
1673                         __get_user(entry, (unsigned long __user *)start);
1674                         __get_user(toc, (unsigned long __user *)start+1);
1675
1676                         /* Check whether the e_entry function descriptor entries
1677                          * need to be relocated before we can use them.
1678                          */
1679                         if (load_addr != 0) {
1680                                 entry += load_addr;
1681                                 toc   += load_addr;
1682                         }
1683                         regs->gpr[2] = toc;
1684                 }
1685                 regs->nip = entry;
1686                 regs->msr = MSR_USER64;
1687         } else {
1688                 regs->nip = start;
1689                 regs->gpr[2] = 0;
1690                 regs->msr = MSR_USER32;
1691         }
1692 #endif
1693 #ifdef CONFIG_VSX
1694         current->thread.used_vsr = 0;
1695 #endif
1696         current->thread.load_fp = 0;
1697         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1698         current->thread.fp_save_area = NULL;
1699 #ifdef CONFIG_ALTIVEC
1700         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1701         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1702         current->thread.vr_save_area = NULL;
1703         current->thread.vrsave = 0;
1704         current->thread.used_vr = 0;
1705         current->thread.load_vec = 0;
1706 #endif /* CONFIG_ALTIVEC */
1707 #ifdef CONFIG_SPE
1708         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1709         current->thread.acc = 0;
1710         current->thread.spefscr = 0;
1711         current->thread.used_spe = 0;
1712 #endif /* CONFIG_SPE */
1713 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1714         current->thread.tm_tfhar = 0;
1715         current->thread.tm_texasr = 0;
1716         current->thread.tm_tfiar = 0;
1717         current->thread.load_tm = 0;
1718 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1719 }
1720 EXPORT_SYMBOL(start_thread);
1721
1722 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1723                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1724
1725 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1726 {
1727         struct pt_regs *regs = tsk->thread.regs;
1728
1729         /* This is a bit hairy.  If we are an SPE enabled  processor
1730          * (have embedded fp) we store the IEEE exception enable flags in
1731          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1732          * mode (asyn, precise, disabled) for 'Classic' FP. */
1733         if (val & PR_FP_EXC_SW_ENABLE) {
1734 #ifdef CONFIG_SPE
1735                 if (cpu_has_feature(CPU_FTR_SPE)) {
1736                         /*
1737                          * When the sticky exception bits are set
1738                          * directly by userspace, it must call prctl
1739                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1740                          * in the existing prctl settings) or
1741                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1742                          * the bits being set).  <fenv.h> functions
1743                          * saving and restoring the whole
1744                          * floating-point environment need to do so
1745                          * anyway to restore the prctl settings from
1746                          * the saved environment.
1747                          */
1748                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1749                         tsk->thread.fpexc_mode = val &
1750                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1751                         return 0;
1752                 } else {
1753                         return -EINVAL;
1754                 }
1755 #else
1756                 return -EINVAL;
1757 #endif
1758         }
1759
1760         /* on a CONFIG_SPE this does not hurt us.  The bits that
1761          * __pack_fe01 use do not overlap with bits used for
1762          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1763          * on CONFIG_SPE implementations are reserved so writing to
1764          * them does not change anything */
1765         if (val > PR_FP_EXC_PRECISE)
1766                 return -EINVAL;
1767         tsk->thread.fpexc_mode = __pack_fe01(val);
1768         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1769                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1770                         | tsk->thread.fpexc_mode;
1771         return 0;
1772 }
1773
1774 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1775 {
1776         unsigned int val;
1777
1778         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1779 #ifdef CONFIG_SPE
1780                 if (cpu_has_feature(CPU_FTR_SPE)) {
1781                         /*
1782                          * When the sticky exception bits are set
1783                          * directly by userspace, it must call prctl
1784                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1785                          * in the existing prctl settings) or
1786                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1787                          * the bits being set).  <fenv.h> functions
1788                          * saving and restoring the whole
1789                          * floating-point environment need to do so
1790                          * anyway to restore the prctl settings from
1791                          * the saved environment.
1792                          */
1793                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1794                         val = tsk->thread.fpexc_mode;
1795                 } else
1796                         return -EINVAL;
1797 #else
1798                 return -EINVAL;
1799 #endif
1800         else
1801                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1802         return put_user(val, (unsigned int __user *) adr);
1803 }
1804
1805 int set_endian(struct task_struct *tsk, unsigned int val)
1806 {
1807         struct pt_regs *regs = tsk->thread.regs;
1808
1809         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1810             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1811                 return -EINVAL;
1812
1813         if (regs == NULL)
1814                 return -EINVAL;
1815
1816         if (val == PR_ENDIAN_BIG)
1817                 regs->msr &= ~MSR_LE;
1818         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1819                 regs->msr |= MSR_LE;
1820         else
1821                 return -EINVAL;
1822
1823         return 0;
1824 }
1825
1826 int get_endian(struct task_struct *tsk, unsigned long adr)
1827 {
1828         struct pt_regs *regs = tsk->thread.regs;
1829         unsigned int val;
1830
1831         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1832             !cpu_has_feature(CPU_FTR_REAL_LE))
1833                 return -EINVAL;
1834
1835         if (regs == NULL)
1836                 return -EINVAL;
1837
1838         if (regs->msr & MSR_LE) {
1839                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1840                         val = PR_ENDIAN_LITTLE;
1841                 else
1842                         val = PR_ENDIAN_PPC_LITTLE;
1843         } else
1844                 val = PR_ENDIAN_BIG;
1845
1846         return put_user(val, (unsigned int __user *)adr);
1847 }
1848
1849 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1850 {
1851         tsk->thread.align_ctl = val;
1852         return 0;
1853 }
1854
1855 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1856 {
1857         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1858 }
1859
1860 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1861                                   unsigned long nbytes)
1862 {
1863         unsigned long stack_page;
1864         unsigned long cpu = task_cpu(p);
1865
1866         /*
1867          * Avoid crashing if the stack has overflowed and corrupted
1868          * task_cpu(p), which is in the thread_info struct.
1869          */
1870         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1871                 stack_page = (unsigned long) hardirq_ctx[cpu];
1872                 if (sp >= stack_page + sizeof(struct thread_struct)
1873                     && sp <= stack_page + THREAD_SIZE - nbytes)
1874                         return 1;
1875
1876                 stack_page = (unsigned long) softirq_ctx[cpu];
1877                 if (sp >= stack_page + sizeof(struct thread_struct)
1878                     && sp <= stack_page + THREAD_SIZE - nbytes)
1879                         return 1;
1880         }
1881         return 0;
1882 }
1883
1884 int validate_sp(unsigned long sp, struct task_struct *p,
1885                        unsigned long nbytes)
1886 {
1887         unsigned long stack_page = (unsigned long)task_stack_page(p);
1888
1889         if (sp >= stack_page + sizeof(struct thread_struct)
1890             && sp <= stack_page + THREAD_SIZE - nbytes)
1891                 return 1;
1892
1893         return valid_irq_stack(sp, p, nbytes);
1894 }
1895
1896 EXPORT_SYMBOL(validate_sp);
1897
1898 unsigned long get_wchan(struct task_struct *p)
1899 {
1900         unsigned long ip, sp;
1901         int count = 0;
1902
1903         if (!p || p == current || p->state == TASK_RUNNING)
1904                 return 0;
1905
1906         sp = p->thread.ksp;
1907         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1908                 return 0;
1909
1910         do {
1911                 sp = *(unsigned long *)sp;
1912                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1913                         return 0;
1914                 if (count > 0) {
1915                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1916                         if (!in_sched_functions(ip))
1917                                 return ip;
1918                 }
1919         } while (count++ < 16);
1920         return 0;
1921 }
1922
1923 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1924
1925 void show_stack(struct task_struct *tsk, unsigned long *stack)
1926 {
1927         unsigned long sp, ip, lr, newsp;
1928         int count = 0;
1929         int firstframe = 1;
1930 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1931         int curr_frame = current->curr_ret_stack;
1932         extern void return_to_handler(void);
1933         unsigned long rth = (unsigned long)return_to_handler;
1934 #endif
1935
1936         sp = (unsigned long) stack;
1937         if (tsk == NULL)
1938                 tsk = current;
1939         if (sp == 0) {
1940                 if (tsk == current)
1941                         sp = current_stack_pointer();
1942                 else
1943                         sp = tsk->thread.ksp;
1944         }
1945
1946         lr = 0;
1947         printk("Call Trace:\n");
1948         do {
1949                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1950                         return;
1951
1952                 stack = (unsigned long *) sp;
1953                 newsp = stack[0];
1954                 ip = stack[STACK_FRAME_LR_SAVE];
1955                 if (!firstframe || ip != lr) {
1956                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1957 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1958                         if ((ip == rth) && curr_frame >= 0) {
1959                                 pr_cont(" (%pS)",
1960                                        (void *)current->ret_stack[curr_frame].ret);
1961                                 curr_frame--;
1962                         }
1963 #endif
1964                         if (firstframe)
1965                                 pr_cont(" (unreliable)");
1966                         pr_cont("\n");
1967                 }
1968                 firstframe = 0;
1969
1970                 /*
1971                  * See if this is an exception frame.
1972                  * We look for the "regshere" marker in the current frame.
1973                  */
1974                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1975                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1976                         struct pt_regs *regs = (struct pt_regs *)
1977                                 (sp + STACK_FRAME_OVERHEAD);
1978                         lr = regs->link;
1979                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1980                                regs->trap, (void *)regs->nip, (void *)lr);
1981                         firstframe = 1;
1982                 }
1983
1984                 sp = newsp;
1985         } while (count++ < kstack_depth_to_print);
1986 }
1987
1988 #ifdef CONFIG_PPC64
1989 /* Called with hard IRQs off */
1990 void notrace __ppc64_runlatch_on(void)
1991 {
1992         struct thread_info *ti = current_thread_info();
1993         unsigned long ctrl;
1994
1995         ctrl = mfspr(SPRN_CTRLF);
1996         ctrl |= CTRL_RUNLATCH;
1997         mtspr(SPRN_CTRLT, ctrl);
1998
1999         ti->local_flags |= _TLF_RUNLATCH;
2000 }
2001
2002 /* Called with hard IRQs off */
2003 void notrace __ppc64_runlatch_off(void)
2004 {
2005         struct thread_info *ti = current_thread_info();
2006         unsigned long ctrl;
2007
2008         ti->local_flags &= ~_TLF_RUNLATCH;
2009
2010         ctrl = mfspr(SPRN_CTRLF);
2011         ctrl &= ~CTRL_RUNLATCH;
2012         mtspr(SPRN_CTRLT, ctrl);
2013 }
2014 #endif /* CONFIG_PPC64 */
2015
2016 unsigned long arch_align_stack(unsigned long sp)
2017 {
2018         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2019                 sp -= get_random_int() & ~PAGE_MASK;
2020         return sp & ~0xf;
2021 }
2022
2023 static inline unsigned long brk_rnd(void)
2024 {
2025         unsigned long rnd = 0;
2026
2027         /* 8MB for 32bit, 1GB for 64bit */
2028         if (is_32bit_task())
2029                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2030         else
2031                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2032
2033         return rnd << PAGE_SHIFT;
2034 }
2035
2036 unsigned long arch_randomize_brk(struct mm_struct *mm)
2037 {
2038         unsigned long base = mm->brk;
2039         unsigned long ret;
2040
2041 #ifdef CONFIG_PPC_STD_MMU_64
2042         /*
2043          * If we are using 1TB segments and we are allowed to randomise
2044          * the heap, we can put it above 1TB so it is backed by a 1TB
2045          * segment. Otherwise the heap will be in the bottom 1TB
2046          * which always uses 256MB segments and this may result in a
2047          * performance penalty. We don't need to worry about radix. For
2048          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2049          */
2050         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2051                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2052 #endif
2053
2054         ret = PAGE_ALIGN(base + brk_rnd());
2055
2056         if (ret < mm->brk)
2057                 return mm->brk;
2058
2059         return ret;
2060 }
2061