2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
37 * Call kvmppc_hv_entry in real mode.
38 * Must be called with interrupts hard-disabled.
42 * LR = return address to continue at after eventually re-enabling MMU
44 _GLOBAL(kvmppc_hv_entry_trampoline)
46 std r0, PPC_LR_STKOFF(r1)
49 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
54 mtmsrd r0,1 /* clear RI in MSR */
62 /* Back from guest - restore host state and return to caller */
64 /* Restore host DABR and DABRX */
65 ld r5,HSTATE_DABR(r13)
75 * Reload DEC. HDEC interrupts were disabled when
76 * we reloaded the host's LPCR value.
78 ld r3, HSTATE_DECEXP(r13)
83 /* Reload the host's PMU registers */
84 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
85 lbz r4, LPPACA_PMCINUSE(r3)
87 beq 23f /* skip if not */
88 lwz r3, HSTATE_PMC(r13)
89 lwz r4, HSTATE_PMC + 4(r13)
90 lwz r5, HSTATE_PMC + 8(r13)
91 lwz r6, HSTATE_PMC + 12(r13)
92 lwz r8, HSTATE_PMC + 16(r13)
93 lwz r9, HSTATE_PMC + 20(r13)
95 lwz r10, HSTATE_PMC + 24(r13)
96 lwz r11, HSTATE_PMC + 28(r13)
97 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
108 ld r3, HSTATE_MMCR(r13)
109 ld r4, HSTATE_MMCR + 8(r13)
110 ld r5, HSTATE_MMCR + 16(r13)
118 * For external and machine check interrupts, we need
119 * to call the Linux handler to process the interrupt.
120 * We do that by jumping to absolute address 0x500 for
121 * external interrupts, or the machine_check_fwnmi label
122 * for machine checks (since firmware might have patched
123 * the vector area at 0x200). The [h]rfid at the end of the
124 * handler will return to the book3s_hv_interrupts.S code.
125 * For other interrupts we do the rfid to get back
126 * to the book3s_hv_interrupts.S code here.
128 ld r8, 112+PPC_LR_STKOFF(r1)
130 ld r7, HSTATE_HOST_MSR(r13)
132 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
133 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
136 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
138 /* RFI into the highmem handler, or branch to interrupt handler */
142 mtmsrd r6, 1 /* Clear RI in MSR */
145 beqa 0x500 /* external interrupt (PPC970) */
146 beq cr1, 13f /* machine check */
149 /* On POWER7, we have external interrupts set to use HSRR0/1 */
150 11: mtspr SPRN_HSRR0, r8
154 13: b machine_check_fwnmi
157 * We come in here when wakened from nap mode on a secondary hw thread.
158 * Relocation is off and most register values are lost.
159 * r13 points to the PACA.
161 .globl kvm_start_guest
163 ld r1,PACAEMERGSP(r13)
164 subi r1,r1,STACK_FRAME_OVERHEAD
167 li r0,KVM_HWTHREAD_IN_KVM
168 stb r0,HSTATE_HWTHREAD_STATE(r13)
170 /* NV GPR values from power7_idle() will no longer be valid */
172 stb r0,PACA_NAPSTATELOST(r13)
174 /* were we napping due to cede? */
175 lbz r0,HSTATE_NAPPING(r13)
180 * We weren't napping due to cede, so this must be a secondary
181 * thread being woken up to run a guest, or being woken up due
182 * to a stray IPI. (Or due to some machine check or hypervisor
183 * maintenance interrupt while the core is in KVM.)
186 /* Check the wake reason in SRR1 to see why we got here */
188 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
189 cmpwi r3,4 /* was it an external interrupt? */
191 ld r5,HSTATE_XICS_PHYS(r13)
192 li r7,XICS_XIRR /* if it was an external interrupt, */
193 lwzcix r8,r5,r7 /* get and ack the interrupt */
195 clrldi. r9,r8,40 /* get interrupt source ID. */
196 beq 28f /* none there? */
197 cmpwi r9,XICS_IPI /* was it an IPI? */
201 stbcix r0,r5,r6 /* clear IPI */
202 stwcix r8,r5,r7 /* EOI the interrupt */
203 sync /* order loading of vcpu after that */
205 /* get vcpu pointer, NULL if we have no vcpu to run */
206 ld r4,HSTATE_KVM_VCPU(r13)
208 /* if we have no vcpu to run, go back to sleep */
212 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
214 28: /* SRR1 said external but ICP said nope?? */
216 29: /* External non-IPI interrupt to offline secondary thread? help?? */
217 stw r8,HSTATE_SAVED_XIRR(r13)
220 30: bl kvmppc_hv_entry
222 /* Back from the guest, go back to nap */
223 /* Clear our vcpu pointer so we don't come back in early */
225 std r0, HSTATE_KVM_VCPU(r13)
227 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
228 * the nap_count, because once the increment to nap_count is
229 * visible we could be given another vcpu.
232 /* Clear any pending IPI - we're an offline thread */
233 ld r5, HSTATE_XICS_PHYS(r13)
235 lwzcix r3, r5, r7 /* ack any pending interrupt */
236 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
241 stbcix r0, r5, r6 /* clear the IPI */
242 stwcix r3, r5, r7 /* EOI it */
245 /* increment the nap count and then go to nap mode */
246 ld r4, HSTATE_KVM_VCORE(r13)
247 addi r4, r4, VCORE_NAP_COUNT
254 li r0, KVM_HWTHREAD_IN_NAP
255 stb r0, HSTATE_HWTHREAD_STATE(r13)
258 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
261 std r0, HSTATE_SCRATCH0(r13)
263 ld r0, HSTATE_SCRATCH0(r13)
269 /******************************************************************************
273 *****************************************************************************/
275 .global kvmppc_hv_entry
284 * all other volatile GPRS = free
287 std r0, PPC_LR_STKOFF(r1)
290 /* Set partition DABR */
291 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
298 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
300 /* Load guest PMU registers */
301 /* R4 is live here (vcpu pointer) */
303 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
304 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
306 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
307 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
308 lwz r6, VCPU_PMC + 8(r4)
309 lwz r7, VCPU_PMC + 12(r4)
310 lwz r8, VCPU_PMC + 16(r4)
311 lwz r9, VCPU_PMC + 20(r4)
313 lwz r10, VCPU_PMC + 24(r4)
314 lwz r11, VCPU_PMC + 28(r4)
315 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
325 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
327 ld r5, VCPU_MMCR + 8(r4)
328 ld r6, VCPU_MMCR + 16(r4)
338 /* Load up FP, VMX and VSX registers */
341 ld r14, VCPU_GPR(R14)(r4)
342 ld r15, VCPU_GPR(R15)(r4)
343 ld r16, VCPU_GPR(R16)(r4)
344 ld r17, VCPU_GPR(R17)(r4)
345 ld r18, VCPU_GPR(R18)(r4)
346 ld r19, VCPU_GPR(R19)(r4)
347 ld r20, VCPU_GPR(R20)(r4)
348 ld r21, VCPU_GPR(R21)(r4)
349 ld r22, VCPU_GPR(R22)(r4)
350 ld r23, VCPU_GPR(R23)(r4)
351 ld r24, VCPU_GPR(R24)(r4)
352 ld r25, VCPU_GPR(R25)(r4)
353 ld r26, VCPU_GPR(R26)(r4)
354 ld r27, VCPU_GPR(R27)(r4)
355 ld r28, VCPU_GPR(R28)(r4)
356 ld r29, VCPU_GPR(R29)(r4)
357 ld r30, VCPU_GPR(R30)(r4)
358 ld r31, VCPU_GPR(R31)(r4)
361 /* Switch DSCR to guest value */
364 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
367 * Set the decrementer to the guest decrementer.
369 ld r8,VCPU_DEC_EXPIRES(r4)
375 ld r5, VCPU_SPRG0(r4)
376 ld r6, VCPU_SPRG1(r4)
377 ld r7, VCPU_SPRG2(r4)
378 ld r8, VCPU_SPRG3(r4)
384 /* Save R1 in the PACA */
385 std r1, HSTATE_HOST_R1(r13)
387 /* Load up DAR and DSISR */
389 lwz r6, VCPU_DSISR(r4)
393 li r6, KVM_GUEST_MODE_HOST_HV
394 stb r6, HSTATE_IN_GUEST(r13)
397 /* Restore AMR and UAMOR, set AMOR to all 1s */
404 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
414 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
416 * POWER7 host -> guest partition switch code.
417 * We don't have to lock against concurrent tlbies,
418 * but we do have to coordinate across hardware threads.
420 /* Increment entry count iff exit count is zero. */
421 ld r5,HSTATE_KVM_VCORE(r13)
422 addi r9,r5,VCORE_ENTRY_EXIT
424 cmpwi r3,0x100 /* any threads starting to exit? */
425 bge secondary_too_late /* if so we're too late to the party */
430 /* Primary thread switches to guest partition. */
431 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
437 li r0,LPID_RSVD /* switch to reserved LPID */
440 mtspr SPRN_SDR1,r6 /* switch to partition page table */
444 /* See if we need to flush the TLB */
445 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
446 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
447 srdi r6,r6,6 /* doubleword number */
448 sldi r6,r6,3 /* address offset */
450 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
456 23: ldarx r7,0,r6 /* if set, clear the bit */
460 li r6,128 /* and flush the TLB */
462 li r7,0x800 /* IS field = 0b10 */
469 /* Add timebase offset onto timebase */
470 22: ld r8,VCORE_TB_OFFSET(r5)
473 mftb r6 /* current host timebase */
475 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
476 mftb r7 /* check if lower 24 bits overflowed */
481 addis r8,r8,0x100 /* if so, increment upper 40 bits */
484 /* Load guest PCR value to select appropriate compat mode */
485 37: ld r7, VCORE_PCR(r5)
491 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
494 /* Secondary threads wait for primary to have done partition switch */
495 20: lbz r0,VCORE_IN_GUEST(r5)
499 /* Set LPCR and RMOR. */
500 10: ld r8,VCORE_LPCR(r5)
506 /* Increment yield count if they have a VPA */
510 lwz r5, LPPACA_YIELDCOUNT(r3)
512 stw r5, LPPACA_YIELDCOUNT(r3)
514 stb r6, VCPU_VPA_DIRTY(r4)
516 /* Check if HDEC expires soon */
519 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
523 /* Save purr/spurr */
526 std r5,HSTATE_PURR(r13)
527 std r6,HSTATE_SPURR(r13)
535 * PPC970 host -> guest partition switch code.
536 * We have to lock against concurrent tlbies,
537 * using native_tlbie_lock to lock against host tlbies
538 * and kvm->arch.tlbie_lock to lock against guest tlbies.
539 * We also have to invalidate the TLB since its
540 * entries aren't tagged with the LPID.
542 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
544 /* first take native_tlbie_lock */
547 .tc native_tlbie_lock[TC],native_tlbie_lock
549 ld r3,toc_tlbie_lock@toc(2)
550 #ifdef __BIG_ENDIAN__
551 lwz r8,PACA_LOCK_TOKEN(r13)
553 lwz r8,PACAPACAINDEX(r13)
562 ld r5,HSTATE_KVM_VCORE(r13)
563 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
565 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
569 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
572 stw r0,0(r3) /* drop native_tlbie_lock */
574 /* invalidate the whole TLB */
583 /* Take the guest's tlbie_lock */
584 addi r3,r9,KVM_TLBIE_LOCK
592 mtspr SPRN_SDR1,r6 /* switch to partition page table */
594 /* Set up HID4 with the guest's LPID etc. */
599 /* drop the guest's tlbie_lock */
603 /* Check if HDEC expires soon */
606 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
610 /* Enable HDEC interrupts */
613 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
623 /* Load up guest SLB entries */
624 31: lwz r5,VCPU_SLB_MAX(r4)
629 1: ld r8,VCPU_SLB_E(r6)
632 addi r6,r6,VCPU_SLB_SIZE
636 /* Restore state of CTRL run bit; assume 1 on entry */
652 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
656 /* r11 = vcpu->arch.msr & ~MSR_HV */
657 rldicl r11, r11, 63 - MSR_HV_LG, 1
658 rotldi r11, r11, 1 + MSR_HV_LG
661 /* Check if we can deliver an external or decrementer interrupt now */
662 ld r0,VCPU_PENDING_EXC(r4)
663 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
673 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
675 li r0,BOOK3S_INTERRUPT_EXTERNAL
679 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
685 li r0,BOOK3S_INTERRUPT_DECREMENTER
688 /* Move SRR0 and SRR1 into the respective regs */
689 5: mtspr SPRN_SRR0, r6
695 * R10: value for HSRR0
696 * R11: value for HSRR1
701 stb r0,VCPU_CEDED(r4) /* cancel cede */
705 /* Activate guest mode, so faults get handled by KVM */
706 li r9, KVM_GUEST_MODE_GUEST_HV
707 stb r9, HSTATE_IN_GUEST(r13)
714 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
717 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
724 ld r1, VCPU_GPR(R1)(r4)
725 ld r2, VCPU_GPR(R2)(r4)
726 ld r3, VCPU_GPR(R3)(r4)
727 ld r5, VCPU_GPR(R5)(r4)
728 ld r6, VCPU_GPR(R6)(r4)
729 ld r7, VCPU_GPR(R7)(r4)
730 ld r8, VCPU_GPR(R8)(r4)
731 ld r9, VCPU_GPR(R9)(r4)
732 ld r10, VCPU_GPR(R10)(r4)
733 ld r11, VCPU_GPR(R11)(r4)
734 ld r12, VCPU_GPR(R12)(r4)
735 ld r13, VCPU_GPR(R13)(r4)
739 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
740 ld r0, VCPU_GPR(R0)(r4)
741 ld r4, VCPU_GPR(R4)(r4)
746 /******************************************************************************
750 *****************************************************************************/
753 * We come here from the first-level interrupt handlers.
755 .globl kvmppc_interrupt_hv
759 * R12 = interrupt vector
761 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
762 * guest R13 saved in SPRN_SCRATCH0
764 std r9, HSTATE_SCRATCH2(r13)
766 lbz r9, HSTATE_IN_GUEST(r13)
767 cmpwi r9, KVM_GUEST_MODE_HOST_HV
768 beq kvmppc_bad_host_intr
769 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
770 cmpwi r9, KVM_GUEST_MODE_GUEST
771 ld r9, HSTATE_SCRATCH2(r13)
772 beq kvmppc_interrupt_pr
774 /* We're now back in the host but in guest MMU context */
775 li r9, KVM_GUEST_MODE_HOST_HV
776 stb r9, HSTATE_IN_GUEST(r13)
778 ld r9, HSTATE_KVM_VCPU(r13)
782 std r0, VCPU_GPR(R0)(r9)
783 std r1, VCPU_GPR(R1)(r9)
784 std r2, VCPU_GPR(R2)(r9)
785 std r3, VCPU_GPR(R3)(r9)
786 std r4, VCPU_GPR(R4)(r9)
787 std r5, VCPU_GPR(R5)(r9)
788 std r6, VCPU_GPR(R6)(r9)
789 std r7, VCPU_GPR(R7)(r9)
790 std r8, VCPU_GPR(R8)(r9)
791 ld r0, HSTATE_SCRATCH2(r13)
792 std r0, VCPU_GPR(R9)(r9)
793 std r10, VCPU_GPR(R10)(r9)
794 std r11, VCPU_GPR(R11)(r9)
795 ld r3, HSTATE_SCRATCH0(r13)
796 lwz r4, HSTATE_SCRATCH1(r13)
797 std r3, VCPU_GPR(R12)(r9)
800 ld r3, HSTATE_CFAR(r13)
801 std r3, VCPU_CFAR(r9)
802 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
804 ld r4, HSTATE_PPR(r13)
806 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
808 /* Restore R1/R2 so we can handle faults */
809 ld r1, HSTATE_HOST_R1(r13)
814 std r10, VCPU_SRR0(r9)
815 std r11, VCPU_SRR1(r9)
816 andi. r0, r12, 2 /* need to read HSRR0/1? */
818 mfspr r10, SPRN_HSRR0
819 mfspr r11, SPRN_HSRR1
821 1: std r10, VCPU_PC(r9)
822 std r11, VCPU_MSR(r9)
826 std r3, VCPU_GPR(R13)(r9)
829 stw r12,VCPU_TRAP(r9)
831 /* Save HEIR (HV emulation assist reg) in last_inst
832 if this is an HEI (HV emulation interrupt, e40) */
833 li r3,KVM_INST_FETCH_FAILED
835 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
838 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
839 11: stw r3,VCPU_LAST_INST(r9)
841 /* these are volatile across C function calls */
848 /* If this is a page table miss then see if it's theirs or ours */
849 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
851 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
853 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
855 /* See if this is a leftover HDEC interrupt */
856 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
862 /* See if this is an hcall we can handle in real mode */
863 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
864 beq hcall_try_real_mode
866 /* Only handle external interrupts here on arch 206 and later */
868 b ext_interrupt_to_host
869 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
871 /* External interrupt ? */
872 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
873 bne+ ext_interrupt_to_host
875 /* External interrupt, first check for host_ipi. If this is
876 * set, we know the host wants us out so let's do it now
881 bgt ext_interrupt_to_host
883 /* Allright, looks like an IPI for the guest, we need to set MER */
884 /* Check if any CPU is heading out to the host, if so head out too */
885 ld r5, HSTATE_KVM_VCORE(r13)
886 lwz r0, VCORE_ENTRY_EXIT(r5)
888 bge ext_interrupt_to_host
890 /* See if there is a pending interrupt for the guest */
892 ld r0, VCPU_PENDING_EXC(r9)
893 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
894 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
895 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
898 /* And if the guest EE is set, we can deliver immediately, else
899 * we return to the guest with MER set
901 andi. r0, r11, MSR_EE
905 li r10, BOOK3S_INTERRUPT_EXTERNAL
906 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
912 ext_interrupt_to_host:
914 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
915 /* Save more register state */
919 stw r7, VCPU_DSISR(r9)
921 /* don't overwrite fault_dar/fault_dsisr if HDSI */
922 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
924 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
925 std r6, VCPU_FAULT_DAR(r9)
926 stw r7, VCPU_FAULT_DSISR(r9)
928 /* See if it is a machine check */
929 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
930 beq machine_check_realmode
933 /* Save guest CTRL register, set runlatch to 1 */
934 6: mfspr r6,SPRN_CTRLF
941 /* Read the guest SLB and save it away */
942 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
948 andis. r0,r8,SLB_ESID_V@h
950 add r8,r8,r6 /* put index in */
952 std r8,VCPU_SLB_E(r7)
953 std r3,VCPU_SLB_V(r7)
954 addi r7,r7,VCPU_SLB_SIZE
958 stw r5,VCPU_SLB_MAX(r9)
961 * Save the guest PURR/SPURR
969 std r6,VCPU_SPURR(r9)
974 * Restore host PURR/SPURR and add guest times
975 * so that the time in the guest gets accounted.
977 ld r3,HSTATE_PURR(r13)
978 ld r4,HSTATE_SPURR(r13)
983 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
991 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
994 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
996 * POWER7 guest -> host partition switch code.
997 * We don't have to lock against tlbies but we do
998 * have to coordinate the hardware threads.
1000 /* Increment the threads-exiting-guest count in the 0xff00
1001 bits of vcore->entry_exit_count */
1002 ld r5,HSTATE_KVM_VCORE(r13)
1003 addi r6,r5,VCORE_ENTRY_EXIT
1008 isync /* order stwcx. vs. reading napping_threads */
1011 * At this point we have an interrupt that we have to pass
1012 * up to the kernel or qemu; we can't handle it in real mode.
1013 * Thus we have to do a partition switch, so we have to
1014 * collect the other threads, if we are the first thread
1015 * to take an interrupt. To do this, we set the HDEC to 0,
1016 * which causes an HDEC interrupt in all threads within 2ns
1017 * because the HDEC register is shared between all 4 threads.
1018 * However, we don't need to bother if this is an HDEC
1019 * interrupt, since the other threads will already be on their
1020 * way here in that case.
1022 cmpwi r3,0x100 /* Are we the first here? */
1024 cmpwi r3,1 /* Are any other threads in the guest? */
1026 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1032 * Send an IPI to any napping threads, since an HDEC interrupt
1033 * doesn't wake CPUs up from nap.
1035 lwz r3,VCORE_NAPPING_THREADS(r5)
1036 lwz r4,VCPU_PTID(r9)
1039 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1041 /* Order entry/exit update vs. IPIs */
1043 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1047 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1050 stbcix r0,r7,r8 /* trigger the IPI */
1052 addi r6,r6,PACA_SIZE
1055 /* Secondary threads wait for primary to do partition switch */
1056 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1057 ld r5,HSTATE_KVM_VCORE(r13)
1058 lwz r3,VCPU_PTID(r9)
1062 13: lbz r3,VCORE_IN_GUEST(r5)
1068 /* Primary thread waits for all the secondaries to exit guest */
1069 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1076 /* Primary thread switches back to host partition */
1077 ld r6,KVM_HOST_SDR1(r4)
1078 lwz r7,KVM_HOST_LPID(r4)
1079 li r8,LPID_RSVD /* switch to reserved LPID */
1082 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1086 /* Subtract timebase offset from timebase */
1087 ld r8,VCORE_TB_OFFSET(r5)
1090 mftb r6 /* current host timebase */
1092 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1093 mftb r7 /* check if lower 24 bits overflowed */
1098 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1102 17: ld r0, VCORE_PCR(r5)
1108 /* Signal secondary CPUs to continue */
1109 stb r0,VCORE_IN_GUEST(r5)
1110 lis r8,0x7fff /* MAX_INT@h */
1113 16: ld r8,KVM_HOST_LPCR(r4)
1119 * PPC970 guest -> host partition switch code.
1120 * We have to lock against concurrent tlbies, and
1121 * we have to flush the whole TLB.
1123 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1125 /* Take the guest's tlbie_lock */
1126 #ifdef __BIG_ENDIAN__
1127 lwz r8,PACA_LOCK_TOKEN(r13)
1129 lwz r8,PACAPACAINDEX(r13)
1131 addi r3,r4,KVM_TLBIE_LOCK
1139 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1141 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1145 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1148 stw r0,0(r3) /* drop guest tlbie_lock */
1150 /* invalidate the whole TLB */
1159 /* take native_tlbie_lock */
1160 ld r3,toc_tlbie_lock@toc(2)
1168 ld r6,KVM_HOST_SDR1(r4)
1169 mtspr SPRN_SDR1,r6 /* switch to host page table */
1171 /* Set up host HID4 value */
1176 stw r0,0(r3) /* drop native_tlbie_lock */
1178 lis r8,0x7fff /* MAX_INT@h */
1181 /* Disable HDEC interrupts */
1184 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1194 /* load host SLB entries */
1195 33: ld r8,PACA_SLBSHADOWPTR(r13)
1197 .rept SLB_NUM_BOLTED
1198 ld r5,SLBSHADOW_SAVEAREA(r8)
1199 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1200 andis. r7,r5,SLB_ESID_V@h
1211 std r5,VCPU_DEC_EXPIRES(r9)
1213 /* Save and reset AMR and UAMOR before turning on the MMU */
1218 std r6,VCPU_UAMOR(r9)
1221 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1223 /* Unset guest mode */
1224 li r0, KVM_GUEST_MODE_NONE
1225 stb r0, HSTATE_IN_GUEST(r13)
1227 /* Switch DSCR back to host value */
1230 ld r7, HSTATE_DSCR(r13)
1231 std r8, VCPU_DSCR(r9)
1233 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1235 /* Save non-volatile GPRs */
1236 std r14, VCPU_GPR(R14)(r9)
1237 std r15, VCPU_GPR(R15)(r9)
1238 std r16, VCPU_GPR(R16)(r9)
1239 std r17, VCPU_GPR(R17)(r9)
1240 std r18, VCPU_GPR(R18)(r9)
1241 std r19, VCPU_GPR(R19)(r9)
1242 std r20, VCPU_GPR(R20)(r9)
1243 std r21, VCPU_GPR(R21)(r9)
1244 std r22, VCPU_GPR(R22)(r9)
1245 std r23, VCPU_GPR(R23)(r9)
1246 std r24, VCPU_GPR(R24)(r9)
1247 std r25, VCPU_GPR(R25)(r9)
1248 std r26, VCPU_GPR(R26)(r9)
1249 std r27, VCPU_GPR(R27)(r9)
1250 std r28, VCPU_GPR(R28)(r9)
1251 std r29, VCPU_GPR(R29)(r9)
1252 std r30, VCPU_GPR(R30)(r9)
1253 std r31, VCPU_GPR(R31)(r9)
1256 mfspr r3, SPRN_SPRG0
1257 mfspr r4, SPRN_SPRG1
1258 mfspr r5, SPRN_SPRG2
1259 mfspr r6, SPRN_SPRG3
1260 std r3, VCPU_SPRG0(r9)
1261 std r4, VCPU_SPRG1(r9)
1262 std r5, VCPU_SPRG2(r9)
1263 std r6, VCPU_SPRG3(r9)
1269 /* Increment yield count if they have a VPA */
1270 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1273 lwz r3, LPPACA_YIELDCOUNT(r8)
1275 stw r3, LPPACA_YIELDCOUNT(r8)
1277 stb r3, VCPU_VPA_DIRTY(r9)
1279 /* Save PMU registers if requested */
1280 /* r8 and cr0.eq are live here */
1282 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1283 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1284 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1285 mfspr r6, SPRN_MMCRA
1287 /* On P7, clear MMCRA in order to disable SDAR updates */
1289 mtspr SPRN_MMCRA, r7
1290 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1292 beq 21f /* if no VPA, save PMU stuff anyway */
1293 lbz r7, LPPACA_PMCINUSE(r8)
1294 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1296 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1298 21: mfspr r5, SPRN_MMCR1
1301 std r4, VCPU_MMCR(r9)
1302 std r5, VCPU_MMCR + 8(r9)
1303 std r6, VCPU_MMCR + 16(r9)
1304 std r7, VCPU_SIAR(r9)
1305 std r8, VCPU_SDAR(r9)
1313 mfspr r10, SPRN_PMC7
1314 mfspr r11, SPRN_PMC8
1315 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1316 stw r3, VCPU_PMC(r9)
1317 stw r4, VCPU_PMC + 4(r9)
1318 stw r5, VCPU_PMC + 8(r9)
1319 stw r6, VCPU_PMC + 12(r9)
1320 stw r7, VCPU_PMC + 16(r9)
1321 stw r8, VCPU_PMC + 20(r9)
1323 stw r10, VCPU_PMC + 24(r9)
1324 stw r11, VCPU_PMC + 28(r9)
1325 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1327 ld r0, 112+PPC_LR_STKOFF(r1)
1332 ld r5,HSTATE_KVM_VCORE(r13)
1334 13: lbz r3,VCORE_IN_GUEST(r5)
1338 li r0, KVM_GUEST_MODE_NONE
1339 stb r0, HSTATE_IN_GUEST(r13)
1340 ld r11,PACA_SLBSHADOWPTR(r13)
1342 .rept SLB_NUM_BOLTED
1343 ld r5,SLBSHADOW_SAVEAREA(r11)
1344 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1345 andis. r7,r5,SLB_ESID_V@h
1353 * Check whether an HDSI is an HPTE not found fault or something else.
1354 * If it is an HPTE not found fault that is due to the guest accessing
1355 * a page that they have mapped but which we have paged out, then
1356 * we continue on with the guest exit path. In all other cases,
1357 * reflect the HDSI to the guest as a DSI.
1361 mfspr r6, SPRN_HDSISR
1362 /* HPTE not found fault or protection fault? */
1363 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1364 beq 1f /* if not, send it to the guest */
1365 andi. r0, r11, MSR_DR /* data relocation enabled? */
1368 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1369 bne 1f /* if no SLB entry found */
1370 4: std r4, VCPU_FAULT_DAR(r9)
1371 stw r6, VCPU_FAULT_DSISR(r9)
1373 /* Search the hash table. */
1374 mr r3, r9 /* vcpu pointer */
1375 li r7, 1 /* data fault */
1376 bl .kvmppc_hpte_hv_fault
1377 ld r9, HSTATE_KVM_VCPU(r13)
1379 ld r11, VCPU_MSR(r9)
1380 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1381 cmpdi r3, 0 /* retry the instruction */
1383 cmpdi r3, -1 /* handle in kernel mode */
1385 cmpdi r3, -2 /* MMIO emulation; need instr word */
1388 /* Synthesize a DSI for the guest */
1389 ld r4, VCPU_FAULT_DAR(r9)
1391 1: mtspr SPRN_DAR, r4
1392 mtspr SPRN_DSISR, r6
1393 mtspr SPRN_SRR0, r10
1394 mtspr SPRN_SRR1, r11
1395 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1396 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1398 fast_interrupt_c_return:
1399 6: ld r7, VCPU_CTR(r9)
1400 lwz r8, VCPU_XER(r9)
1406 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1407 ld r5, KVM_VRMA_SLB_V(r5)
1410 /* If this is for emulated MMIO, load the instruction word */
1411 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1413 /* Set guest mode to 'jump over instruction' so if lwz faults
1414 * we'll just continue at the next IP. */
1415 li r0, KVM_GUEST_MODE_SKIP
1416 stb r0, HSTATE_IN_GUEST(r13)
1418 /* Do the access with MSR:DR enabled */
1420 ori r4, r3, MSR_DR /* Enable paging for data */
1425 /* Store the result */
1426 stw r8, VCPU_LAST_INST(r9)
1428 /* Unset guest mode. */
1429 li r0, KVM_GUEST_MODE_HOST_HV
1430 stb r0, HSTATE_IN_GUEST(r13)
1434 * Similarly for an HISI, reflect it to the guest as an ISI unless
1435 * it is an HPTE not found fault for a page that we have paged out.
1438 andis. r0, r11, SRR1_ISI_NOPT@h
1440 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1443 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1444 bne 1f /* if no SLB entry found */
1446 /* Search the hash table. */
1447 mr r3, r9 /* vcpu pointer */
1450 li r7, 0 /* instruction fault */
1451 bl .kvmppc_hpte_hv_fault
1452 ld r9, HSTATE_KVM_VCPU(r13)
1454 ld r11, VCPU_MSR(r9)
1455 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1456 cmpdi r3, 0 /* retry the instruction */
1457 beq fast_interrupt_c_return
1458 cmpdi r3, -1 /* handle in kernel mode */
1461 /* Synthesize an ISI for the guest */
1463 1: mtspr SPRN_SRR0, r10
1464 mtspr SPRN_SRR1, r11
1465 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1466 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1468 b fast_interrupt_c_return
1470 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1471 ld r5, KVM_VRMA_SLB_V(r6)
1475 * Try to handle an hcall in real mode.
1476 * Returns to the guest if we handle it, or continues on up to
1477 * the kernel if we can't (i.e. if we don't have a handler for
1478 * it, or if the handler returns H_TOO_HARD).
1480 .globl hcall_try_real_mode
1481 hcall_try_real_mode:
1482 ld r3,VCPU_GPR(R3)(r9)
1484 /* sc 1 from userspace - reflect to guest syscall */
1485 bne sc_1_fast_return
1487 cmpldi r3,hcall_real_table_end - hcall_real_table
1489 LOAD_REG_ADDR(r4, hcall_real_table)
1495 mr r3,r9 /* get vcpu pointer */
1496 ld r4,VCPU_GPR(R4)(r9)
1499 beq hcall_real_fallback
1500 ld r4,HSTATE_KVM_VCPU(r13)
1501 std r3,VCPU_GPR(R3)(r4)
1509 li r10, BOOK3S_INTERRUPT_SYSCALL
1510 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1515 /* We've attempted a real mode hcall, but it's punted it back
1516 * to userspace. We need to restore some clobbered volatiles
1517 * before resuming the pass-it-to-qemu path */
1518 hcall_real_fallback:
1519 li r12,BOOK3S_INTERRUPT_SYSCALL
1520 ld r9, HSTATE_KVM_VCPU(r13)
1524 .globl hcall_real_table
1526 .long 0 /* 0 - unused */
1527 .long .kvmppc_h_remove - hcall_real_table
1528 .long .kvmppc_h_enter - hcall_real_table
1529 .long .kvmppc_h_read - hcall_real_table
1530 .long 0 /* 0x10 - H_CLEAR_MOD */
1531 .long 0 /* 0x14 - H_CLEAR_REF */
1532 .long .kvmppc_h_protect - hcall_real_table
1533 .long 0 /* 0x1c - H_GET_TCE */
1534 .long .kvmppc_h_put_tce - hcall_real_table
1535 .long 0 /* 0x24 - H_SET_SPRG0 */
1536 .long .kvmppc_h_set_dabr - hcall_real_table
1551 #ifdef CONFIG_KVM_XICS
1552 .long .kvmppc_rm_h_eoi - hcall_real_table
1553 .long .kvmppc_rm_h_cppr - hcall_real_table
1554 .long .kvmppc_rm_h_ipi - hcall_real_table
1555 .long 0 /* 0x70 - H_IPOLL */
1556 .long .kvmppc_rm_h_xirr - hcall_real_table
1558 .long 0 /* 0x64 - H_EOI */
1559 .long 0 /* 0x68 - H_CPPR */
1560 .long 0 /* 0x6c - H_IPI */
1561 .long 0 /* 0x70 - H_IPOLL */
1562 .long 0 /* 0x74 - H_XIRR */
1590 .long .kvmppc_h_cede - hcall_real_table
1607 .long .kvmppc_h_bulk_remove - hcall_real_table
1608 hcall_real_table_end:
1614 _GLOBAL(kvmppc_h_set_dabr)
1615 std r4,VCPU_DABR(r3)
1616 /* Work around P7 bug where DABR can get corrupted on mtspr */
1617 1: mtspr SPRN_DABR,r4
1625 _GLOBAL(kvmppc_h_cede)
1627 std r11,VCPU_MSR(r3)
1629 stb r0,VCPU_CEDED(r3)
1630 sync /* order setting ceded vs. testing prodded */
1631 lbz r5,VCPU_PRODDED(r3)
1633 bne kvm_cede_prodded
1634 li r0,0 /* set trap to 0 to say hcall is handled */
1635 stw r0,VCPU_TRAP(r3)
1637 std r0,VCPU_GPR(R3)(r3)
1639 b kvm_cede_exit /* just send it up to host on 970 */
1640 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1643 * Set our bit in the bitmask of napping threads unless all the
1644 * other threads are already napping, in which case we send this
1647 ld r5,HSTATE_KVM_VCORE(r13)
1648 lwz r6,VCPU_PTID(r3)
1649 lwz r8,VCORE_ENTRY_EXIT(r5)
1653 addi r6,r5,VCORE_NAPPING_THREADS
1661 /* order napping_threads update vs testing entry_exit_count */
1664 stb r0,HSTATE_NAPPING(r13)
1666 lwz r7,VCORE_ENTRY_EXIT(r5)
1668 bge 33f /* another thread already exiting */
1671 * Although not specifically required by the architecture, POWER7
1672 * preserves the following registers in nap mode, even if an SMT mode
1673 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1674 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1676 /* Save non-volatile GPRs */
1677 std r14, VCPU_GPR(R14)(r3)
1678 std r15, VCPU_GPR(R15)(r3)
1679 std r16, VCPU_GPR(R16)(r3)
1680 std r17, VCPU_GPR(R17)(r3)
1681 std r18, VCPU_GPR(R18)(r3)
1682 std r19, VCPU_GPR(R19)(r3)
1683 std r20, VCPU_GPR(R20)(r3)
1684 std r21, VCPU_GPR(R21)(r3)
1685 std r22, VCPU_GPR(R22)(r3)
1686 std r23, VCPU_GPR(R23)(r3)
1687 std r24, VCPU_GPR(R24)(r3)
1688 std r25, VCPU_GPR(R25)(r3)
1689 std r26, VCPU_GPR(R26)(r3)
1690 std r27, VCPU_GPR(R27)(r3)
1691 std r28, VCPU_GPR(R28)(r3)
1692 std r29, VCPU_GPR(R29)(r3)
1693 std r30, VCPU_GPR(R30)(r3)
1694 std r31, VCPU_GPR(R31)(r3)
1700 * Take a nap until a decrementer or external interrupt occurs,
1701 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1704 stb r0,HSTATE_HWTHREAD_REQ(r13)
1706 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1710 std r0, HSTATE_SCRATCH0(r13)
1712 ld r0, HSTATE_SCRATCH0(r13)
1719 /* get vcpu pointer */
1720 ld r4, HSTATE_KVM_VCPU(r13)
1722 /* Woken by external or decrementer interrupt */
1723 ld r1, HSTATE_HOST_R1(r13)
1725 /* load up FP state */
1729 ld r14, VCPU_GPR(R14)(r4)
1730 ld r15, VCPU_GPR(R15)(r4)
1731 ld r16, VCPU_GPR(R16)(r4)
1732 ld r17, VCPU_GPR(R17)(r4)
1733 ld r18, VCPU_GPR(R18)(r4)
1734 ld r19, VCPU_GPR(R19)(r4)
1735 ld r20, VCPU_GPR(R20)(r4)
1736 ld r21, VCPU_GPR(R21)(r4)
1737 ld r22, VCPU_GPR(R22)(r4)
1738 ld r23, VCPU_GPR(R23)(r4)
1739 ld r24, VCPU_GPR(R24)(r4)
1740 ld r25, VCPU_GPR(R25)(r4)
1741 ld r26, VCPU_GPR(R26)(r4)
1742 ld r27, VCPU_GPR(R27)(r4)
1743 ld r28, VCPU_GPR(R28)(r4)
1744 ld r29, VCPU_GPR(R29)(r4)
1745 ld r30, VCPU_GPR(R30)(r4)
1746 ld r31, VCPU_GPR(R31)(r4)
1748 /* clear our bit in vcore->napping_threads */
1749 33: ld r5,HSTATE_KVM_VCORE(r13)
1750 lwz r3,VCPU_PTID(r4)
1753 addi r6,r5,VCORE_NAPPING_THREADS
1759 stb r0,HSTATE_NAPPING(r13)
1761 /* Check the wake reason in SRR1 to see why we got here */
1763 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1764 cmpwi r3, 4 /* was it an external interrupt? */
1765 li r12, BOOK3S_INTERRUPT_EXTERNAL
1768 ld r11, VCPU_MSR(r9)
1769 beq do_ext_interrupt /* if so */
1771 /* see if any other thread is already exiting */
1772 lwz r0,VCORE_ENTRY_EXIT(r5)
1774 blt kvmppc_cede_reentry /* if not go back to guest */
1776 /* some threads are exiting, so go to the guest exit path */
1777 b hcall_real_fallback
1779 /* cede when already previously prodded case */
1782 stb r0,VCPU_PRODDED(r3)
1783 sync /* order testing prodded vs. clearing ceded */
1784 stb r0,VCPU_CEDED(r3)
1788 /* we've ceded but we want to give control to the host */
1790 b hcall_real_fallback
1792 /* Try to handle a machine check in real mode */
1793 machine_check_realmode:
1794 mr r3, r9 /* get vcpu pointer */
1795 bl .kvmppc_realmode_machine_check
1797 cmpdi r3, 0 /* continue exiting from guest? */
1798 ld r9, HSTATE_KVM_VCPU(r13)
1799 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1801 /* If not, deliver a machine check. SRR0/1 are already set */
1802 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1803 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1805 b fast_interrupt_c_return
1808 * Determine what sort of external interrupt is pending (if any).
1810 * 0 if no interrupt is pending
1811 * 1 if an interrupt is pending that needs to be handled by the host
1812 * -1 if there was a guest wakeup IPI (which has now been cleared)
1815 /* see if a host IPI is pending */
1817 lbz r0, HSTATE_HOST_IPI(r13)
1821 /* Now read the interrupt from the ICP */
1822 ld r6, HSTATE_XICS_PHYS(r13)
1827 rlwinm. r3, r0, 0, 0xffffff
1829 beq 1f /* if nothing pending in the ICP */
1831 /* We found something in the ICP...
1833 * If it's not an IPI, stash it in the PACA and return to
1834 * the host, we don't (yet) handle directing real external
1835 * interrupts directly to the guest
1837 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1841 /* It's an IPI, clear the MFRR and EOI it */
1844 stbcix r3, r6, r8 /* clear the IPI */
1845 stwcix r0, r6, r7 /* EOI it */
1848 /* We need to re-check host IPI now in case it got set in the
1849 * meantime. If it's clear, we bounce the interrupt to the
1852 lbz r0, HSTATE_HOST_IPI(r13)
1856 /* OK, it's an IPI for us */
1860 42: /* It's not an IPI and it's for the host, stash it in the PACA
1861 * before exit, it will be picked up by the host ICP driver
1863 stw r0, HSTATE_SAVED_XIRR(r13)
1866 43: /* We raced with the host, we need to resend that IPI, bummer */
1868 stbcix r0, r6, r8 /* set the IPI */
1873 * Save away FP, VMX and VSX registers.
1876 _GLOBAL(kvmppc_save_fp)
1879 #ifdef CONFIG_ALTIVEC
1881 oris r8,r8,MSR_VEC@h
1882 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1886 oris r8,r8,MSR_VSX@h
1887 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1895 li r6,reg*16+VCPU_VSRS
1903 stfd reg,reg*8+VCPU_FPRS(r3)
1907 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1910 stfd fr0,VCPU_FPSCR(r3)
1912 #ifdef CONFIG_ALTIVEC
1916 li r6,reg*16+VCPU_VRS
1923 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1925 mfspr r6,SPRN_VRSAVE
1926 stw r6,VCPU_VRSAVE(r3)
1932 * Load up FP, VMX and VSX registers
1935 .globl kvmppc_load_fp
1939 #ifdef CONFIG_ALTIVEC
1941 oris r8,r8,MSR_VEC@h
1942 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1946 oris r8,r8,MSR_VSX@h
1947 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1951 lfd fr0,VCPU_FPSCR(r4)
1957 li r7,reg*16+VCPU_VSRS
1965 lfd reg,reg*8+VCPU_FPRS(r4)
1969 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1972 #ifdef CONFIG_ALTIVEC
1979 li r7,reg*16+VCPU_VRS
1983 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1985 lwz r7,VCPU_VRSAVE(r4)
1986 mtspr SPRN_VRSAVE,r7
1990 * We come here if we get any exception or interrupt while we are
1991 * executing host real mode code while in guest MMU context.
1992 * For now just spin, but we should do something better.
1994 kvmppc_bad_host_intr: