arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/kernel.h>
  21 #include <linux/msi.h>
  22 #include <linux/notifier.h>
  23 #include <linux/pci.h>
  24 #include <linux/string.h>
  25
  26 #include <asm/eeh.h>
  27 #include <asm/eeh_event.h>
  28 #include <asm/io.h>
  29 #include <asm/iommu.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/opal.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/tce.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 static char *hub_diag = NULL;
  40 static int ioda_eeh_nb_init = 0;
  41
  42 static int ioda_eeh_event(struct notifier_block *nb,
  43                           unsigned long events, void *change)
  44 {
  45         uint64_t changed_evts = (uint64_t)change;
  46
  47         /* We simply send special EEH event */
  48         if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
  49             (events & OPAL_EVENT_PCI_ERROR))
  50                 eeh_send_failure_event(NULL);
  51
  52         return 0;
  53 }
  54
  55 static struct notifier_block ioda_eeh_nb = {
  56         .notifier_call  = ioda_eeh_event,
  57         .next           = NULL,
  58         .priority       = 0
  59 };
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 static int ioda_eeh_dbgfs_set(void *data, u64 val)
  63 {
  64         struct pci_controller *hose = data;
  65         struct pnv_phb *phb = hose->private_data;
  66
  67         out_be64(phb->regs + 0xD10, val);
  68         return 0;
  69 }
  70
  71 static int ioda_eeh_dbgfs_get(void *data, u64 *val)
  72 {
  73         struct pci_controller *hose = data;
  74         struct pnv_phb *phb = hose->private_data;
  75
  76         *val = in_be64(phb->regs + 0xD10);
  77         return 0;
  78 }
  79
  80 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_dbgfs_ops, ioda_eeh_dbgfs_get,
  81                         ioda_eeh_dbgfs_set, "0x%llx\n");
  82 #endif /* CONFIG_DEBUG_FS */
  83
  84 /**
  85  * ioda_eeh_post_init - Chip dependent post initialization
  86  * @hose: PCI controller
  87  *
  88  * The function will be called after eeh PEs and devices
  89  * have been built. That means the EEH is ready to supply
  90  * service with I/O cache.
  91  */
  92 static int ioda_eeh_post_init(struct pci_controller *hose)
  93 {
  94         struct pnv_phb *phb = hose->private_data;
  95         int ret;
  96
  97         /* Register OPAL event notifier */
  98         if (!ioda_eeh_nb_init) {
  99                 ret = opal_notifier_register(&ioda_eeh_nb);
 100                 if (ret) {
 101                         pr_err("%s: Can't register OPAL event notifier (%d)\n",
 102                                __func__, ret);
 103                         return ret;
 104                 }
 105
 106                 ioda_eeh_nb_init = 1;
 107         }
 108
 109         /* FIXME: Enable it for PHB3 later */
 110         if (phb->type == PNV_PHB_IODA1) {
 111                 if (!hub_diag) {
 112                         hub_diag = (char *)__get_free_page(GFP_KERNEL |
 113                                                            __GFP_ZERO);
 114                         if (!hub_diag) {
 115                                 pr_err("%s: Out of memory !\n",
 116                                        __func__);
 117                                 return -ENOMEM;
 118                         }
 119                 }
 120
 121 #ifdef CONFIG_DEBUG_FS
 122                 if (phb->dbgfs)
 123                         debugfs_create_file("err_injct", 0600,
 124                                             phb->dbgfs, hose,
 125                                             &ioda_eeh_dbgfs_ops);
 126 #endif
 127
 128                 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
 129         }
 130
 131         return 0;
 132 }
 133
 134 /**
 135  * ioda_eeh_set_option - Set EEH operation or I/O setting
 136  * @pe: EEH PE
 137  * @option: options
 138  *
 139  * Enable or disable EEH option for the indicated PE. The
 140  * function also can be used to enable I/O or DMA for the
 141  * PE.
 142  */
 143 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
 144 {
 145         s64 ret;
 146         u32 pe_no;
 147         struct pci_controller *hose = pe->phb;
 148         struct pnv_phb *phb = hose->private_data;
 149
 150         /* Check on PE number */
 151         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 152                 pr_err("%s: PE address %x out of range [0, %x] "
 153                        "on PHB#%x\n",
 154                         __func__, pe->addr, phb->ioda.total_pe,
 155                         hose->global_number);
 156                 return -EINVAL;
 157         }
 158
 159         pe_no = pe->addr;
 160         switch (option) {
 161         case EEH_OPT_DISABLE:
 162                 ret = -EEXIST;
 163                 break;
 164         case EEH_OPT_ENABLE:
 165                 ret = 0;
 166                 break;
 167         case EEH_OPT_THAW_MMIO:
 168                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 169                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 170                 if (ret) {
 171                         pr_warning("%s: Failed to enable MMIO for "
 172                                    "PHB#%x-PE#%x, err=%lld\n",
 173                                 __func__, hose->global_number, pe_no, ret);
 174                         return -EIO;
 175                 }
 176
 177                 break;
 178         case EEH_OPT_THAW_DMA:
 179                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 180                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 181                 if (ret) {
 182                         pr_warning("%s: Failed to enable DMA for "
 183                                    "PHB#%x-PE#%x, err=%lld\n",
 184                                 __func__, hose->global_number, pe_no, ret);
 185                         return -EIO;
 186                 }
 187
 188                 break;
 189         default:
 190                 pr_warning("%s: Invalid option %d\n", __func__, option);
 191                 return -EINVAL;
 192         }
 193
 194         return ret;
 195 }
 196
 197 /**
 198  * ioda_eeh_get_state - Retrieve the state of PE
 199  * @pe: EEH PE
 200  *
 201  * The PE's state should be retrieved from the PEEV, PEST
 202  * IODA tables. Since the OPAL has exported the function
 203  * to do it, it'd better to use that.
 204  */
 205 static int ioda_eeh_get_state(struct eeh_pe *pe)
 206 {
 207         s64 ret = 0;
 208         u8 fstate;
 209         u16 pcierr;
 210         u32 pe_no;
 211         int result;
 212         struct pci_controller *hose = pe->phb;
 213         struct pnv_phb *phb = hose->private_data;
 214
 215         /*
 216          * Sanity check on PE address. The PHB PE address should
 217          * be zero.
 218          */
 219         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 220                 pr_err("%s: PE address %x out of range [0, %x] "
 221                        "on PHB#%x\n",
 222                        __func__, pe->addr, phb->ioda.total_pe,
 223                        hose->global_number);
 224                 return EEH_STATE_NOT_SUPPORT;
 225         }
 226
 227         /* Retrieve PE status through OPAL */
 228         pe_no = pe->addr;
 229         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 230                         &fstate, &pcierr, NULL);
 231         if (ret) {
 232                 pr_err("%s: Failed to get EEH status on "
 233                        "PHB#%x-PE#%x\n, err=%lld\n",
 234                        __func__, hose->global_number, pe_no, ret);
 235                 return EEH_STATE_NOT_SUPPORT;
 236         }
 237
 238         /* Check PHB status */
 239         if (pe->type & EEH_PE_PHB) {
 240                 result = 0;
 241                 result &= ~EEH_STATE_RESET_ACTIVE;
 242
 243                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 244                         result |= EEH_STATE_MMIO_ACTIVE;
 245                         result |= EEH_STATE_DMA_ACTIVE;
 246                         result |= EEH_STATE_MMIO_ENABLED;
 247                         result |= EEH_STATE_DMA_ENABLED;
 248                 }
 249
 250                 return result;
 251         }
 252
 253         /* Parse result out */
 254         result = 0;
 255         switch (fstate) {
 256         case OPAL_EEH_STOPPED_NOT_FROZEN:
 257                 result &= ~EEH_STATE_RESET_ACTIVE;
 258                 result |= EEH_STATE_MMIO_ACTIVE;
 259                 result |= EEH_STATE_DMA_ACTIVE;
 260                 result |= EEH_STATE_MMIO_ENABLED;
 261                 result |= EEH_STATE_DMA_ENABLED;
 262                 break;
 263         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 264                 result &= ~EEH_STATE_RESET_ACTIVE;
 265                 result |= EEH_STATE_DMA_ACTIVE;
 266                 result |= EEH_STATE_DMA_ENABLED;
 267                 break;
 268         case OPAL_EEH_STOPPED_DMA_FREEZE:
 269                 result &= ~EEH_STATE_RESET_ACTIVE;
 270                 result |= EEH_STATE_MMIO_ACTIVE;
 271                 result |= EEH_STATE_MMIO_ENABLED;
 272                 break;
 273         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 274                 result &= ~EEH_STATE_RESET_ACTIVE;
 275                 break;
 276         case OPAL_EEH_STOPPED_RESET:
 277                 result |= EEH_STATE_RESET_ACTIVE;
 278                 break;
 279         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 280                 result |= EEH_STATE_UNAVAILABLE;
 281                 break;
 282         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 283                 result |= EEH_STATE_NOT_SUPPORT;
 284                 break;
 285         default:
 286                 pr_warning("%s: Unexpected EEH status 0x%x "
 287                            "on PHB#%x-PE#%x\n",
 288                            __func__, fstate, hose->global_number, pe_no);
 289         }
 290
 291         return result;
 292 }
 293
 294 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
 295 {
 296         struct pci_controller *hose;
 297         struct pnv_phb *phb;
 298         u32 pe_no;
 299         u8 fstate;
 300         u16 pcierr;
 301         s64 ret;
 302
 303         pe_no = pe->addr;
 304         hose = pe->phb;
 305         phb = pe->phb->private_data;
 306
 307         /* Clear the EEH error on the PE */
 308         ret = opal_pci_eeh_freeze_clear(phb->opal_id,
 309                         pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 310         if (ret) {
 311                 pr_err("%s: Failed to clear EEH error for "
 312                        "PHB#%x-PE#%x, err=%lld\n",
 313                        __func__, hose->global_number, pe_no, ret);
 314                 return -EIO;
 315         }
 316
 317         /*
 318          * Read the PE state back and verify that the frozen
 319          * state has been removed.
 320          */
 321         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 322                         &fstate, &pcierr, NULL);
 323         if (ret) {
 324                 pr_err("%s: Failed to get EEH status on "
 325                        "PHB#%x-PE#%x\n, err=%lld\n",
 326                        __func__, hose->global_number, pe_no, ret);
 327                 return -EIO;
 328         }
 329
 330         if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
 331                 pr_err("%s: Frozen state not cleared on "
 332                        "PHB#%x-PE#%x, sts=%x\n",
 333                        __func__, hose->global_number, pe_no, fstate);
 334                 return -EIO;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 341 {
 342         s64 rc = OPAL_HARDWARE;
 343
 344         while (1) {
 345                 rc = opal_pci_poll(phb->opal_id);
 346                 if (rc <= 0)
 347                         break;
 348
 349                 msleep(rc);
 350         }
 351
 352         return rc;
 353 }
 354
 355 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 356 {
 357         struct pnv_phb *phb = hose->private_data;
 358         s64 rc = OPAL_HARDWARE;
 359
 360         pr_debug("%s: Reset PHB#%x, option=%d\n",
 361                  __func__, hose->global_number, option);
 362
 363         /* Issue PHB complete reset request */
 364         if (option == EEH_RESET_FUNDAMENTAL ||
 365             option == EEH_RESET_HOT)
 366                 rc = opal_pci_reset(phb->opal_id,
 367                                 OPAL_PHB_COMPLETE,
 368                                 OPAL_ASSERT_RESET);
 369         else if (option == EEH_RESET_DEACTIVATE)
 370                 rc = opal_pci_reset(phb->opal_id,
 371                                 OPAL_PHB_COMPLETE,
 372                                 OPAL_DEASSERT_RESET);
 373         if (rc < 0)
 374                 goto out;
 375
 376         /*
 377          * Poll state of the PHB until the request is done
 378          * successfully.
 379          */
 380         rc = ioda_eeh_phb_poll(phb);
 381 out:
 382         if (rc != OPAL_SUCCESS)
 383                 return -EIO;
 384
 385         return 0;
 386 }
 387
 388 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 389 {
 390         struct pnv_phb *phb = hose->private_data;
 391         s64 rc = OPAL_SUCCESS;
 392
 393         pr_debug("%s: Reset PHB#%x, option=%d\n",
 394                  __func__, hose->global_number, option);
 395
 396         /*
 397          * During the reset deassert time, we needn't care
 398          * the reset scope because the firmware does nothing
 399          * for fundamental or hot reset during deassert phase.
 400          */
 401         if (option == EEH_RESET_FUNDAMENTAL)
 402                 rc = opal_pci_reset(phb->opal_id,
 403                                 OPAL_PCI_FUNDAMENTAL_RESET,
 404                                 OPAL_ASSERT_RESET);
 405         else if (option == EEH_RESET_HOT)
 406                 rc = opal_pci_reset(phb->opal_id,
 407                                 OPAL_PCI_HOT_RESET,
 408                                 OPAL_ASSERT_RESET);
 409         else if (option == EEH_RESET_DEACTIVATE)
 410                 rc = opal_pci_reset(phb->opal_id,
 411                                 OPAL_PCI_HOT_RESET,
 412                                 OPAL_DEASSERT_RESET);
 413         if (rc < 0)
 414                 goto out;
 415
 416         /* Poll state of the PHB until the request is done */
 417         rc = ioda_eeh_phb_poll(phb);
 418 out:
 419         if (rc != OPAL_SUCCESS)
 420                 return -EIO;
 421
 422         return 0;
 423 }
 424
 425 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 426                 struct pci_dev *dev, int option)
 427 {
 428         u16 ctrl;
 429
 430         pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
 431                  __func__, hose->global_number, dev->bus->number,
 432                  PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
 433
 434         switch (option) {
 435         case EEH_RESET_FUNDAMENTAL:
 436         case EEH_RESET_HOT:
 437                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 438                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 439                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 440                 break;
 441         case EEH_RESET_DEACTIVATE:
 442                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 443                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 444                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 445                 break;
 446         }
 447
 448         return 0;
 449 }
 450
 451 /**
 452  * ioda_eeh_reset - Reset the indicated PE
 453  * @pe: EEH PE
 454  * @option: reset option
 455  *
 456  * Do reset on the indicated PE. For PCI bus sensitive PE,
 457  * we need to reset the parent p2p bridge. The PHB has to
 458  * be reinitialized if the p2p bridge is root bridge. For
 459  * PCI device sensitive PE, we will try to reset the device
 460  * through FLR. For now, we don't have OPAL APIs to do HARD
 461  * reset yet, so all reset would be SOFT (HOT) reset.
 462  */
 463 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 464 {
 465         struct pci_controller *hose = pe->phb;
 466         struct eeh_dev *edev;
 467         struct pci_dev *dev;
 468         int ret;
 469
 470         /*
 471          * Anyway, we have to clear the problematic state for the
 472          * corresponding PE. However, we needn't do it if the PE
 473          * is PHB associated. That means the PHB is having fatal
 474          * errors and it needs reset. Further more, the AIB interface
 475          * isn't reliable any more.
 476          */
 477         if (!(pe->type & EEH_PE_PHB) &&
 478             (option == EEH_RESET_HOT ||
 479             option == EEH_RESET_FUNDAMENTAL)) {
 480                 ret = ioda_eeh_pe_clear(pe);
 481                 if (ret)
 482                         return -EIO;
 483         }
 484
 485         /*
 486          * The rules applied to reset, either fundamental or hot reset:
 487          *
 488          * We always reset the direct upstream bridge of the PE. If the
 489          * direct upstream bridge isn't root bridge, we always take hot
 490          * reset no matter what option (fundamental or hot) is. Otherwise,
 491          * we should do the reset according to the required option.
 492          */
 493         if (pe->type & EEH_PE_PHB) {
 494                 ret = ioda_eeh_phb_reset(hose, option);
 495         } else {
 496                 if (pe->type & EEH_PE_DEVICE) {
 497                         /*
 498                          * If it's device PE, we didn't refer to the parent
 499                          * PCI bus yet. So we have to figure it out indirectly.
 500                          */
 501                         edev = list_first_entry(&pe->edevs,
 502                                         struct eeh_dev, list);
 503                         dev = eeh_dev_to_pci_dev(edev);
 504                         dev = dev->bus->self;
 505                 } else {
 506                         /*
 507                          * If it's bus PE, the parent PCI bus is already there
 508                          * and just pick it up.
 509                          */
 510                         dev = pe->bus->self;
 511                 }
 512
 513                 /*
 514                  * Do reset based on the fact that the direct upstream bridge
 515                  * is root bridge (port) or not.
 516                  */
 517                 if (dev->bus->number == 0)
 518                         ret = ioda_eeh_root_reset(hose, option);
 519                 else
 520                         ret = ioda_eeh_bridge_reset(hose, dev, option);
 521         }
 522
 523         return ret;
 524 }
 525
 526 /**
 527  * ioda_eeh_get_log - Retrieve error log
 528  * @pe: EEH PE
 529  * @severity: Severity level of the log
 530  * @drv_log: buffer to store the log
 531  * @len: space of the log buffer
 532  *
 533  * The function is used to retrieve error log from P7IOC.
 534  */
 535 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
 536                             char *drv_log, unsigned long len)
 537 {
 538         s64 ret;
 539         unsigned long flags;
 540         struct pci_controller *hose = pe->phb;
 541         struct pnv_phb *phb = hose->private_data;
 542
 543         spin_lock_irqsave(&phb->lock, flags);
 544
 545         ret = opal_pci_get_phb_diag_data2(phb->opal_id,
 546                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 547         if (ret) {
 548                 spin_unlock_irqrestore(&phb->lock, flags);
 549                 pr_warning("%s: Failed to get log for PHB#%x-PE#%x\n",
 550                            __func__, hose->global_number, pe->addr);
 551                 return -EIO;
 552         }
 553
 554         /*
 555          * FIXME: We probably need log the error in somewhere.
 556          * Lets make it up in future.
 557          */
 558         /* pr_info("%s", phb->diag.blob); */
 559
 560         spin_unlock_irqrestore(&phb->lock, flags);
 561
 562         return 0;
 563 }
 564
 565 /**
 566  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 567  * @pe: EEH PE
 568  *
 569  * For particular PE, it might have included PCI bridges. In order
 570  * to make the PE work properly, those PCI bridges should be configured
 571  * correctly. However, we need do nothing on P7IOC since the reset
 572  * function will do everything that should be covered by the function.
 573  */
 574 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 575 {
 576         return 0;
 577 }
 578
 579 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 580 {
 581         /* GEM */
 582         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 583         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 584         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 585         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 586         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 587
 588         /* LEM */
 589         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 590         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 591         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 592         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 593         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 594 }
 595
 596 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 597 {
 598         struct pnv_phb *phb = hose->private_data;
 599         struct OpalIoP7IOCErrorData *data;
 600         long rc;
 601
 602         data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
 603         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
 604         if (rc != OPAL_SUCCESS) {
 605                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 606                            __func__, phb->hub_id, rc);
 607                 return;
 608         }
 609
 610         switch (data->type) {
 611         case OPAL_P7IOC_DIAG_TYPE_RGC:
 612                 pr_info("P7IOC diag-data for RGC\n\n");
 613                 ioda_eeh_hub_diag_common(data);
 614                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 615                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 616                 break;
 617         case OPAL_P7IOC_DIAG_TYPE_BI:
 618                 pr_info("P7IOC diag-data for BI %s\n\n",
 619                         data->bi.biDownbound ? "Downbound" : "Upbound");
 620                 ioda_eeh_hub_diag_common(data);
 621                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 622                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 623                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 624                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 625                 break;
 626         case OPAL_P7IOC_DIAG_TYPE_CI:
 627                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 628                         data->ci.ciPort);
 629                 ioda_eeh_hub_diag_common(data);
 630                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 631                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 632                 break;
 633         case OPAL_P7IOC_DIAG_TYPE_MISC:
 634                 pr_info("P7IOC diag-data for MISC\n\n");
 635                 ioda_eeh_hub_diag_common(data);
 636                 break;
 637         case OPAL_P7IOC_DIAG_TYPE_I2C:
 638                 pr_info("P7IOC diag-data for I2C\n\n");
 639                 ioda_eeh_hub_diag_common(data);
 640                 break;
 641         default:
 642                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 643                            __func__, phb->hub_id, data->type);
 644         }
 645 }
 646
 647 static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
 648                                     struct OpalIoPhbErrorCommon *common)
 649 {
 650         struct OpalIoP7IOCPhbErrorData *data;
 651         int i;
 652
 653         data = (struct OpalIoP7IOCPhbErrorData *)common;
 654
 655         pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
 656                 hose->global_number, common->version);
 657
 658         pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
 659
 660         pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
 661         pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
 662         pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
 663
 664         pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
 665         pr_info("  slotStatus:           %08x\n", data->slotStatus);
 666         pr_info("  linkStatus:           %08x\n", data->linkStatus);
 667         pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
 668         pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
 669
 670         pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
 671         pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
 672         pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
 673         pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
 674         pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
 675         pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
 676         pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
 677         pr_info("  sourceId:             %08x\n", data->sourceId);
 678
 679         pr_info("  errorClass:           %016llx\n", data->errorClass);
 680         pr_info("  correlator:           %016llx\n", data->correlator);
 681         pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
 682         pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
 683         pr_info("  lemFir:               %016llx\n", data->lemFir);
 684         pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
 685         pr_info("  lemWOF:               %016llx\n", data->lemWOF);
 686         pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
 687         pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
 688         pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
 689         pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
 690         pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
 691         pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
 692         pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
 693         pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
 694         pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
 695         pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
 696         pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
 697         pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
 698         pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
 699         pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
 700         pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
 701         pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
 702
 703         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 704                 if ((data->pestA[i] >> 63) == 0 &&
 705                     (data->pestB[i] >> 63) == 0)
 706                         continue;
 707
 708                 pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
 709                 pr_info("          PESTB:        %016llx\n", data->pestB[i]);
 710         }
 711 }
 712
 713 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 714 {
 715         struct pnv_phb *phb = hose->private_data;
 716         struct OpalIoPhbErrorCommon *common;
 717         long rc;
 718
 719         common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
 720         rc = opal_pci_get_phb_diag_data2(phb->opal_id, common, PAGE_SIZE);
 721         if (rc != OPAL_SUCCESS) {
 722                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 723                             __func__, hose->global_number, rc);
 724                 return;
 725         }
 726
 727         switch (common->ioType) {
 728         case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
 729                 ioda_eeh_p7ioc_phb_diag(hose, common);
 730                 break;
 731         default:
 732                 pr_warning("%s: Unrecognized I/O chip %d\n",
 733                            __func__, common->ioType);
 734         }
 735 }
 736
 737 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
 738                                struct eeh_pe **pe)
 739 {
 740         struct eeh_pe *phb_pe;
 741
 742         phb_pe = eeh_phb_pe_get(hose);
 743         if (!phb_pe) {
 744                 pr_warning("%s Can't find PE for PHB#%d\n",
 745                            __func__, hose->global_number);
 746                 return -EEXIST;
 747         }
 748
 749         *pe = phb_pe;
 750         return 0;
 751 }
 752
 753 static int ioda_eeh_get_pe(struct pci_controller *hose,
 754                            u16 pe_no, struct eeh_pe **pe)
 755 {
 756         struct eeh_pe *phb_pe, *dev_pe;
 757         struct eeh_dev dev;
 758
 759         /* Find the PHB PE */
 760         if (ioda_eeh_get_phb_pe(hose, &phb_pe))
 761                 return -EEXIST;
 762
 763         /* Find the PE according to PE# */
 764         memset(&dev, 0, sizeof(struct eeh_dev));
 765         dev.phb = hose;
 766         dev.pe_config_addr = pe_no;
 767         dev_pe = eeh_pe_get(&dev);
 768         if (!dev_pe) {
 769                 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
 770                            __func__, hose->global_number, pe_no);
 771                 return -EEXIST;
 772         }
 773
 774         *pe = dev_pe;
 775         return 0;
 776 }
 777
 778 /**
 779  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 780  * @pe: The affected PE
 781  *
 782  * The function is expected to be called by EEH core while it gets
 783  * special EEH event (without binding PE). The function calls to
 784  * OPAL APIs for next error to handle. The informational error is
 785  * handled internally by platform. However, the dead IOC, dead PHB,
 786  * fenced PHB and frozen PE should be handled by EEH core eventually.
 787  */
 788 static int ioda_eeh_next_error(struct eeh_pe **pe)
 789 {
 790         struct pci_controller *hose, *tmp;
 791         struct pnv_phb *phb;
 792         u64 frozen_pe_no;
 793         u16 err_type, severity;
 794         long rc;
 795         int ret = 1;
 796
 797         /*
 798          * While running here, it's safe to purge the event queue.
 799          * And we should keep the cached OPAL notifier event sychronized
 800          * between the kernel and firmware.
 801          */
 802         eeh_remove_event(NULL);
 803         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 804
 805         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 806                 /*
 807                  * If the subordinate PCI buses of the PHB has been
 808                  * removed, we needn't take care of it any more.
 809                  */
 810                 phb = hose->private_data;
 811                 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
 812                         continue;
 813
 814                 rc = opal_pci_next_error(phb->opal_id,
 815                                 &frozen_pe_no, &err_type, &severity);
 816
 817                 /* If OPAL API returns error, we needn't proceed */
 818                 if (rc != OPAL_SUCCESS) {
 819                         pr_devel("%s: Invalid return value on "
 820                                  "PHB#%x (0x%lx) from opal_pci_next_error",
 821                                  __func__, hose->global_number, rc);
 822                         continue;
 823                 }
 824
 825                 /* If the PHB doesn't have error, stop processing */
 826                 if (err_type == OPAL_EEH_NO_ERROR ||
 827                     severity == OPAL_EEH_SEV_NO_ERROR) {
 828                         pr_devel("%s: No error found on PHB#%x\n",
 829                                  __func__, hose->global_number);
 830                         continue;
 831                 }
 832
 833                 /*
 834                  * Processing the error. We're expecting the error with
 835                  * highest priority reported upon multiple errors on the
 836                  * specific PHB.
 837                  */
 838                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
 839                          __func__, err_type, severity,
 840                          frozen_pe_no, hose->global_number);
 841                 switch (err_type) {
 842                 case OPAL_EEH_IOC_ERROR:
 843                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 844                                 list_for_each_entry_safe(hose, tmp,
 845                                                 &hose_list, list_node) {
 846                                         phb = hose->private_data;
 847                                         phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 848                                 }
 849
 850                                 pr_err("EEH: dead IOC detected\n");
 851                                 ret = 4;
 852                                 goto out;
 853                         } else if (severity == OPAL_EEH_SEV_INF) {
 854                                 pr_info("EEH: IOC informative error "
 855                                         "detected\n");
 856                                 ioda_eeh_hub_diag(hose);
 857                         }
 858
 859                         break;
 860                 case OPAL_EEH_PHB_ERROR:
 861                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 862                                 if (ioda_eeh_get_phb_pe(hose, pe))
 863                                         break;
 864
 865                                 pr_err("EEH: dead PHB#%x detected\n",
 866                                         hose->global_number);
 867                                 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 868                                 ret = 3;
 869                                 goto out;
 870                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 871                                 if (ioda_eeh_get_phb_pe(hose, pe))
 872                                         break;
 873
 874                                 pr_err("EEH: fenced PHB#%x detected\n",
 875                                         hose->global_number);
 876                                 ret = 2;
 877                                 goto out;
 878                         } else if (severity == OPAL_EEH_SEV_INF) {
 879                                 pr_info("EEH: PHB#%x informative error "
 880                                         "detected\n",
 881                                         hose->global_number);
 882                                 ioda_eeh_phb_diag(hose);
 883                         }
 884
 885                         break;
 886                 case OPAL_EEH_PE_ERROR:
 887                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
 888                                 break;
 889
 890                         pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
 891                                 (*pe)->addr, (*pe)->phb->global_number);
 892                         ret = 1;
 893                         goto out;
 894                 }
 895         }
 896
 897         ret = 0;
 898 out:
 899         return ret;
 900 }
 901
 902 struct pnv_eeh_ops ioda_eeh_ops = {
 903         .post_init              = ioda_eeh_post_init,
 904         .set_option             = ioda_eeh_set_option,
 905         .get_state              = ioda_eeh_get_state,
 906         .reset                  = ioda_eeh_reset,
 907         .get_log                = ioda_eeh_get_log,
 908         .configure_bridge       = ioda_eeh_configure_bridge,
 909         .next_error             = ioda_eeh_next_error
 910 };