arch/sparc/kernel/setup_64.c

   1 /*
   2  *  linux/arch/sparc64/kernel/setup.c
   3  *
   4  *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/errno.h>
   9 #include <linux/sched.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mm.h>
  12 #include <linux/stddef.h>
  13 #include <linux/unistd.h>
  14 #include <linux/ptrace.h>
  15 #include <asm/smp.h>
  16 #include <linux/user.h>
  17 #include <linux/screen_info.h>
  18 #include <linux/delay.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/syscalls.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/init.h>
  26 #include <linux/inet.h>
  27 #include <linux/console.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/cpu.h>
  31 #include <linux/initrd.h>
  32 #include <linux/module.h>
  33 #include <linux/start_kernel.h>
  34 #include <linux/bootmem.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/processor.h>
  38 #include <asm/oplib.h>
  39 #include <asm/page.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/idprom.h>
  42 #include <asm/head.h>
  43 #include <asm/starfire.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/timer.h>
  46 #include <asm/sections.h>
  47 #include <asm/setup.h>
  48 #include <asm/mmu.h>
  49 #include <asm/ns87303.h>
  50 #include <asm/btext.h>
  51 #include <asm/elf.h>
  52 #include <asm/mdesc.h>
  53 #include <asm/cacheflush.h>
  54 #include <asm/dma.h>
  55 #include <asm/irq.h>
  56
  57 #ifdef CONFIG_IP_PNP
  58 #include <net/ipconfig.h>
  59 #endif
  60
  61 #include "entry.h"
  62 #include "kernel.h"
  63
  64 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  65  * operations in asm/ns87303.h
  66  */
  67 DEFINE_SPINLOCK(ns87303_lock);
  68 EXPORT_SYMBOL(ns87303_lock);
  69
  70 struct screen_info screen_info = {
  71         0, 0,                   /* orig-x, orig-y */
  72         0,                      /* unused */
  73         0,                      /* orig-video-page */
  74         0,                      /* orig-video-mode */
  75         128,                    /* orig-video-cols */
  76         0, 0, 0,                /* unused, ega_bx, unused */
  77         54,                     /* orig-video-lines */
  78         0,                      /* orig-video-isVGA */
  79         16                      /* orig-video-points */
  80 };
  81
  82 static void
  83 prom_console_write(struct console *con, const char *s, unsigned int n)
  84 {
  85         prom_write(s, n);
  86 }
  87
  88 /* Exported for mm/init.c:paging_init. */
  89 unsigned long cmdline_memory_size = 0;
  90
  91 static struct console prom_early_console = {
  92         .name =         "earlyprom",
  93         .write =        prom_console_write,
  94         .flags =        CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
  95         .index =        -1,
  96 };
  97
  98 /*
  99  * Process kernel command line switches that are specific to the
 100  * SPARC or that require special low-level processing.
 101  */
 102 static void __init process_switch(char c)
 103 {
 104         switch (c) {
 105         case 'd':
 106         case 's':
 107                 break;
 108         case 'h':
 109                 prom_printf("boot_flags_init: Halt!\n");
 110                 prom_halt();
 111                 break;
 112         case 'p':
 113                 prom_early_console.flags &= ~CON_BOOT;
 114                 break;
 115         case 'P':
 116                 /* Force UltraSPARC-III P-Cache on. */
 117                 if (tlb_type != cheetah) {
 118                         printk("BOOT: Ignoring P-Cache force option.\n");
 119                         break;
 120                 }
 121                 cheetah_pcache_forced_on = 1;
 122                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
 123                 cheetah_enable_pcache();
 124                 break;
 125
 126         default:
 127                 printk("Unknown boot switch (-%c)\n", c);
 128                 break;
 129         }
 130 }
 131
 132 static void __init boot_flags_init(char *commands)
 133 {
 134         while (*commands) {
 135                 /* Move to the start of the next "argument". */
 136                 while (*commands == ' ')
 137                         commands++;
 138
 139                 /* Process any command switches, otherwise skip it. */
 140                 if (*commands == '\0')
 141                         break;
 142                 if (*commands == '-') {
 143                         commands++;
 144                         while (*commands && *commands != ' ')
 145                                 process_switch(*commands++);
 146                         continue;
 147                 }
 148                 if (!strncmp(commands, "mem=", 4))
 149                         cmdline_memory_size = memparse(commands + 4, &commands);
 150
 151                 while (*commands && *commands != ' ')
 152                         commands++;
 153         }
 154 }
 155
 156 extern unsigned short root_flags;
 157 extern unsigned short root_dev;
 158 extern unsigned short ram_flags;
 159 #define RAMDISK_IMAGE_START_MASK        0x07FF
 160 #define RAMDISK_PROMPT_FLAG             0x8000
 161 #define RAMDISK_LOAD_FLAG               0x4000
 162
 163 extern int root_mountflags;
 164
 165 char reboot_command[COMMAND_LINE_SIZE];
 166
 167 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
 168
 169 static void __init per_cpu_patch(void)
 170 {
 171         struct cpuid_patch_entry *p;
 172         unsigned long ver;
 173         int is_jbus;
 174
 175         if (tlb_type == spitfire && !this_is_starfire)
 176                 return;
 177
 178         is_jbus = 0;
 179         if (tlb_type != hypervisor) {
 180                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 181                 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
 182                            (ver >> 32UL) == __SERRANO_ID);
 183         }
 184
 185         p = &__cpuid_patch;
 186         while (p < &__cpuid_patch_end) {
 187                 unsigned long addr = p->addr;
 188                 unsigned int *insns;
 189
 190                 switch (tlb_type) {
 191                 case spitfire:
 192                         insns = &p->starfire[0];
 193                         break;
 194                 case cheetah:
 195                 case cheetah_plus:
 196                         if (is_jbus)
 197                                 insns = &p->cheetah_jbus[0];
 198                         else
 199                                 insns = &p->cheetah_safari[0];
 200                         break;
 201                 case hypervisor:
 202                         insns = &p->sun4v[0];
 203                         break;
 204                 default:
 205                         prom_printf("Unknown cpu type, halting.\n");
 206                         prom_halt();
 207                 }
 208
 209                 *(unsigned int *) (addr +  0) = insns[0];
 210                 wmb();
 211                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 212
 213                 *(unsigned int *) (addr +  4) = insns[1];
 214                 wmb();
 215                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 216
 217                 *(unsigned int *) (addr +  8) = insns[2];
 218                 wmb();
 219                 __asm__ __volatile__("flush     %0" : : "r" (addr +  8));
 220
 221                 *(unsigned int *) (addr + 12) = insns[3];
 222                 wmb();
 223                 __asm__ __volatile__("flush     %0" : : "r" (addr + 12));
 224
 225                 p++;
 226         }
 227 }
 228
 229 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
 230                              struct sun4v_1insn_patch_entry *end)
 231 {
 232         while (start < end) {
 233                 unsigned long addr = start->addr;
 234
 235                 *(unsigned int *) (addr +  0) = start->insn;
 236                 wmb();
 237                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 238
 239                 start++;
 240         }
 241 }
 242
 243 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
 244                              struct sun4v_2insn_patch_entry *end)
 245 {
 246         while (start < end) {
 247                 unsigned long addr = start->addr;
 248
 249                 *(unsigned int *) (addr +  0) = start->insns[0];
 250                 wmb();
 251                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 252
 253                 *(unsigned int *) (addr +  4) = start->insns[1];
 254                 wmb();
 255                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 256
 257                 start++;
 258         }
 259 }
 260
 261 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
 262                              struct sun4v_2insn_patch_entry *end)
 263 {
 264         while (start < end) {
 265                 unsigned long addr = start->addr;
 266
 267                 *(unsigned int *) (addr +  0) = start->insns[0];
 268                 wmb();
 269                 __asm__ __volatile__("flush     %0" : : "r" (addr +  0));
 270
 271                 *(unsigned int *) (addr +  4) = start->insns[1];
 272                 wmb();
 273                 __asm__ __volatile__("flush     %0" : : "r" (addr +  4));
 274
 275                 start++;
 276         }
 277 }
 278
 279 static void __init sun4v_patch(void)
 280 {
 281         extern void sun4v_hvapi_init(void);
 282
 283         if (tlb_type != hypervisor)
 284                 return;
 285
 286         sun4v_patch_1insn_range(&__sun4v_1insn_patch,
 287                                 &__sun4v_1insn_patch_end);
 288
 289         sun4v_patch_2insn_range(&__sun4v_2insn_patch,
 290                                 &__sun4v_2insn_patch_end);
 291
 292         switch (sun4v_chip_type) {
 293         case SUN4V_CHIP_SPARC_M7:
 294         case SUN4V_CHIP_SPARC_M8:
 295         case SUN4V_CHIP_SPARC_SN:
 296                 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
 297                                          &__sun_m7_2insn_patch_end);
 298                 break;
 299         default:
 300                 break;
 301         }
 302
 303         sun4v_hvapi_init();
 304 }
 305
 306 static void __init popc_patch(void)
 307 {
 308         struct popc_3insn_patch_entry *p3;
 309         struct popc_6insn_patch_entry *p6;
 310
 311         p3 = &__popc_3insn_patch;
 312         while (p3 < &__popc_3insn_patch_end) {
 313                 unsigned long i, addr = p3->addr;
 314
 315                 for (i = 0; i < 3; i++) {
 316                         *(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
 317                         wmb();
 318                         __asm__ __volatile__("flush     %0"
 319                                              : : "r" (addr +  (i * 4)));
 320                 }
 321
 322                 p3++;
 323         }
 324
 325         p6 = &__popc_6insn_patch;
 326         while (p6 < &__popc_6insn_patch_end) {
 327                 unsigned long i, addr = p6->addr;
 328
 329                 for (i = 0; i < 6; i++) {
 330                         *(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
 331                         wmb();
 332                         __asm__ __volatile__("flush     %0"
 333                                              : : "r" (addr +  (i * 4)));
 334                 }
 335
 336                 p6++;
 337         }
 338 }
 339
 340 static void __init pause_patch(void)
 341 {
 342         struct pause_patch_entry *p;
 343
 344         p = &__pause_3insn_patch;
 345         while (p < &__pause_3insn_patch_end) {
 346                 unsigned long i, addr = p->addr;
 347
 348                 for (i = 0; i < 3; i++) {
 349                         *(unsigned int *) (addr +  (i * 4)) = p->insns[i];
 350                         wmb();
 351                         __asm__ __volatile__("flush     %0"
 352                                              : : "r" (addr +  (i * 4)));
 353                 }
 354
 355                 p++;
 356         }
 357 }
 358
 359 void __init start_early_boot(void)
 360 {
 361         int cpu;
 362
 363         check_if_starfire();
 364         per_cpu_patch();
 365         sun4v_patch();
 366
 367         cpu = hard_smp_processor_id();
 368         if (cpu >= NR_CPUS) {
 369                 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
 370                             cpu, NR_CPUS);
 371                 prom_halt();
 372         }
 373         current_thread_info()->cpu = cpu;
 374
 375         time_init_early();
 376         prom_init_report();
 377         start_kernel();
 378 }
 379
 380 /* On Ultra, we support all of the v8 capabilities. */
 381 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
 382                                    HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
 383                                    HWCAP_SPARC_V9);
 384 EXPORT_SYMBOL(sparc64_elf_hwcap);
 385
 386 static const char *hwcaps[] = {
 387         "flush", "stbar", "swap", "muldiv", "v9",
 388         "ultra3", "blkinit", "n2",
 389
 390         /* These strings are as they appear in the machine description
 391          * 'hwcap-list' property for cpu nodes.
 392          */
 393         "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
 394         "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
 395         "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
 396         "adp",
 397 };
 398
 399 static const char *crypto_hwcaps[] = {
 400         "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
 401         "sha512", "mpmul", "montmul", "montsqr", "crc32c",
 402 };
 403
 404 void cpucap_info(struct seq_file *m)
 405 {
 406         unsigned long caps = sparc64_elf_hwcap;
 407         int i, printed = 0;
 408
 409         seq_puts(m, "cpucaps\t\t: ");
 410         for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 411                 unsigned long bit = 1UL << i;
 412                 if (hwcaps[i] && (caps & bit)) {
 413                         seq_printf(m, "%s%s",
 414                                    printed ? "," : "", hwcaps[i]);
 415                         printed++;
 416                 }
 417         }
 418         if (caps & HWCAP_SPARC_CRYPTO) {
 419                 unsigned long cfr;
 420
 421                 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
 422                 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 423                         unsigned long bit = 1UL << i;
 424                         if (cfr & bit) {
 425                                 seq_printf(m, "%s%s",
 426                                            printed ? "," : "", crypto_hwcaps[i]);
 427                                 printed++;
 428                         }
 429                 }
 430         }
 431         seq_putc(m, '\n');
 432 }
 433
 434 static void __init report_one_hwcap(int *printed, const char *name)
 435 {
 436         if ((*printed) == 0)
 437                 printk(KERN_INFO "CPU CAPS: [");
 438         printk(KERN_CONT "%s%s",
 439                (*printed) ? "," : "", name);
 440         if (++(*printed) == 8) {
 441                 printk(KERN_CONT "]\n");
 442                 *printed = 0;
 443         }
 444 }
 445
 446 static void __init report_crypto_hwcaps(int *printed)
 447 {
 448         unsigned long cfr;
 449         int i;
 450
 451         __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
 452
 453         for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 454                 unsigned long bit = 1UL << i;
 455                 if (cfr & bit)
 456                         report_one_hwcap(printed, crypto_hwcaps[i]);
 457         }
 458 }
 459
 460 static void __init report_hwcaps(unsigned long caps)
 461 {
 462         int i, printed = 0;
 463
 464         for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 465                 unsigned long bit = 1UL << i;
 466                 if (hwcaps[i] && (caps & bit))
 467                         report_one_hwcap(&printed, hwcaps[i]);
 468         }
 469         if (caps & HWCAP_SPARC_CRYPTO)
 470                 report_crypto_hwcaps(&printed);
 471         if (printed != 0)
 472                 printk(KERN_CONT "]\n");
 473 }
 474
 475 static unsigned long __init mdesc_cpu_hwcap_list(void)
 476 {
 477         struct mdesc_handle *hp;
 478         unsigned long caps = 0;
 479         const char *prop;
 480         int len;
 481         u64 pn;
 482
 483         hp = mdesc_grab();
 484         if (!hp)
 485                 return 0;
 486
 487         pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
 488         if (pn == MDESC_NODE_NULL)
 489                 goto out;
 490
 491         prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
 492         if (!prop)
 493                 goto out;
 494
 495         while (len) {
 496                 int i, plen;
 497
 498                 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
 499                         unsigned long bit = 1UL << i;
 500
 501                         if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
 502                                 caps |= bit;
 503                                 break;
 504                         }
 505                 }
 506                 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
 507                         if (!strcmp(prop, crypto_hwcaps[i]))
 508                                 caps |= HWCAP_SPARC_CRYPTO;
 509                 }
 510
 511                 plen = strlen(prop) + 1;
 512                 prop += plen;
 513                 len -= plen;
 514         }
 515
 516 out:
 517         mdesc_release(hp);
 518         return caps;
 519 }
 520
 521 /* This yields a mask that user programs can use to figure out what
 522  * instruction set this cpu supports.
 523  */
 524 static void __init init_sparc64_elf_hwcap(void)
 525 {
 526         unsigned long cap = sparc64_elf_hwcap;
 527         unsigned long mdesc_caps;
 528
 529         if (tlb_type == cheetah || tlb_type == cheetah_plus)
 530                 cap |= HWCAP_SPARC_ULTRA3;
 531         else if (tlb_type == hypervisor) {
 532                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
 533                     sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 534                     sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 535                     sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 536                     sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 537                     sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 538                     sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 539                     sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
 540                     sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
 541                     sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 542                         cap |= HWCAP_SPARC_BLKINIT;
 543                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 544                     sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 545                     sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 546                     sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 547                     sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 548                     sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 549                     sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
 550                     sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
 551                     sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 552                         cap |= HWCAP_SPARC_N2;
 553         }
 554
 555         cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
 556
 557         mdesc_caps = mdesc_cpu_hwcap_list();
 558         if (!mdesc_caps) {
 559                 if (tlb_type == spitfire)
 560                         cap |= AV_SPARC_VIS;
 561                 if (tlb_type == cheetah || tlb_type == cheetah_plus)
 562                         cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
 563                 if (tlb_type == cheetah_plus) {
 564                         unsigned long impl, ver;
 565
 566                         __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
 567                         impl = ((ver >> 32) & 0xffff);
 568                         if (impl == PANTHER_IMPL)
 569                                 cap |= AV_SPARC_POPC;
 570                 }
 571                 if (tlb_type == hypervisor) {
 572                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
 573                                 cap |= AV_SPARC_ASI_BLK_INIT;
 574                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
 575                             sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 576                             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 577                             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 578                             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 579                             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 580                             sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
 581                             sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
 582                             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 583                                 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
 584                                         AV_SPARC_ASI_BLK_INIT |
 585                                         AV_SPARC_POPC);
 586                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
 587                             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
 588                             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
 589                             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
 590                             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
 591                             sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
 592                             sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
 593                             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
 594                                 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
 595                                         AV_SPARC_FMAF);
 596                 }
 597         }
 598         sparc64_elf_hwcap = cap | mdesc_caps;
 599
 600         report_hwcaps(sparc64_elf_hwcap);
 601
 602         if (sparc64_elf_hwcap & AV_SPARC_POPC)
 603                 popc_patch();
 604         if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
 605                 pause_patch();
 606 }
 607
 608 void __init alloc_irqstack_bootmem(void)
 609 {
 610         unsigned int i, node;
 611
 612         for_each_possible_cpu(i) {
 613                 node = cpu_to_node(i);
 614
 615                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
 616                                                         THREAD_SIZE,
 617                                                         THREAD_SIZE, 0);
 618                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
 619                                                         THREAD_SIZE,
 620                                                         THREAD_SIZE, 0);
 621         }
 622 }
 623
 624 void __init setup_arch(char **cmdline_p)
 625 {
 626         /* Initialize PROM console and command line. */
 627         *cmdline_p = prom_getbootargs();
 628         strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
 629         parse_early_param();
 630
 631         boot_flags_init(*cmdline_p);
 632 #ifdef CONFIG_EARLYFB
 633         if (btext_find_display())
 634 #endif
 635                 register_console(&prom_early_console);
 636
 637         if (tlb_type == hypervisor)
 638                 printk("ARCH: SUN4V\n");
 639         else
 640                 printk("ARCH: SUN4U\n");
 641
 642 #ifdef CONFIG_DUMMY_CONSOLE
 643         conswitchp = &dummy_con;
 644 #endif
 645
 646         idprom_init();
 647
 648         if (!root_flags)
 649                 root_mountflags &= ~MS_RDONLY;
 650         ROOT_DEV = old_decode_dev(root_dev);
 651 #ifdef CONFIG_BLK_DEV_RAM
 652         rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
 653         rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
 654         rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
 655 #endif
 656
 657         task_thread_info(&init_task)->kregs = &fake_swapper_regs;
 658
 659 #ifdef CONFIG_IP_PNP
 660         if (!ic_set_manually) {
 661                 phandle chosen = prom_finddevice("/chosen");
 662                 u32 cl, sv, gw;
 663
 664                 cl = prom_getintdefault (chosen, "client-ip", 0);
 665                 sv = prom_getintdefault (chosen, "server-ip", 0);
 666                 gw = prom_getintdefault (chosen, "gateway-ip", 0);
 667                 if (cl && sv) {
 668                         ic_myaddr = cl;
 669                         ic_servaddr = sv;
 670                         if (gw)
 671                                 ic_gateway = gw;
 672 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
 673                         ic_proto_enabled = 0;
 674 #endif
 675                 }
 676         }
 677 #endif
 678
 679         /* Get boot processor trap_block[] setup.  */
 680         init_cur_cpu_trap(current_thread_info());
 681
 682         paging_init();
 683         init_sparc64_elf_hwcap();
 684         smp_fill_in_cpu_possible_map();
 685         /*
 686          * Once the OF device tree and MDESC have been setup and nr_cpus has
 687          * been parsed, we know the list of possible cpus.  Therefore we can
 688          * allocate the IRQ stacks.
 689          */
 690         alloc_irqstack_bootmem();
 691 }
 692
 693 extern int stop_a_enabled;
 694
 695 void sun_do_break(void)
 696 {
 697         if (!stop_a_enabled)
 698                 return;
 699
 700         prom_printf("\n");
 701         flush_user_windows();
 702
 703         prom_cmdline();
 704 }
 705 EXPORT_SYMBOL(sun_do_break);
 706
 707 int stop_a_enabled = 1;
 708 EXPORT_SYMBOL(stop_a_enabled);