2 * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
3 * Copyright (C) 2013 Google, Inc., Stephane Eranian
5 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
6 * section 14.7.1 (September 2013)
8 * RAPL provides more controls than just reporting energy consumption
9 * however here we only expose the 3 energy consumption free running
10 * counters (pp0, pkg, dram).
12 * Each of those counters increments in a power unit defined by the
13 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules
16 * Counter to rapl events mappings:
18 * pp0 counter: consumption of all physical cores (power plane 0)
19 * event: rapl_energy_cores
22 * pkg counter: consumption of the whole processor package
23 * event: rapl_energy_pkg
26 * dram counter: consumption of the dram domain (servers only)
27 * event: rapl_energy_dram
30 * gpu counter: consumption of the builtin-gpu domain (client only)
31 * event: rapl_energy_gpu
34 * psys counter: consumption of the builtin-psys domain (client only)
35 * event: rapl_energy_psys
38 * We manage those counters as free running (read-only). They may be
39 * use simultaneously by other tools, such as turbostat.
41 * The events only support system-wide mode counting. There is no
42 * sampling support because it does not make sense and is not
43 * supported by the RAPL hardware.
45 * Because we want to avoid floating-point operations in the kernel,
46 * the events are all reported in fixed point arithmetic (32.32).
47 * Tools must adjust the counts to convert them to Watts using
48 * the duration of the measurement. Tools may use a function such as
49 * ldexp(raw_count, -32);
52 #define pr_fmt(fmt) "RAPL PMU: " fmt
54 #include <linux/module.h>
55 #include <linux/slab.h>
56 #include <linux/perf_event.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
59 #include "../perf_event.h"
61 MODULE_LICENSE("GPL");
64 * RAPL energy status counters
66 #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */
67 #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */
68 #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */
69 #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
70 #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
71 #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
72 #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */
73 #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
74 #define RAPL_IDX_PSYS_NRG_STAT 4 /* psys */
75 #define INTEL_RAPL_PSYS 0x5 /* pseudo-encoding */
77 #define NR_RAPL_DOMAINS 0x5
78 static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = {
86 /* Clients have PP0, PKG */
87 #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
88 1<<RAPL_IDX_PKG_NRG_STAT|\
89 1<<RAPL_IDX_PP1_NRG_STAT)
91 /* Servers have PP0, PKG, RAM */
92 #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
93 1<<RAPL_IDX_PKG_NRG_STAT|\
94 1<<RAPL_IDX_RAM_NRG_STAT)
96 /* Servers have PP0, PKG, RAM, PP1 */
97 #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\
98 1<<RAPL_IDX_PKG_NRG_STAT|\
99 1<<RAPL_IDX_RAM_NRG_STAT|\
100 1<<RAPL_IDX_PP1_NRG_STAT)
102 /* SKL clients have PP0, PKG, RAM, PP1, PSYS */
103 #define RAPL_IDX_SKL_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
104 1<<RAPL_IDX_PKG_NRG_STAT|\
105 1<<RAPL_IDX_RAM_NRG_STAT|\
106 1<<RAPL_IDX_PP1_NRG_STAT|\
107 1<<RAPL_IDX_PSYS_NRG_STAT)
109 /* Knights Landing has PKG, RAM */
110 #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\
111 1<<RAPL_IDX_RAM_NRG_STAT)
114 * event code: LSB 8 bits, passed in attr->config
115 * any other bit is reserved
117 #define RAPL_EVENT_MASK 0xFFULL
119 #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \
120 static ssize_t __rapl_##_var##_show(struct kobject *kobj, \
121 struct kobj_attribute *attr, \
124 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
125 return sprintf(page, _format "\n"); \
127 static struct kobj_attribute format_attr_##_var = \
128 __ATTR(_name, 0444, __rapl_##_var##_show, NULL)
130 #define RAPL_CNTR_WIDTH 32
132 #define RAPL_EVENT_ATTR_STR(_name, v, str) \
133 static struct perf_pmu_events_attr event_attr_##v = { \
134 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \
143 struct list_head active_list;
145 ktime_t timer_interval;
146 struct hrtimer hrtimer;
152 struct rapl_pmu *pmus[];
155 /* 1/2^hw_unit Joule */
156 static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly;
157 static struct rapl_pmus *rapl_pmus;
158 static cpumask_t rapl_cpu_mask;
159 static unsigned int rapl_cntr_mask;
160 static u64 rapl_timer_ms;
162 static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu)
164 return rapl_pmus->pmus[topology_logical_package_id(cpu)];
167 static inline u64 rapl_read_counter(struct perf_event *event)
170 rdmsrl(event->hw.event_base, raw);
174 static inline u64 rapl_scale(u64 v, int cfg)
176 if (cfg > NR_RAPL_DOMAINS) {
177 pr_warn("Invalid domain %d, failed to scale data\n", cfg);
181 * scale delta to smallest unit (1/2^32)
182 * users must then scale back: count * 1/(1e9*2^32) to get Joules
183 * or use ldexp(count, -32).
184 * Watts = Joules/Time delta
186 return v << (32 - rapl_hw_unit[cfg - 1]);
189 static u64 rapl_event_update(struct perf_event *event)
191 struct hw_perf_event *hwc = &event->hw;
192 u64 prev_raw_count, new_raw_count;
194 int shift = RAPL_CNTR_WIDTH;
197 prev_raw_count = local64_read(&hwc->prev_count);
198 rdmsrl(event->hw.event_base, new_raw_count);
200 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
201 new_raw_count) != prev_raw_count) {
207 * Now we have the new raw value and have updated the prev
208 * timestamp already. We can now calculate the elapsed delta
209 * (event-)time and add that to the generic event.
211 * Careful, not all hw sign-extends above the physical width
214 delta = (new_raw_count << shift) - (prev_raw_count << shift);
217 sdelta = rapl_scale(delta, event->hw.config);
219 local64_add(sdelta, &event->count);
221 return new_raw_count;
224 static void rapl_start_hrtimer(struct rapl_pmu *pmu)
226 hrtimer_start(&pmu->hrtimer, pmu->timer_interval,
227 HRTIMER_MODE_REL_PINNED);
230 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
232 struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer);
233 struct perf_event *event;
237 return HRTIMER_NORESTART;
239 raw_spin_lock_irqsave(&pmu->lock, flags);
241 list_for_each_entry(event, &pmu->active_list, active_entry)
242 rapl_event_update(event);
244 raw_spin_unlock_irqrestore(&pmu->lock, flags);
246 hrtimer_forward_now(hrtimer, pmu->timer_interval);
248 return HRTIMER_RESTART;
251 static void rapl_hrtimer_init(struct rapl_pmu *pmu)
253 struct hrtimer *hr = &pmu->hrtimer;
255 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
256 hr->function = rapl_hrtimer_handle;
259 static void __rapl_pmu_event_start(struct rapl_pmu *pmu,
260 struct perf_event *event)
262 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
267 list_add_tail(&event->active_entry, &pmu->active_list);
269 local64_set(&event->hw.prev_count, rapl_read_counter(event));
272 if (pmu->n_active == 1)
273 rapl_start_hrtimer(pmu);
276 static void rapl_pmu_event_start(struct perf_event *event, int mode)
278 struct rapl_pmu *pmu = event->pmu_private;
281 raw_spin_lock_irqsave(&pmu->lock, flags);
282 __rapl_pmu_event_start(pmu, event);
283 raw_spin_unlock_irqrestore(&pmu->lock, flags);
286 static void rapl_pmu_event_stop(struct perf_event *event, int mode)
288 struct rapl_pmu *pmu = event->pmu_private;
289 struct hw_perf_event *hwc = &event->hw;
292 raw_spin_lock_irqsave(&pmu->lock, flags);
294 /* mark event as deactivated and stopped */
295 if (!(hwc->state & PERF_HES_STOPPED)) {
296 WARN_ON_ONCE(pmu->n_active <= 0);
298 if (pmu->n_active == 0)
299 hrtimer_cancel(&pmu->hrtimer);
301 list_del(&event->active_entry);
303 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
304 hwc->state |= PERF_HES_STOPPED;
307 /* check if update of sw counter is necessary */
308 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
310 * Drain the remaining delta count out of a event
311 * that we are disabling:
313 rapl_event_update(event);
314 hwc->state |= PERF_HES_UPTODATE;
317 raw_spin_unlock_irqrestore(&pmu->lock, flags);
320 static int rapl_pmu_event_add(struct perf_event *event, int mode)
322 struct rapl_pmu *pmu = event->pmu_private;
323 struct hw_perf_event *hwc = &event->hw;
326 raw_spin_lock_irqsave(&pmu->lock, flags);
328 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
330 if (mode & PERF_EF_START)
331 __rapl_pmu_event_start(pmu, event);
333 raw_spin_unlock_irqrestore(&pmu->lock, flags);
338 static void rapl_pmu_event_del(struct perf_event *event, int flags)
340 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
343 static int rapl_pmu_event_init(struct perf_event *event)
345 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
346 int bit, msr, ret = 0;
347 struct rapl_pmu *pmu;
349 /* only look at RAPL events */
350 if (event->attr.type != rapl_pmus->pmu.type)
353 /* check only supported bits are set */
354 if (event->attr.config & ~RAPL_EVENT_MASK)
361 * check event is known (determines counter)
365 bit = RAPL_IDX_PP0_NRG_STAT;
366 msr = MSR_PP0_ENERGY_STATUS;
369 bit = RAPL_IDX_PKG_NRG_STAT;
370 msr = MSR_PKG_ENERGY_STATUS;
373 bit = RAPL_IDX_RAM_NRG_STAT;
374 msr = MSR_DRAM_ENERGY_STATUS;
377 bit = RAPL_IDX_PP1_NRG_STAT;
378 msr = MSR_PP1_ENERGY_STATUS;
380 case INTEL_RAPL_PSYS:
381 bit = RAPL_IDX_PSYS_NRG_STAT;
382 msr = MSR_PLATFORM_ENERGY_STATUS;
387 /* check event supported */
388 if (!(rapl_cntr_mask & (1 << bit)))
391 /* unsupported modes and filters */
392 if (event->attr.exclude_user ||
393 event->attr.exclude_kernel ||
394 event->attr.exclude_hv ||
395 event->attr.exclude_idle ||
396 event->attr.exclude_host ||
397 event->attr.exclude_guest ||
398 event->attr.sample_period) /* no sampling */
401 /* must be done before validate_group */
402 pmu = cpu_to_rapl_pmu(event->cpu);
403 event->cpu = pmu->cpu;
404 event->pmu_private = pmu;
405 event->hw.event_base = msr;
406 event->hw.config = cfg;
412 static void rapl_pmu_event_read(struct perf_event *event)
414 rapl_event_update(event);
417 static ssize_t rapl_get_attr_cpumask(struct device *dev,
418 struct device_attribute *attr, char *buf)
420 return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask);
423 static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL);
425 static struct attribute *rapl_pmu_attrs[] = {
426 &dev_attr_cpumask.attr,
430 static struct attribute_group rapl_pmu_attr_group = {
431 .attrs = rapl_pmu_attrs,
434 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
435 RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
436 RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
437 RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
438 RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05");
440 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
441 RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
442 RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
443 RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
444 RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_psys_unit, "Joules");
447 * we compute in 0.23 nJ increments regardless of MSR
449 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
450 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
451 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
452 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
453 RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10");
455 static struct attribute *rapl_events_srv_attr[] = {
456 EVENT_PTR(rapl_cores),
460 EVENT_PTR(rapl_cores_unit),
461 EVENT_PTR(rapl_pkg_unit),
462 EVENT_PTR(rapl_ram_unit),
464 EVENT_PTR(rapl_cores_scale),
465 EVENT_PTR(rapl_pkg_scale),
466 EVENT_PTR(rapl_ram_scale),
470 static struct attribute *rapl_events_cln_attr[] = {
471 EVENT_PTR(rapl_cores),
475 EVENT_PTR(rapl_cores_unit),
476 EVENT_PTR(rapl_pkg_unit),
477 EVENT_PTR(rapl_gpu_unit),
479 EVENT_PTR(rapl_cores_scale),
480 EVENT_PTR(rapl_pkg_scale),
481 EVENT_PTR(rapl_gpu_scale),
485 static struct attribute *rapl_events_hsw_attr[] = {
486 EVENT_PTR(rapl_cores),
491 EVENT_PTR(rapl_cores_unit),
492 EVENT_PTR(rapl_pkg_unit),
493 EVENT_PTR(rapl_gpu_unit),
494 EVENT_PTR(rapl_ram_unit),
496 EVENT_PTR(rapl_cores_scale),
497 EVENT_PTR(rapl_pkg_scale),
498 EVENT_PTR(rapl_gpu_scale),
499 EVENT_PTR(rapl_ram_scale),
503 static struct attribute *rapl_events_skl_attr[] = {
504 EVENT_PTR(rapl_cores),
508 EVENT_PTR(rapl_psys),
510 EVENT_PTR(rapl_cores_unit),
511 EVENT_PTR(rapl_pkg_unit),
512 EVENT_PTR(rapl_gpu_unit),
513 EVENT_PTR(rapl_ram_unit),
514 EVENT_PTR(rapl_psys_unit),
516 EVENT_PTR(rapl_cores_scale),
517 EVENT_PTR(rapl_pkg_scale),
518 EVENT_PTR(rapl_gpu_scale),
519 EVENT_PTR(rapl_ram_scale),
520 EVENT_PTR(rapl_psys_scale),
524 static struct attribute *rapl_events_knl_attr[] = {
528 EVENT_PTR(rapl_pkg_unit),
529 EVENT_PTR(rapl_ram_unit),
531 EVENT_PTR(rapl_pkg_scale),
532 EVENT_PTR(rapl_ram_scale),
536 static struct attribute_group rapl_pmu_events_group = {
538 .attrs = NULL, /* patched at runtime */
541 DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7");
542 static struct attribute *rapl_formats_attr[] = {
543 &format_attr_event.attr,
547 static struct attribute_group rapl_pmu_format_group = {
549 .attrs = rapl_formats_attr,
552 const struct attribute_group *rapl_attr_groups[] = {
553 &rapl_pmu_attr_group,
554 &rapl_pmu_format_group,
555 &rapl_pmu_events_group,
559 static void rapl_cpu_exit(int cpu)
561 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
564 /* Check if exiting cpu is used for collecting rapl events */
565 if (!cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask))
569 /* Find a new cpu to collect rapl events */
570 target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
572 /* Migrate rapl events to the new target */
573 if (target < nr_cpu_ids) {
574 cpumask_set_cpu(target, &rapl_cpu_mask);
576 perf_pmu_migrate_context(pmu->pmu, cpu, target);
580 static void rapl_cpu_init(int cpu)
582 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
586 * Check if there is an online cpu in the package which collects rapl
589 target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu));
590 if (target < nr_cpu_ids)
593 cpumask_set_cpu(cpu, &rapl_cpu_mask);
597 static int rapl_cpu_prepare(int cpu)
599 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
604 pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
608 raw_spin_lock_init(&pmu->lock);
609 INIT_LIST_HEAD(&pmu->active_list);
610 pmu->pmu = &rapl_pmus->pmu;
611 pmu->timer_interval = ms_to_ktime(rapl_timer_ms);
613 rapl_hrtimer_init(pmu);
614 rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu;
618 static int rapl_cpu_notifier(struct notifier_block *self,
619 unsigned long action, void *hcpu)
621 unsigned int cpu = (long)hcpu;
623 switch (action & ~CPU_TASKS_FROZEN) {
625 rapl_cpu_prepare(cpu);
628 case CPU_DOWN_FAILED:
633 case CPU_DOWN_PREPARE:
640 static struct notifier_block rapl_cpu_nb = {
641 .notifier_call = rapl_cpu_notifier,
642 .priority = CPU_PRI_PERF + 1,
645 static int rapl_check_hw_unit(bool apply_quirk)
647 u64 msr_rapl_power_unit_bits;
650 /* protect rdmsrl() to handle virtualization */
651 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
653 for (i = 0; i < NR_RAPL_DOMAINS; i++)
654 rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
657 * DRAM domain on HSW server and KNL has fixed energy unit which can be
658 * different than the unit from power unit MSR. See
659 * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
660 * of 2. Datasheet, September 2014, Reference Number: 330784-001 "
663 rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16;
666 * Calculate the timer rate:
667 * Use reference of 200W for scaling the timeout to avoid counter
668 * overflows. 200W = 200 Joules/sec
669 * Divide interval by 2 to avoid lockstep (2 * 100)
670 * if hw unit is 32, then we use 2 ms 1/200/2
673 if (rapl_hw_unit[0] < 32) {
674 rapl_timer_ms = (1000 / (2 * 100));
675 rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1));
680 static void __init rapl_advertise(void)
684 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n",
685 hweight32(rapl_cntr_mask), rapl_timer_ms);
687 for (i = 0; i < NR_RAPL_DOMAINS; i++) {
688 if (rapl_cntr_mask & (1 << i)) {
689 pr_info("hw unit of domain %s 2^-%d Joules\n",
690 rapl_domain_names[i], rapl_hw_unit[i]);
695 static int __init rapl_prepare_cpus(void)
697 unsigned int cpu, pkg;
700 for_each_online_cpu(cpu) {
701 pkg = topology_logical_package_id(cpu);
702 if (rapl_pmus->pmus[pkg])
705 ret = rapl_cpu_prepare(cpu);
713 static void cleanup_rapl_pmus(void)
717 for (i = 0; i < rapl_pmus->maxpkg; i++)
718 kfree(rapl_pmus->pmus[i]);
722 static int __init init_rapl_pmus(void)
724 int maxpkg = topology_max_packages();
727 size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *);
728 rapl_pmus = kzalloc(size, GFP_KERNEL);
732 rapl_pmus->maxpkg = maxpkg;
733 rapl_pmus->pmu.attr_groups = rapl_attr_groups;
734 rapl_pmus->pmu.task_ctx_nr = perf_invalid_context;
735 rapl_pmus->pmu.event_init = rapl_pmu_event_init;
736 rapl_pmus->pmu.add = rapl_pmu_event_add;
737 rapl_pmus->pmu.del = rapl_pmu_event_del;
738 rapl_pmus->pmu.start = rapl_pmu_event_start;
739 rapl_pmus->pmu.stop = rapl_pmu_event_stop;
740 rapl_pmus->pmu.read = rapl_pmu_event_read;
744 #define X86_RAPL_MODEL_MATCH(model, init) \
745 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init }
747 struct intel_rapl_init_fun {
750 struct attribute **attrs;
753 static const struct intel_rapl_init_fun snb_rapl_init __initconst = {
754 .apply_quirk = false,
755 .cntr_mask = RAPL_IDX_CLN,
756 .attrs = rapl_events_cln_attr,
759 static const struct intel_rapl_init_fun hsx_rapl_init __initconst = {
761 .cntr_mask = RAPL_IDX_SRV,
762 .attrs = rapl_events_srv_attr,
765 static const struct intel_rapl_init_fun hsw_rapl_init __initconst = {
766 .apply_quirk = false,
767 .cntr_mask = RAPL_IDX_HSW,
768 .attrs = rapl_events_hsw_attr,
771 static const struct intel_rapl_init_fun snbep_rapl_init __initconst = {
772 .apply_quirk = false,
773 .cntr_mask = RAPL_IDX_SRV,
774 .attrs = rapl_events_srv_attr,
777 static const struct intel_rapl_init_fun knl_rapl_init __initconst = {
779 .cntr_mask = RAPL_IDX_KNL,
780 .attrs = rapl_events_knl_attr,
783 static const struct intel_rapl_init_fun skl_rapl_init __initconst = {
784 .apply_quirk = false,
785 .cntr_mask = RAPL_IDX_SKL_CLN,
786 .attrs = rapl_events_skl_attr,
789 static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
790 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_rapl_init),
791 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_rapl_init),
793 X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE, snb_rapl_init),
794 X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X, snbep_rapl_init),
796 X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE, hsw_rapl_init),
797 X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_X, hsw_rapl_init),
798 X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT, hsw_rapl_init),
799 X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E, hsw_rapl_init),
801 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, hsw_rapl_init),
802 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, hsw_rapl_init),
803 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, hsw_rapl_init),
804 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, hsw_rapl_init),
806 X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_rapl_init),
808 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init),
809 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init),
810 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init),
814 MODULE_DEVICE_TABLE(x86cpu, rapl_cpu_match);
816 static int __init rapl_pmu_init(void)
818 const struct x86_cpu_id *id;
819 struct intel_rapl_init_fun *rapl_init;
823 id = x86_match_cpu(rapl_cpu_match);
827 rapl_init = (struct intel_rapl_init_fun *)id->driver_data;
828 apply_quirk = rapl_init->apply_quirk;
829 rapl_cntr_mask = rapl_init->cntr_mask;
830 rapl_pmu_events_group.attrs = rapl_init->attrs;
832 ret = rapl_check_hw_unit(apply_quirk);
836 ret = init_rapl_pmus();
840 cpu_notifier_register_begin();
842 ret = rapl_prepare_cpus();
846 ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1);
850 __register_cpu_notifier(&rapl_cpu_nb);
851 cpu_notifier_register_done();
856 pr_warn("Initialization failed (%d), disabled\n", ret);
858 cpu_notifier_register_done();
861 module_init(rapl_pmu_init);
863 static void __exit intel_rapl_exit(void)
865 cpu_notifier_register_begin();
866 __unregister_cpu_notifier(&rapl_cpu_nb);
867 perf_pmu_unregister(&rapl_pmus->pmu);
869 cpu_notifier_register_done();
871 module_exit(intel_rapl_exit);