2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/dmar.h>
17 #include <linux/hpet.h>
18 #include <linux/msi.h>
19 #include <asm/irqdomain.h>
20 #include <asm/msidef.h>
22 #include <asm/hw_irq.h>
24 #include <asm/irq_remapping.h>
26 static struct irq_domain *msi_default_domain;
28 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
30 struct irq_cfg *cfg = irqd_cfg(data);
32 msg->address_hi = MSI_ADDR_BASE_HI;
35 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
39 ((apic->irq_dest_mode == 0) ?
40 MSI_ADDR_DEST_MODE_PHYSICAL :
41 MSI_ADDR_DEST_MODE_LOGICAL) |
42 ((apic->irq_delivery_mode != dest_LowestPrio) ?
43 MSI_ADDR_REDIRECTION_CPU :
44 MSI_ADDR_REDIRECTION_LOWPRI) |
45 MSI_ADDR_DEST_ID(cfg->dest_apicid);
48 MSI_DATA_TRIGGER_EDGE |
49 MSI_DATA_LEVEL_ASSERT |
50 ((apic->irq_delivery_mode != dest_LowestPrio) ?
51 MSI_DATA_DELIVERY_FIXED :
52 MSI_DATA_DELIVERY_LOWPRI) |
53 MSI_DATA_VECTOR(cfg->vector);
57 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
58 * which implement the MSI or MSI-X Capability Structure.
60 static struct irq_chip pci_msi_controller = {
62 .irq_unmask = pci_msi_unmask_irq,
63 .irq_mask = pci_msi_mask_irq,
64 .irq_ack = irq_chip_ack_parent,
65 .irq_retrigger = irq_chip_retrigger_hierarchy,
66 .irq_compose_msi_msg = irq_msi_compose_msg,
67 .flags = IRQCHIP_SKIP_SET_WAKE,
70 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
72 struct irq_domain *domain;
73 struct irq_alloc_info info;
75 init_irq_alloc_info(&info, NULL);
76 info.type = X86_IRQ_ALLOC_TYPE_MSI;
79 domain = irq_remapping_get_irq_domain(&info);
81 domain = msi_default_domain;
85 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
88 void native_teardown_msi_irq(unsigned int irq)
90 irq_domain_free_irqs(irq, 1);
93 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
94 msi_alloc_info_t *arg)
96 return arg->msi_hwirq;
99 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
100 msi_alloc_info_t *arg)
102 struct pci_dev *pdev = to_pci_dev(dev);
103 struct msi_desc *desc = first_pci_msi_entry(pdev);
105 init_irq_alloc_info(arg, NULL);
107 if (desc->msi_attrib.is_msix) {
108 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
110 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
111 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
116 EXPORT_SYMBOL_GPL(pci_msi_prepare);
118 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
120 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
122 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
124 static struct msi_domain_ops pci_msi_domain_ops = {
125 .get_hwirq = pci_msi_get_hwirq,
126 .msi_prepare = pci_msi_prepare,
127 .set_desc = pci_msi_set_desc,
130 static struct msi_domain_info pci_msi_domain_info = {
131 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
133 .ops = &pci_msi_domain_ops,
134 .chip = &pci_msi_controller,
135 .handler = handle_edge_irq,
136 .handler_name = "edge",
139 void arch_init_msi_domain(struct irq_domain *parent)
144 msi_default_domain = pci_msi_create_irq_domain(NULL,
145 &pci_msi_domain_info, parent);
146 if (!msi_default_domain)
147 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
150 #ifdef CONFIG_IRQ_REMAP
151 static struct irq_chip pci_msi_ir_controller = {
152 .name = "IR-PCI-MSI",
153 .irq_unmask = pci_msi_unmask_irq,
154 .irq_mask = pci_msi_mask_irq,
155 .irq_ack = irq_chip_ack_parent,
156 .irq_retrigger = irq_chip_retrigger_hierarchy,
157 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
158 .flags = IRQCHIP_SKIP_SET_WAKE,
161 static struct msi_domain_info pci_msi_ir_domain_info = {
162 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
163 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
164 .ops = &pci_msi_domain_ops,
165 .chip = &pci_msi_ir_controller,
166 .handler = handle_edge_irq,
167 .handler_name = "edge",
170 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
171 const char *name, int id)
173 struct fwnode_handle *fn;
174 struct irq_domain *d;
176 fn = irq_domain_alloc_named_id_fwnode(name, id);
179 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
180 irq_domain_free_fwnode(fn);
184 struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
186 return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
191 #ifdef CONFIG_DMAR_TABLE
192 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
194 dmar_msi_write(data->irq, msg);
197 static struct irq_chip dmar_msi_controller = {
199 .irq_unmask = dmar_msi_unmask,
200 .irq_mask = dmar_msi_mask,
201 .irq_ack = irq_chip_ack_parent,
202 .irq_set_affinity = msi_domain_set_affinity,
203 .irq_retrigger = irq_chip_retrigger_hierarchy,
204 .irq_compose_msi_msg = irq_msi_compose_msg,
205 .irq_write_msi_msg = dmar_msi_write_msg,
206 .flags = IRQCHIP_SKIP_SET_WAKE,
209 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
210 msi_alloc_info_t *arg)
215 static int dmar_msi_init(struct irq_domain *domain,
216 struct msi_domain_info *info, unsigned int virq,
217 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
219 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
220 handle_edge_irq, arg->dmar_data, "edge");
225 static struct msi_domain_ops dmar_msi_domain_ops = {
226 .get_hwirq = dmar_msi_get_hwirq,
227 .msi_init = dmar_msi_init,
230 static struct msi_domain_info dmar_msi_domain_info = {
231 .ops = &dmar_msi_domain_ops,
232 .chip = &dmar_msi_controller,
235 static struct irq_domain *dmar_get_irq_domain(void)
237 static struct irq_domain *dmar_domain;
238 static DEFINE_MUTEX(dmar_lock);
240 mutex_lock(&dmar_lock);
241 if (dmar_domain == NULL)
242 dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
244 mutex_unlock(&dmar_lock);
249 int dmar_alloc_hwirq(int id, int node, void *arg)
251 struct irq_domain *domain = dmar_get_irq_domain();
252 struct irq_alloc_info info;
257 init_irq_alloc_info(&info, NULL);
258 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
260 info.dmar_data = arg;
262 return irq_domain_alloc_irqs(domain, 1, node, &info);
265 void dmar_free_hwirq(int irq)
267 irq_domain_free_irqs(irq, 1);
272 * MSI message composition
274 #ifdef CONFIG_HPET_TIMER
275 static inline int hpet_dev_id(struct irq_domain *domain)
277 struct msi_domain_info *info = msi_get_domain_info(domain);
279 return (int)(long)info->data;
282 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
284 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
287 static struct irq_chip hpet_msi_controller __ro_after_init = {
289 .irq_unmask = hpet_msi_unmask,
290 .irq_mask = hpet_msi_mask,
291 .irq_ack = irq_chip_ack_parent,
292 .irq_set_affinity = msi_domain_set_affinity,
293 .irq_retrigger = irq_chip_retrigger_hierarchy,
294 .irq_compose_msi_msg = irq_msi_compose_msg,
295 .irq_write_msi_msg = hpet_msi_write_msg,
296 .flags = IRQCHIP_SKIP_SET_WAKE,
299 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
300 msi_alloc_info_t *arg)
302 return arg->hpet_index;
305 static int hpet_msi_init(struct irq_domain *domain,
306 struct msi_domain_info *info, unsigned int virq,
307 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
309 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
310 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
311 handle_edge_irq, arg->hpet_data, "edge");
316 static void hpet_msi_free(struct irq_domain *domain,
317 struct msi_domain_info *info, unsigned int virq)
319 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
322 static struct msi_domain_ops hpet_msi_domain_ops = {
323 .get_hwirq = hpet_msi_get_hwirq,
324 .msi_init = hpet_msi_init,
325 .msi_free = hpet_msi_free,
328 static struct msi_domain_info hpet_msi_domain_info = {
329 .ops = &hpet_msi_domain_ops,
330 .chip = &hpet_msi_controller,
333 struct irq_domain *hpet_create_irq_domain(int hpet_id)
335 struct irq_domain *parent;
336 struct irq_alloc_info info;
337 struct msi_domain_info *domain_info;
339 if (x86_vector_domain == NULL)
342 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
346 *domain_info = hpet_msi_domain_info;
347 domain_info->data = (void *)(long)hpet_id;
349 init_irq_alloc_info(&info, NULL);
350 info.type = X86_IRQ_ALLOC_TYPE_HPET;
351 info.hpet_id = hpet_id;
352 parent = irq_remapping_get_ir_irq_domain(&info);
354 parent = x86_vector_domain;
356 hpet_msi_controller.name = "IR-HPET-MSI";
358 return msi_create_irq_domain(NULL, domain_info, parent);
361 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
364 struct irq_alloc_info info;
366 init_irq_alloc_info(&info, NULL);
367 info.type = X86_IRQ_ALLOC_TYPE_HPET;
368 info.hpet_data = dev;
369 info.hpet_id = hpet_dev_id(domain);
370 info.hpet_index = dev_num;
372 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);