arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        (PAGE_SIZE << 4)
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114
 115         dse.val = PERF_MEM_NA;
 116
 117         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 118                 dse.mem_op = PERF_MEM_OP_STORE;
 119         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 120                 dse.mem_op = PERF_MEM_OP_LOAD;
 121
 122         /*
 123          * L1 info only valid for following events:
 124          *
 125          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 126          * MEM_UOPS_RETIRED.LOCK_STORES
 127          * MEM_UOPS_RETIRED.SPLIT_STORES
 128          * MEM_UOPS_RETIRED.ALL_STORES
 129          */
 130         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 131                 if (status & 1)
 132                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133                 else
 134                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135         }
 136         return dse.val;
 137 }
 138
 139 static u64 load_latency_data(u64 status)
 140 {
 141         union intel_x86_pebs_dse dse;
 142         u64 val;
 143         int model = boot_cpu_data.x86_model;
 144         int fam = boot_cpu_data.x86;
 145
 146         dse.val = status;
 147
 148         /*
 149          * use the mapping table for bit 0-3
 150          */
 151         val = pebs_data_source[dse.ld_dse];
 152
 153         /*
 154          * Nehalem models do not support TLB, Lock infos
 155          */
 156         if (fam == 0x6 && (model == 26 || model == 30
 157             || model == 31 || model == 46)) {
 158                 val |= P(TLB, NA) | P(LOCK, NA);
 159                 return val;
 160         }
 161         /*
 162          * bit 4: TLB access
 163          * 0 = did not miss 2nd level TLB
 164          * 1 = missed 2nd level TLB
 165          */
 166         if (dse.ld_stlb_miss)
 167                 val |= P(TLB, MISS) | P(TLB, L2);
 168         else
 169                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 170
 171         /*
 172          * bit 5: locked prefix
 173          */
 174         if (dse.ld_locked)
 175                 val |= P(LOCK, LOCKED);
 176
 177         return val;
 178 }
 179
 180 struct pebs_record_core {
 181         u64 flags, ip;
 182         u64 ax, bx, cx, dx;
 183         u64 si, di, bp, sp;
 184         u64 r8,  r9,  r10, r11;
 185         u64 r12, r13, r14, r15;
 186 };
 187
 188 struct pebs_record_nhm {
 189         u64 flags, ip;
 190         u64 ax, bx, cx, dx;
 191         u64 si, di, bp, sp;
 192         u64 r8,  r9,  r10, r11;
 193         u64 r12, r13, r14, r15;
 194         u64 status, dla, dse, lat;
 195 };
 196
 197 /*
 198  * Same as pebs_record_nhm, with two additional fields.
 199  */
 200 struct pebs_record_hsw {
 201         u64 flags, ip;
 202         u64 ax, bx, cx, dx;
 203         u64 si, di, bp, sp;
 204         u64 r8,  r9,  r10, r11;
 205         u64 r12, r13, r14, r15;
 206         u64 status, dla, dse, lat;
 207         u64 real_ip, tsx_tuning;
 208 };
 209
 210 union hsw_tsx_tuning {
 211         struct {
 212                 u32 cycles_last_block     : 32,
 213                     hle_abort             : 1,
 214                     rtm_abort             : 1,
 215                     instruction_abort     : 1,
 216                     non_instruction_abort : 1,
 217                     retry                 : 1,
 218                     data_conflict         : 1,
 219                     capacity_writes       : 1,
 220                     capacity_reads        : 1;
 221         };
 222         u64         value;
 223 };
 224
 225 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 226
 227 /* Same as HSW, plus TSC */
 228
 229 struct pebs_record_skl {
 230         u64 flags, ip;
 231         u64 ax, bx, cx, dx;
 232         u64 si, di, bp, sp;
 233         u64 r8,  r9,  r10, r11;
 234         u64 r12, r13, r14, r15;
 235         u64 status, dla, dse, lat;
 236         u64 real_ip, tsx_tuning;
 237         u64 tsc;
 238 };
 239
 240 void init_debug_store_on_cpu(int cpu)
 241 {
 242         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 243
 244         if (!ds)
 245                 return;
 246
 247         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 248                      (u32)((u64)(unsigned long)ds),
 249                      (u32)((u64)(unsigned long)ds >> 32));
 250 }
 251
 252 void fini_debug_store_on_cpu(int cpu)
 253 {
 254         if (!per_cpu(cpu_hw_events, cpu).ds)
 255                 return;
 256
 257         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 258 }
 259
 260 static DEFINE_PER_CPU(void *, insn_buffer);
 261
 262 static int alloc_pebs_buffer(int cpu)
 263 {
 264         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 265         int node = cpu_to_node(cpu);
 266         int max;
 267         void *buffer, *ibuffer;
 268
 269         if (!x86_pmu.pebs)
 270                 return 0;
 271
 272         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 273         if (unlikely(!buffer))
 274                 return -ENOMEM;
 275
 276         /*
 277          * HSW+ already provides us the eventing ip; no need to allocate this
 278          * buffer then.
 279          */
 280         if (x86_pmu.intel_cap.pebs_format < 2) {
 281                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 282                 if (!ibuffer) {
 283                         kfree(buffer);
 284                         return -ENOMEM;
 285                 }
 286                 per_cpu(insn_buffer, cpu) = ibuffer;
 287         }
 288
 289         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 290
 291         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 292         ds->pebs_index = ds->pebs_buffer_base;
 293         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 294                 max * x86_pmu.pebs_record_size;
 295
 296         return 0;
 297 }
 298
 299 static void release_pebs_buffer(int cpu)
 300 {
 301         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 302
 303         if (!ds || !x86_pmu.pebs)
 304                 return;
 305
 306         kfree(per_cpu(insn_buffer, cpu));
 307         per_cpu(insn_buffer, cpu) = NULL;
 308
 309         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 310         ds->pebs_buffer_base = 0;
 311 }
 312
 313 static int alloc_bts_buffer(int cpu)
 314 {
 315         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 316         int node = cpu_to_node(cpu);
 317         int max, thresh;
 318         void *buffer;
 319
 320         if (!x86_pmu.bts)
 321                 return 0;
 322
 323         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 324         if (unlikely(!buffer)) {
 325                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 326                 return -ENOMEM;
 327         }
 328
 329         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 330         thresh = max / 16;
 331
 332         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 333         ds->bts_index = ds->bts_buffer_base;
 334         ds->bts_absolute_maximum = ds->bts_buffer_base +
 335                 max * BTS_RECORD_SIZE;
 336         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 337                 thresh * BTS_RECORD_SIZE;
 338
 339         return 0;
 340 }
 341
 342 static void release_bts_buffer(int cpu)
 343 {
 344         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 345
 346         if (!ds || !x86_pmu.bts)
 347                 return;
 348
 349         kfree((void *)(unsigned long)ds->bts_buffer_base);
 350         ds->bts_buffer_base = 0;
 351 }
 352
 353 static int alloc_ds_buffer(int cpu)
 354 {
 355         int node = cpu_to_node(cpu);
 356         struct debug_store *ds;
 357
 358         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 359         if (unlikely(!ds))
 360                 return -ENOMEM;
 361
 362         per_cpu(cpu_hw_events, cpu).ds = ds;
 363
 364         return 0;
 365 }
 366
 367 static void release_ds_buffer(int cpu)
 368 {
 369         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 370
 371         if (!ds)
 372                 return;
 373
 374         per_cpu(cpu_hw_events, cpu).ds = NULL;
 375         kfree(ds);
 376 }
 377
 378 void release_ds_buffers(void)
 379 {
 380         int cpu;
 381
 382         if (!x86_pmu.bts && !x86_pmu.pebs)
 383                 return;
 384
 385         get_online_cpus();
 386         for_each_online_cpu(cpu)
 387                 fini_debug_store_on_cpu(cpu);
 388
 389         for_each_possible_cpu(cpu) {
 390                 release_pebs_buffer(cpu);
 391                 release_bts_buffer(cpu);
 392                 release_ds_buffer(cpu);
 393         }
 394         put_online_cpus();
 395 }
 396
 397 void reserve_ds_buffers(void)
 398 {
 399         int bts_err = 0, pebs_err = 0;
 400         int cpu;
 401
 402         x86_pmu.bts_active = 0;
 403         x86_pmu.pebs_active = 0;
 404
 405         if (!x86_pmu.bts && !x86_pmu.pebs)
 406                 return;
 407
 408         if (!x86_pmu.bts)
 409                 bts_err = 1;
 410
 411         if (!x86_pmu.pebs)
 412                 pebs_err = 1;
 413
 414         get_online_cpus();
 415
 416         for_each_possible_cpu(cpu) {
 417                 if (alloc_ds_buffer(cpu)) {
 418                         bts_err = 1;
 419                         pebs_err = 1;
 420                 }
 421
 422                 if (!bts_err && alloc_bts_buffer(cpu))
 423                         bts_err = 1;
 424
 425                 if (!pebs_err && alloc_pebs_buffer(cpu))
 426                         pebs_err = 1;
 427
 428                 if (bts_err && pebs_err)
 429                         break;
 430         }
 431
 432         if (bts_err) {
 433                 for_each_possible_cpu(cpu)
 434                         release_bts_buffer(cpu);
 435         }
 436
 437         if (pebs_err) {
 438                 for_each_possible_cpu(cpu)
 439                         release_pebs_buffer(cpu);
 440         }
 441
 442         if (bts_err && pebs_err) {
 443                 for_each_possible_cpu(cpu)
 444                         release_ds_buffer(cpu);
 445         } else {
 446                 if (x86_pmu.bts && !bts_err)
 447                         x86_pmu.bts_active = 1;
 448
 449                 if (x86_pmu.pebs && !pebs_err)
 450                         x86_pmu.pebs_active = 1;
 451
 452                 for_each_online_cpu(cpu)
 453                         init_debug_store_on_cpu(cpu);
 454         }
 455
 456         put_online_cpus();
 457 }
 458
 459 /*
 460  * BTS
 461  */
 462
 463 struct event_constraint bts_constraint =
 464         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 465
 466 void intel_pmu_enable_bts(u64 config)
 467 {
 468         unsigned long debugctlmsr;
 469
 470         debugctlmsr = get_debugctlmsr();
 471
 472         debugctlmsr |= DEBUGCTLMSR_TR;
 473         debugctlmsr |= DEBUGCTLMSR_BTS;
 474         if (config & ARCH_PERFMON_EVENTSEL_INT)
 475                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 476
 477         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 478                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 479
 480         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 481                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 482
 483         update_debugctlmsr(debugctlmsr);
 484 }
 485
 486 void intel_pmu_disable_bts(void)
 487 {
 488         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 489         unsigned long debugctlmsr;
 490
 491         if (!cpuc->ds)
 492                 return;
 493
 494         debugctlmsr = get_debugctlmsr();
 495
 496         debugctlmsr &=
 497                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 498                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 499
 500         update_debugctlmsr(debugctlmsr);
 501 }
 502
 503 int intel_pmu_drain_bts_buffer(void)
 504 {
 505         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 506         struct debug_store *ds = cpuc->ds;
 507         struct bts_record {
 508                 u64     from;
 509                 u64     to;
 510                 u64     flags;
 511         };
 512         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 513         struct bts_record *at, *base, *top;
 514         struct perf_output_handle handle;
 515         struct perf_event_header header;
 516         struct perf_sample_data data;
 517         unsigned long skip = 0;
 518         struct pt_regs regs;
 519
 520         if (!event)
 521                 return 0;
 522
 523         if (!x86_pmu.bts_active)
 524                 return 0;
 525
 526         base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 527         top  = (struct bts_record *)(unsigned long)ds->bts_index;
 528
 529         if (top <= base)
 530                 return 0;
 531
 532         memset(&regs, 0, sizeof(regs));
 533
 534         ds->bts_index = ds->bts_buffer_base;
 535
 536         perf_sample_data_init(&data, 0, event->hw.last_period);
 537
 538         /*
 539          * BTS leaks kernel addresses in branches across the cpl boundary,
 540          * such as traps or system calls, so unless the user is asking for
 541          * kernel tracing (and right now it's not possible), we'd need to
 542          * filter them out. But first we need to count how many of those we
 543          * have in the current batch. This is an extra O(n) pass, however,
 544          * it's much faster than the other one especially considering that
 545          * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
 546          * alloc_bts_buffer()).
 547          */
 548         for (at = base; at < top; at++) {
 549                 /*
 550                  * Note that right now *this* BTS code only works if
 551                  * attr::exclude_kernel is set, but let's keep this extra
 552                  * check here in case that changes.
 553                  */
 554                 if (event->attr.exclude_kernel &&
 555                     (kernel_ip(at->from) || kernel_ip(at->to)))
 556                         skip++;
 557         }
 558
 559         /*
 560          * Prepare a generic sample, i.e. fill in the invariant fields.
 561          * We will overwrite the from and to address before we output
 562          * the sample.
 563          */
 564         perf_prepare_sample(&header, &data, event, &regs);
 565
 566         if (perf_output_begin(&handle, event, header.size *
 567                               (top - base - skip)))
 568                 return 1;
 569
 570         for (at = base; at < top; at++) {
 571                 /* Filter out any records that contain kernel addresses. */
 572                 if (event->attr.exclude_kernel &&
 573                     (kernel_ip(at->from) || kernel_ip(at->to)))
 574                         continue;
 575
 576                 data.ip         = at->from;
 577                 data.addr       = at->to;
 578
 579                 perf_output_sample(&handle, &header, &data, event);
 580         }
 581
 582         perf_output_end(&handle);
 583
 584         /* There's new data available. */
 585         event->hw.interrupts++;
 586         event->pending_kill = POLL_IN;
 587         return 1;
 588 }
 589
 590 static inline void intel_pmu_drain_pebs_buffer(void)
 591 {
 592         struct pt_regs regs;
 593
 594         x86_pmu.drain_pebs(&regs);
 595 }
 596
 597 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 598 {
 599         if (!sched_in)
 600                 intel_pmu_drain_pebs_buffer();
 601 }
 602
 603 /*
 604  * PEBS
 605  */
 606 struct event_constraint intel_core2_pebs_event_constraints[] = {
 607         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 608         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 609         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 610         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 611         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 612         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 613         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 614         EVENT_CONSTRAINT_END
 615 };
 616
 617 struct event_constraint intel_atom_pebs_event_constraints[] = {
 618         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 619         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 620         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 621         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 622         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 623         /* Allow all events as PEBS with no flags */
 624         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 625         EVENT_CONSTRAINT_END
 626 };
 627
 628 struct event_constraint intel_slm_pebs_event_constraints[] = {
 629         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 630         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
 631         /* Allow all events as PEBS with no flags */
 632         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 633         EVENT_CONSTRAINT_END
 634 };
 635
 636 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 637         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 638         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 639         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 640         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 641         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 642         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 643         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 644         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 645         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 646         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 647         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 648         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 649         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 650         EVENT_CONSTRAINT_END
 651 };
 652
 653 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 654         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 655         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 656         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 657         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 658         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 659         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 660         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 661         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 662         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 663         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 664         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 665         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 666         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 667         EVENT_CONSTRAINT_END
 668 };
 669
 670 struct event_constraint intel_snb_pebs_event_constraints[] = {
 671         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 672         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 673         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 674         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 675         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 676         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 677         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 678         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 679         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 680         /* Allow all events as PEBS with no flags */
 681         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 682         EVENT_CONSTRAINT_END
 683 };
 684
 685 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 686         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 687         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 688         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 689         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 690         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 691         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 692         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 693         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 694         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 695         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 696         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 697         /* Allow all events as PEBS with no flags */
 698         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 699         EVENT_CONSTRAINT_END
 700 };
 701
 702 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 703         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 704         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 705         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 706         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 707         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 708         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 709         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 710         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 711         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 712         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 713         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 714         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 715         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 716         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 717         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 718         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 719         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 720         /* Allow all events as PEBS with no flags */
 721         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 722         EVENT_CONSTRAINT_END
 723 };
 724
 725 struct event_constraint intel_skl_pebs_event_constraints[] = {
 726         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 727         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 728         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 729         /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
 730         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 731         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 732         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 733         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 734         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 735         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 736         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 737         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 738         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 739         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 740         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 741         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 742         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 743         /* Allow all events as PEBS with no flags */
 744         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 745         EVENT_CONSTRAINT_END
 746 };
 747
 748 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 749 {
 750         struct event_constraint *c;
 751
 752         if (!event->attr.precise_ip)
 753                 return NULL;
 754
 755         if (x86_pmu.pebs_constraints) {
 756                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 757                         if ((event->hw.config & c->cmask) == c->code) {
 758                                 event->hw.flags |= c->flags;
 759                                 return c;
 760                         }
 761                 }
 762         }
 763
 764         return &emptyconstraint;
 765 }
 766
 767 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
 768 {
 769         return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
 770 }
 771
 772 void intel_pmu_pebs_enable(struct perf_event *event)
 773 {
 774         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 775         struct hw_perf_event *hwc = &event->hw;
 776         struct debug_store *ds = cpuc->ds;
 777         bool first_pebs;
 778         u64 threshold;
 779
 780         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 781
 782         first_pebs = !pebs_is_enabled(cpuc);
 783         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 784
 785         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 786                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 787         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 788                 cpuc->pebs_enabled |= 1ULL << 63;
 789
 790         /*
 791          * When the event is constrained enough we can use a larger
 792          * threshold and run the event with less frequent PMI.
 793          */
 794         if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
 795                 threshold = ds->pebs_absolute_maximum -
 796                         x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
 797
 798                 if (first_pebs)
 799                         perf_sched_cb_inc(event->ctx->pmu);
 800         } else {
 801                 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 802
 803                 /*
 804                  * If not all events can use larger buffer,
 805                  * roll back to threshold = 1
 806                  */
 807                 if (!first_pebs &&
 808                     (ds->pebs_interrupt_threshold > threshold))
 809                         perf_sched_cb_dec(event->ctx->pmu);
 810         }
 811
 812         /* Use auto-reload if possible to save a MSR write in the PMI */
 813         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
 814                 ds->pebs_event_reset[hwc->idx] =
 815                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
 816         }
 817
 818         if (first_pebs || ds->pebs_interrupt_threshold > threshold)
 819                 ds->pebs_interrupt_threshold = threshold;
 820 }
 821
 822 void intel_pmu_pebs_disable(struct perf_event *event)
 823 {
 824         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 825         struct hw_perf_event *hwc = &event->hw;
 826         struct debug_store *ds = cpuc->ds;
 827         bool large_pebs = ds->pebs_interrupt_threshold >
 828                 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 829
 830         if (large_pebs)
 831                 intel_pmu_drain_pebs_buffer();
 832
 833         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 834
 835         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 836                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 837         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 838                 cpuc->pebs_enabled &= ~(1ULL << 63);
 839
 840         if (large_pebs && !pebs_is_enabled(cpuc))
 841                 perf_sched_cb_dec(event->ctx->pmu);
 842
 843         if (cpuc->enabled)
 844                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 845
 846         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 847 }
 848
 849 void intel_pmu_pebs_enable_all(void)
 850 {
 851         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 852
 853         if (cpuc->pebs_enabled)
 854                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 855 }
 856
 857 void intel_pmu_pebs_disable_all(void)
 858 {
 859         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 860
 861         if (cpuc->pebs_enabled)
 862                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 863 }
 864
 865 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 866 {
 867         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 868         unsigned long from = cpuc->lbr_entries[0].from;
 869         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 870         unsigned long ip = regs->ip;
 871         int is_64bit = 0;
 872         void *kaddr;
 873         int size;
 874
 875         /*
 876          * We don't need to fixup if the PEBS assist is fault like
 877          */
 878         if (!x86_pmu.intel_cap.pebs_trap)
 879                 return 1;
 880
 881         /*
 882          * No LBR entry, no basic block, no rewinding
 883          */
 884         if (!cpuc->lbr_stack.nr || !from || !to)
 885                 return 0;
 886
 887         /*
 888          * Basic blocks should never cross user/kernel boundaries
 889          */
 890         if (kernel_ip(ip) != kernel_ip(to))
 891                 return 0;
 892
 893         /*
 894          * unsigned math, either ip is before the start (impossible) or
 895          * the basic block is larger than 1 page (sanity)
 896          */
 897         if ((ip - to) > PEBS_FIXUP_SIZE)
 898                 return 0;
 899
 900         /*
 901          * We sampled a branch insn, rewind using the LBR stack
 902          */
 903         if (ip == to) {
 904                 set_linear_ip(regs, from);
 905                 return 1;
 906         }
 907
 908         size = ip - to;
 909         if (!kernel_ip(ip)) {
 910                 int bytes;
 911                 u8 *buf = this_cpu_read(insn_buffer);
 912
 913                 /* 'size' must fit our buffer, see above */
 914                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 915                 if (bytes != 0)
 916                         return 0;
 917
 918                 kaddr = buf;
 919         } else {
 920                 kaddr = (void *)to;
 921         }
 922
 923         do {
 924                 struct insn insn;
 925
 926                 old_to = to;
 927
 928 #ifdef CONFIG_X86_64
 929                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 930 #endif
 931                 insn_init(&insn, kaddr, size, is_64bit);
 932                 insn_get_length(&insn);
 933                 /*
 934                  * Make sure there was not a problem decoding the
 935                  * instruction and getting the length.  This is
 936                  * doubly important because we have an infinite
 937                  * loop if insn.length=0.
 938                  */
 939                 if (!insn.length)
 940                         break;
 941
 942                 to += insn.length;
 943                 kaddr += insn.length;
 944                 size -= insn.length;
 945         } while (to < ip);
 946
 947         if (to == ip) {
 948                 set_linear_ip(regs, old_to);
 949                 return 1;
 950         }
 951
 952         /*
 953          * Even though we decoded the basic block, the instruction stream
 954          * never matched the given IP, either the TO or the IP got corrupted.
 955          */
 956         return 0;
 957 }
 958
 959 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
 960 {
 961         if (pebs->tsx_tuning) {
 962                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 963                 return tsx.cycles_last_block;
 964         }
 965         return 0;
 966 }
 967
 968 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
 969 {
 970         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 971
 972         /* For RTM XABORTs also log the abort code from AX */
 973         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 974                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 975         return txn;
 976 }
 977
 978 static void setup_pebs_sample_data(struct perf_event *event,
 979                                    struct pt_regs *iregs, void *__pebs,
 980                                    struct perf_sample_data *data,
 981                                    struct pt_regs *regs)
 982 {
 983 #define PERF_X86_EVENT_PEBS_HSW_PREC \
 984                 (PERF_X86_EVENT_PEBS_ST_HSW | \
 985                  PERF_X86_EVENT_PEBS_LD_HSW | \
 986                  PERF_X86_EVENT_PEBS_NA_HSW)
 987         /*
 988          * We cast to the biggest pebs_record but are careful not to
 989          * unconditionally access the 'extra' entries.
 990          */
 991         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 992         struct pebs_record_skl *pebs = __pebs;
 993         u64 sample_type;
 994         int fll, fst, dsrc;
 995         int fl = event->hw.flags;
 996
 997         if (pebs == NULL)
 998                 return;
 999
1000         sample_type = event->attr.sample_type;
1001         dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1002
1003         fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1004         fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1005
1006         perf_sample_data_init(data, 0, event->hw.last_period);
1007
1008         data->period = event->hw.last_period;
1009
1010         /*
1011          * Use latency for weight (only avail with PEBS-LL)
1012          */
1013         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1014                 data->weight = pebs->lat;
1015
1016         /*
1017          * data.data_src encodes the data source
1018          */
1019         if (dsrc) {
1020                 u64 val = PERF_MEM_NA;
1021                 if (fll)
1022                         val = load_latency_data(pebs->dse);
1023                 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1024                         val = precise_datala_hsw(event, pebs->dse);
1025                 else if (fst)
1026                         val = precise_store_data(pebs->dse);
1027                 data->data_src.val = val;
1028         }
1029
1030         /*
1031          * We use the interrupt regs as a base because the PEBS record
1032          * does not contain a full regs set, specifically it seems to
1033          * lack segment descriptors, which get used by things like
1034          * user_mode().
1035          *
1036          * In the simple case fix up only the IP and BP,SP regs, for
1037          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1038          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1039          */
1040         *regs = *iregs;
1041         regs->flags = pebs->flags;
1042         set_linear_ip(regs, pebs->ip);
1043         regs->bp = pebs->bp;
1044         regs->sp = pebs->sp;
1045
1046         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1047                 regs->ax = pebs->ax;
1048                 regs->bx = pebs->bx;
1049                 regs->cx = pebs->cx;
1050                 regs->dx = pebs->dx;
1051                 regs->si = pebs->si;
1052                 regs->di = pebs->di;
1053                 regs->bp = pebs->bp;
1054                 regs->sp = pebs->sp;
1055
1056                 regs->flags = pebs->flags;
1057 #ifndef CONFIG_X86_32
1058                 regs->r8 = pebs->r8;
1059                 regs->r9 = pebs->r9;
1060                 regs->r10 = pebs->r10;
1061                 regs->r11 = pebs->r11;
1062                 regs->r12 = pebs->r12;
1063                 regs->r13 = pebs->r13;
1064                 regs->r14 = pebs->r14;
1065                 regs->r15 = pebs->r15;
1066 #endif
1067         }
1068
1069         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1070                 regs->ip = pebs->real_ip;
1071                 regs->flags |= PERF_EFLAGS_EXACT;
1072         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1073                 regs->flags |= PERF_EFLAGS_EXACT;
1074         else
1075                 regs->flags &= ~PERF_EFLAGS_EXACT;
1076
1077         if ((sample_type & PERF_SAMPLE_ADDR) &&
1078             x86_pmu.intel_cap.pebs_format >= 1)
1079                 data->addr = pebs->dla;
1080
1081         if (x86_pmu.intel_cap.pebs_format >= 2) {
1082                 /* Only set the TSX weight when no memory weight. */
1083                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1084                         data->weight = intel_hsw_weight(pebs);
1085
1086                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1087                         data->txn = intel_hsw_transaction(pebs);
1088         }
1089
1090         /*
1091          * v3 supplies an accurate time stamp, so we use that
1092          * for the time stamp.
1093          *
1094          * We can only do this for the default trace clock.
1095          */
1096         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1097                 event->attr.use_clockid == 0)
1098                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1099
1100         if (has_branch_stack(event))
1101                 data->br_stack = &cpuc->lbr_stack;
1102 }
1103
1104 static inline void *
1105 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1106 {
1107         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1108         void *at;
1109         u64 pebs_status;
1110
1111         /*
1112          * fmt0 does not have a status bitfield (does not use
1113          * perf_record_nhm format)
1114          */
1115         if (x86_pmu.intel_cap.pebs_format < 1)
1116                 return base;
1117
1118         if (base == NULL)
1119                 return NULL;
1120
1121         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1122                 struct pebs_record_nhm *p = at;
1123
1124                 if (test_bit(bit, (unsigned long *)&p->status)) {
1125                         /* PEBS v3 has accurate status bits */
1126                         if (x86_pmu.intel_cap.pebs_format >= 3)
1127                                 return at;
1128
1129                         if (p->status == (1 << bit))
1130                                 return at;
1131
1132                         /* clear non-PEBS bit and re-check */
1133                         pebs_status = p->status & cpuc->pebs_enabled;
1134                         pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1135                         if (pebs_status == (1 << bit))
1136                                 return at;
1137                 }
1138         }
1139         return NULL;
1140 }
1141
1142 static void __intel_pmu_pebs_event(struct perf_event *event,
1143                                    struct pt_regs *iregs,
1144                                    void *base, void *top,
1145                                    int bit, int count)
1146 {
1147         struct perf_sample_data data;
1148         struct pt_regs regs;
1149         void *at = get_next_pebs_record_by_bit(base, top, bit);
1150
1151         if (!intel_pmu_save_and_restart(event) &&
1152             !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1153                 return;
1154
1155         while (count > 1) {
1156                 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1157                 perf_event_output(event, &data, &regs);
1158                 at += x86_pmu.pebs_record_size;
1159                 at = get_next_pebs_record_by_bit(at, top, bit);
1160                 count--;
1161         }
1162
1163         setup_pebs_sample_data(event, iregs, at, &data, &regs);
1164
1165         /*
1166          * All but the last records are processed.
1167          * The last one is left to be able to call the overflow handler.
1168          */
1169         if (perf_event_overflow(event, &data, &regs)) {
1170                 x86_pmu_stop(event, 0);
1171                 return;
1172         }
1173
1174 }
1175
1176 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1177 {
1178         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1179         struct debug_store *ds = cpuc->ds;
1180         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1181         struct pebs_record_core *at, *top;
1182         int n;
1183
1184         if (!x86_pmu.pebs_active)
1185                 return;
1186
1187         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1188         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1189
1190         /*
1191          * Whatever else happens, drain the thing
1192          */
1193         ds->pebs_index = ds->pebs_buffer_base;
1194
1195         if (!test_bit(0, cpuc->active_mask))
1196                 return;
1197
1198         WARN_ON_ONCE(!event);
1199
1200         if (!event->attr.precise_ip)
1201                 return;
1202
1203         n = top - at;
1204         if (n <= 0)
1205                 return;
1206
1207         __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1208 }
1209
1210 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1211 {
1212         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1213         struct debug_store *ds = cpuc->ds;
1214         struct perf_event *event;
1215         void *base, *at, *top;
1216         short counts[MAX_PEBS_EVENTS] = {};
1217         short error[MAX_PEBS_EVENTS] = {};
1218         int bit, i;
1219
1220         if (!x86_pmu.pebs_active)
1221                 return;
1222
1223         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1224         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1225
1226         ds->pebs_index = ds->pebs_buffer_base;
1227
1228         if (unlikely(base >= top))
1229                 return;
1230
1231         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1232                 struct pebs_record_nhm *p = at;
1233                 u64 pebs_status;
1234
1235                 /* PEBS v3 has accurate status bits */
1236                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1237                         for_each_set_bit(bit, (unsigned long *)&p->status,
1238                                          MAX_PEBS_EVENTS)
1239                                 counts[bit]++;
1240
1241                         continue;
1242                 }
1243
1244                 pebs_status = p->status & cpuc->pebs_enabled;
1245                 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1246
1247                 /*
1248                  * On some CPUs the PEBS status can be zero when PEBS is
1249                  * racing with clearing of GLOBAL_STATUS.
1250                  *
1251                  * Normally we would drop that record, but in the
1252                  * case when there is only a single active PEBS event
1253                  * we can assume it's for that event.
1254                  */
1255                 if (!pebs_status && cpuc->pebs_enabled &&
1256                         !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1257                         pebs_status = cpuc->pebs_enabled;
1258
1259                 bit = find_first_bit((unsigned long *)&pebs_status,
1260                                         x86_pmu.max_pebs_events);
1261                 if (bit >= x86_pmu.max_pebs_events)
1262                         continue;
1263
1264                 /*
1265                  * The PEBS hardware does not deal well with the situation
1266                  * when events happen near to each other and multiple bits
1267                  * are set. But it should happen rarely.
1268                  *
1269                  * If these events include one PEBS and multiple non-PEBS
1270                  * events, it doesn't impact PEBS record. The record will
1271                  * be handled normally. (slow path)
1272                  *
1273                  * If these events include two or more PEBS events, the
1274                  * records for the events can be collapsed into a single
1275                  * one, and it's not possible to reconstruct all events
1276                  * that caused the PEBS record. It's called collision.
1277                  * If collision happened, the record will be dropped.
1278                  */
1279                 if (p->status != (1ULL << bit)) {
1280                         for_each_set_bit(i, (unsigned long *)&pebs_status,
1281                                          x86_pmu.max_pebs_events)
1282                                 error[i]++;
1283                         continue;
1284                 }
1285
1286                 counts[bit]++;
1287         }
1288
1289         for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1290                 if ((counts[bit] == 0) && (error[bit] == 0))
1291                         continue;
1292
1293                 event = cpuc->events[bit];
1294                 WARN_ON_ONCE(!event);
1295                 WARN_ON_ONCE(!event->attr.precise_ip);
1296
1297                 /* log dropped samples number */
1298                 if (error[bit])
1299                         perf_log_lost_samples(event, error[bit]);
1300
1301                 if (counts[bit]) {
1302                         __intel_pmu_pebs_event(event, iregs, base,
1303                                                top, bit, counts[bit]);
1304                 }
1305         }
1306 }
1307
1308 /*
1309  * BTS, PEBS probe and setup
1310  */
1311
1312 void __init intel_ds_init(void)
1313 {
1314         /*
1315          * No support for 32bit formats
1316          */
1317         if (!boot_cpu_has(X86_FEATURE_DTES64))
1318                 return;
1319
1320         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1321         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1322         if (x86_pmu.pebs) {
1323                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1324                 int format = x86_pmu.intel_cap.pebs_format;
1325
1326                 switch (format) {
1327                 case 0:
1328                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1329                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1330                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1331                         break;
1332
1333                 case 1:
1334                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1335                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1336                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1337                         break;
1338
1339                 case 2:
1340                         pr_cont("PEBS fmt2%c, ", pebs_type);
1341                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1342                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1343                         break;
1344
1345                 case 3:
1346                         pr_cont("PEBS fmt3%c, ", pebs_type);
1347                         x86_pmu.pebs_record_size =
1348                                                 sizeof(struct pebs_record_skl);
1349                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1350                         x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1351                         break;
1352
1353                 default:
1354                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1355                         x86_pmu.pebs = 0;
1356                 }
1357         }
1358 }
1359
1360 void perf_restore_debug_store(void)
1361 {
1362         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1363
1364         if (!x86_pmu.bts && !x86_pmu.pebs)
1365                 return;
1366
1367         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1368 }