2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
57 #include <asm/trampoline.h>
60 #include <asm/pgtable.h>
61 #include <asm/tlbflush.h>
65 #include <asm/setup.h>
66 #include <asm/uv/uv.h>
67 #include <linux/mc146818rtc.h>
69 #include <asm/smpboot_hooks.h>
72 u8 apicid_2_node[MAX_APICID];
75 /* State of each CPU */
76 DEFINE_PER_CPU(int, cpu_state) = { 0 };
78 /* Store all idle threads, this can be reused instead of creating
79 * a new thread. Also avoids complicated thread destroy functionality
82 #ifdef CONFIG_HOTPLUG_CPU
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
97 void cpu_hotplug_driver_lock()
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
102 void cpu_hotplug_driver_unlock()
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
115 /* Number of siblings per CPU package */
116 int smp_num_siblings = 1;
117 EXPORT_SYMBOL(smp_num_siblings);
119 /* Last level cache ID of each logical CPU */
120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
122 /* representing HT siblings of each logical CPU */
123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
126 /* representing HT and core siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
130 /* Per CPU bogomips and other parameters */
131 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
132 EXPORT_PER_CPU_SYMBOL(cpu_info);
134 atomic_t init_deasserted;
136 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
137 /* which node each logical CPU is on */
138 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
139 EXPORT_SYMBOL(cpu_to_node_map);
141 /* set up a mapping between cpu and node. */
142 static void map_cpu_to_node(int cpu, int node)
144 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
145 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
146 cpu_to_node_map[cpu] = node;
149 /* undo a mapping between cpu and node. */
150 static void unmap_cpu_to_node(int cpu)
154 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
155 for (node = 0; node < MAX_NUMNODES; node++)
156 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
157 cpu_to_node_map[cpu] = 0;
159 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
160 #define map_cpu_to_node(cpu, node) ({})
161 #define unmap_cpu_to_node(cpu) ({})
165 static int boot_cpu_logical_apicid;
167 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
168 { [0 ... NR_CPUS-1] = BAD_APICID };
170 static void map_cpu_to_logical_apicid(void)
172 int cpu = smp_processor_id();
173 int apicid = logical_smp_processor_id();
174 int node = apic->apicid_to_node(apicid);
176 if (!node_online(node))
177 node = first_online_node;
179 cpu_2_logical_apicid[cpu] = apicid;
180 map_cpu_to_node(cpu, node);
183 void numa_remove_cpu(int cpu)
185 cpu_2_logical_apicid[cpu] = BAD_APICID;
186 unmap_cpu_to_node(cpu);
189 #define map_cpu_to_logical_apicid() do {} while (0)
193 * Report back to the Boot Processor.
196 static void __cpuinit smp_callin(void)
199 unsigned long timeout;
202 * If waken up by an INIT in an 82489DX configuration
203 * we may get here before an INIT-deassert IPI reaches
204 * our local APIC. We have to wait for the IPI or we'll
205 * lock up on an APIC access.
207 if (apic->wait_for_init_deassert)
208 apic->wait_for_init_deassert(&init_deasserted);
211 * (This works even if the APIC is not enabled.)
213 phys_id = read_apic_id();
214 cpuid = smp_processor_id();
215 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
216 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
219 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
222 * STARTUP IPIs are fragile beasts as they might sometimes
223 * trigger some glue motherboard logic. Complete APIC bus
224 * silence for 1 second, this overestimates the time the
225 * boot CPU is spending to send the up to 2 STARTUP IPIs
226 * by a factor of two. This should be enough.
230 * Waiting 2s total for startup (udelay is not yet working)
232 timeout = jiffies + 2*HZ;
233 while (time_before(jiffies, timeout)) {
235 * Has the boot CPU finished it's STARTUP sequence?
237 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
242 if (!time_before(jiffies, timeout)) {
243 panic("%s: CPU%d started up but did not get a callout!\n",
248 * the boot CPU has finished the init stage and is spinning
249 * on callin_map until we finish. We are free to set up this
250 * CPU, first the APIC. (this is probably redundant on most
254 pr_debug("CALLIN, before setup_local_APIC().\n");
255 if (apic->smp_callin_clear_local_apic)
256 apic->smp_callin_clear_local_apic();
258 end_local_APIC_setup();
259 map_cpu_to_logical_apicid();
261 notify_cpu_starting(cpuid);
265 * Need to enable IRQs because it can take longer and then
266 * the NMI watchdog might kill us.
271 pr_debug("Stack at about %p\n", &cpuid);
274 * Save our processor parameters
276 smp_store_cpu_info(cpuid);
279 * Allow the master to continue.
281 cpumask_set_cpu(cpuid, cpu_callin_mask);
285 * Activate a secondary processor.
287 notrace static void __cpuinit start_secondary(void *unused)
290 * Don't put *anything* before cpu_init(), SMP booting is too
291 * fragile that we want to limit the things done here to the
292 * most necessary things.
297 * Switch away from the trampoline page-table
299 * Do this before cpu_init() because it needs to access per-cpu
300 * data which may not be mapped in the trampoline page-table.
302 load_cr3(swapper_pg_dir);
311 /* otherwise gcc will move up smp_processor_id before the cpu_init */
314 * Check TSC synchronization with the BP:
316 check_tsc_sync_target();
318 if (nmi_watchdog == NMI_IO_APIC) {
319 disable_8259A_irq(0);
320 enable_NMI_through_LVT0();
324 /* This must be done before setting cpu_online_mask */
325 set_cpu_sibling_map(raw_smp_processor_id());
329 * We need to hold call_lock, so there is no inconsistency
330 * between the time smp_call_function() determines number of
331 * IPI recipients, and the time when the determination is made
332 * for which cpus receive the IPI. Holding this
333 * lock helps us to not include this cpu in a currently in progress
334 * smp_call_function().
336 * We need to hold vector_lock so there the set of online cpus
337 * does not change while we are assigning vectors to cpus. Holding
338 * this lock ensures we don't half assign or remove an irq from a cpu.
342 __setup_vector_irq(smp_processor_id());
343 set_cpu_online(smp_processor_id(), true);
344 unlock_vector_lock();
346 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
348 /* enable local interrupts */
351 x86_cpuinit.setup_percpu_clockev();
357 #ifdef CONFIG_CPUMASK_OFFSTACK
358 /* In this case, llc_shared_map is a pointer to a cpumask. */
359 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
360 const struct cpuinfo_x86 *src)
362 struct cpumask *llc = dst->llc_shared_map;
364 dst->llc_shared_map = llc;
367 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
368 const struct cpuinfo_x86 *src)
372 #endif /* CONFIG_CPUMASK_OFFSTACK */
375 * The bootstrap kernel entry code has set these up. Save them for
379 void __cpuinit smp_store_cpu_info(int id)
381 struct cpuinfo_x86 *c = &cpu_data(id);
383 copy_cpuinfo_x86(c, &boot_cpu_data);
386 identify_secondary_cpu(c);
390 void __cpuinit set_cpu_sibling_map(int cpu)
393 struct cpuinfo_x86 *c = &cpu_data(cpu);
395 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
397 if (smp_num_siblings > 1) {
398 for_each_cpu(i, cpu_sibling_setup_mask) {
399 struct cpuinfo_x86 *o = &cpu_data(i);
401 if (c->phys_proc_id == o->phys_proc_id &&
402 c->cpu_core_id == o->cpu_core_id) {
403 cpumask_set_cpu(i, cpu_sibling_mask(cpu));
404 cpumask_set_cpu(cpu, cpu_sibling_mask(i));
405 cpumask_set_cpu(i, cpu_core_mask(cpu));
406 cpumask_set_cpu(cpu, cpu_core_mask(i));
407 cpumask_set_cpu(i, c->llc_shared_map);
408 cpumask_set_cpu(cpu, o->llc_shared_map);
412 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
415 cpumask_set_cpu(cpu, c->llc_shared_map);
417 if (current_cpu_data.x86_max_cores == 1) {
418 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
423 for_each_cpu(i, cpu_sibling_setup_mask) {
424 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
425 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
426 cpumask_set_cpu(i, c->llc_shared_map);
427 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
429 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
430 cpumask_set_cpu(i, cpu_core_mask(cpu));
431 cpumask_set_cpu(cpu, cpu_core_mask(i));
433 * Does this new cpu bringup a new core?
435 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
437 * for each core in package, increment
438 * the booted_cores for this new cpu
440 if (cpumask_first(cpu_sibling_mask(i)) == i)
443 * increment the core count for all
444 * the other cpus in this package
447 cpu_data(i).booted_cores++;
448 } else if (i != cpu && !c->booted_cores)
449 c->booted_cores = cpu_data(i).booted_cores;
454 /* maps the cpu to the sched domain representing multi-core */
455 const struct cpumask *cpu_coregroup_mask(int cpu)
457 struct cpuinfo_x86 *c = &cpu_data(cpu);
459 * For perf, we return last level cache shared map.
460 * And for power savings, we return cpu_core_map
462 if ((sched_mc_power_savings || sched_smt_power_savings) &&
463 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
464 return cpu_core_mask(cpu);
466 return c->llc_shared_map;
469 static void impress_friends(void)
472 unsigned long bogosum = 0;
474 * Allow the user to impress friends.
476 pr_debug("Before bogomips.\n");
477 for_each_possible_cpu(cpu)
478 if (cpumask_test_cpu(cpu, cpu_callout_mask))
479 bogosum += cpu_data(cpu).loops_per_jiffy;
481 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
484 (bogosum/(5000/HZ))%100);
486 pr_debug("Before bogocount - setting activated=1.\n");
489 void __inquire_remote_apic(int apicid)
491 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
492 char *names[] = { "ID", "VERSION", "SPIV" };
496 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
498 for (i = 0; i < ARRAY_SIZE(regs); i++) {
499 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
504 status = safe_apic_wait_icr_idle();
507 "a previous APIC delivery may have failed\n");
509 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
514 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
515 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
518 case APIC_ICR_RR_VALID:
519 status = apic_read(APIC_RRR);
520 printk(KERN_CONT "%08x\n", status);
523 printk(KERN_CONT "failed\n");
529 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
530 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
531 * won't ... remember to clear down the APIC, etc later.
534 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
536 unsigned long send_status, accept_status = 0;
540 /* Boot on the stack */
541 /* Kick the second */
542 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
548 * Give the other CPU some time to accept the IPI.
551 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
552 maxlvt = lapic_get_maxlvt();
553 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
554 apic_write(APIC_ESR, 0);
555 accept_status = (apic_read(APIC_ESR) & 0xEF);
557 pr_debug("NMI sent.\n");
560 printk(KERN_ERR "APIC never delivered???\n");
562 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
564 return (send_status | accept_status);
568 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
570 unsigned long send_status, accept_status = 0;
571 int maxlvt, num_starts, j;
573 maxlvt = lapic_get_maxlvt();
576 * Be paranoid about clearing APIC errors.
578 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
579 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
580 apic_write(APIC_ESR, 0);
584 pr_debug("Asserting INIT.\n");
587 * Turn INIT on target chip
592 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
595 pr_debug("Waiting for send to finish...\n");
596 send_status = safe_apic_wait_icr_idle();
600 pr_debug("Deasserting INIT.\n");
604 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
606 pr_debug("Waiting for send to finish...\n");
607 send_status = safe_apic_wait_icr_idle();
610 atomic_set(&init_deasserted, 1);
613 * Should we send STARTUP IPIs ?
615 * Determine this based on the APIC version.
616 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
618 if (APIC_INTEGRATED(apic_version[phys_apicid]))
624 * Paravirt / VMI wants a startup IPI hook here to set up the
625 * target processor state.
627 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
628 (unsigned long)stack_start.sp);
631 * Run STARTUP IPI loop.
633 pr_debug("#startup loops: %d.\n", num_starts);
635 for (j = 1; j <= num_starts; j++) {
636 pr_debug("Sending STARTUP #%d.\n", j);
637 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
638 apic_write(APIC_ESR, 0);
640 pr_debug("After apic_write.\n");
647 /* Boot on the stack */
648 /* Kick the second */
649 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
653 * Give the other CPU some time to accept the IPI.
657 pr_debug("Startup point 1.\n");
659 pr_debug("Waiting for send to finish...\n");
660 send_status = safe_apic_wait_icr_idle();
663 * Give the other CPU some time to accept the IPI.
666 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
667 apic_write(APIC_ESR, 0);
668 accept_status = (apic_read(APIC_ESR) & 0xEF);
669 if (send_status || accept_status)
672 pr_debug("After Startup.\n");
675 printk(KERN_ERR "APIC never delivered???\n");
677 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
679 return (send_status | accept_status);
683 struct work_struct work;
684 struct task_struct *idle;
685 struct completion done;
689 static void __cpuinit do_fork_idle(struct work_struct *work)
691 struct create_idle *c_idle =
692 container_of(work, struct create_idle, work);
694 c_idle->idle = fork_idle(c_idle->cpu);
695 complete(&c_idle->done);
699 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
700 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
701 * Returns zero if CPU booted OK, else error code from
702 * ->wakeup_secondary_cpu.
704 static int __cpuinit do_boot_cpu(int apicid, int cpu)
706 unsigned long boot_error = 0;
707 unsigned long start_ip;
709 struct create_idle c_idle = {
711 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
714 INIT_WORK(&c_idle.work, do_fork_idle);
716 alternatives_smp_switch(1);
718 c_idle.idle = get_idle_for_cpu(cpu);
721 * We can't use kernel_thread since we must avoid to
722 * reschedule the child.
725 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
726 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
727 init_idle(c_idle.idle, cpu);
731 if (!keventd_up() || current_is_keventd())
732 c_idle.work.func(&c_idle.work);
734 schedule_work(&c_idle.work);
735 wait_for_completion(&c_idle.done);
738 if (IS_ERR(c_idle.idle)) {
739 printk("failed fork for CPU %d\n", cpu);
740 return PTR_ERR(c_idle.idle);
743 set_idle_for_cpu(cpu, c_idle.idle);
745 per_cpu(current_task, cpu) = c_idle.idle;
747 /* Stack for startup_32 can be just as for start_secondary onwards */
749 initial_page_table = __pa(&trampoline_pg_dir);
751 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
752 initial_gs = per_cpu_offset(cpu);
753 per_cpu(kernel_stack, cpu) =
754 (unsigned long)task_stack_page(c_idle.idle) -
755 KERNEL_STACK_OFFSET + THREAD_SIZE;
757 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
758 initial_code = (unsigned long)start_secondary;
759 stack_start.sp = (void *) c_idle.idle->thread.sp;
761 /* start_ip had better be page-aligned! */
762 start_ip = setup_trampoline();
764 /* So we see what's up */
765 printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n",
766 cpu, apicid, start_ip);
769 * This grunge runs the startup process for
770 * the targeted processor.
773 atomic_set(&init_deasserted, 0);
775 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
777 pr_debug("Setting warm reset code and vector.\n");
779 smpboot_setup_warm_reset_vector(start_ip);
781 * Be paranoid about clearing APIC errors.
783 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
784 apic_write(APIC_ESR, 0);
790 * Kick the secondary CPU. Use the method in the APIC driver
791 * if it's defined - or use an INIT boot APIC message otherwise:
793 if (apic->wakeup_secondary_cpu)
794 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
796 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
800 * allow APs to start initializing.
802 pr_debug("Before Callout %d.\n", cpu);
803 cpumask_set_cpu(cpu, cpu_callout_mask);
804 pr_debug("After Callout %d.\n", cpu);
807 * Wait 5s total for a response
809 for (timeout = 0; timeout < 50000; timeout++) {
810 if (cpumask_test_cpu(cpu, cpu_callin_mask))
811 break; /* It has booted */
815 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
816 /* number CPUs logically, starting from 1 (BSP is 0) */
818 printk(KERN_INFO "CPU%d: ", cpu);
819 print_cpu_info(&cpu_data(cpu));
820 pr_debug("CPU has booted.\n");
823 if (*((volatile unsigned char *)trampoline_base)
825 /* trampoline started but...? */
826 printk(KERN_ERR "Stuck ??\n");
828 /* trampoline code not run */
829 printk(KERN_ERR "Not responding.\n");
830 if (apic->inquire_remote_apic)
831 apic->inquire_remote_apic(apicid);
836 /* Try to put things back the way they were before ... */
837 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
839 /* was set by do_boot_cpu() */
840 cpumask_clear_cpu(cpu, cpu_callout_mask);
842 /* was set by cpu_init() */
843 cpumask_clear_cpu(cpu, cpu_initialized_mask);
845 set_cpu_present(cpu, false);
846 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
849 /* mark "stuck" area as not stuck */
850 *((volatile unsigned long *)trampoline_base) = 0;
852 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
854 * Cleanup possible dangling ends...
856 smpboot_restore_warm_reset_vector();
862 int __cpuinit native_cpu_up(unsigned int cpu)
864 int apicid = apic->cpu_present_to_apicid(cpu);
868 WARN_ON(irqs_disabled());
870 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
872 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
873 !physid_isset(apicid, phys_cpu_present_map)) {
874 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
879 * Already booted CPU?
881 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
882 pr_debug("do_boot_cpu %d Already started\n", cpu);
887 * Save current MTRR state in case it was changed since early boot
888 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
892 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
894 err = do_boot_cpu(apicid, cpu);
897 pr_debug("do_boot_cpu failed %d\n", err);
902 * Check TSC synchronization with the AP (keep irqs disabled
905 local_irq_save(flags);
906 check_tsc_sync_source(cpu);
907 local_irq_restore(flags);
909 while (!cpu_online(cpu)) {
911 touch_nmi_watchdog();
918 * Fall back to non SMP mode after errors.
920 * RED-PEN audit/test this more. I bet there is more state messed up here.
922 static __init void disable_smp(void)
924 init_cpu_present(cpumask_of(0));
925 init_cpu_possible(cpumask_of(0));
926 smpboot_clear_io_apic_irqs();
928 if (smp_found_config)
929 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
931 physid_set_mask_of_physid(0, &phys_cpu_present_map);
932 map_cpu_to_logical_apicid();
933 cpumask_set_cpu(0, cpu_sibling_mask(0));
934 cpumask_set_cpu(0, cpu_core_mask(0));
938 * Various sanity checks.
940 static int __init smp_sanity_check(unsigned max_cpus)
944 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
945 if (def_to_bigsmp && nr_cpu_ids > 8) {
950 "More than 8 CPUs detected - skipping them.\n"
951 "Use CONFIG_X86_BIGSMP.\n");
954 for_each_present_cpu(cpu) {
956 set_cpu_present(cpu, false);
961 for_each_possible_cpu(cpu) {
963 set_cpu_possible(cpu, false);
971 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
973 "weird, boot CPU (#%d) not listed by the BIOS.\n",
974 hard_smp_processor_id());
976 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
980 * If we couldn't find an SMP configuration at boot time,
981 * get out of here now!
983 if (!smp_found_config && !acpi_lapic) {
985 printk(KERN_NOTICE "SMP motherboard not detected.\n");
987 if (APIC_init_uniprocessor())
988 printk(KERN_NOTICE "Local APIC not detected."
989 " Using dummy APIC emulation.\n");
994 * Should not be necessary because the MP table should list the boot
995 * CPU too, but we do it for the sake of robustness anyway.
997 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
999 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1000 boot_cpu_physical_apicid);
1001 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1006 * If we couldn't find a local APIC, then get out of here now!
1008 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1010 if (!disable_apic) {
1011 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1012 boot_cpu_physical_apicid);
1013 pr_err("... forcing use of dummy APIC emulation."
1014 "(tell your hw vendor)\n");
1016 smpboot_clear_io_apic();
1017 arch_disable_smp_support();
1021 verify_local_APIC();
1024 * If SMP should be disabled, then really disable it!
1027 printk(KERN_INFO "SMP mode deactivated.\n");
1028 smpboot_clear_io_apic();
1030 localise_nmi_watchdog();
1034 end_local_APIC_setup();
1041 static void __init smp_cpu_index_default(void)
1044 struct cpuinfo_x86 *c;
1046 for_each_possible_cpu(i) {
1048 /* mark all to hotplug */
1049 c->cpu_index = nr_cpu_ids;
1054 * Prepare for SMP bootup. The MP table or ACPI has been read
1055 * earlier. Just do some sanity checking here and enable APIC mode.
1057 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1062 smp_cpu_index_default();
1063 current_cpu_data = boot_cpu_data;
1064 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1067 * Setup boot CPU information
1069 smp_store_cpu_info(0); /* Final full version of the data */
1070 #ifdef CONFIG_X86_32
1071 boot_cpu_logical_apicid = logical_smp_processor_id();
1073 current_thread_info()->cpu = 0; /* needed? */
1074 for_each_possible_cpu(i) {
1075 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1076 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1077 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1079 set_cpu_sibling_map(0);
1082 default_setup_apic_routing();
1084 if (smp_sanity_check(max_cpus) < 0) {
1085 printk(KERN_INFO "SMP disabled\n");
1091 if (read_apic_id() != boot_cpu_physical_apicid) {
1092 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1093 read_apic_id(), boot_cpu_physical_apicid);
1094 /* Or can we switch back to PIC here? */
1101 * Switch from PIC to APIC mode.
1106 * Enable IO APIC before setting up error vector
1108 if (!skip_ioapic_setup && nr_ioapics)
1111 end_local_APIC_setup();
1113 map_cpu_to_logical_apicid();
1115 if (apic->setup_portio_remap)
1116 apic->setup_portio_remap();
1118 smpboot_setup_io_apic();
1120 * Set up local APIC timer on boot CPU.
1123 printk(KERN_INFO "CPU%d: ", 0);
1124 print_cpu_info(&cpu_data(0));
1125 x86_init.timers.setup_percpu_clockev();
1130 set_mtrr_aps_delayed_init();
1135 void arch_enable_nonboot_cpus_begin(void)
1137 set_mtrr_aps_delayed_init();
1140 void arch_enable_nonboot_cpus_end(void)
1146 * Early setup to make printk work.
1148 void __init native_smp_prepare_boot_cpu(void)
1150 int me = smp_processor_id();
1151 switch_to_new_gdt(me);
1152 /* already set me in cpu_online_mask in boot_cpu_init() */
1153 cpumask_set_cpu(me, cpu_callout_mask);
1154 per_cpu(cpu_state, me) = CPU_ONLINE;
1157 void __init native_smp_cpus_done(unsigned int max_cpus)
1159 pr_debug("Boot done.\n");
1162 #ifdef CONFIG_X86_IO_APIC
1163 setup_ioapic_dest();
1165 check_nmi_watchdog();
1169 static int __initdata setup_possible_cpus = -1;
1170 static int __init _setup_possible_cpus(char *str)
1172 get_option(&str, &setup_possible_cpus);
1175 early_param("possible_cpus", _setup_possible_cpus);
1179 * cpu_possible_mask should be static, it cannot change as cpu's
1180 * are onlined, or offlined. The reason is per-cpu data-structures
1181 * are allocated by some modules at init time, and dont expect to
1182 * do this dynamically on cpu arrival/departure.
1183 * cpu_present_mask on the other hand can change dynamically.
1184 * In case when cpu_hotplug is not compiled, then we resort to current
1185 * behaviour, which is cpu_possible == cpu_present.
1188 * Three ways to find out the number of additional hotplug CPUs:
1189 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1190 * - The user can overwrite it with possible_cpus=NUM
1191 * - Otherwise don't reserve additional CPUs.
1192 * We do this because additional CPUs waste a lot of memory.
1195 __init void prefill_possible_map(void)
1199 /* no processor from mptable or madt */
1200 if (!num_processors)
1203 if (setup_possible_cpus == -1)
1204 possible = num_processors + disabled_cpus;
1206 possible = setup_possible_cpus;
1208 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1210 if (possible > CONFIG_NR_CPUS) {
1212 "%d Processors exceeds NR_CPUS limit of %d\n",
1213 possible, CONFIG_NR_CPUS);
1214 possible = CONFIG_NR_CPUS;
1217 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1218 possible, max_t(int, possible - num_processors, 0));
1220 for (i = 0; i < possible; i++)
1221 set_cpu_possible(i, true);
1223 nr_cpu_ids = possible;
1226 #ifdef CONFIG_HOTPLUG_CPU
1228 static void remove_siblinginfo(int cpu)
1231 struct cpuinfo_x86 *c = &cpu_data(cpu);
1233 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1234 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1236 * last thread sibling in this cpu core going down
1238 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1239 cpu_data(sibling).booted_cores--;
1242 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1243 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1244 cpumask_clear(cpu_sibling_mask(cpu));
1245 cpumask_clear(cpu_core_mask(cpu));
1246 c->phys_proc_id = 0;
1248 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1251 static void __ref remove_cpu_from_maps(int cpu)
1253 set_cpu_online(cpu, false);
1254 cpumask_clear_cpu(cpu, cpu_callout_mask);
1255 cpumask_clear_cpu(cpu, cpu_callin_mask);
1256 /* was set by cpu_init() */
1257 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1258 numa_remove_cpu(cpu);
1261 void cpu_disable_common(void)
1263 int cpu = smp_processor_id();
1266 * Allow any queued timer interrupts to get serviced
1267 * This is only a temporary solution until we cleanup
1268 * fixup_irqs as we do for IA64.
1273 local_irq_disable();
1274 remove_siblinginfo(cpu);
1276 /* It's now safe to remove this processor from the online map */
1278 remove_cpu_from_maps(cpu);
1279 unlock_vector_lock();
1283 int native_cpu_disable(void)
1285 int cpu = smp_processor_id();
1288 * Perhaps use cpufreq to drop frequency, but that could go
1289 * into generic code.
1291 * We won't take down the boot processor on i386 due to some
1292 * interrupts only being able to be serviced by the BSP.
1293 * Especially so if we're not using an IOAPIC -zwane
1298 if (nmi_watchdog == NMI_LOCAL_APIC)
1299 stop_apic_nmi_watchdog(NULL);
1302 cpu_disable_common();
1306 void native_cpu_die(unsigned int cpu)
1308 /* We don't do anything here: idle task is faking death itself. */
1311 for (i = 0; i < 10; i++) {
1312 /* They ack this in play_dead by setting CPU_DEAD */
1313 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1314 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1315 if (1 == num_online_cpus())
1316 alternatives_smp_switch(0);
1321 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1324 void play_dead_common(void)
1327 reset_lazy_tlbstate();
1328 irq_ctx_exit(raw_smp_processor_id());
1329 c1e_remove_cpu(raw_smp_processor_id());
1333 __get_cpu_var(cpu_state) = CPU_DEAD;
1336 * With physical CPU hotplug, we should halt the cpu
1338 local_irq_disable();
1341 #define MWAIT_SUBSTATE_MASK 0xf
1342 #define MWAIT_SUBSTATE_SIZE 4
1344 #define CPUID_MWAIT_LEAF 5
1345 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
1348 * We need to flush the caches before going to sleep, lest we have
1349 * dirty data in our caches when we come back up.
1351 static inline void mwait_play_dead(void)
1353 unsigned int eax, ebx, ecx, edx;
1354 unsigned int highest_cstate = 0;
1355 unsigned int highest_subcstate = 0;
1359 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT))
1361 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH))
1363 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1366 eax = CPUID_MWAIT_LEAF;
1368 native_cpuid(&eax, &ebx, &ecx, &edx);
1371 * eax will be 0 if EDX enumeration is not valid.
1372 * Initialized below to cstate, sub_cstate value when EDX is valid.
1374 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1377 edx >>= MWAIT_SUBSTATE_SIZE;
1378 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1379 if (edx & MWAIT_SUBSTATE_MASK) {
1381 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1384 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1385 (highest_subcstate - 1);
1389 * This should be a memory location in a cache line which is
1390 * unlikely to be touched by other processors. The actual
1391 * content is immaterial as it is not actually modified in any way.
1393 mwait_ptr = ¤t_thread_info()->flags;
1399 * The CLFLUSH is a workaround for erratum AAI65 for
1400 * the Xeon 7400 series. It's not clear it is actually
1401 * needed, but it should be harmless in either case.
1402 * The WBINVD is insufficient due to the spurious-wakeup
1403 * case where we return around the loop.
1406 __monitor(mwait_ptr, 0, 0);
1412 static inline void hlt_play_dead(void)
1414 if (current_cpu_data.x86 >= 4)
1422 void native_play_dead(void)
1425 tboot_shutdown(TB_SHUTDOWN_WFS);
1427 mwait_play_dead(); /* Only returns on failure */
1431 #else /* ... !CONFIG_HOTPLUG_CPU */
1432 int native_cpu_disable(void)
1437 void native_cpu_die(unsigned int cpu)
1439 /* We said "no" in __cpu_disable */
1443 void native_play_dead(void)