4 * @remark Copyright 2002-2009 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
9 * @author Barry Kasindorf <barry.kasindorf@amd.com>
10 * @author Jason Yeh <jason.yeh@amd.com>
11 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/sysdev.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
27 #include "op_counter.h"
28 #include "op_x86_model.h"
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
34 /* 0 == registered but off, 1 == registered and on */
35 static int nmi_enabled = 0;
37 struct op_counter_config counter_config[OP_MAX_COUNTER];
39 /* common functions */
41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
42 struct op_counter_config *counter_config)
45 u16 event = (u16)counter_config->event;
47 val |= ARCH_PERFMON_EVENTSEL_INT;
48 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
49 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
50 val |= (counter_config->unit_mask & 0xFF) << 8;
51 event &= model->event_mask ? model->event_mask : 0xFF;
53 val |= (event & 0x0F00) << 24;
59 static int profile_exceptions_notify(struct notifier_block *self,
60 unsigned long val, void *data)
62 struct die_args *args = (struct die_args *)data;
63 int ret = NOTIFY_DONE;
64 int cpu = smp_processor_id();
69 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
80 struct op_msr *counters = msrs->counters;
81 struct op_msr *controls = msrs->controls;
84 for (i = 0; i < model->num_counters; ++i) {
86 rdmsrl(counters[i].addr, counters[i].saved);
89 for (i = 0; i < model->num_controls; ++i) {
91 rdmsrl(controls[i].addr, controls[i].saved);
95 static void nmi_cpu_start(void *dummy)
97 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
104 static int nmi_start(void)
106 on_each_cpu(nmi_cpu_start, NULL, 1);
110 static void nmi_cpu_stop(void *dummy)
112 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
119 static void nmi_stop(void)
121 on_each_cpu(nmi_cpu_stop, NULL, 1);
124 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
126 static DEFINE_PER_CPU(int, switch_index);
128 static inline int has_mux(void)
130 return !!model->switch_ctrl;
133 inline int op_x86_phys_to_virt(int phys)
135 return __get_cpu_var(switch_index) + phys;
138 inline int op_x86_virt_to_phys(int virt)
140 return virt % model->num_counters;
143 static void nmi_shutdown_mux(void)
150 for_each_possible_cpu(i) {
151 kfree(per_cpu(cpu_msrs, i).multiplex);
152 per_cpu(cpu_msrs, i).multiplex = NULL;
153 per_cpu(switch_index, i) = 0;
157 static int nmi_setup_mux(void)
159 size_t multiplex_size =
160 sizeof(struct op_msr) * model->num_virt_counters;
166 for_each_possible_cpu(i) {
167 per_cpu(cpu_msrs, i).multiplex =
168 kzalloc(multiplex_size, GFP_KERNEL);
169 if (!per_cpu(cpu_msrs, i).multiplex)
176 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
179 struct op_msr *multiplex = msrs->multiplex;
184 for (i = 0; i < model->num_virt_counters; ++i) {
185 if (counter_config[i].enabled) {
186 multiplex[i].saved = -(u64)counter_config[i].count;
188 multiplex[i].saved = 0;
192 per_cpu(switch_index, cpu) = 0;
195 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
197 struct op_msr *counters = msrs->counters;
198 struct op_msr *multiplex = msrs->multiplex;
201 for (i = 0; i < model->num_counters; ++i) {
202 int virt = op_x86_phys_to_virt(i);
203 if (counters[i].addr)
204 rdmsrl(counters[i].addr, multiplex[virt].saved);
208 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
210 struct op_msr *counters = msrs->counters;
211 struct op_msr *multiplex = msrs->multiplex;
214 for (i = 0; i < model->num_counters; ++i) {
215 int virt = op_x86_phys_to_virt(i);
216 if (counters[i].addr)
217 wrmsrl(counters[i].addr, multiplex[virt].saved);
221 static void nmi_cpu_switch(void *dummy)
223 int cpu = smp_processor_id();
224 int si = per_cpu(switch_index, cpu);
225 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
228 nmi_cpu_save_mpx_registers(msrs);
230 /* move to next set */
231 si += model->num_counters;
232 if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
233 per_cpu(switch_index, cpu) = 0;
235 per_cpu(switch_index, cpu) = si;
237 model->switch_ctrl(model, msrs);
238 nmi_cpu_restore_mpx_registers(msrs);
245 * Quick check to see if multiplexing is necessary.
246 * The check should be sufficient since counters are used
249 static int nmi_multiplex_on(void)
251 return counter_config[model->num_counters].count ? 0 : -EINVAL;
254 static int nmi_switch_event(void)
257 return -ENOSYS; /* not implemented */
258 if (nmi_multiplex_on() < 0)
259 return -EINVAL; /* not necessary */
261 on_each_cpu(nmi_cpu_switch, NULL, 1);
266 static inline void mux_init(struct oprofile_operations *ops)
269 ops->switch_events = nmi_switch_event;
272 static void mux_clone(int cpu)
277 memcpy(per_cpu(cpu_msrs, cpu).multiplex,
278 per_cpu(cpu_msrs, 0).multiplex,
279 sizeof(struct op_msr) * model->num_virt_counters);
284 inline int op_x86_phys_to_virt(int phys) { return phys; }
285 inline int op_x86_virt_to_phys(int virt) { return virt; }
286 static inline void nmi_shutdown_mux(void) { }
287 static inline int nmi_setup_mux(void) { return 1; }
289 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
290 static inline void mux_init(struct oprofile_operations *ops) { }
291 static void mux_clone(int cpu) { }
295 static void free_msrs(void)
298 for_each_possible_cpu(i) {
299 kfree(per_cpu(cpu_msrs, i).counters);
300 per_cpu(cpu_msrs, i).counters = NULL;
301 kfree(per_cpu(cpu_msrs, i).controls);
302 per_cpu(cpu_msrs, i).controls = NULL;
306 static int allocate_msrs(void)
308 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
309 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
312 for_each_possible_cpu(i) {
313 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
315 if (!per_cpu(cpu_msrs, i).counters)
317 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
319 if (!per_cpu(cpu_msrs, i).controls)
326 static void nmi_cpu_setup(void *dummy)
328 int cpu = smp_processor_id();
329 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
330 nmi_cpu_save_registers(msrs);
331 spin_lock(&oprofilefs_lock);
332 model->setup_ctrs(model, msrs);
333 nmi_cpu_setup_mux(cpu, msrs);
334 spin_unlock(&oprofilefs_lock);
335 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
336 apic_write(APIC_LVTPC, APIC_DM_NMI);
339 static struct notifier_block profile_exceptions_nb = {
340 .notifier_call = profile_exceptions_notify,
345 static int nmi_setup(void)
350 if (!allocate_msrs())
352 else if (!nmi_setup_mux())
355 err = register_die_notifier(&profile_exceptions_nb);
363 /* We need to serialize save and setup for HT because the subset
364 * of msrs are distinct for save and setup operations
367 /* Assume saved/restored counters are the same on all CPUs */
368 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
369 for_each_possible_cpu(cpu) {
373 memcpy(per_cpu(cpu_msrs, cpu).counters,
374 per_cpu(cpu_msrs, 0).counters,
375 sizeof(struct op_msr) * model->num_counters);
377 memcpy(per_cpu(cpu_msrs, cpu).controls,
378 per_cpu(cpu_msrs, 0).controls,
379 sizeof(struct op_msr) * model->num_controls);
383 on_each_cpu(nmi_cpu_setup, NULL, 1);
388 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
390 struct op_msr *counters = msrs->counters;
391 struct op_msr *controls = msrs->controls;
394 for (i = 0; i < model->num_controls; ++i) {
395 if (controls[i].addr)
396 wrmsrl(controls[i].addr, controls[i].saved);
399 for (i = 0; i < model->num_counters; ++i) {
400 if (counters[i].addr)
401 wrmsrl(counters[i].addr, counters[i].saved);
405 static void nmi_cpu_shutdown(void *dummy)
408 int cpu = smp_processor_id();
409 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
411 /* restoring APIC_LVTPC can trigger an apic error because the delivery
412 * mode and vector nr combination can be illegal. That's by design: on
413 * power on apic lvt contain a zero vector nr which are legal only for
414 * NMI delivery mode. So inhibit apic err before restoring lvtpc
416 v = apic_read(APIC_LVTERR);
417 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
418 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
419 apic_write(APIC_LVTERR, v);
420 nmi_cpu_restore_registers(msrs);
423 static void nmi_shutdown(void)
425 struct op_msrs *msrs;
428 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
429 unregister_die_notifier(&profile_exceptions_nb);
431 msrs = &get_cpu_var(cpu_msrs);
432 model->shutdown(msrs);
434 put_cpu_var(cpu_msrs);
437 static int nmi_create_files(struct super_block *sb, struct dentry *root)
441 for (i = 0; i < model->num_virt_counters; ++i) {
445 /* quick little hack to _not_ expose a counter if it is not
446 * available for use. This should protect userspace app.
447 * NOTE: assumes 1:1 mapping here (that counters are organized
448 * sequentially in their struct assignment).
450 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
453 snprintf(buf, sizeof(buf), "%d", i);
454 dir = oprofilefs_mkdir(sb, root, buf);
455 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
456 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
457 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
458 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
459 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
460 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
467 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
470 int cpu = (unsigned long)data;
472 case CPU_DOWN_FAILED:
474 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
476 case CPU_DOWN_PREPARE:
477 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
483 static struct notifier_block oprofile_cpu_nb = {
484 .notifier_call = oprofile_cpu_notifier
490 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
492 /* Only one CPU left, just stop that one */
493 if (nmi_enabled == 1)
498 static int nmi_resume(struct sys_device *dev)
500 if (nmi_enabled == 1)
505 static struct sysdev_class oprofile_sysclass = {
507 .resume = nmi_resume,
508 .suspend = nmi_suspend,
511 static struct sys_device device_oprofile = {
513 .cls = &oprofile_sysclass,
516 static int __init init_sysfs(void)
520 error = sysdev_class_register(&oprofile_sysclass);
524 error = sysdev_register(&device_oprofile);
526 sysdev_class_unregister(&oprofile_sysclass);
531 static void exit_sysfs(void)
533 sysdev_unregister(&device_oprofile);
534 sysdev_class_unregister(&oprofile_sysclass);
539 static inline int init_sysfs(void) { return 0; }
540 static inline void exit_sysfs(void) { }
542 #endif /* CONFIG_PM */
544 static int __init p4_init(char **cpu_type)
546 __u8 cpu_model = boot_cpu_data.x86_model;
548 if (cpu_model > 6 || cpu_model == 5)
552 *cpu_type = "i386/p4";
556 switch (smp_num_siblings) {
558 *cpu_type = "i386/p4";
563 *cpu_type = "i386/p4-ht";
564 model = &op_p4_ht2_spec;
569 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
570 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
574 static int force_arch_perfmon;
575 static int force_cpu_type(const char *str, struct kernel_param *kp)
577 if (!strcmp(str, "arch_perfmon")) {
578 force_arch_perfmon = 1;
579 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
584 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
586 static int __init ppro_init(char **cpu_type)
588 __u8 cpu_model = boot_cpu_data.x86_model;
589 struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
591 if (force_arch_perfmon && cpu_has_arch_perfmon)
595 * Documentation on identifying Intel processors by CPU family
596 * and model can be found in the Intel Software Developer's
599 * http://www.intel.com/products/processor/manuals/
601 * As of May 2010 the documentation for this was in the:
602 * "Intel 64 and IA-32 Architectures Software Developer's
603 * Manual Volume 3B: System Programming Guide", "Table B-1
604 * CPUID Signature Values of DisplayFamily_DisplayModel".
608 *cpu_type = "i386/ppro";
611 *cpu_type = "i386/pii";
615 *cpu_type = "i386/piii";
619 *cpu_type = "i386/p6_mobile";
622 *cpu_type = "i386/core";
628 *cpu_type = "i386/core_2";
633 spec = &op_arch_perfmon_spec;
634 *cpu_type = "i386/core_i7";
637 *cpu_type = "i386/atom";
648 /* in order to get sysfs right */
649 static int using_nmi;
651 int __init op_nmi_init(struct oprofile_operations *ops)
653 __u8 vendor = boot_cpu_data.x86_vendor;
654 __u8 family = boot_cpu_data.x86;
655 char *cpu_type = NULL;
665 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
669 cpu_type = "i386/athlon";
673 * Actually it could be i386/hammer too, but
674 * give user space an consistent name.
676 cpu_type = "x86-64/hammer";
679 cpu_type = "x86-64/family10";
682 cpu_type = "x86-64/family11h";
687 model = &op_amd_spec;
690 case X86_VENDOR_INTEL:
697 /* A P6-class processor */
699 ppro_init(&cpu_type);
709 if (!cpu_has_arch_perfmon)
712 /* use arch perfmon as fallback */
713 cpu_type = "i386/arch_perfmon";
714 model = &op_arch_perfmon_spec;
722 register_cpu_notifier(&oprofile_cpu_nb);
724 /* default values, can be overwritten by model */
725 ops->create_files = nmi_create_files;
726 ops->setup = nmi_setup;
727 ops->shutdown = nmi_shutdown;
728 ops->start = nmi_start;
729 ops->stop = nmi_stop;
730 ops->cpu_type = cpu_type;
733 ret = model->init(ops);
737 if (!model->num_virt_counters)
738 model->num_virt_counters = model->num_counters;
747 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
751 void op_nmi_exit(void)
757 unregister_cpu_notifier(&oprofile_cpu_nb);