drivers/clk/microchip/clk-pic32mzda.c

   1 /*
   2  * Purna Chandra Mandal,<purna.mandal@microchip.com>
   3  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   4  *
   5  * This program is free software; you can distribute it and/or modify it
   6  * under the terms of the GNU General Public License (Version 2) as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  */
  14 #include <dt-bindings/clock/microchip,pic32-clock.h>
  15 #include <linux/clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/module.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <asm/traps.h>
  23
  24 #include "clk-core.h"
  25
  26 /* FRC Postscaler */
  27 #define OSC_FRCDIV_MASK         0x07
  28 #define OSC_FRCDIV_SHIFT        24
  29
  30 /* SPLL fields */
  31 #define PLL_ICLK_MASK           0x01
  32 #define PLL_ICLK_SHIFT          7
  33
  34 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags)    \
  35         {                                                       \
  36                 .ctrl_reg = (__reg),                            \
  37                 .init_data = {                                  \
  38                         .name = (__clk_name),                   \
  39                         .parent_names = (const char *[]) {      \
  40                                 "sys_clk"                       \
  41                         },                                      \
  42                         .num_parents = 1,                       \
  43                         .ops = &pic32_pbclk_ops,                \
  44                         .flags = (__flags),                     \
  45                 },                                              \
  46         }
  47
  48 #define DECLARE_REFO_CLOCK(__clkid, __reg)                              \
  49         {                                                               \
  50                 .ctrl_reg = (__reg),                                    \
  51                 .init_data = {                                          \
  52                         .name = "refo" #__clkid "_clk",                 \
  53                         .parent_names = (const char *[]) {              \
  54                                 "sys_clk", "pb1_clk", "posc_clk",       \
  55                                 "frc_clk", "lprc_clk", "sosc_clk",      \
  56                                 "sys_pll", "refi" #__clkid "_clk",      \
  57                                 "bfrc_clk",                             \
  58                         },                                              \
  59                         .num_parents = 9,                               \
  60                         .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
  61                         .ops = &pic32_roclk_ops,                        \
  62                 },                                                      \
  63                 .parent_map = (const u32[]) {                           \
  64                         0, 1, 2, 3, 4, 5, 7, 8, 9                       \
  65                 },                                                      \
  66         }
  67
  68 static const struct pic32_ref_osc_data ref_clks[] = {
  69         DECLARE_REFO_CLOCK(1, 0x80),
  70         DECLARE_REFO_CLOCK(2, 0xa0),
  71         DECLARE_REFO_CLOCK(3, 0xc0),
  72         DECLARE_REFO_CLOCK(4, 0xe0),
  73         DECLARE_REFO_CLOCK(5, 0x100),
  74 };
  75
  76 static const struct pic32_periph_clk_data periph_clocks[] = {
  77         DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
  78         DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
  79         DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
  80         DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
  81         DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
  82         DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
  83         DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
  84 };
  85
  86 static const struct pic32_sys_clk_data sys_mux_clk = {
  87         .slew_reg = 0x1c0,
  88         .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
  89         .init_data = {
  90                 .name = "sys_clk",
  91                 .parent_names = (const char *[]) {
  92                         "frcdiv_clk", "sys_pll", "posc_clk",
  93                         "sosc_clk", "lprc_clk", "frcdiv_clk",
  94                 },
  95                 .num_parents = 6,
  96                 .ops = &pic32_sclk_ops,
  97         },
  98         .parent_map = (const u32[]) {
  99                 0, 1, 2, 4, 5, 7,
 100         },
 101 };
 102
 103 static const struct pic32_sys_pll_data sys_pll = {
 104         .ctrl_reg = 0x020,
 105         .status_reg = 0x1d0,
 106         .lock_mask = BIT(7),
 107         .init_data = {
 108                 .name = "sys_pll",
 109                 .parent_names = (const char *[]) {
 110                         "spll_mux_clk"
 111                 },
 112                 .num_parents = 1,
 113                 .ops = &pic32_spll_ops,
 114         },
 115 };
 116
 117 static const struct pic32_sec_osc_data sosc_clk = {
 118         .status_reg = 0x1d0,
 119         .enable_mask = BIT(1),
 120         .status_mask = BIT(4),
 121         .init_data = {
 122                 .name = "sosc_clk",
 123                 .parent_names = NULL,
 124                 .ops = &pic32_sosc_ops,
 125         },
 126 };
 127
 128 static int pic32mzda_critical_clks[] = {
 129         PB2CLK, PB7CLK
 130 };
 131
 132 /* PIC32MZDA clock data */
 133 struct pic32mzda_clk_data {
 134         struct clk *clks[MAXCLKS];
 135         struct pic32_clk_common core;
 136         struct clk_onecell_data onecell_data;
 137         struct notifier_block failsafe_notifier;
 138 };
 139
 140 static int pic32_fscm_nmi(struct notifier_block *nb,
 141                           unsigned long action, void *data)
 142 {
 143         struct pic32mzda_clk_data *cd;
 144
 145         cd  = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
 146
 147         /* SYSCLK is now running from BFRCCLK. Report clock failure. */
 148         if (readl(cd->core.iobase) & BIT(2))
 149                 pr_alert("pic32-clk: FSCM detected clk failure.\n");
 150
 151         /* TODO: detect reason of failure and recover accordingly */
 152
 153         return NOTIFY_OK;
 154 }
 155
 156 static int pic32mzda_clk_probe(struct platform_device *pdev)
 157 {
 158         const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
 159         struct device_node *np = pdev->dev.of_node;
 160         struct pic32mzda_clk_data *cd;
 161         struct pic32_clk_common *core;
 162         struct clk *pll_mux_clk, *clk;
 163         struct clk **clks;
 164         int nr_clks, i, ret;
 165
 166         cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
 167         if (!cd)
 168                 return -ENOMEM;
 169
 170         core = &cd->core;
 171         core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
 172         if (IS_ERR(core->iobase)) {
 173                 dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
 174                 return PTR_ERR(core->iobase);
 175         }
 176
 177         spin_lock_init(&core->reg_lock);
 178         core->dev = &pdev->dev;
 179         clks = &cd->clks[0];
 180
 181         /* register fixed rate clocks */
 182         clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
 183                                                 0, 24000000);
 184         clks[FRCCLK] =  clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
 185                                                 0, 8000000);
 186         clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
 187                                                 0, 8000000);
 188         clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
 189                                                 0, 32000);
 190         clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
 191                                                 0, 24000000);
 192         /* fixed rate (optional) clock */
 193         if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
 194                 pr_info("pic32-clk: dt requests SOSC.\n");
 195                 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
 196         }
 197         /* divider clock */
 198         clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
 199                                                "frc_clk", 0,
 200                                                core->iobase,
 201                                                OSC_FRCDIV_SHIFT,
 202                                                OSC_FRCDIV_MASK,
 203                                                CLK_DIVIDER_POWER_OF_TWO,
 204                                                &core->reg_lock);
 205         /* PLL ICLK mux */
 206         pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
 207                                        pll_mux_parents, 2, 0,
 208                                        core->iobase + 0x020,
 209                                        PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
 210         if (IS_ERR(pll_mux_clk))
 211                 pr_err("spll_mux_clk: clk register failed\n");
 212
 213         /* PLL */
 214         clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
 215         /* SYSTEM clock */
 216         clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
 217         /* Peripheral bus clocks */
 218         for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
 219                 clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
 220                                                           core);
 221         /* Reference oscillator clock */
 222         for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
 223                 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
 224
 225         /* register clkdev */
 226         for (i = 0; i < MAXCLKS; i++) {
 227                 if (IS_ERR(clks[i]))
 228                         continue;
 229                 clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
 230         }
 231
 232         /* register clock provider */
 233         cd->onecell_data.clks = clks;
 234         cd->onecell_data.clk_num = MAXCLKS;
 235         ret = of_clk_add_provider(np, of_clk_src_onecell_get,
 236                                   &cd->onecell_data);
 237         if (ret)
 238                 return ret;
 239
 240         /* force enable critical clocks */
 241         for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
 242                 clk = clks[pic32mzda_critical_clks[i]];
 243                 if (clk_prepare_enable(clk))
 244                         dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
 245                                 __clk_get_name(clk));
 246         }
 247
 248         /* register NMI for failsafe clock monitor */
 249         cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
 250         return register_nmi_notifier(&cd->failsafe_notifier);
 251 }
 252
 253 static const struct of_device_id pic32mzda_clk_match_table[] = {
 254         { .compatible = "microchip,pic32mzda-clk", },
 255         { }
 256 };
 257 MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
 258
 259 static struct platform_driver pic32mzda_clk_driver = {
 260         .probe          = pic32mzda_clk_probe,
 261         .driver         = {
 262                 .name   = "clk-pic32mzda",
 263                 .of_match_table = pic32mzda_clk_match_table,
 264         },
 265 };
 266
 267 static int __init microchip_pic32mzda_clk_init(void)
 268 {
 269         return platform_driver_register(&pic32mzda_clk_driver);
 270 }
 271 core_initcall(microchip_pic32mzda_clk_init);
 272
 273 MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
 274 MODULE_LICENSE("GPL v2");
 275 MODULE_ALIAS("platform:clk-pic32mzda");