2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
20 struct mv_cesa_ahash_dma_iter {
21 struct mv_cesa_dma_iter base;
22 struct mv_cesa_sg_dma_iter src;
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
27 struct ahash_request *req)
29 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
30 unsigned int len = req->nbytes + creq->cache_ptr;
33 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
35 mv_cesa_req_dma_iter_init(&iter->base, len);
36 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
37 iter->src.op_offset = creq->cache_ptr;
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
43 iter->src.op_offset = 0;
45 return mv_cesa_req_dma_iter_next_op(&iter->base);
49 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
51 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
60 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
65 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
69 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
75 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
83 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
88 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
93 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
95 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
97 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
100 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
102 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
104 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
105 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
106 mv_cesa_dma_cleanup(&creq->req.dma.base);
109 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
111 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
113 if (creq->req.base.type == CESA_DMA_REQ)
114 mv_cesa_ahash_dma_cleanup(req);
117 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
119 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
121 if (creq->req.base.type == CESA_DMA_REQ)
122 mv_cesa_ahash_dma_last_cleanup(req);
125 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
127 unsigned int index, padlen;
129 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
130 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
135 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
137 unsigned int index, padlen;
140 /* Pad out to 56 mod 64 */
141 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
142 padlen = mv_cesa_ahash_pad_len(creq);
143 memset(buf + 1, 0, padlen - 1);
146 __le64 bits = cpu_to_le64(creq->len << 3);
147 memcpy(buf + padlen, &bits, sizeof(bits));
149 __be64 bits = cpu_to_be64(creq->len << 3);
150 memcpy(buf + padlen, &bits, sizeof(bits));
156 static void mv_cesa_ahash_std_step(struct ahash_request *req)
158 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
159 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
160 struct mv_cesa_engine *engine = sreq->base.engine;
161 struct mv_cesa_op_ctx *op;
162 unsigned int new_cache_ptr = 0;
167 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
168 creq->cache, creq->cache_ptr);
170 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
171 CESA_SA_SRAM_PAYLOAD_SIZE);
173 if (!creq->last_req) {
174 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
175 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
178 if (len - creq->cache_ptr)
179 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
181 CESA_SA_DATA_SRAM_OFFSET +
183 len - creq->cache_ptr,
188 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
190 if (creq->last_req && sreq->offset == req->nbytes &&
191 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
192 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
193 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
194 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
195 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
198 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
199 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
201 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
202 mv_cesa_set_mac_op_total_len(op, creq->len);
204 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
206 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
207 len &= CESA_HASH_BLOCK_SIZE_MSK;
208 new_cache_ptr = 64 - trailerlen;
209 memcpy_fromio(creq->cache,
211 CESA_SA_DATA_SRAM_OFFSET + len,
214 len += mv_cesa_ahash_pad_req(creq,
216 CESA_SA_DATA_SRAM_OFFSET);
219 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
220 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
222 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
226 mv_cesa_set_mac_op_frag_len(op, len);
227 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
229 /* FIXME: only update enc_len field */
230 memcpy_toio(engine->sram, op, sizeof(*op));
232 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
233 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
234 CESA_SA_DESC_CFG_FRAG_MSK);
236 creq->cache_ptr = new_cache_ptr;
238 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
239 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
240 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
243 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
245 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
246 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
248 if (sreq->offset < (req->nbytes - creq->cache_ptr))
254 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
256 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
257 struct mv_cesa_tdma_req *dreq = &creq->req.dma.base;
259 mv_cesa_dma_prepare(dreq, dreq->base.engine);
262 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
264 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
265 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
266 struct mv_cesa_engine *engine = sreq->base.engine;
269 mv_cesa_adjust_op(engine, &creq->op_tmpl);
270 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
273 static void mv_cesa_ahash_step(struct crypto_async_request *req)
275 struct ahash_request *ahashreq = ahash_request_cast(req);
276 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
278 if (creq->req.base.type == CESA_DMA_REQ)
279 mv_cesa_dma_step(&creq->req.dma.base);
281 mv_cesa_ahash_std_step(ahashreq);
284 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
286 struct ahash_request *ahashreq = ahash_request_cast(req);
287 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
288 struct mv_cesa_engine *engine = creq->req.base.engine;
289 unsigned int digsize;
292 if (creq->req.base.type == CESA_DMA_REQ)
293 ret = mv_cesa_dma_process(&creq->req.dma.base, status);
295 ret = mv_cesa_ahash_std_process(ahashreq, status);
297 if (ret == -EINPROGRESS)
300 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
301 for (i = 0; i < digsize / 4; i++)
302 creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));
305 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
308 ahashreq->nbytes - creq->cache_ptr);
310 if (creq->last_req) {
312 * Hardware's MD5 digest is in little endian format, but
313 * SHA in big endian format
316 __le32 *result = (void *)ahashreq->result;
318 for (i = 0; i < digsize / 4; i++)
319 result[i] = cpu_to_le32(creq->state[i]);
321 __be32 *result = (void *)ahashreq->result;
323 for (i = 0; i < digsize / 4; i++)
324 result[i] = cpu_to_be32(creq->state[i]);
331 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
332 struct mv_cesa_engine *engine)
334 struct ahash_request *ahashreq = ahash_request_cast(req);
335 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
336 unsigned int digsize;
339 creq->req.base.engine = engine;
341 if (creq->req.base.type == CESA_DMA_REQ)
342 mv_cesa_ahash_dma_prepare(ahashreq);
344 mv_cesa_ahash_std_prepare(ahashreq);
346 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
347 for (i = 0; i < digsize / 4; i++)
348 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
351 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
353 struct ahash_request *ahashreq = ahash_request_cast(req);
354 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
357 mv_cesa_ahash_last_cleanup(ahashreq);
359 mv_cesa_ahash_cleanup(ahashreq);
362 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
363 .step = mv_cesa_ahash_step,
364 .process = mv_cesa_ahash_process,
365 .prepare = mv_cesa_ahash_prepare,
366 .cleanup = mv_cesa_ahash_req_cleanup,
369 static int mv_cesa_ahash_init(struct ahash_request *req,
370 struct mv_cesa_op_ctx *tmpl, bool algo_le)
372 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
374 memset(creq, 0, sizeof(*creq));
375 mv_cesa_update_op_cfg(tmpl,
376 CESA_SA_DESC_CFG_OP_MAC_ONLY |
377 CESA_SA_DESC_CFG_FIRST_FRAG,
378 CESA_SA_DESC_CFG_OP_MSK |
379 CESA_SA_DESC_CFG_FRAG_MSK);
380 mv_cesa_set_mac_op_total_len(tmpl, 0);
381 mv_cesa_set_mac_op_frag_len(tmpl, 0);
382 creq->op_tmpl = *tmpl;
384 creq->algo_le = algo_le;
389 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
391 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
393 ctx->base.ops = &mv_cesa_ahash_req_ops;
395 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
396 sizeof(struct mv_cesa_ahash_req));
400 static int mv_cesa_ahash_cache_req(struct ahash_request *req, bool *cached)
402 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
404 if (creq->cache_ptr + req->nbytes < 64 && !creq->last_req) {
410 sg_pcopy_to_buffer(req->src, creq->src_nents,
411 creq->cache + creq->cache_ptr,
414 creq->cache_ptr += req->nbytes;
420 static struct mv_cesa_op_ctx *
421 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
422 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
425 struct mv_cesa_op_ctx *op;
428 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
432 /* Set the operation block fragment length. */
433 mv_cesa_set_mac_op_frag_len(op, frag_len);
435 /* Append dummy desc to launch operation */
436 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
440 if (mv_cesa_mac_op_is_first_frag(tmpl))
441 mv_cesa_update_op_cfg(tmpl,
442 CESA_SA_DESC_CFG_MID_FRAG,
443 CESA_SA_DESC_CFG_FRAG_MSK);
449 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
450 struct mv_cesa_ahash_dma_iter *dma_iter,
451 struct mv_cesa_ahash_req *creq,
454 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
457 if (!creq->cache_ptr)
460 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
464 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
466 return mv_cesa_dma_add_data_transfer(chain,
467 CESA_SA_DATA_SRAM_OFFSET,
468 ahashdreq->cache_dma,
470 CESA_TDMA_DST_IN_SRAM,
474 static struct mv_cesa_op_ctx *
475 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
476 struct mv_cesa_ahash_dma_iter *dma_iter,
477 struct mv_cesa_ahash_req *creq,
478 unsigned int frag_len, gfp_t flags)
480 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
481 unsigned int len, trailerlen, padoff = 0;
482 struct mv_cesa_op_ctx *op;
486 * If the transfer is smaller than our maximum length, and we have
487 * some data outstanding, we can ask the engine to finish the hash.
489 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
490 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
495 mv_cesa_set_mac_op_total_len(op, creq->len);
496 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
497 CESA_SA_DESC_CFG_NOT_FRAG :
498 CESA_SA_DESC_CFG_LAST_FRAG,
499 CESA_SA_DESC_CFG_FRAG_MSK);
505 * The request is longer than the engine can handle, or we have
506 * no data outstanding. Manually generate the padding, adding it
507 * as a "mid" fragment.
509 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
513 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
515 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
517 ret = mv_cesa_dma_add_data_transfer(chain,
518 CESA_SA_DATA_SRAM_OFFSET +
520 ahashdreq->padding_dma,
521 len, CESA_TDMA_DST_IN_SRAM,
526 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
531 if (len == trailerlen)
537 ret = mv_cesa_dma_add_data_transfer(chain,
538 CESA_SA_DATA_SRAM_OFFSET,
539 ahashdreq->padding_dma +
542 CESA_TDMA_DST_IN_SRAM,
547 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
551 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
553 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
554 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
555 GFP_KERNEL : GFP_ATOMIC;
556 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
557 struct mv_cesa_tdma_req *dreq = &ahashdreq->base;
558 struct mv_cesa_ahash_dma_iter iter;
559 struct mv_cesa_op_ctx *op = NULL;
560 unsigned int frag_len;
563 dreq->chain.first = NULL;
564 dreq->chain.last = NULL;
566 if (creq->src_nents) {
567 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
575 mv_cesa_tdma_desc_iter_init(&dreq->chain);
576 mv_cesa_ahash_req_iter_init(&iter, req);
579 * Add the cache (left-over data from a previous block) first.
580 * This will never overflow the SRAM size.
582 ret = mv_cesa_ahash_dma_add_cache(&dreq->chain, &iter, creq, flags);
588 * Add all the new data, inserting an operation block and
589 * launch command between each full SRAM block-worth of
590 * data. We intentionally do not add the final op block.
593 ret = mv_cesa_dma_add_op_transfers(&dreq->chain,
599 frag_len = iter.base.op_len;
601 if (!mv_cesa_ahash_req_iter_next_op(&iter))
604 op = mv_cesa_dma_add_frag(&dreq->chain, &creq->op_tmpl,
612 /* Account for the data that was in the cache. */
613 frag_len = iter.base.op_len;
617 * At this point, frag_len indicates whether we have any data
618 * outstanding which needs an operation. Queue up the final
619 * operation, which depends whether this is the final request.
622 op = mv_cesa_ahash_dma_last_req(&dreq->chain, &iter, creq,
625 op = mv_cesa_dma_add_frag(&dreq->chain, &creq->op_tmpl,
634 /* Add dummy desc to wait for crypto operation end */
635 ret = mv_cesa_dma_add_dummy_end(&dreq->chain, flags);
641 creq->cache_ptr = req->nbytes + creq->cache_ptr -
649 mv_cesa_dma_cleanup(dreq);
650 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
653 mv_cesa_ahash_last_cleanup(req);
658 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
660 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
663 if (cesa_dev->caps->has_tdma)
664 creq->req.base.type = CESA_DMA_REQ;
666 creq->req.base.type = CESA_STD_REQ;
668 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
669 if (creq->src_nents < 0) {
670 dev_err(cesa_dev->dev, "Invalid number of src SG");
671 return creq->src_nents;
674 ret = mv_cesa_ahash_cache_req(req, cached);
681 if (creq->req.base.type == CESA_DMA_REQ)
682 ret = mv_cesa_ahash_dma_req_init(req);
687 static int mv_cesa_ahash_update(struct ahash_request *req)
689 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
693 creq->len += req->nbytes;
694 ret = mv_cesa_ahash_req_init(req, &cached);
701 ret = mv_cesa_queue_req(&req->base);
702 if (mv_cesa_req_needs_cleanup(&req->base, ret))
703 mv_cesa_ahash_cleanup(req);
708 static int mv_cesa_ahash_final(struct ahash_request *req)
710 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
711 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
715 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
716 creq->last_req = true;
719 ret = mv_cesa_ahash_req_init(req, &cached);
726 ret = mv_cesa_queue_req(&req->base);
727 if (mv_cesa_req_needs_cleanup(&req->base, ret))
728 mv_cesa_ahash_cleanup(req);
733 static int mv_cesa_ahash_finup(struct ahash_request *req)
735 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
736 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
740 creq->len += req->nbytes;
741 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
742 creq->last_req = true;
744 ret = mv_cesa_ahash_req_init(req, &cached);
751 ret = mv_cesa_queue_req(&req->base);
752 if (mv_cesa_req_needs_cleanup(&req->base, ret))
753 mv_cesa_ahash_cleanup(req);
758 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
759 u64 *len, void *cache)
761 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
762 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
763 unsigned int digsize = crypto_ahash_digestsize(ahash);
764 unsigned int blocksize;
766 blocksize = crypto_ahash_blocksize(ahash);
769 memcpy(hash, creq->state, digsize);
770 memset(cache, 0, blocksize);
771 memcpy(cache, creq->cache, creq->cache_ptr);
776 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
777 u64 len, const void *cache)
779 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
780 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
781 unsigned int digsize = crypto_ahash_digestsize(ahash);
782 unsigned int blocksize;
783 unsigned int cache_ptr;
786 ret = crypto_ahash_init(req);
790 blocksize = crypto_ahash_blocksize(ahash);
791 if (len >= blocksize)
792 mv_cesa_update_op_cfg(&creq->op_tmpl,
793 CESA_SA_DESC_CFG_MID_FRAG,
794 CESA_SA_DESC_CFG_FRAG_MSK);
797 memcpy(creq->state, hash, digsize);
800 cache_ptr = do_div(len, blocksize);
804 memcpy(creq->cache, cache, cache_ptr);
805 creq->cache_ptr = cache_ptr;
810 static int mv_cesa_md5_init(struct ahash_request *req)
812 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
813 struct mv_cesa_op_ctx tmpl = { };
815 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
816 creq->state[0] = MD5_H0;
817 creq->state[1] = MD5_H1;
818 creq->state[2] = MD5_H2;
819 creq->state[3] = MD5_H3;
821 mv_cesa_ahash_init(req, &tmpl, true);
826 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
828 struct md5_state *out_state = out;
830 return mv_cesa_ahash_export(req, out_state->hash,
831 &out_state->byte_count, out_state->block);
834 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
836 const struct md5_state *in_state = in;
838 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
842 static int mv_cesa_md5_digest(struct ahash_request *req)
846 ret = mv_cesa_md5_init(req);
850 return mv_cesa_ahash_finup(req);
853 struct ahash_alg mv_md5_alg = {
854 .init = mv_cesa_md5_init,
855 .update = mv_cesa_ahash_update,
856 .final = mv_cesa_ahash_final,
857 .finup = mv_cesa_ahash_finup,
858 .digest = mv_cesa_md5_digest,
859 .export = mv_cesa_md5_export,
860 .import = mv_cesa_md5_import,
862 .digestsize = MD5_DIGEST_SIZE,
863 .statesize = sizeof(struct md5_state),
866 .cra_driver_name = "mv-md5",
868 .cra_flags = CRYPTO_ALG_ASYNC |
869 CRYPTO_ALG_KERN_DRIVER_ONLY,
870 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
871 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
872 .cra_init = mv_cesa_ahash_cra_init,
873 .cra_module = THIS_MODULE,
878 static int mv_cesa_sha1_init(struct ahash_request *req)
880 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
881 struct mv_cesa_op_ctx tmpl = { };
883 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
884 creq->state[0] = SHA1_H0;
885 creq->state[1] = SHA1_H1;
886 creq->state[2] = SHA1_H2;
887 creq->state[3] = SHA1_H3;
888 creq->state[4] = SHA1_H4;
890 mv_cesa_ahash_init(req, &tmpl, false);
895 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
897 struct sha1_state *out_state = out;
899 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
903 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
905 const struct sha1_state *in_state = in;
907 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
911 static int mv_cesa_sha1_digest(struct ahash_request *req)
915 ret = mv_cesa_sha1_init(req);
919 return mv_cesa_ahash_finup(req);
922 struct ahash_alg mv_sha1_alg = {
923 .init = mv_cesa_sha1_init,
924 .update = mv_cesa_ahash_update,
925 .final = mv_cesa_ahash_final,
926 .finup = mv_cesa_ahash_finup,
927 .digest = mv_cesa_sha1_digest,
928 .export = mv_cesa_sha1_export,
929 .import = mv_cesa_sha1_import,
931 .digestsize = SHA1_DIGEST_SIZE,
932 .statesize = sizeof(struct sha1_state),
935 .cra_driver_name = "mv-sha1",
937 .cra_flags = CRYPTO_ALG_ASYNC |
938 CRYPTO_ALG_KERN_DRIVER_ONLY,
939 .cra_blocksize = SHA1_BLOCK_SIZE,
940 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
941 .cra_init = mv_cesa_ahash_cra_init,
942 .cra_module = THIS_MODULE,
947 static int mv_cesa_sha256_init(struct ahash_request *req)
949 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
950 struct mv_cesa_op_ctx tmpl = { };
952 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
953 creq->state[0] = SHA256_H0;
954 creq->state[1] = SHA256_H1;
955 creq->state[2] = SHA256_H2;
956 creq->state[3] = SHA256_H3;
957 creq->state[4] = SHA256_H4;
958 creq->state[5] = SHA256_H5;
959 creq->state[6] = SHA256_H6;
960 creq->state[7] = SHA256_H7;
962 mv_cesa_ahash_init(req, &tmpl, false);
967 static int mv_cesa_sha256_digest(struct ahash_request *req)
971 ret = mv_cesa_sha256_init(req);
975 return mv_cesa_ahash_finup(req);
978 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
980 struct sha256_state *out_state = out;
982 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
986 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
988 const struct sha256_state *in_state = in;
990 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
994 struct ahash_alg mv_sha256_alg = {
995 .init = mv_cesa_sha256_init,
996 .update = mv_cesa_ahash_update,
997 .final = mv_cesa_ahash_final,
998 .finup = mv_cesa_ahash_finup,
999 .digest = mv_cesa_sha256_digest,
1000 .export = mv_cesa_sha256_export,
1001 .import = mv_cesa_sha256_import,
1003 .digestsize = SHA256_DIGEST_SIZE,
1004 .statesize = sizeof(struct sha256_state),
1006 .cra_name = "sha256",
1007 .cra_driver_name = "mv-sha256",
1008 .cra_priority = 300,
1009 .cra_flags = CRYPTO_ALG_ASYNC |
1010 CRYPTO_ALG_KERN_DRIVER_ONLY,
1011 .cra_blocksize = SHA256_BLOCK_SIZE,
1012 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1013 .cra_init = mv_cesa_ahash_cra_init,
1014 .cra_module = THIS_MODULE,
1019 struct mv_cesa_ahash_result {
1020 struct completion completion;
1024 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1027 struct mv_cesa_ahash_result *result = req->data;
1029 if (error == -EINPROGRESS)
1032 result->error = error;
1033 complete(&result->completion);
1036 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1037 void *state, unsigned int blocksize)
1039 struct mv_cesa_ahash_result result;
1040 struct scatterlist sg;
1043 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1044 mv_cesa_hmac_ahash_complete, &result);
1045 sg_init_one(&sg, pad, blocksize);
1046 ahash_request_set_crypt(req, &sg, pad, blocksize);
1047 init_completion(&result.completion);
1049 ret = crypto_ahash_init(req);
1053 ret = crypto_ahash_update(req);
1054 if (ret && ret != -EINPROGRESS)
1057 wait_for_completion_interruptible(&result.completion);
1059 return result.error;
1061 ret = crypto_ahash_export(req, state);
1068 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1069 const u8 *key, unsigned int keylen,
1071 unsigned int blocksize)
1073 struct mv_cesa_ahash_result result;
1074 struct scatterlist sg;
1078 if (keylen <= blocksize) {
1079 memcpy(ipad, key, keylen);
1081 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1086 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1087 mv_cesa_hmac_ahash_complete,
1089 sg_init_one(&sg, keydup, keylen);
1090 ahash_request_set_crypt(req, &sg, ipad, keylen);
1091 init_completion(&result.completion);
1093 ret = crypto_ahash_digest(req);
1094 if (ret == -EINPROGRESS) {
1095 wait_for_completion_interruptible(&result.completion);
1099 /* Set the memory region to 0 to avoid any leak. */
1100 memset(keydup, 0, keylen);
1106 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1109 memset(ipad + keylen, 0, blocksize - keylen);
1110 memcpy(opad, ipad, blocksize);
1112 for (i = 0; i < blocksize; i++) {
1120 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1121 const u8 *key, unsigned int keylen,
1122 void *istate, void *ostate)
1124 struct ahash_request *req;
1125 struct crypto_ahash *tfm;
1126 unsigned int blocksize;
1131 tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1132 CRYPTO_ALG_TYPE_AHASH_MASK);
1134 return PTR_ERR(tfm);
1136 req = ahash_request_alloc(tfm, GFP_KERNEL);
1142 crypto_ahash_clear_flags(tfm, ~0);
1144 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1146 ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1152 opad = ipad + blocksize;
1154 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1158 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1162 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1167 ahash_request_free(req);
1169 crypto_free_ahash(tfm);
1174 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1176 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1178 ctx->base.ops = &mv_cesa_ahash_req_ops;
1180 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1181 sizeof(struct mv_cesa_ahash_req));
1185 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1187 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1188 struct mv_cesa_op_ctx tmpl = { };
1190 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1191 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1193 mv_cesa_ahash_init(req, &tmpl, true);
1198 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1199 unsigned int keylen)
1201 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1202 struct md5_state istate, ostate;
1205 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1209 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1210 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1212 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1213 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1218 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1222 ret = mv_cesa_ahmac_md5_init(req);
1226 return mv_cesa_ahash_finup(req);
1229 struct ahash_alg mv_ahmac_md5_alg = {
1230 .init = mv_cesa_ahmac_md5_init,
1231 .update = mv_cesa_ahash_update,
1232 .final = mv_cesa_ahash_final,
1233 .finup = mv_cesa_ahash_finup,
1234 .digest = mv_cesa_ahmac_md5_digest,
1235 .setkey = mv_cesa_ahmac_md5_setkey,
1236 .export = mv_cesa_md5_export,
1237 .import = mv_cesa_md5_import,
1239 .digestsize = MD5_DIGEST_SIZE,
1240 .statesize = sizeof(struct md5_state),
1242 .cra_name = "hmac(md5)",
1243 .cra_driver_name = "mv-hmac-md5",
1244 .cra_priority = 300,
1245 .cra_flags = CRYPTO_ALG_ASYNC |
1246 CRYPTO_ALG_KERN_DRIVER_ONLY,
1247 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1248 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1249 .cra_init = mv_cesa_ahmac_cra_init,
1250 .cra_module = THIS_MODULE,
1255 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1257 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1258 struct mv_cesa_op_ctx tmpl = { };
1260 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1261 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1263 mv_cesa_ahash_init(req, &tmpl, false);
1268 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1269 unsigned int keylen)
1271 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1272 struct sha1_state istate, ostate;
1275 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1279 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1280 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1282 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1283 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1288 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1292 ret = mv_cesa_ahmac_sha1_init(req);
1296 return mv_cesa_ahash_finup(req);
1299 struct ahash_alg mv_ahmac_sha1_alg = {
1300 .init = mv_cesa_ahmac_sha1_init,
1301 .update = mv_cesa_ahash_update,
1302 .final = mv_cesa_ahash_final,
1303 .finup = mv_cesa_ahash_finup,
1304 .digest = mv_cesa_ahmac_sha1_digest,
1305 .setkey = mv_cesa_ahmac_sha1_setkey,
1306 .export = mv_cesa_sha1_export,
1307 .import = mv_cesa_sha1_import,
1309 .digestsize = SHA1_DIGEST_SIZE,
1310 .statesize = sizeof(struct sha1_state),
1312 .cra_name = "hmac(sha1)",
1313 .cra_driver_name = "mv-hmac-sha1",
1314 .cra_priority = 300,
1315 .cra_flags = CRYPTO_ALG_ASYNC |
1316 CRYPTO_ALG_KERN_DRIVER_ONLY,
1317 .cra_blocksize = SHA1_BLOCK_SIZE,
1318 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1319 .cra_init = mv_cesa_ahmac_cra_init,
1320 .cra_module = THIS_MODULE,
1325 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1326 unsigned int keylen)
1328 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1329 struct sha256_state istate, ostate;
1332 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1336 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1337 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1339 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1340 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1345 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1347 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1348 struct mv_cesa_op_ctx tmpl = { };
1350 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1351 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1353 mv_cesa_ahash_init(req, &tmpl, false);
1358 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1362 ret = mv_cesa_ahmac_sha256_init(req);
1366 return mv_cesa_ahash_finup(req);
1369 struct ahash_alg mv_ahmac_sha256_alg = {
1370 .init = mv_cesa_ahmac_sha256_init,
1371 .update = mv_cesa_ahash_update,
1372 .final = mv_cesa_ahash_final,
1373 .finup = mv_cesa_ahash_finup,
1374 .digest = mv_cesa_ahmac_sha256_digest,
1375 .setkey = mv_cesa_ahmac_sha256_setkey,
1376 .export = mv_cesa_sha256_export,
1377 .import = mv_cesa_sha256_import,
1379 .digestsize = SHA256_DIGEST_SIZE,
1380 .statesize = sizeof(struct sha256_state),
1382 .cra_name = "hmac(sha256)",
1383 .cra_driver_name = "mv-hmac-sha256",
1384 .cra_priority = 300,
1385 .cra_flags = CRYPTO_ALG_ASYNC |
1386 CRYPTO_ALG_KERN_DRIVER_ONLY,
1387 .cra_blocksize = SHA256_BLOCK_SIZE,
1388 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1389 .cra_init = mv_cesa_ahmac_cra_init,
1390 .cra_module = THIS_MODULE,