2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
57 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
58 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
60 #define AMDGPU_RESUME_MS 2000
62 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
63 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
64 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
66 static const char *amdgpu_asic_name[] = {
90 bool amdgpu_device_is_px(struct drm_device *dev)
92 struct amdgpu_device *adev = dev->dev_private;
94 if (adev->flags & AMD_IS_PX)
100 * MMIO register access helper functions.
102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
107 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
108 BUG_ON(in_interrupt());
109 return amdgpu_virt_kiq_rreg(adev, reg);
112 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
113 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
117 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
118 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
119 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
120 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
122 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
126 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
129 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
131 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
132 BUG_ON(in_interrupt());
133 return amdgpu_virt_kiq_wreg(adev, reg, v);
136 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
137 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
141 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
142 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
143 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
144 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
148 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
150 if ((reg * 4) < adev->rio_mem_size)
151 return ioread32(adev->rio_mem + (reg * 4));
153 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
154 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
158 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
161 if ((reg * 4) < adev->rio_mem_size)
162 iowrite32(v, adev->rio_mem + (reg * 4));
164 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
165 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
170 * amdgpu_mm_rdoorbell - read a doorbell dword
172 * @adev: amdgpu_device pointer
173 * @index: doorbell index
175 * Returns the value in the doorbell aperture at the
176 * requested doorbell index (CIK).
178 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
180 if (index < adev->doorbell.num_doorbells) {
181 return readl(adev->doorbell.ptr + index);
183 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
189 * amdgpu_mm_wdoorbell - write a doorbell dword
191 * @adev: amdgpu_device pointer
192 * @index: doorbell index
195 * Writes @v to the doorbell aperture at the
196 * requested doorbell index (CIK).
198 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
200 if (index < adev->doorbell.num_doorbells) {
201 writel(v, adev->doorbell.ptr + index);
203 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
208 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
210 * @adev: amdgpu_device pointer
211 * @index: doorbell index
213 * Returns the value in the doorbell aperture at the
214 * requested doorbell index (VEGA10+).
216 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
218 if (index < adev->doorbell.num_doorbells) {
219 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
221 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
227 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
229 * @adev: amdgpu_device pointer
230 * @index: doorbell index
233 * Writes @v to the doorbell aperture at the
234 * requested doorbell index (VEGA10+).
236 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
238 if (index < adev->doorbell.num_doorbells) {
239 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
241 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
246 * amdgpu_invalid_rreg - dummy reg read function
248 * @adev: amdgpu device pointer
249 * @reg: offset of register
251 * Dummy register read function. Used for register blocks
252 * that certain asics don't have (all asics).
253 * Returns the value in the register.
255 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
257 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
263 * amdgpu_invalid_wreg - dummy reg write function
265 * @adev: amdgpu device pointer
266 * @reg: offset of register
267 * @v: value to write to the register
269 * Dummy register read function. Used for register blocks
270 * that certain asics don't have (all asics).
272 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
274 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
280 * amdgpu_block_invalid_rreg - dummy reg read function
282 * @adev: amdgpu device pointer
283 * @block: offset of instance
284 * @reg: offset of register
286 * Dummy register read function. Used for register blocks
287 * that certain asics don't have (all asics).
288 * Returns the value in the register.
290 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
291 uint32_t block, uint32_t reg)
293 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
300 * amdgpu_block_invalid_wreg - dummy reg write function
302 * @adev: amdgpu device pointer
303 * @block: offset of instance
304 * @reg: offset of register
305 * @v: value to write to the register
307 * Dummy register read function. Used for register blocks
308 * that certain asics don't have (all asics).
310 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
312 uint32_t reg, uint32_t v)
314 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
319 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
323 if (adev->vram_scratch.robj == NULL) {
324 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
325 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
326 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
327 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
328 NULL, NULL, &adev->vram_scratch.robj);
334 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
335 if (unlikely(r != 0))
337 r = amdgpu_bo_pin(adev->vram_scratch.robj,
338 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
340 amdgpu_bo_unreserve(adev->vram_scratch.robj);
343 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
344 (void **)&adev->vram_scratch.ptr);
346 amdgpu_bo_unpin(adev->vram_scratch.robj);
347 amdgpu_bo_unreserve(adev->vram_scratch.robj);
352 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
356 if (adev->vram_scratch.robj == NULL) {
359 r = amdgpu_bo_reserve(adev->vram_scratch.robj, true);
360 if (likely(r == 0)) {
361 amdgpu_bo_kunmap(adev->vram_scratch.robj);
362 amdgpu_bo_unpin(adev->vram_scratch.robj);
363 amdgpu_bo_unreserve(adev->vram_scratch.robj);
365 amdgpu_bo_unref(&adev->vram_scratch.robj);
369 * amdgpu_program_register_sequence - program an array of registers.
371 * @adev: amdgpu_device pointer
372 * @registers: pointer to the register array
373 * @array_size: size of the register array
375 * Programs an array or registers with and and or masks.
376 * This is a helper for setting golden registers.
378 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
379 const u32 *registers,
380 const u32 array_size)
382 u32 tmp, reg, and_mask, or_mask;
388 for (i = 0; i < array_size; i +=3) {
389 reg = registers[i + 0];
390 and_mask = registers[i + 1];
391 or_mask = registers[i + 2];
393 if (and_mask == 0xffffffff) {
404 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
406 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
410 * GPU doorbell aperture helpers function.
413 * amdgpu_doorbell_init - Init doorbell driver information.
415 * @adev: amdgpu_device pointer
417 * Init doorbell driver information (CIK)
418 * Returns 0 on success, error on failure.
420 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
422 /* doorbell bar mapping */
423 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
424 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
426 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
427 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
428 if (adev->doorbell.num_doorbells == 0)
431 adev->doorbell.ptr = ioremap(adev->doorbell.base,
432 adev->doorbell.num_doorbells *
434 if (adev->doorbell.ptr == NULL)
441 * amdgpu_doorbell_fini - Tear down doorbell driver information.
443 * @adev: amdgpu_device pointer
445 * Tear down doorbell driver information (CIK)
447 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
449 iounmap(adev->doorbell.ptr);
450 adev->doorbell.ptr = NULL;
454 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
457 * @adev: amdgpu_device pointer
458 * @aperture_base: output returning doorbell aperture base physical address
459 * @aperture_size: output returning doorbell aperture size in bytes
460 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
462 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
463 * takes doorbells required for its own rings and reports the setup to amdkfd.
464 * amdgpu reserved doorbells are at the start of the doorbell aperture.
466 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
467 phys_addr_t *aperture_base,
468 size_t *aperture_size,
469 size_t *start_offset)
472 * The first num_doorbells are used by amdgpu.
473 * amdkfd takes whatever's left in the aperture.
475 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
476 *aperture_base = adev->doorbell.base;
477 *aperture_size = adev->doorbell.size;
478 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
488 * Writeback is the method by which the GPU updates special pages in memory
489 * with the status of certain GPU events (fences, ring pointers,etc.).
493 * amdgpu_wb_fini - Disable Writeback and free memory
495 * @adev: amdgpu_device pointer
497 * Disables Writeback and frees the Writeback memory (all asics).
498 * Used at driver shutdown.
500 static void amdgpu_wb_fini(struct amdgpu_device *adev)
502 if (adev->wb.wb_obj) {
503 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
505 (void **)&adev->wb.wb);
506 adev->wb.wb_obj = NULL;
511 * amdgpu_wb_init- Init Writeback driver info and allocate memory
513 * @adev: amdgpu_device pointer
515 * Initializes writeback and allocates writeback memory (all asics).
516 * Used at driver startup.
517 * Returns 0 on success or an -error on failure.
519 static int amdgpu_wb_init(struct amdgpu_device *adev)
523 if (adev->wb.wb_obj == NULL) {
524 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t),
525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
526 &adev->wb.wb_obj, &adev->wb.gpu_addr,
527 (void **)&adev->wb.wb);
529 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
533 adev->wb.num_wb = AMDGPU_MAX_WB;
534 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
536 /* clear wb memory */
537 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
544 * amdgpu_wb_get - Allocate a wb entry
546 * @adev: amdgpu_device pointer
549 * Allocate a wb slot for use by the driver (all asics).
550 * Returns 0 on success or -EINVAL on failure.
552 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
554 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
555 if (offset < adev->wb.num_wb) {
556 __set_bit(offset, adev->wb.used);
565 * amdgpu_wb_get_64bit - Allocate a wb entry
567 * @adev: amdgpu_device pointer
570 * Allocate a wb slot for use by the driver (all asics).
571 * Returns 0 on success or -EINVAL on failure.
573 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
575 unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
576 adev->wb.num_wb, 0, 2, 7, 0);
577 if ((offset + 1) < adev->wb.num_wb) {
578 __set_bit(offset, adev->wb.used);
579 __set_bit(offset + 1, adev->wb.used);
588 * amdgpu_wb_free - Free a wb entry
590 * @adev: amdgpu_device pointer
593 * Free a wb slot allocated for use by the driver (all asics)
595 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
597 if (wb < adev->wb.num_wb)
598 __clear_bit(wb, adev->wb.used);
602 * amdgpu_wb_free_64bit - Free a wb entry
604 * @adev: amdgpu_device pointer
607 * Free a wb slot allocated for use by the driver (all asics)
609 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
611 if ((wb + 1) < adev->wb.num_wb) {
612 __clear_bit(wb, adev->wb.used);
613 __clear_bit(wb + 1, adev->wb.used);
618 * amdgpu_vram_location - try to find VRAM location
619 * @adev: amdgpu device structure holding all necessary informations
620 * @mc: memory controller structure holding memory informations
621 * @base: base address at which to put VRAM
623 * Function will try to place VRAM at base address provided
624 * as parameter (which is so far either PCI aperture address or
625 * for IGP TOM base address).
627 * If there is not enough space to fit the unvisible VRAM in the 32bits
628 * address space then we limit the VRAM size to the aperture.
630 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
631 * this shouldn't be a problem as we are using the PCI aperture as a reference.
632 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
635 * Note: we use mc_vram_size as on some board we need to program the mc to
636 * cover the whole aperture even if VRAM size is inferior to aperture size
637 * Novell bug 204882 + along with lots of ubuntu ones
639 * Note: when limiting vram it's safe to overwritte real_vram_size because
640 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
641 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
644 * Note: IGP TOM addr should be the same as the aperture addr, we don't
645 * explicitly check for that though.
647 * FIXME: when reducing VRAM size align new size on power of 2.
649 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
651 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
653 mc->vram_start = base;
654 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
655 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
656 mc->real_vram_size = mc->aper_size;
657 mc->mc_vram_size = mc->aper_size;
659 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
660 if (limit && limit < mc->real_vram_size)
661 mc->real_vram_size = limit;
662 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
663 mc->mc_vram_size >> 20, mc->vram_start,
664 mc->vram_end, mc->real_vram_size >> 20);
668 * amdgpu_gtt_location - try to find GTT location
669 * @adev: amdgpu device structure holding all necessary informations
670 * @mc: memory controller structure holding memory informations
672 * Function will place try to place GTT before or after VRAM.
674 * If GTT size is bigger than space left then we ajust GTT size.
675 * Thus function will never fails.
677 * FIXME: when reducing GTT size align new size on power of 2.
679 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
681 u64 size_af, size_bf;
683 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
684 size_bf = mc->vram_start & ~mc->gtt_base_align;
685 if (size_bf > size_af) {
686 if (mc->gtt_size > size_bf) {
687 dev_warn(adev->dev, "limiting GTT\n");
688 mc->gtt_size = size_bf;
692 if (mc->gtt_size > size_af) {
693 dev_warn(adev->dev, "limiting GTT\n");
694 mc->gtt_size = size_af;
696 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
698 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
699 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
700 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
704 * GPU helpers function.
707 * amdgpu_need_post - check if the hw need post or not
709 * @adev: amdgpu_device pointer
711 * Check if the asic has been initialized (all asics) at driver startup
712 * or post is needed if hw reset is performed.
713 * Returns true if need or false if not.
715 bool amdgpu_need_post(struct amdgpu_device *adev)
719 if (adev->has_hw_reset) {
720 adev->has_hw_reset = false;
723 /* then check MEM_SIZE, in case the crtcs are off */
724 reg = amdgpu_asic_get_config_memsize(adev);
726 if ((reg != 0) && (reg != 0xffffffff))
733 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
735 if (amdgpu_sriov_vf(adev))
738 if (amdgpu_passthrough(adev)) {
739 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
740 * some old smc fw still need driver do vPost otherwise gpu hang, while
741 * those smc fw version above 22.15 doesn't have this flaw, so we force
742 * vpost executed for smc version below 22.15
744 if (adev->asic_type == CHIP_FIJI) {
747 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
748 /* force vPost if error occured */
752 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
753 if (fw_ver < 0x00160e00)
757 return amdgpu_need_post(adev);
761 * amdgpu_dummy_page_init - init dummy page used by the driver
763 * @adev: amdgpu_device pointer
765 * Allocate the dummy page used by the driver (all asics).
766 * This dummy page is used by the driver as a filler for gart entries
767 * when pages are taken out of the GART
768 * Returns 0 on sucess, -ENOMEM on failure.
770 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
772 if (adev->dummy_page.page)
774 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
775 if (adev->dummy_page.page == NULL)
777 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
778 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
779 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
780 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
781 __free_page(adev->dummy_page.page);
782 adev->dummy_page.page = NULL;
789 * amdgpu_dummy_page_fini - free dummy page used by the driver
791 * @adev: amdgpu_device pointer
793 * Frees the dummy page used by the driver (all asics).
795 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
797 if (adev->dummy_page.page == NULL)
799 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
800 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
801 __free_page(adev->dummy_page.page);
802 adev->dummy_page.page = NULL;
806 /* ATOM accessor methods */
808 * ATOM is an interpreted byte code stored in tables in the vbios. The
809 * driver registers callbacks to access registers and the interpreter
810 * in the driver parses the tables and executes then to program specific
811 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
812 * atombios.h, and atom.c
816 * cail_pll_read - read PLL register
818 * @info: atom card_info pointer
819 * @reg: PLL register offset
821 * Provides a PLL register accessor for the atom interpreter (r4xx+).
822 * Returns the value of the PLL register.
824 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
830 * cail_pll_write - write PLL register
832 * @info: atom card_info pointer
833 * @reg: PLL register offset
834 * @val: value to write to the pll register
836 * Provides a PLL register accessor for the atom interpreter (r4xx+).
838 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
844 * cail_mc_read - read MC (Memory Controller) register
846 * @info: atom card_info pointer
847 * @reg: MC register offset
849 * Provides an MC register accessor for the atom interpreter (r4xx+).
850 * Returns the value of the MC register.
852 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
858 * cail_mc_write - write MC (Memory Controller) register
860 * @info: atom card_info pointer
861 * @reg: MC register offset
862 * @val: value to write to the pll register
864 * Provides a MC register accessor for the atom interpreter (r4xx+).
866 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
872 * cail_reg_write - write MMIO register
874 * @info: atom card_info pointer
875 * @reg: MMIO register offset
876 * @val: value to write to the pll register
878 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
880 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
882 struct amdgpu_device *adev = info->dev->dev_private;
888 * cail_reg_read - read MMIO register
890 * @info: atom card_info pointer
891 * @reg: MMIO register offset
893 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
894 * Returns the value of the MMIO register.
896 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
898 struct amdgpu_device *adev = info->dev->dev_private;
906 * cail_ioreg_write - write IO register
908 * @info: atom card_info pointer
909 * @reg: IO register offset
910 * @val: value to write to the pll register
912 * Provides a IO register accessor for the atom interpreter (r4xx+).
914 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
916 struct amdgpu_device *adev = info->dev->dev_private;
922 * cail_ioreg_read - read IO register
924 * @info: atom card_info pointer
925 * @reg: IO register offset
927 * Provides an IO register accessor for the atom interpreter (r4xx+).
928 * Returns the value of the IO register.
930 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
932 struct amdgpu_device *adev = info->dev->dev_private;
940 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
942 * @adev: amdgpu_device pointer
944 * Frees the driver info and register access callbacks for the ATOM
945 * interpreter (r4xx+).
946 * Called at driver shutdown.
948 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
950 if (adev->mode_info.atom_context) {
951 kfree(adev->mode_info.atom_context->scratch);
952 kfree(adev->mode_info.atom_context->iio);
954 kfree(adev->mode_info.atom_context);
955 adev->mode_info.atom_context = NULL;
956 kfree(adev->mode_info.atom_card_info);
957 adev->mode_info.atom_card_info = NULL;
961 * amdgpu_atombios_init - init the driver info and callbacks for atombios
963 * @adev: amdgpu_device pointer
965 * Initializes the driver info and register access callbacks for the
966 * ATOM interpreter (r4xx+).
967 * Returns 0 on sucess, -ENOMEM on failure.
968 * Called at driver startup.
970 static int amdgpu_atombios_init(struct amdgpu_device *adev)
972 struct card_info *atom_card_info =
973 kzalloc(sizeof(struct card_info), GFP_KERNEL);
978 adev->mode_info.atom_card_info = atom_card_info;
979 atom_card_info->dev = adev->ddev;
980 atom_card_info->reg_read = cail_reg_read;
981 atom_card_info->reg_write = cail_reg_write;
982 /* needed for iio ops */
984 atom_card_info->ioreg_read = cail_ioreg_read;
985 atom_card_info->ioreg_write = cail_ioreg_write;
987 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
988 atom_card_info->ioreg_read = cail_reg_read;
989 atom_card_info->ioreg_write = cail_reg_write;
991 atom_card_info->mc_read = cail_mc_read;
992 atom_card_info->mc_write = cail_mc_write;
993 atom_card_info->pll_read = cail_pll_read;
994 atom_card_info->pll_write = cail_pll_write;
996 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
997 if (!adev->mode_info.atom_context) {
998 amdgpu_atombios_fini(adev);
1002 mutex_init(&adev->mode_info.atom_context->mutex);
1003 if (adev->is_atom_fw) {
1004 amdgpu_atomfirmware_scratch_regs_init(adev);
1005 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1007 amdgpu_atombios_scratch_regs_init(adev);
1008 amdgpu_atombios_allocate_fb_scratch(adev);
1013 /* if we get transitioned to only one device, take VGA back */
1015 * amdgpu_vga_set_decode - enable/disable vga decode
1017 * @cookie: amdgpu_device pointer
1018 * @state: enable/disable vga decode
1020 * Enable/disable vga decode (all asics).
1021 * Returns VGA resource flags.
1023 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1025 struct amdgpu_device *adev = cookie;
1026 amdgpu_asic_set_vga_state(adev, state);
1028 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1029 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1031 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1035 * amdgpu_check_pot_argument - check that argument is a power of two
1037 * @arg: value to check
1039 * Validates that a certain argument is a power of two (all asics).
1040 * Returns true if argument is valid.
1042 static bool amdgpu_check_pot_argument(int arg)
1044 return (arg & (arg - 1)) == 0;
1047 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1049 /* defines number of bits in page table versus page directory,
1050 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1051 * page table and the remaining bits are in the page directory */
1052 if (amdgpu_vm_block_size == -1)
1055 if (amdgpu_vm_block_size < 9) {
1056 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1057 amdgpu_vm_block_size);
1061 if (amdgpu_vm_block_size > 24 ||
1062 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1063 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1064 amdgpu_vm_block_size);
1071 amdgpu_vm_block_size = -1;
1074 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1076 /* no need to check the default value */
1077 if (amdgpu_vm_size == -1)
1080 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1081 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1086 if (amdgpu_vm_size < 1) {
1087 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1093 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1095 if (amdgpu_vm_size > 1024) {
1096 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1104 amdgpu_vm_size = -1;
1108 * amdgpu_check_arguments - validate module params
1110 * @adev: amdgpu_device pointer
1112 * Validates certain module parameters and updates
1113 * the associated values used by the driver (all asics).
1115 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1117 if (amdgpu_sched_jobs < 4) {
1118 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1120 amdgpu_sched_jobs = 4;
1121 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
1122 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1124 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1127 if (amdgpu_gart_size != -1) {
1128 /* gtt size must be greater or equal to 32M */
1129 if (amdgpu_gart_size < 32) {
1130 dev_warn(adev->dev, "gart size (%d) too small\n",
1132 amdgpu_gart_size = -1;
1136 amdgpu_check_vm_size(adev);
1138 amdgpu_check_block_size(adev);
1140 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1141 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1142 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1143 amdgpu_vram_page_split);
1144 amdgpu_vram_page_split = 1024;
1149 * amdgpu_switcheroo_set_state - set switcheroo state
1151 * @pdev: pci dev pointer
1152 * @state: vga_switcheroo state
1154 * Callback for the switcheroo driver. Suspends or resumes the
1155 * the asics before or after it is powered up using ACPI methods.
1157 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1159 struct drm_device *dev = pci_get_drvdata(pdev);
1161 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1164 if (state == VGA_SWITCHEROO_ON) {
1165 pr_info("amdgpu: switched on\n");
1166 /* don't suspend or resume card normally */
1167 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1169 amdgpu_device_resume(dev, true, true);
1171 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1172 drm_kms_helper_poll_enable(dev);
1174 pr_info("amdgpu: switched off\n");
1175 drm_kms_helper_poll_disable(dev);
1176 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1177 amdgpu_device_suspend(dev, true, true);
1178 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1183 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1185 * @pdev: pci dev pointer
1187 * Callback for the switcheroo driver. Check of the switcheroo
1188 * state can be changed.
1189 * Returns true if the state can be changed, false if not.
1191 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1193 struct drm_device *dev = pci_get_drvdata(pdev);
1196 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1197 * locking inversion with the driver load path. And the access here is
1198 * completely racy anyway. So don't bother with locking for now.
1200 return dev->open_count == 0;
1203 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1204 .set_gpu_state = amdgpu_switcheroo_set_state,
1206 .can_switch = amdgpu_switcheroo_can_switch,
1209 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1210 enum amd_ip_block_type block_type,
1211 enum amd_clockgating_state state)
1215 for (i = 0; i < adev->num_ip_blocks; i++) {
1216 if (!adev->ip_blocks[i].status.valid)
1218 if (adev->ip_blocks[i].version->type != block_type)
1220 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1222 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1223 (void *)adev, state);
1225 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1226 adev->ip_blocks[i].version->funcs->name, r);
1231 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1232 enum amd_ip_block_type block_type,
1233 enum amd_powergating_state state)
1237 for (i = 0; i < adev->num_ip_blocks; i++) {
1238 if (!adev->ip_blocks[i].status.valid)
1240 if (adev->ip_blocks[i].version->type != block_type)
1242 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1244 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1245 (void *)adev, state);
1247 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1248 adev->ip_blocks[i].version->funcs->name, r);
1253 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1257 for (i = 0; i < adev->num_ip_blocks; i++) {
1258 if (!adev->ip_blocks[i].status.valid)
1260 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1261 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1265 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1266 enum amd_ip_block_type block_type)
1270 for (i = 0; i < adev->num_ip_blocks; i++) {
1271 if (!adev->ip_blocks[i].status.valid)
1273 if (adev->ip_blocks[i].version->type == block_type) {
1274 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1284 bool amdgpu_is_idle(struct amdgpu_device *adev,
1285 enum amd_ip_block_type block_type)
1289 for (i = 0; i < adev->num_ip_blocks; i++) {
1290 if (!adev->ip_blocks[i].status.valid)
1292 if (adev->ip_blocks[i].version->type == block_type)
1293 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1299 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1300 enum amd_ip_block_type type)
1304 for (i = 0; i < adev->num_ip_blocks; i++)
1305 if (adev->ip_blocks[i].version->type == type)
1306 return &adev->ip_blocks[i];
1312 * amdgpu_ip_block_version_cmp
1314 * @adev: amdgpu_device pointer
1315 * @type: enum amd_ip_block_type
1316 * @major: major version
1317 * @minor: minor version
1319 * return 0 if equal or greater
1320 * return 1 if smaller or the ip_block doesn't exist
1322 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1323 enum amd_ip_block_type type,
1324 u32 major, u32 minor)
1326 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1328 if (ip_block && ((ip_block->version->major > major) ||
1329 ((ip_block->version->major == major) &&
1330 (ip_block->version->minor >= minor))))
1337 * amdgpu_ip_block_add
1339 * @adev: amdgpu_device pointer
1340 * @ip_block_version: pointer to the IP to add
1342 * Adds the IP block driver information to the collection of IPs
1345 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1346 const struct amdgpu_ip_block_version *ip_block_version)
1348 if (!ip_block_version)
1351 DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1352 ip_block_version->funcs->name);
1354 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1359 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1361 adev->enable_virtual_display = false;
1363 if (amdgpu_virtual_display) {
1364 struct drm_device *ddev = adev->ddev;
1365 const char *pci_address_name = pci_name(ddev->pdev);
1366 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1368 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1369 pciaddstr_tmp = pciaddstr;
1370 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1371 pciaddname = strsep(&pciaddname_tmp, ",");
1372 if (!strcmp("all", pciaddname)
1373 || !strcmp(pci_address_name, pciaddname)) {
1377 adev->enable_virtual_display = true;
1380 res = kstrtol(pciaddname_tmp, 10,
1388 adev->mode_info.num_crtc = num_crtc;
1390 adev->mode_info.num_crtc = 1;
1396 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1397 amdgpu_virtual_display, pci_address_name,
1398 adev->enable_virtual_display, adev->mode_info.num_crtc);
1404 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1406 const char *chip_name;
1409 const struct gpu_info_firmware_header_v1_0 *hdr;
1411 adev->firmware.gpu_info_fw = NULL;
1413 switch (adev->asic_type) {
1417 case CHIP_POLARIS11:
1418 case CHIP_POLARIS10:
1419 case CHIP_POLARIS12:
1422 #ifdef CONFIG_DRM_AMDGPU_SI
1429 #ifdef CONFIG_DRM_AMDGPU_CIK
1439 chip_name = "vega10";
1442 chip_name = "raven";
1446 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1447 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1450 "Failed to load gpu_info firmware \"%s\"\n",
1454 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1457 "Failed to validate gpu_info firmware \"%s\"\n",
1462 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1463 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1465 switch (hdr->version_major) {
1468 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1469 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1470 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1472 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1473 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1474 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1475 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1476 adev->gfx.config.max_texture_channel_caches =
1477 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1478 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1479 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1480 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1481 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1482 adev->gfx.config.double_offchip_lds_buf =
1483 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1484 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1485 adev->gfx.cu_info.max_waves_per_simd =
1486 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1487 adev->gfx.cu_info.max_scratch_slots_per_cu =
1488 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1489 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1494 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1502 static int amdgpu_early_init(struct amdgpu_device *adev)
1506 amdgpu_device_enable_virtual_display(adev);
1508 switch (adev->asic_type) {
1512 case CHIP_POLARIS11:
1513 case CHIP_POLARIS10:
1514 case CHIP_POLARIS12:
1517 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1518 adev->family = AMDGPU_FAMILY_CZ;
1520 adev->family = AMDGPU_FAMILY_VI;
1522 r = vi_set_ip_blocks(adev);
1526 #ifdef CONFIG_DRM_AMDGPU_SI
1532 adev->family = AMDGPU_FAMILY_SI;
1533 r = si_set_ip_blocks(adev);
1538 #ifdef CONFIG_DRM_AMDGPU_CIK
1544 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1545 adev->family = AMDGPU_FAMILY_CI;
1547 adev->family = AMDGPU_FAMILY_KV;
1549 r = cik_set_ip_blocks(adev);
1556 if (adev->asic_type == CHIP_RAVEN)
1557 adev->family = AMDGPU_FAMILY_RV;
1559 adev->family = AMDGPU_FAMILY_AI;
1561 r = soc15_set_ip_blocks(adev);
1566 /* FIXME: not supported yet */
1570 r = amdgpu_device_parse_gpu_info_fw(adev);
1574 if (amdgpu_sriov_vf(adev)) {
1575 r = amdgpu_virt_request_full_gpu(adev, true);
1580 for (i = 0; i < adev->num_ip_blocks; i++) {
1581 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1582 DRM_ERROR("disabled ip block: %d <%s>\n",
1583 i, adev->ip_blocks[i].version->funcs->name);
1584 adev->ip_blocks[i].status.valid = false;
1586 if (adev->ip_blocks[i].version->funcs->early_init) {
1587 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1589 adev->ip_blocks[i].status.valid = false;
1591 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1592 adev->ip_blocks[i].version->funcs->name, r);
1595 adev->ip_blocks[i].status.valid = true;
1598 adev->ip_blocks[i].status.valid = true;
1603 adev->cg_flags &= amdgpu_cg_mask;
1604 adev->pg_flags &= amdgpu_pg_mask;
1609 static int amdgpu_init(struct amdgpu_device *adev)
1613 for (i = 0; i < adev->num_ip_blocks; i++) {
1614 if (!adev->ip_blocks[i].status.valid)
1616 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1618 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1619 adev->ip_blocks[i].version->funcs->name, r);
1622 adev->ip_blocks[i].status.sw = true;
1623 /* need to do gmc hw init early so we can allocate gpu mem */
1624 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1625 r = amdgpu_vram_scratch_init(adev);
1627 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1630 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1632 DRM_ERROR("hw_init %d failed %d\n", i, r);
1635 r = amdgpu_wb_init(adev);
1637 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1640 adev->ip_blocks[i].status.hw = true;
1642 /* right after GMC hw init, we create CSA */
1643 if (amdgpu_sriov_vf(adev)) {
1644 r = amdgpu_allocate_static_csa(adev);
1646 DRM_ERROR("allocate CSA failed %d\n", r);
1653 for (i = 0; i < adev->num_ip_blocks; i++) {
1654 if (!adev->ip_blocks[i].status.sw)
1656 /* gmc hw init is done early */
1657 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1659 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1661 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1662 adev->ip_blocks[i].version->funcs->name, r);
1665 adev->ip_blocks[i].status.hw = true;
1671 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1673 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1676 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1678 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1679 AMDGPU_RESET_MAGIC_NUM);
1682 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1686 for (i = 0; i < adev->num_ip_blocks; i++) {
1687 if (!adev->ip_blocks[i].status.valid)
1689 /* skip CG for VCE/UVD, it's handled specially */
1690 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1691 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1692 /* enable clockgating to save power */
1693 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1696 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1697 adev->ip_blocks[i].version->funcs->name, r);
1705 static int amdgpu_late_init(struct amdgpu_device *adev)
1709 for (i = 0; i < adev->num_ip_blocks; i++) {
1710 if (!adev->ip_blocks[i].status.valid)
1712 if (adev->ip_blocks[i].version->funcs->late_init) {
1713 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1715 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1716 adev->ip_blocks[i].version->funcs->name, r);
1719 adev->ip_blocks[i].status.late_initialized = true;
1723 mod_delayed_work(system_wq, &adev->late_init_work,
1724 msecs_to_jiffies(AMDGPU_RESUME_MS));
1726 amdgpu_fill_reset_magic(adev);
1731 static int amdgpu_fini(struct amdgpu_device *adev)
1735 /* need to disable SMC first */
1736 for (i = 0; i < adev->num_ip_blocks; i++) {
1737 if (!adev->ip_blocks[i].status.hw)
1739 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1740 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1741 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1742 AMD_CG_STATE_UNGATE);
1744 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1745 adev->ip_blocks[i].version->funcs->name, r);
1748 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1749 /* XXX handle errors */
1751 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1752 adev->ip_blocks[i].version->funcs->name, r);
1754 adev->ip_blocks[i].status.hw = false;
1759 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1760 if (!adev->ip_blocks[i].status.hw)
1762 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1763 amdgpu_wb_fini(adev);
1764 amdgpu_vram_scratch_fini(adev);
1767 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1768 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1769 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1770 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1771 AMD_CG_STATE_UNGATE);
1773 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1774 adev->ip_blocks[i].version->funcs->name, r);
1779 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1780 /* XXX handle errors */
1782 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1783 adev->ip_blocks[i].version->funcs->name, r);
1786 adev->ip_blocks[i].status.hw = false;
1789 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1790 if (!adev->ip_blocks[i].status.sw)
1792 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1793 /* XXX handle errors */
1795 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1796 adev->ip_blocks[i].version->funcs->name, r);
1798 adev->ip_blocks[i].status.sw = false;
1799 adev->ip_blocks[i].status.valid = false;
1802 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1803 if (!adev->ip_blocks[i].status.late_initialized)
1805 if (adev->ip_blocks[i].version->funcs->late_fini)
1806 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1807 adev->ip_blocks[i].status.late_initialized = false;
1810 if (amdgpu_sriov_vf(adev)) {
1811 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
1812 amdgpu_virt_release_full_gpu(adev, false);
1818 static void amdgpu_late_init_func_handler(struct work_struct *work)
1820 struct amdgpu_device *adev =
1821 container_of(work, struct amdgpu_device, late_init_work.work);
1822 amdgpu_late_set_cg_state(adev);
1825 int amdgpu_suspend(struct amdgpu_device *adev)
1829 if (amdgpu_sriov_vf(adev))
1830 amdgpu_virt_request_full_gpu(adev, false);
1832 /* ungate SMC block first */
1833 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1834 AMD_CG_STATE_UNGATE);
1836 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1839 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1840 if (!adev->ip_blocks[i].status.valid)
1842 /* ungate blocks so that suspend can properly shut them down */
1843 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1844 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1845 AMD_CG_STATE_UNGATE);
1847 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1848 adev->ip_blocks[i].version->funcs->name, r);
1851 /* XXX handle errors */
1852 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1853 /* XXX handle errors */
1855 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1856 adev->ip_blocks[i].version->funcs->name, r);
1860 if (amdgpu_sriov_vf(adev))
1861 amdgpu_virt_release_full_gpu(adev, false);
1866 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1870 static enum amd_ip_block_type ip_order[] = {
1871 AMD_IP_BLOCK_TYPE_GMC,
1872 AMD_IP_BLOCK_TYPE_COMMON,
1873 AMD_IP_BLOCK_TYPE_IH,
1876 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1878 struct amdgpu_ip_block *block;
1880 for (j = 0; j < adev->num_ip_blocks; j++) {
1881 block = &adev->ip_blocks[j];
1883 if (block->version->type != ip_order[i] ||
1884 !block->status.valid)
1887 r = block->version->funcs->hw_init(adev);
1888 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1895 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1899 static enum amd_ip_block_type ip_order[] = {
1900 AMD_IP_BLOCK_TYPE_SMC,
1901 AMD_IP_BLOCK_TYPE_DCE,
1902 AMD_IP_BLOCK_TYPE_GFX,
1903 AMD_IP_BLOCK_TYPE_SDMA,
1904 AMD_IP_BLOCK_TYPE_VCE,
1907 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1909 struct amdgpu_ip_block *block;
1911 for (j = 0; j < adev->num_ip_blocks; j++) {
1912 block = &adev->ip_blocks[j];
1914 if (block->version->type != ip_order[i] ||
1915 !block->status.valid)
1918 r = block->version->funcs->hw_init(adev);
1919 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1926 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
1930 for (i = 0; i < adev->num_ip_blocks; i++) {
1931 if (!adev->ip_blocks[i].status.valid)
1933 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1934 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1935 adev->ip_blocks[i].version->type ==
1936 AMD_IP_BLOCK_TYPE_IH) {
1937 r = adev->ip_blocks[i].version->funcs->resume(adev);
1939 DRM_ERROR("resume of IP block <%s> failed %d\n",
1940 adev->ip_blocks[i].version->funcs->name, r);
1949 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
1953 for (i = 0; i < adev->num_ip_blocks; i++) {
1954 if (!adev->ip_blocks[i].status.valid)
1956 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1957 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1958 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1960 r = adev->ip_blocks[i].version->funcs->resume(adev);
1962 DRM_ERROR("resume of IP block <%s> failed %d\n",
1963 adev->ip_blocks[i].version->funcs->name, r);
1971 static int amdgpu_resume(struct amdgpu_device *adev)
1975 r = amdgpu_resume_phase1(adev);
1978 r = amdgpu_resume_phase2(adev);
1983 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1985 if (adev->is_atom_fw) {
1986 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1987 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1989 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1990 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1995 * amdgpu_device_init - initialize the driver
1997 * @adev: amdgpu_device pointer
1998 * @pdev: drm dev pointer
1999 * @pdev: pci dev pointer
2000 * @flags: driver flags
2002 * Initializes the driver info and hw (all asics).
2003 * Returns 0 for success or an error on failure.
2004 * Called at driver startup.
2006 int amdgpu_device_init(struct amdgpu_device *adev,
2007 struct drm_device *ddev,
2008 struct pci_dev *pdev,
2012 bool runtime = false;
2015 adev->shutdown = false;
2016 adev->dev = &pdev->dev;
2019 adev->flags = flags;
2020 adev->asic_type = flags & AMD_ASIC_MASK;
2021 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2022 adev->mc.gtt_size = 512 * 1024 * 1024;
2023 adev->accel_working = false;
2024 adev->num_rings = 0;
2025 adev->mman.buffer_funcs = NULL;
2026 adev->mman.buffer_funcs_ring = NULL;
2027 adev->vm_manager.vm_pte_funcs = NULL;
2028 adev->vm_manager.vm_pte_num_rings = 0;
2029 adev->gart.gart_funcs = NULL;
2030 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2032 adev->smc_rreg = &amdgpu_invalid_rreg;
2033 adev->smc_wreg = &amdgpu_invalid_wreg;
2034 adev->pcie_rreg = &amdgpu_invalid_rreg;
2035 adev->pcie_wreg = &amdgpu_invalid_wreg;
2036 adev->pciep_rreg = &amdgpu_invalid_rreg;
2037 adev->pciep_wreg = &amdgpu_invalid_wreg;
2038 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2039 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2040 adev->didt_rreg = &amdgpu_invalid_rreg;
2041 adev->didt_wreg = &amdgpu_invalid_wreg;
2042 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2043 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2044 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2045 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2048 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2049 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2050 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2052 /* mutex initialization are all done here so we
2053 * can recall function without having locking issues */
2054 atomic_set(&adev->irq.ih.lock, 0);
2055 mutex_init(&adev->firmware.mutex);
2056 mutex_init(&adev->pm.mutex);
2057 mutex_init(&adev->gfx.gpu_clock_mutex);
2058 mutex_init(&adev->srbm_mutex);
2059 mutex_init(&adev->grbm_idx_mutex);
2060 mutex_init(&adev->mn_lock);
2061 hash_init(adev->mn_hash);
2063 amdgpu_check_arguments(adev);
2065 spin_lock_init(&adev->mmio_idx_lock);
2066 spin_lock_init(&adev->smc_idx_lock);
2067 spin_lock_init(&adev->pcie_idx_lock);
2068 spin_lock_init(&adev->uvd_ctx_idx_lock);
2069 spin_lock_init(&adev->didt_idx_lock);
2070 spin_lock_init(&adev->gc_cac_idx_lock);
2071 spin_lock_init(&adev->audio_endpt_idx_lock);
2072 spin_lock_init(&adev->mm_stats.lock);
2074 INIT_LIST_HEAD(&adev->shadow_list);
2075 mutex_init(&adev->shadow_list_lock);
2077 INIT_LIST_HEAD(&adev->gtt_list);
2078 spin_lock_init(&adev->gtt_list_lock);
2080 INIT_LIST_HEAD(&adev->ring_lru_list);
2081 spin_lock_init(&adev->ring_lru_list_lock);
2083 INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2085 /* Registers mapping */
2086 /* TODO: block userspace mapping of io register */
2087 if (adev->asic_type >= CHIP_BONAIRE) {
2088 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2089 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2091 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2092 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2095 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2096 if (adev->rmmio == NULL) {
2099 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2100 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2102 if (adev->asic_type >= CHIP_BONAIRE)
2103 /* doorbell bar mapping */
2104 amdgpu_doorbell_init(adev);
2106 /* io port mapping */
2107 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2108 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2109 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2110 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2114 if (adev->rio_mem == NULL)
2115 DRM_INFO("PCI I/O BAR is not found.\n");
2117 /* early init functions */
2118 r = amdgpu_early_init(adev);
2122 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2123 /* this will fail for cards that aren't VGA class devices, just
2125 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2127 if (amdgpu_runtime_pm == 1)
2129 if (amdgpu_device_is_px(ddev))
2131 if (!pci_is_thunderbolt_attached(adev->pdev))
2132 vga_switcheroo_register_client(adev->pdev,
2133 &amdgpu_switcheroo_ops, runtime);
2135 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2138 if (!amdgpu_get_bios(adev)) {
2143 r = amdgpu_atombios_init(adev);
2145 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2149 /* detect if we are with an SRIOV vbios */
2150 amdgpu_device_detect_sriov_bios(adev);
2152 /* Post card if necessary */
2153 if (amdgpu_vpost_needed(adev)) {
2155 dev_err(adev->dev, "no vBIOS found\n");
2159 DRM_INFO("GPU posting now...\n");
2160 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2162 dev_err(adev->dev, "gpu post error!\n");
2166 DRM_INFO("GPU post is not needed\n");
2169 if (!adev->is_atom_fw) {
2170 /* Initialize clocks */
2171 r = amdgpu_atombios_get_clock_info(adev);
2173 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2176 /* init i2c buses */
2177 amdgpu_atombios_i2c_init(adev);
2181 r = amdgpu_fence_driver_init(adev);
2183 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2187 /* init the mode config */
2188 drm_mode_config_init(adev->ddev);
2190 r = amdgpu_init(adev);
2192 dev_err(adev->dev, "amdgpu_init failed\n");
2197 adev->accel_working = true;
2199 amdgpu_vm_check_compute_bug(adev);
2201 /* Initialize the buffer migration limit. */
2202 if (amdgpu_moverate >= 0)
2203 max_MBps = amdgpu_moverate;
2205 max_MBps = 8; /* Allow 8 MB/s. */
2206 /* Get a log2 for easy divisions. */
2207 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2209 r = amdgpu_ib_pool_init(adev);
2211 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2215 r = amdgpu_ib_ring_tests(adev);
2217 DRM_ERROR("ib ring test failed (%d).\n", r);
2219 amdgpu_fbdev_init(adev);
2221 r = amdgpu_gem_debugfs_init(adev);
2223 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2225 r = amdgpu_debugfs_regs_init(adev);
2227 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2229 r = amdgpu_debugfs_test_ib_ring_init(adev);
2231 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2233 r = amdgpu_debugfs_firmware_init(adev);
2235 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2237 if ((amdgpu_testing & 1)) {
2238 if (adev->accel_working)
2239 amdgpu_test_moves(adev);
2241 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2243 if (amdgpu_benchmarking) {
2244 if (adev->accel_working)
2245 amdgpu_benchmark(adev, amdgpu_benchmarking);
2247 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2250 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2251 * explicit gating rather than handling it automatically.
2253 r = amdgpu_late_init(adev);
2255 dev_err(adev->dev, "amdgpu_late_init failed\n");
2263 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2268 * amdgpu_device_fini - tear down the driver
2270 * @adev: amdgpu_device pointer
2272 * Tear down the driver info (all asics).
2273 * Called at driver shutdown.
2275 void amdgpu_device_fini(struct amdgpu_device *adev)
2279 DRM_INFO("amdgpu: finishing device.\n");
2280 adev->shutdown = true;
2281 if (adev->mode_info.mode_config_initialized)
2282 drm_crtc_force_disable_all(adev->ddev);
2283 /* evict vram memory */
2284 amdgpu_bo_evict_vram(adev);
2285 amdgpu_ib_pool_fini(adev);
2286 amdgpu_fence_driver_fini(adev);
2287 amdgpu_fbdev_fini(adev);
2288 r = amdgpu_fini(adev);
2289 if (adev->firmware.gpu_info_fw) {
2290 release_firmware(adev->firmware.gpu_info_fw);
2291 adev->firmware.gpu_info_fw = NULL;
2293 adev->accel_working = false;
2294 cancel_delayed_work_sync(&adev->late_init_work);
2295 /* free i2c buses */
2296 amdgpu_i2c_fini(adev);
2297 amdgpu_atombios_fini(adev);
2300 if (!pci_is_thunderbolt_attached(adev->pdev))
2301 vga_switcheroo_unregister_client(adev->pdev);
2302 if (adev->flags & AMD_IS_PX)
2303 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2304 vga_client_register(adev->pdev, NULL, NULL, NULL);
2306 pci_iounmap(adev->pdev, adev->rio_mem);
2307 adev->rio_mem = NULL;
2308 iounmap(adev->rmmio);
2310 if (adev->asic_type >= CHIP_BONAIRE)
2311 amdgpu_doorbell_fini(adev);
2312 amdgpu_debugfs_regs_cleanup(adev);
2320 * amdgpu_device_suspend - initiate device suspend
2322 * @pdev: drm dev pointer
2323 * @state: suspend state
2325 * Puts the hw in the suspend state (all asics).
2326 * Returns 0 for success or an error on failure.
2327 * Called at driver suspend.
2329 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2331 struct amdgpu_device *adev;
2332 struct drm_crtc *crtc;
2333 struct drm_connector *connector;
2336 if (dev == NULL || dev->dev_private == NULL) {
2340 adev = dev->dev_private;
2342 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2345 drm_kms_helper_poll_disable(dev);
2347 /* turn off display hw */
2348 drm_modeset_lock_all(dev);
2349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2350 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2352 drm_modeset_unlock_all(dev);
2354 /* unpin the front buffers and cursors */
2355 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2356 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2357 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2358 struct amdgpu_bo *robj;
2360 if (amdgpu_crtc->cursor_bo) {
2361 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2362 r = amdgpu_bo_reserve(aobj, true);
2364 amdgpu_bo_unpin(aobj);
2365 amdgpu_bo_unreserve(aobj);
2369 if (rfb == NULL || rfb->obj == NULL) {
2372 robj = gem_to_amdgpu_bo(rfb->obj);
2373 /* don't unpin kernel fb objects */
2374 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2375 r = amdgpu_bo_reserve(robj, true);
2377 amdgpu_bo_unpin(robj);
2378 amdgpu_bo_unreserve(robj);
2382 /* evict vram memory */
2383 amdgpu_bo_evict_vram(adev);
2385 amdgpu_fence_driver_suspend(adev);
2387 r = amdgpu_suspend(adev);
2389 /* evict remaining vram memory
2390 * This second call to evict vram is to evict the gart page table
2393 amdgpu_bo_evict_vram(adev);
2395 if (adev->is_atom_fw)
2396 amdgpu_atomfirmware_scratch_regs_save(adev);
2398 amdgpu_atombios_scratch_regs_save(adev);
2399 pci_save_state(dev->pdev);
2401 /* Shut down the device */
2402 pci_disable_device(dev->pdev);
2403 pci_set_power_state(dev->pdev, PCI_D3hot);
2405 r = amdgpu_asic_reset(adev);
2407 DRM_ERROR("amdgpu asic reset failed\n");
2412 amdgpu_fbdev_set_suspend(adev, 1);
2419 * amdgpu_device_resume - initiate device resume
2421 * @pdev: drm dev pointer
2423 * Bring the hw back to operating state (all asics).
2424 * Returns 0 for success or an error on failure.
2425 * Called at driver resume.
2427 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2429 struct drm_connector *connector;
2430 struct amdgpu_device *adev = dev->dev_private;
2431 struct drm_crtc *crtc;
2434 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2441 pci_set_power_state(dev->pdev, PCI_D0);
2442 pci_restore_state(dev->pdev);
2443 r = pci_enable_device(dev->pdev);
2447 if (adev->is_atom_fw)
2448 amdgpu_atomfirmware_scratch_regs_restore(adev);
2450 amdgpu_atombios_scratch_regs_restore(adev);
2453 if (amdgpu_need_post(adev)) {
2454 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2456 DRM_ERROR("amdgpu asic init failed\n");
2459 r = amdgpu_resume(adev);
2461 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2464 amdgpu_fence_driver_resume(adev);
2467 r = amdgpu_ib_ring_tests(adev);
2469 DRM_ERROR("ib ring test failed (%d).\n", r);
2472 r = amdgpu_late_init(adev);
2477 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2478 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2480 if (amdgpu_crtc->cursor_bo) {
2481 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2482 r = amdgpu_bo_reserve(aobj, true);
2484 r = amdgpu_bo_pin(aobj,
2485 AMDGPU_GEM_DOMAIN_VRAM,
2486 &amdgpu_crtc->cursor_addr);
2488 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2489 amdgpu_bo_unreserve(aobj);
2494 /* blat the mode back in */
2496 drm_helper_resume_force_mode(dev);
2497 /* turn on display hw */
2498 drm_modeset_lock_all(dev);
2499 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2500 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2502 drm_modeset_unlock_all(dev);
2505 drm_kms_helper_poll_enable(dev);
2508 * Most of the connector probing functions try to acquire runtime pm
2509 * refs to ensure that the GPU is powered on when connector polling is
2510 * performed. Since we're calling this from a runtime PM callback,
2511 * trying to acquire rpm refs will cause us to deadlock.
2513 * Since we're guaranteed to be holding the rpm lock, it's safe to
2514 * temporarily disable the rpm helpers so this doesn't deadlock us.
2517 dev->dev->power.disable_depth++;
2519 drm_helper_hpd_irq_event(dev);
2521 dev->dev->power.disable_depth--;
2525 amdgpu_fbdev_set_suspend(adev, 0);
2534 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2537 bool asic_hang = false;
2539 for (i = 0; i < adev->num_ip_blocks; i++) {
2540 if (!adev->ip_blocks[i].status.valid)
2542 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2543 adev->ip_blocks[i].status.hang =
2544 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2545 if (adev->ip_blocks[i].status.hang) {
2546 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2553 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2557 for (i = 0; i < adev->num_ip_blocks; i++) {
2558 if (!adev->ip_blocks[i].status.valid)
2560 if (adev->ip_blocks[i].status.hang &&
2561 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2562 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2571 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2575 for (i = 0; i < adev->num_ip_blocks; i++) {
2576 if (!adev->ip_blocks[i].status.valid)
2578 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2579 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2580 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2581 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2582 if (adev->ip_blocks[i].status.hang) {
2583 DRM_INFO("Some block need full reset!\n");
2591 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2595 for (i = 0; i < adev->num_ip_blocks; i++) {
2596 if (!adev->ip_blocks[i].status.valid)
2598 if (adev->ip_blocks[i].status.hang &&
2599 adev->ip_blocks[i].version->funcs->soft_reset) {
2600 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2609 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2613 for (i = 0; i < adev->num_ip_blocks; i++) {
2614 if (!adev->ip_blocks[i].status.valid)
2616 if (adev->ip_blocks[i].status.hang &&
2617 adev->ip_blocks[i].version->funcs->post_soft_reset)
2618 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2626 bool amdgpu_need_backup(struct amdgpu_device *adev)
2628 if (adev->flags & AMD_IS_APU)
2631 return amdgpu_lockup_timeout > 0 ? true : false;
2634 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2635 struct amdgpu_ring *ring,
2636 struct amdgpu_bo *bo,
2637 struct dma_fence **fence)
2645 r = amdgpu_bo_reserve(bo, true);
2648 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2649 /* if bo has been evicted, then no need to recover */
2650 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2651 r = amdgpu_bo_validate(bo->shadow);
2653 DRM_ERROR("bo validate failed!\n");
2657 r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem);
2659 DRM_ERROR("%p bind failed\n", bo->shadow);
2663 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2666 DRM_ERROR("recover page table failed!\n");
2671 amdgpu_bo_unreserve(bo);
2676 * amdgpu_sriov_gpu_reset - reset the asic
2678 * @adev: amdgpu device pointer
2679 * @job: which job trigger hang
2681 * Attempt the reset the GPU if it has hung (all asics).
2683 * Returns 0 for success or an error on failure.
2685 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
2689 struct amdgpu_bo *bo, *tmp;
2690 struct amdgpu_ring *ring;
2691 struct dma_fence *fence = NULL, *next = NULL;
2693 mutex_lock(&adev->virt.lock_reset);
2694 atomic_inc(&adev->gpu_reset_counter);
2695 adev->gfx.in_reset = true;
2698 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2700 /* we start from the ring trigger GPU hang */
2701 j = job ? job->ring->idx : 0;
2703 /* block scheduler */
2704 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2705 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2706 if (!ring || !ring->sched.thread)
2709 kthread_park(ring->sched.thread);
2714 /* here give the last chance to check if job removed from mirror-list
2715 * since we already pay some time on kthread_park */
2716 if (job && list_empty(&job->base.node)) {
2717 kthread_unpark(ring->sched.thread);
2721 if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
2722 amd_sched_job_kickout(&job->base);
2724 /* only do job_reset on the hang ring if @job not NULL */
2725 amd_sched_hw_job_reset(&ring->sched);
2727 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2728 amdgpu_fence_driver_force_completion_ring(ring);
2731 /* request to take full control of GPU before re-initialization */
2733 amdgpu_virt_reset_gpu(adev);
2735 amdgpu_virt_request_full_gpu(adev, true);
2738 /* Resume IP prior to SMC */
2739 amdgpu_sriov_reinit_early(adev);
2741 /* we need recover gart prior to run SMC/CP/SDMA resume */
2742 amdgpu_ttm_recover_gart(adev);
2744 /* now we are okay to resume SMC/CP/SDMA */
2745 amdgpu_sriov_reinit_late(adev);
2747 amdgpu_irq_gpu_reset_resume_helper(adev);
2749 if (amdgpu_ib_ring_tests(adev))
2750 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2752 /* release full control of GPU after ib test */
2753 amdgpu_virt_release_full_gpu(adev, true);
2755 DRM_INFO("recover vram bo from shadow\n");
2757 ring = adev->mman.buffer_funcs_ring;
2758 mutex_lock(&adev->shadow_list_lock);
2759 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2761 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2763 r = dma_fence_wait(fence, false);
2765 WARN(r, "recovery from shadow isn't completed\n");
2770 dma_fence_put(fence);
2773 mutex_unlock(&adev->shadow_list_lock);
2776 r = dma_fence_wait(fence, false);
2778 WARN(r, "recovery from shadow isn't completed\n");
2780 dma_fence_put(fence);
2782 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2783 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2784 if (!ring || !ring->sched.thread)
2787 if (job && j != i) {
2788 kthread_unpark(ring->sched.thread);
2792 amd_sched_job_recovery(&ring->sched);
2793 kthread_unpark(ring->sched.thread);
2796 drm_helper_resume_force_mode(adev->ddev);
2798 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2800 /* bad news, how to tell it to userspace ? */
2801 dev_info(adev->dev, "GPU reset failed\n");
2803 dev_info(adev->dev, "GPU reset successed!\n");
2806 adev->gfx.in_reset = false;
2807 mutex_unlock(&adev->virt.lock_reset);
2812 * amdgpu_gpu_reset - reset the asic
2814 * @adev: amdgpu device pointer
2816 * Attempt the reset the GPU if it has hung (all asics).
2817 * Returns 0 for success or an error on failure.
2819 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2823 bool need_full_reset, vram_lost = false;
2825 if (!amdgpu_check_soft_reset(adev)) {
2826 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2830 atomic_inc(&adev->gpu_reset_counter);
2833 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2835 /* block scheduler */
2836 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2837 struct amdgpu_ring *ring = adev->rings[i];
2839 if (!ring || !ring->sched.thread)
2841 kthread_park(ring->sched.thread);
2842 amd_sched_hw_job_reset(&ring->sched);
2844 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2845 amdgpu_fence_driver_force_completion(adev);
2847 need_full_reset = amdgpu_need_full_reset(adev);
2849 if (!need_full_reset) {
2850 amdgpu_pre_soft_reset(adev);
2851 r = amdgpu_soft_reset(adev);
2852 amdgpu_post_soft_reset(adev);
2853 if (r || amdgpu_check_soft_reset(adev)) {
2854 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2855 need_full_reset = true;
2859 if (need_full_reset) {
2860 r = amdgpu_suspend(adev);
2863 /* Disable fb access */
2864 if (adev->mode_info.num_crtc) {
2865 struct amdgpu_mode_mc_save save;
2866 amdgpu_display_stop_mc_access(adev, &save);
2867 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2869 if (adev->is_atom_fw)
2870 amdgpu_atomfirmware_scratch_regs_save(adev);
2872 amdgpu_atombios_scratch_regs_save(adev);
2873 r = amdgpu_asic_reset(adev);
2874 if (adev->is_atom_fw)
2875 amdgpu_atomfirmware_scratch_regs_restore(adev);
2877 amdgpu_atombios_scratch_regs_restore(adev);
2879 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2882 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2883 r = amdgpu_resume_phase1(adev);
2886 vram_lost = amdgpu_check_vram_lost(adev);
2888 DRM_ERROR("VRAM is lost!\n");
2889 atomic_inc(&adev->vram_lost_counter);
2891 r = amdgpu_ttm_recover_gart(adev);
2894 r = amdgpu_resume_phase2(adev);
2898 amdgpu_fill_reset_magic(adev);
2903 amdgpu_irq_gpu_reset_resume_helper(adev);
2904 r = amdgpu_ib_ring_tests(adev);
2906 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2907 r = amdgpu_suspend(adev);
2908 need_full_reset = true;
2912 * recovery vm page tables, since we cannot depend on VRAM is
2913 * consistent after gpu full reset.
2915 if (need_full_reset && amdgpu_need_backup(adev)) {
2916 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2917 struct amdgpu_bo *bo, *tmp;
2918 struct dma_fence *fence = NULL, *next = NULL;
2920 DRM_INFO("recover vram bo from shadow\n");
2921 mutex_lock(&adev->shadow_list_lock);
2922 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2924 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2926 r = dma_fence_wait(fence, false);
2928 WARN(r, "recovery from shadow isn't completed\n");
2933 dma_fence_put(fence);
2936 mutex_unlock(&adev->shadow_list_lock);
2938 r = dma_fence_wait(fence, false);
2940 WARN(r, "recovery from shadow isn't completed\n");
2942 dma_fence_put(fence);
2944 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2945 struct amdgpu_ring *ring = adev->rings[i];
2947 if (!ring || !ring->sched.thread)
2950 amd_sched_job_recovery(&ring->sched);
2951 kthread_unpark(ring->sched.thread);
2954 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2955 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2956 if (adev->rings[i] && adev->rings[i]->sched.thread) {
2957 kthread_unpark(adev->rings[i]->sched.thread);
2962 drm_helper_resume_force_mode(adev->ddev);
2964 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2966 /* bad news, how to tell it to userspace ? */
2967 dev_info(adev->dev, "GPU reset failed\n");
2969 dev_info(adev->dev, "GPU reset successed!\n");
2974 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2979 if (amdgpu_pcie_gen_cap)
2980 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2982 if (amdgpu_pcie_lane_cap)
2983 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2985 /* covers APUs as well */
2986 if (pci_is_root_bus(adev->pdev->bus)) {
2987 if (adev->pm.pcie_gen_mask == 0)
2988 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2989 if (adev->pm.pcie_mlw_mask == 0)
2990 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2994 if (adev->pm.pcie_gen_mask == 0) {
2995 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2997 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2998 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2999 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3001 if (mask & DRM_PCIE_SPEED_25)
3002 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3003 if (mask & DRM_PCIE_SPEED_50)
3004 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
3005 if (mask & DRM_PCIE_SPEED_80)
3006 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
3008 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3011 if (adev->pm.pcie_mlw_mask == 0) {
3012 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3016 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3017 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3018 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3019 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3020 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3021 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3022 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3025 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3026 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3027 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3028 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3029 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3030 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3033 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3034 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3035 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3036 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3037 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3040 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3041 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3042 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3043 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3046 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3047 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3048 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3051 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3052 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3055 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3061 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3069 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3070 const struct drm_info_list *files,
3075 for (i = 0; i < adev->debugfs_count; i++) {
3076 if (adev->debugfs[i].files == files) {
3077 /* Already registered */
3082 i = adev->debugfs_count + 1;
3083 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3084 DRM_ERROR("Reached maximum number of debugfs components.\n");
3085 DRM_ERROR("Report so we increase "
3086 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3089 adev->debugfs[adev->debugfs_count].files = files;
3090 adev->debugfs[adev->debugfs_count].num_files = nfiles;
3091 adev->debugfs_count = i;
3092 #if defined(CONFIG_DEBUG_FS)
3093 drm_debugfs_create_files(files, nfiles,
3094 adev->ddev->primary->debugfs_root,
3095 adev->ddev->primary);
3100 #if defined(CONFIG_DEBUG_FS)
3102 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3103 size_t size, loff_t *pos)
3105 struct amdgpu_device *adev = file_inode(f)->i_private;
3108 bool pm_pg_lock, use_bank;
3109 unsigned instance_bank, sh_bank, se_bank;
3111 if (size & 0x3 || *pos & 0x3)
3114 /* are we reading registers for which a PG lock is necessary? */
3115 pm_pg_lock = (*pos >> 23) & 1;
3117 if (*pos & (1ULL << 62)) {
3118 se_bank = (*pos >> 24) & 0x3FF;
3119 sh_bank = (*pos >> 34) & 0x3FF;
3120 instance_bank = (*pos >> 44) & 0x3FF;
3122 if (se_bank == 0x3FF)
3123 se_bank = 0xFFFFFFFF;
3124 if (sh_bank == 0x3FF)
3125 sh_bank = 0xFFFFFFFF;
3126 if (instance_bank == 0x3FF)
3127 instance_bank = 0xFFFFFFFF;
3133 *pos &= (1UL << 22) - 1;
3136 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3137 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3139 mutex_lock(&adev->grbm_idx_mutex);
3140 amdgpu_gfx_select_se_sh(adev, se_bank,
3141 sh_bank, instance_bank);
3145 mutex_lock(&adev->pm.mutex);
3150 if (*pos > adev->rmmio_size)
3153 value = RREG32(*pos >> 2);
3154 r = put_user(value, (uint32_t *)buf);
3168 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3169 mutex_unlock(&adev->grbm_idx_mutex);
3173 mutex_unlock(&adev->pm.mutex);
3178 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3179 size_t size, loff_t *pos)
3181 struct amdgpu_device *adev = file_inode(f)->i_private;
3184 bool pm_pg_lock, use_bank;
3185 unsigned instance_bank, sh_bank, se_bank;
3187 if (size & 0x3 || *pos & 0x3)
3190 /* are we reading registers for which a PG lock is necessary? */
3191 pm_pg_lock = (*pos >> 23) & 1;
3193 if (*pos & (1ULL << 62)) {
3194 se_bank = (*pos >> 24) & 0x3FF;
3195 sh_bank = (*pos >> 34) & 0x3FF;
3196 instance_bank = (*pos >> 44) & 0x3FF;
3198 if (se_bank == 0x3FF)
3199 se_bank = 0xFFFFFFFF;
3200 if (sh_bank == 0x3FF)
3201 sh_bank = 0xFFFFFFFF;
3202 if (instance_bank == 0x3FF)
3203 instance_bank = 0xFFFFFFFF;
3209 *pos &= (1UL << 22) - 1;
3212 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3213 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3215 mutex_lock(&adev->grbm_idx_mutex);
3216 amdgpu_gfx_select_se_sh(adev, se_bank,
3217 sh_bank, instance_bank);
3221 mutex_lock(&adev->pm.mutex);
3226 if (*pos > adev->rmmio_size)
3229 r = get_user(value, (uint32_t *)buf);
3233 WREG32(*pos >> 2, value);
3242 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3243 mutex_unlock(&adev->grbm_idx_mutex);
3247 mutex_unlock(&adev->pm.mutex);
3252 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3253 size_t size, loff_t *pos)
3255 struct amdgpu_device *adev = file_inode(f)->i_private;
3259 if (size & 0x3 || *pos & 0x3)
3265 value = RREG32_PCIE(*pos >> 2);
3266 r = put_user(value, (uint32_t *)buf);
3279 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3280 size_t size, loff_t *pos)
3282 struct amdgpu_device *adev = file_inode(f)->i_private;
3286 if (size & 0x3 || *pos & 0x3)
3292 r = get_user(value, (uint32_t *)buf);
3296 WREG32_PCIE(*pos >> 2, value);
3307 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3308 size_t size, loff_t *pos)
3310 struct amdgpu_device *adev = file_inode(f)->i_private;
3314 if (size & 0x3 || *pos & 0x3)
3320 value = RREG32_DIDT(*pos >> 2);
3321 r = put_user(value, (uint32_t *)buf);
3334 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3335 size_t size, loff_t *pos)
3337 struct amdgpu_device *adev = file_inode(f)->i_private;
3341 if (size & 0x3 || *pos & 0x3)
3347 r = get_user(value, (uint32_t *)buf);
3351 WREG32_DIDT(*pos >> 2, value);
3362 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3363 size_t size, loff_t *pos)
3365 struct amdgpu_device *adev = file_inode(f)->i_private;
3369 if (size & 0x3 || *pos & 0x3)
3375 value = RREG32_SMC(*pos);
3376 r = put_user(value, (uint32_t *)buf);
3389 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3390 size_t size, loff_t *pos)
3392 struct amdgpu_device *adev = file_inode(f)->i_private;
3396 if (size & 0x3 || *pos & 0x3)
3402 r = get_user(value, (uint32_t *)buf);
3406 WREG32_SMC(*pos, value);
3417 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3418 size_t size, loff_t *pos)
3420 struct amdgpu_device *adev = file_inode(f)->i_private;
3423 uint32_t *config, no_regs = 0;
3425 if (size & 0x3 || *pos & 0x3)
3428 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3432 /* version, increment each time something is added */
3433 config[no_regs++] = 3;
3434 config[no_regs++] = adev->gfx.config.max_shader_engines;
3435 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3436 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3437 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3438 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3439 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3440 config[no_regs++] = adev->gfx.config.max_gprs;
3441 config[no_regs++] = adev->gfx.config.max_gs_threads;
3442 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3443 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3444 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3445 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3446 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3447 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3448 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3449 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3450 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3451 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3452 config[no_regs++] = adev->gfx.config.num_gpus;
3453 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3454 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3455 config[no_regs++] = adev->gfx.config.gb_addr_config;
3456 config[no_regs++] = adev->gfx.config.num_rbs;
3459 config[no_regs++] = adev->rev_id;
3460 config[no_regs++] = adev->pg_flags;
3461 config[no_regs++] = adev->cg_flags;
3464 config[no_regs++] = adev->family;
3465 config[no_regs++] = adev->external_rev_id;
3468 config[no_regs++] = adev->pdev->device;
3469 config[no_regs++] = adev->pdev->revision;
3470 config[no_regs++] = adev->pdev->subsystem_device;
3471 config[no_regs++] = adev->pdev->subsystem_vendor;
3473 while (size && (*pos < no_regs * 4)) {
3476 value = config[*pos >> 2];
3477 r = put_user(value, (uint32_t *)buf);
3493 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3494 size_t size, loff_t *pos)
3496 struct amdgpu_device *adev = file_inode(f)->i_private;
3497 int idx, x, outsize, r, valuesize;
3498 uint32_t values[16];
3500 if (size & 3 || *pos & 0x3)
3503 if (amdgpu_dpm == 0)
3506 /* convert offset to sensor number */
3509 valuesize = sizeof(values);
3510 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3511 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
3512 else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
3513 r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
3518 if (size > valuesize)
3525 r = put_user(values[x++], (int32_t *)buf);
3532 return !r ? outsize : r;
3535 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3536 size_t size, loff_t *pos)
3538 struct amdgpu_device *adev = f->f_inode->i_private;
3541 uint32_t offset, se, sh, cu, wave, simd, data[32];
3543 if (size & 3 || *pos & 3)
3547 offset = (*pos & 0x7F);
3548 se = ((*pos >> 7) & 0xFF);
3549 sh = ((*pos >> 15) & 0xFF);
3550 cu = ((*pos >> 23) & 0xFF);
3551 wave = ((*pos >> 31) & 0xFF);
3552 simd = ((*pos >> 37) & 0xFF);
3554 /* switch to the specific se/sh/cu */
3555 mutex_lock(&adev->grbm_idx_mutex);
3556 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3559 if (adev->gfx.funcs->read_wave_data)
3560 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3562 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3563 mutex_unlock(&adev->grbm_idx_mutex);
3568 while (size && (offset < x * 4)) {
3571 value = data[offset >> 2];
3572 r = put_user(value, (uint32_t *)buf);
3585 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3586 size_t size, loff_t *pos)
3588 struct amdgpu_device *adev = f->f_inode->i_private;
3591 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3593 if (size & 3 || *pos & 3)
3597 offset = (*pos & 0xFFF); /* in dwords */
3598 se = ((*pos >> 12) & 0xFF);
3599 sh = ((*pos >> 20) & 0xFF);
3600 cu = ((*pos >> 28) & 0xFF);
3601 wave = ((*pos >> 36) & 0xFF);
3602 simd = ((*pos >> 44) & 0xFF);
3603 thread = ((*pos >> 52) & 0xFF);
3604 bank = ((*pos >> 60) & 1);
3606 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3610 /* switch to the specific se/sh/cu */
3611 mutex_lock(&adev->grbm_idx_mutex);
3612 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3615 if (adev->gfx.funcs->read_wave_vgprs)
3616 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3618 if (adev->gfx.funcs->read_wave_sgprs)
3619 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3622 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3623 mutex_unlock(&adev->grbm_idx_mutex);
3628 value = data[offset++];
3629 r = put_user(value, (uint32_t *)buf);
3645 static const struct file_operations amdgpu_debugfs_regs_fops = {
3646 .owner = THIS_MODULE,
3647 .read = amdgpu_debugfs_regs_read,
3648 .write = amdgpu_debugfs_regs_write,
3649 .llseek = default_llseek
3651 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3652 .owner = THIS_MODULE,
3653 .read = amdgpu_debugfs_regs_didt_read,
3654 .write = amdgpu_debugfs_regs_didt_write,
3655 .llseek = default_llseek
3657 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3658 .owner = THIS_MODULE,
3659 .read = amdgpu_debugfs_regs_pcie_read,
3660 .write = amdgpu_debugfs_regs_pcie_write,
3661 .llseek = default_llseek
3663 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3664 .owner = THIS_MODULE,
3665 .read = amdgpu_debugfs_regs_smc_read,
3666 .write = amdgpu_debugfs_regs_smc_write,
3667 .llseek = default_llseek
3670 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3671 .owner = THIS_MODULE,
3672 .read = amdgpu_debugfs_gca_config_read,
3673 .llseek = default_llseek
3676 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3677 .owner = THIS_MODULE,
3678 .read = amdgpu_debugfs_sensor_read,
3679 .llseek = default_llseek
3682 static const struct file_operations amdgpu_debugfs_wave_fops = {
3683 .owner = THIS_MODULE,
3684 .read = amdgpu_debugfs_wave_read,
3685 .llseek = default_llseek
3687 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3688 .owner = THIS_MODULE,
3689 .read = amdgpu_debugfs_gpr_read,
3690 .llseek = default_llseek
3693 static const struct file_operations *debugfs_regs[] = {
3694 &amdgpu_debugfs_regs_fops,
3695 &amdgpu_debugfs_regs_didt_fops,
3696 &amdgpu_debugfs_regs_pcie_fops,
3697 &amdgpu_debugfs_regs_smc_fops,
3698 &amdgpu_debugfs_gca_config_fops,
3699 &amdgpu_debugfs_sensors_fops,
3700 &amdgpu_debugfs_wave_fops,
3701 &amdgpu_debugfs_gpr_fops,
3704 static const char *debugfs_regs_names[] = {
3709 "amdgpu_gca_config",
3715 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3717 struct drm_minor *minor = adev->ddev->primary;
3718 struct dentry *ent, *root = minor->debugfs_root;
3721 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3722 ent = debugfs_create_file(debugfs_regs_names[i],
3723 S_IFREG | S_IRUGO, root,
3724 adev, debugfs_regs[i]);
3726 for (j = 0; j < i; j++) {
3727 debugfs_remove(adev->debugfs_regs[i]);
3728 adev->debugfs_regs[i] = NULL;
3730 return PTR_ERR(ent);
3734 i_size_write(ent->d_inode, adev->rmmio_size);
3735 adev->debugfs_regs[i] = ent;
3741 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3745 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3746 if (adev->debugfs_regs[i]) {
3747 debugfs_remove(adev->debugfs_regs[i]);
3748 adev->debugfs_regs[i] = NULL;
3753 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3755 struct drm_info_node *node = (struct drm_info_node *) m->private;
3756 struct drm_device *dev = node->minor->dev;
3757 struct amdgpu_device *adev = dev->dev_private;
3760 /* hold on the scheduler */
3761 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3762 struct amdgpu_ring *ring = adev->rings[i];
3764 if (!ring || !ring->sched.thread)
3766 kthread_park(ring->sched.thread);
3769 seq_printf(m, "run ib test:\n");
3770 r = amdgpu_ib_ring_tests(adev);
3772 seq_printf(m, "ib ring tests failed (%d).\n", r);
3774 seq_printf(m, "ib ring tests passed.\n");
3776 /* go on the scheduler */
3777 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3778 struct amdgpu_ring *ring = adev->rings[i];
3780 if (!ring || !ring->sched.thread)
3782 kthread_unpark(ring->sched.thread);
3788 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
3789 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
3792 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3794 return amdgpu_debugfs_add_files(adev,
3795 amdgpu_debugfs_test_ib_ring_list, 1);
3798 int amdgpu_debugfs_init(struct drm_minor *minor)
3803 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3807 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3811 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }