drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  38 {
  39         if (adev->pp_enabled)
  40                 /* TODO */
  41                 return;
  42
  43         if (adev->pm.dpm_enabled) {
  44                 mutex_lock(&adev->pm.mutex);
  45                 if (power_supply_is_system_supplied() > 0)
  46                         adev->pm.dpm.ac_power = true;
  47                 else
  48                         adev->pm.dpm.ac_power = false;
  49                 if (adev->pm.funcs->enable_bapm)
  50                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  51                 mutex_unlock(&adev->pm.mutex);
  52         }
  53 }
  54
  55 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  56                                     struct device_attribute *attr,
  57                                     char *buf)
  58 {
  59         struct drm_device *ddev = dev_get_drvdata(dev);
  60         struct amdgpu_device *adev = ddev->dev_private;
  61         enum amd_pm_state_type pm;
  62
  63         if (adev->pp_enabled) {
  64                 pm = amdgpu_dpm_get_current_power_state(adev);
  65         } else
  66                 pm = adev->pm.dpm.user_state;
  67
  68         return snprintf(buf, PAGE_SIZE, "%s\n",
  69                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  70                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  71 }
  72
  73 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  74                                     struct device_attribute *attr,
  75                                     const char *buf,
  76                                     size_t count)
  77 {
  78         struct drm_device *ddev = dev_get_drvdata(dev);
  79         struct amdgpu_device *adev = ddev->dev_private;
  80         enum amd_pm_state_type  state;
  81
  82         if (strncmp("battery", buf, strlen("battery")) == 0)
  83                 state = POWER_STATE_TYPE_BATTERY;
  84         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
  85                 state = POWER_STATE_TYPE_BALANCED;
  86         else if (strncmp("performance", buf, strlen("performance")) == 0)
  87                 state = POWER_STATE_TYPE_PERFORMANCE;
  88         else {
  89                 count = -EINVAL;
  90                 goto fail;
  91         }
  92
  93         if (adev->pp_enabled) {
  94                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
  95         } else {
  96                 mutex_lock(&adev->pm.mutex);
  97                 adev->pm.dpm.user_state = state;
  98                 mutex_unlock(&adev->pm.mutex);
  99
 100                 /* Can't set dpm state when the card is off */
 101                 if (!(adev->flags & AMD_IS_PX) ||
 102                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 103                         amdgpu_pm_compute_clocks(adev);
 104         }
 105 fail:
 106         return count;
 107 }
 108
 109 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 110                                                 struct device_attribute *attr,
 111                                                                 char *buf)
 112 {
 113         struct drm_device *ddev = dev_get_drvdata(dev);
 114         struct amdgpu_device *adev = ddev->dev_private;
 115
 116         if  ((adev->flags & AMD_IS_PX) &&
 117              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 118                 return snprintf(buf, PAGE_SIZE, "off\n");
 119
 120         if (adev->pp_enabled) {
 121                 enum amd_dpm_forced_level level;
 122
 123                 level = amdgpu_dpm_get_performance_level(adev);
 124                 return snprintf(buf, PAGE_SIZE, "%s\n",
 125                                 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 126                                 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 127                                 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 128                                 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
 129         } else {
 130                 enum amdgpu_dpm_forced_level level;
 131
 132                 level = adev->pm.dpm.forced_level;
 133                 return snprintf(buf, PAGE_SIZE, "%s\n",
 134                                 (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 135                                 (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 136         }
 137 }
 138
 139 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 140                                                        struct device_attribute *attr,
 141                                                        const char *buf,
 142                                                        size_t count)
 143 {
 144         struct drm_device *ddev = dev_get_drvdata(dev);
 145         struct amdgpu_device *adev = ddev->dev_private;
 146         enum amdgpu_dpm_forced_level level;
 147         int ret = 0;
 148
 149         /* Can't force performance level when the card is off */
 150         if  ((adev->flags & AMD_IS_PX) &&
 151              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 152                 return -EINVAL;
 153
 154         if (strncmp("low", buf, strlen("low")) == 0) {
 155                 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
 156         } else if (strncmp("high", buf, strlen("high")) == 0) {
 157                 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
 158         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 159                 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
 160         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 161                 level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
 162         } else {
 163                 count = -EINVAL;
 164                 goto fail;
 165         }
 166
 167         if (adev->pp_enabled)
 168                 amdgpu_dpm_force_performance_level(adev, level);
 169         else {
 170                 mutex_lock(&adev->pm.mutex);
 171                 if (adev->pm.dpm.thermal_active) {
 172                         count = -EINVAL;
 173                         mutex_unlock(&adev->pm.mutex);
 174                         goto fail;
 175                 }
 176                 ret = amdgpu_dpm_force_performance_level(adev, level);
 177                 if (ret)
 178                         count = -EINVAL;
 179                 else
 180                         adev->pm.dpm.forced_level = level;
 181                 mutex_unlock(&adev->pm.mutex);
 182         }
 183 fail:
 184         return count;
 185 }
 186
 187 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 188                 struct device_attribute *attr,
 189                 char *buf)
 190 {
 191         struct drm_device *ddev = dev_get_drvdata(dev);
 192         struct amdgpu_device *adev = ddev->dev_private;
 193         struct pp_states_info data;
 194         int i, buf_len;
 195
 196         if (adev->pp_enabled)
 197                 amdgpu_dpm_get_pp_num_states(adev, &data);
 198
 199         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 200         for (i = 0; i < data.nums; i++)
 201                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 202                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 203                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 204                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 205                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 206
 207         return buf_len;
 208 }
 209
 210 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 211                 struct device_attribute *attr,
 212                 char *buf)
 213 {
 214         struct drm_device *ddev = dev_get_drvdata(dev);
 215         struct amdgpu_device *adev = ddev->dev_private;
 216         struct pp_states_info data;
 217         enum amd_pm_state_type pm = 0;
 218         int i = 0;
 219
 220         if (adev->pp_enabled) {
 221
 222                 pm = amdgpu_dpm_get_current_power_state(adev);
 223                 amdgpu_dpm_get_pp_num_states(adev, &data);
 224
 225                 for (i = 0; i < data.nums; i++) {
 226                         if (pm == data.states[i])
 227                                 break;
 228                 }
 229
 230                 if (i == data.nums)
 231                         i = -EINVAL;
 232         }
 233
 234         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 235 }
 236
 237 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 238                 struct device_attribute *attr,
 239                 char *buf)
 240 {
 241         struct drm_device *ddev = dev_get_drvdata(dev);
 242         struct amdgpu_device *adev = ddev->dev_private;
 243         struct pp_states_info data;
 244         enum amd_pm_state_type pm = 0;
 245         int i;
 246
 247         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 248                 pm = amdgpu_dpm_get_current_power_state(adev);
 249                 amdgpu_dpm_get_pp_num_states(adev, &data);
 250
 251                 for (i = 0; i < data.nums; i++) {
 252                         if (pm == data.states[i])
 253                                 break;
 254                 }
 255
 256                 if (i == data.nums)
 257                         i = -EINVAL;
 258
 259                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 260
 261         } else
 262                 return snprintf(buf, PAGE_SIZE, "\n");
 263 }
 264
 265 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 266                 struct device_attribute *attr,
 267                 const char *buf,
 268                 size_t count)
 269 {
 270         struct drm_device *ddev = dev_get_drvdata(dev);
 271         struct amdgpu_device *adev = ddev->dev_private;
 272         enum amd_pm_state_type state = 0;
 273         unsigned long idx;
 274         int ret;
 275
 276         if (strlen(buf) == 1)
 277                 adev->pp_force_state_enabled = false;
 278         else if (adev->pp_enabled) {
 279                 struct pp_states_info data;
 280
 281                 ret = kstrtoul(buf, 0, &idx);
 282                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 283                         count = -EINVAL;
 284                         goto fail;
 285                 }
 286
 287                 amdgpu_dpm_get_pp_num_states(adev, &data);
 288                 state = data.states[idx];
 289                 /* only set user selected power states */
 290                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 291                     state != POWER_STATE_TYPE_DEFAULT) {
 292                         amdgpu_dpm_dispatch_task(adev,
 293                                         AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 294                         adev->pp_force_state_enabled = true;
 295                 }
 296         }
 297 fail:
 298         return count;
 299 }
 300
 301 static ssize_t amdgpu_get_pp_table(struct device *dev,
 302                 struct device_attribute *attr,
 303                 char *buf)
 304 {
 305         struct drm_device *ddev = dev_get_drvdata(dev);
 306         struct amdgpu_device *adev = ddev->dev_private;
 307         char *table = NULL;
 308         int size, i;
 309
 310         if (adev->pp_enabled)
 311                 size = amdgpu_dpm_get_pp_table(adev, &table);
 312         else
 313                 return 0;
 314
 315         if (size >= PAGE_SIZE)
 316                 size = PAGE_SIZE - 1;
 317
 318         for (i = 0; i < size; i++) {
 319                 sprintf(buf + i, "%02x", table[i]);
 320         }
 321         sprintf(buf + i, "\n");
 322
 323         return size;
 324 }
 325
 326 static ssize_t amdgpu_set_pp_table(struct device *dev,
 327                 struct device_attribute *attr,
 328                 const char *buf,
 329                 size_t count)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = ddev->dev_private;
 333
 334         if (adev->pp_enabled)
 335                 amdgpu_dpm_set_pp_table(adev, buf, count);
 336
 337         return count;
 338 }
 339
 340 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 341                 struct device_attribute *attr,
 342                 char *buf)
 343 {
 344         struct drm_device *ddev = dev_get_drvdata(dev);
 345         struct amdgpu_device *adev = ddev->dev_private;
 346         ssize_t size = 0;
 347
 348         if (adev->pp_enabled)
 349                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 350
 351         return size;
 352 }
 353
 354 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 355                 struct device_attribute *attr,
 356                 const char *buf,
 357                 size_t count)
 358 {
 359         struct drm_device *ddev = dev_get_drvdata(dev);
 360         struct amdgpu_device *adev = ddev->dev_private;
 361         int ret;
 362         long level;
 363         uint32_t i, mask = 0;
 364         char sub_str[2];
 365
 366         for (i = 0; i < strlen(buf) - 1; i++) {
 367                 sub_str[0] = *(buf + i);
 368                 sub_str[1] = '\0';
 369                 ret = kstrtol(sub_str, 0, &level);
 370
 371                 if (ret) {
 372                         count = -EINVAL;
 373                         goto fail;
 374                 }
 375                 mask |= 1 << level;
 376         }
 377
 378         if (adev->pp_enabled)
 379                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 380 fail:
 381         return count;
 382 }
 383
 384 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 385                 struct device_attribute *attr,
 386                 char *buf)
 387 {
 388         struct drm_device *ddev = dev_get_drvdata(dev);
 389         struct amdgpu_device *adev = ddev->dev_private;
 390         ssize_t size = 0;
 391
 392         if (adev->pp_enabled)
 393                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 394
 395         return size;
 396 }
 397
 398 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 399                 struct device_attribute *attr,
 400                 const char *buf,
 401                 size_t count)
 402 {
 403         struct drm_device *ddev = dev_get_drvdata(dev);
 404         struct amdgpu_device *adev = ddev->dev_private;
 405         int ret;
 406         long level;
 407         uint32_t i, mask = 0;
 408         char sub_str[2];
 409
 410         for (i = 0; i < strlen(buf) - 1; i++) {
 411                 sub_str[0] = *(buf + i);
 412                 sub_str[1] = '\0';
 413                 ret = kstrtol(sub_str, 0, &level);
 414
 415                 if (ret) {
 416                         count = -EINVAL;
 417                         goto fail;
 418                 }
 419                 mask |= 1 << level;
 420         }
 421
 422         if (adev->pp_enabled)
 423                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 424 fail:
 425         return count;
 426 }
 427
 428 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 429                 struct device_attribute *attr,
 430                 char *buf)
 431 {
 432         struct drm_device *ddev = dev_get_drvdata(dev);
 433         struct amdgpu_device *adev = ddev->dev_private;
 434         ssize_t size = 0;
 435
 436         if (adev->pp_enabled)
 437                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 438
 439         return size;
 440 }
 441
 442 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 443                 struct device_attribute *attr,
 444                 const char *buf,
 445                 size_t count)
 446 {
 447         struct drm_device *ddev = dev_get_drvdata(dev);
 448         struct amdgpu_device *adev = ddev->dev_private;
 449         int ret;
 450         long level;
 451         uint32_t i, mask = 0;
 452         char sub_str[2];
 453
 454         for (i = 0; i < strlen(buf) - 1; i++) {
 455                 sub_str[0] = *(buf + i);
 456                 sub_str[1] = '\0';
 457                 ret = kstrtol(sub_str, 0, &level);
 458
 459                 if (ret) {
 460                         count = -EINVAL;
 461                         goto fail;
 462                 }
 463                 mask |= 1 << level;
 464         }
 465
 466         if (adev->pp_enabled)
 467                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 468 fail:
 469         return count;
 470 }
 471
 472 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 473 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 474                    amdgpu_get_dpm_forced_performance_level,
 475                    amdgpu_set_dpm_forced_performance_level);
 476 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 477 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 478 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 479                 amdgpu_get_pp_force_state,
 480                 amdgpu_set_pp_force_state);
 481 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 482                 amdgpu_get_pp_table,
 483                 amdgpu_set_pp_table);
 484 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 485                 amdgpu_get_pp_dpm_sclk,
 486                 amdgpu_set_pp_dpm_sclk);
 487 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 488                 amdgpu_get_pp_dpm_mclk,
 489                 amdgpu_set_pp_dpm_mclk);
 490 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 491                 amdgpu_get_pp_dpm_pcie,
 492                 amdgpu_set_pp_dpm_pcie);
 493
 494 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 495                                       struct device_attribute *attr,
 496                                       char *buf)
 497 {
 498         struct amdgpu_device *adev = dev_get_drvdata(dev);
 499         struct drm_device *ddev = adev->ddev;
 500         int temp;
 501
 502         /* Can't get temperature when the card is off */
 503         if  ((adev->flags & AMD_IS_PX) &&
 504              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 505                 return -EINVAL;
 506
 507         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 508                 temp = 0;
 509         else
 510                 temp = amdgpu_dpm_get_temperature(adev);
 511
 512         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 513 }
 514
 515 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 516                                              struct device_attribute *attr,
 517                                              char *buf)
 518 {
 519         struct amdgpu_device *adev = dev_get_drvdata(dev);
 520         int hyst = to_sensor_dev_attr(attr)->index;
 521         int temp;
 522
 523         if (hyst)
 524                 temp = adev->pm.dpm.thermal.min_temp;
 525         else
 526                 temp = adev->pm.dpm.thermal.max_temp;
 527
 528         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 529 }
 530
 531 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 532                                             struct device_attribute *attr,
 533                                             char *buf)
 534 {
 535         struct amdgpu_device *adev = dev_get_drvdata(dev);
 536         u32 pwm_mode = 0;
 537
 538         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 539                 return -EINVAL;
 540
 541         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 542
 543         /* never 0 (full-speed), fuse or smc-controlled always */
 544         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 545 }
 546
 547 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 548                                             struct device_attribute *attr,
 549                                             const char *buf,
 550                                             size_t count)
 551 {
 552         struct amdgpu_device *adev = dev_get_drvdata(dev);
 553         int err;
 554         int value;
 555
 556         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 557                 return -EINVAL;
 558
 559         err = kstrtoint(buf, 10, &value);
 560         if (err)
 561                 return err;
 562
 563         switch (value) {
 564         case 1: /* manual, percent-based */
 565                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 566                 break;
 567         default: /* disable */
 568                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 569                 break;
 570         }
 571
 572         return count;
 573 }
 574
 575 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 576                                          struct device_attribute *attr,
 577                                          char *buf)
 578 {
 579         return sprintf(buf, "%i\n", 0);
 580 }
 581
 582 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 583                                          struct device_attribute *attr,
 584                                          char *buf)
 585 {
 586         return sprintf(buf, "%i\n", 255);
 587 }
 588
 589 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 590                                      struct device_attribute *attr,
 591                                      const char *buf, size_t count)
 592 {
 593         struct amdgpu_device *adev = dev_get_drvdata(dev);
 594         int err;
 595         u32 value;
 596
 597         err = kstrtou32(buf, 10, &value);
 598         if (err)
 599                 return err;
 600
 601         value = (value * 100) / 255;
 602
 603         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 604         if (err)
 605                 return err;
 606
 607         return count;
 608 }
 609
 610 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 611                                      struct device_attribute *attr,
 612                                      char *buf)
 613 {
 614         struct amdgpu_device *adev = dev_get_drvdata(dev);
 615         int err;
 616         u32 speed;
 617
 618         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 619         if (err)
 620                 return err;
 621
 622         speed = (speed * 255) / 100;
 623
 624         return sprintf(buf, "%i\n", speed);
 625 }
 626
 627 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 628 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 629 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 630 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 631 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 632 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 633 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 634
 635 static struct attribute *hwmon_attributes[] = {
 636         &sensor_dev_attr_temp1_input.dev_attr.attr,
 637         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 638         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 639         &sensor_dev_attr_pwm1.dev_attr.attr,
 640         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 641         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 642         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 643         NULL
 644 };
 645
 646 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 647                                         struct attribute *attr, int index)
 648 {
 649         struct device *dev = kobj_to_dev(kobj);
 650         struct amdgpu_device *adev = dev_get_drvdata(dev);
 651         umode_t effective_mode = attr->mode;
 652
 653         /* Skip limit attributes if DPM is not enabled */
 654         if (!adev->pm.dpm_enabled &&
 655             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 656              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 657              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 658              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 659              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 660              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 661                 return 0;
 662
 663         if (adev->pp_enabled)
 664                 return effective_mode;
 665
 666         /* Skip fan attributes if fan is not present */
 667         if (adev->pm.no_fan &&
 668             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 669              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 670              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 671              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 672                 return 0;
 673
 674         /* mask fan attributes if we have no bindings for this asic to expose */
 675         if ((!adev->pm.funcs->get_fan_speed_percent &&
 676              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 677             (!adev->pm.funcs->get_fan_control_mode &&
 678              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 679                 effective_mode &= ~S_IRUGO;
 680
 681         if ((!adev->pm.funcs->set_fan_speed_percent &&
 682              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 683             (!adev->pm.funcs->set_fan_control_mode &&
 684              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 685                 effective_mode &= ~S_IWUSR;
 686
 687         /* hide max/min values if we can't both query and manage the fan */
 688         if ((!adev->pm.funcs->set_fan_speed_percent &&
 689              !adev->pm.funcs->get_fan_speed_percent) &&
 690             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 691              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 692                 return 0;
 693
 694         return effective_mode;
 695 }
 696
 697 static const struct attribute_group hwmon_attrgroup = {
 698         .attrs = hwmon_attributes,
 699         .is_visible = hwmon_attributes_visible,
 700 };
 701
 702 static const struct attribute_group *hwmon_groups[] = {
 703         &hwmon_attrgroup,
 704         NULL
 705 };
 706
 707 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 708 {
 709         struct amdgpu_device *adev =
 710                 container_of(work, struct amdgpu_device,
 711                              pm.dpm.thermal.work);
 712         /* switch to the thermal state */
 713         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 714
 715         if (!adev->pm.dpm_enabled)
 716                 return;
 717
 718         if (adev->pm.funcs->get_temperature) {
 719                 int temp = amdgpu_dpm_get_temperature(adev);
 720
 721                 if (temp < adev->pm.dpm.thermal.min_temp)
 722                         /* switch back the user state */
 723                         dpm_state = adev->pm.dpm.user_state;
 724         } else {
 725                 if (adev->pm.dpm.thermal.high_to_low)
 726                         /* switch back the user state */
 727                         dpm_state = adev->pm.dpm.user_state;
 728         }
 729         mutex_lock(&adev->pm.mutex);
 730         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 731                 adev->pm.dpm.thermal_active = true;
 732         else
 733                 adev->pm.dpm.thermal_active = false;
 734         adev->pm.dpm.state = dpm_state;
 735         mutex_unlock(&adev->pm.mutex);
 736
 737         amdgpu_pm_compute_clocks(adev);
 738 }
 739
 740 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 741                                                      enum amd_pm_state_type dpm_state)
 742 {
 743         int i;
 744         struct amdgpu_ps *ps;
 745         u32 ui_class;
 746         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 747                 true : false;
 748
 749         /* check if the vblank period is too short to adjust the mclk */
 750         if (single_display && adev->pm.funcs->vblank_too_short) {
 751                 if (amdgpu_dpm_vblank_too_short(adev))
 752                         single_display = false;
 753         }
 754
 755         /* certain older asics have a separare 3D performance state,
 756          * so try that first if the user selected performance
 757          */
 758         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 759                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 760         /* balanced states don't exist at the moment */
 761         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 762                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 763
 764 restart_search:
 765         /* Pick the best power state based on current conditions */
 766         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 767                 ps = &adev->pm.dpm.ps[i];
 768                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 769                 switch (dpm_state) {
 770                 /* user states */
 771                 case POWER_STATE_TYPE_BATTERY:
 772                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 773                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 774                                         if (single_display)
 775                                                 return ps;
 776                                 } else
 777                                         return ps;
 778                         }
 779                         break;
 780                 case POWER_STATE_TYPE_BALANCED:
 781                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 782                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 783                                         if (single_display)
 784                                                 return ps;
 785                                 } else
 786                                         return ps;
 787                         }
 788                         break;
 789                 case POWER_STATE_TYPE_PERFORMANCE:
 790                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 791                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 792                                         if (single_display)
 793                                                 return ps;
 794                                 } else
 795                                         return ps;
 796                         }
 797                         break;
 798                 /* internal states */
 799                 case POWER_STATE_TYPE_INTERNAL_UVD:
 800                         if (adev->pm.dpm.uvd_ps)
 801                                 return adev->pm.dpm.uvd_ps;
 802                         else
 803                                 break;
 804                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 805                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 806                                 return ps;
 807                         break;
 808                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 809                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 810                                 return ps;
 811                         break;
 812                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 813                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 814                                 return ps;
 815                         break;
 816                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 817                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 818                                 return ps;
 819                         break;
 820                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 821                         return adev->pm.dpm.boot_ps;
 822                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 823                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 824                                 return ps;
 825                         break;
 826                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 827                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 828                                 return ps;
 829                         break;
 830                 case POWER_STATE_TYPE_INTERNAL_ULV:
 831                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 832                                 return ps;
 833                         break;
 834                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 835                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 836                                 return ps;
 837                         break;
 838                 default:
 839                         break;
 840                 }
 841         }
 842         /* use a fallback state if we didn't match */
 843         switch (dpm_state) {
 844         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 845                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 846                 goto restart_search;
 847         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 848         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 849         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 850                 if (adev->pm.dpm.uvd_ps) {
 851                         return adev->pm.dpm.uvd_ps;
 852                 } else {
 853                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 854                         goto restart_search;
 855                 }
 856         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 857                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 858                 goto restart_search;
 859         case POWER_STATE_TYPE_INTERNAL_ACPI:
 860                 dpm_state = POWER_STATE_TYPE_BATTERY;
 861                 goto restart_search;
 862         case POWER_STATE_TYPE_BATTERY:
 863         case POWER_STATE_TYPE_BALANCED:
 864         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 865                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 866                 goto restart_search;
 867         default:
 868                 break;
 869         }
 870
 871         return NULL;
 872 }
 873
 874 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 875 {
 876         int i;
 877         struct amdgpu_ps *ps;
 878         enum amd_pm_state_type dpm_state;
 879         int ret;
 880
 881         /* if dpm init failed */
 882         if (!adev->pm.dpm_enabled)
 883                 return;
 884
 885         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
 886                 /* add other state override checks here */
 887                 if ((!adev->pm.dpm.thermal_active) &&
 888                     (!adev->pm.dpm.uvd_active))
 889                         adev->pm.dpm.state = adev->pm.dpm.user_state;
 890         }
 891         dpm_state = adev->pm.dpm.state;
 892
 893         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
 894         if (ps)
 895                 adev->pm.dpm.requested_ps = ps;
 896         else
 897                 return;
 898
 899         /* no need to reprogram if nothing changed unless we are on BTC+ */
 900         if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
 901                 /* vce just modifies an existing state so force a change */
 902                 if (ps->vce_active != adev->pm.dpm.vce_active)
 903                         goto force;
 904                 if (adev->flags & AMD_IS_APU) {
 905                         /* for APUs if the num crtcs changed but state is the same,
 906                          * all we need to do is update the display configuration.
 907                          */
 908                         if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
 909                                 /* update display watermarks based on new power state */
 910                                 amdgpu_display_bandwidth_update(adev);
 911                                 /* update displays */
 912                                 amdgpu_dpm_display_configuration_changed(adev);
 913                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 914                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 915                         }
 916                         return;
 917                 } else {
 918                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 919                          * nothing to do, if the num crtcs is > 1 and state is the same,
 920                          * update display configuration.
 921                          */
 922                         if (adev->pm.dpm.new_active_crtcs ==
 923                             adev->pm.dpm.current_active_crtcs) {
 924                                 return;
 925                         } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
 926                                    (adev->pm.dpm.new_active_crtc_count > 1)) {
 927                                 /* update display watermarks based on new power state */
 928                                 amdgpu_display_bandwidth_update(adev);
 929                                 /* update displays */
 930                                 amdgpu_dpm_display_configuration_changed(adev);
 931                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 932                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 933                                 return;
 934                         }
 935                 }
 936         }
 937
 938 force:
 939         if (amdgpu_dpm == 1) {
 940                 printk("switching from power state:\n");
 941                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
 942                 printk("switching to power state:\n");
 943                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
 944         }
 945
 946         /* update whether vce is active */
 947         ps->vce_active = adev->pm.dpm.vce_active;
 948
 949         ret = amdgpu_dpm_pre_set_power_state(adev);
 950         if (ret)
 951                 return;
 952
 953         /* update display watermarks based on new power state */
 954         amdgpu_display_bandwidth_update(adev);
 955
 956         /* wait for the rings to drain */
 957         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 958                 struct amdgpu_ring *ring = adev->rings[i];
 959                 if (ring && ring->ready)
 960                         amdgpu_fence_wait_empty(ring);
 961         }
 962
 963         /* program the new power state */
 964         amdgpu_dpm_set_power_state(adev);
 965
 966         /* update current power state */
 967         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
 968
 969         amdgpu_dpm_post_set_power_state(adev);
 970
 971         /* update displays */
 972         amdgpu_dpm_display_configuration_changed(adev);
 973
 974         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 975         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 976
 977         if (adev->pm.funcs->force_performance_level) {
 978                 if (adev->pm.dpm.thermal_active) {
 979                         enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
 980                         /* force low perf level for thermal */
 981                         amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
 982                         /* save the user's level */
 983                         adev->pm.dpm.forced_level = level;
 984                 } else {
 985                         /* otherwise, user selected level */
 986                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
 987                 }
 988         }
 989 }
 990
 991 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 992 {
 993         if (adev->pp_enabled)
 994                 amdgpu_dpm_powergate_uvd(adev, !enable);
 995         else {
 996                 if (adev->pm.funcs->powergate_uvd) {
 997                         mutex_lock(&adev->pm.mutex);
 998                         /* enable/disable UVD */
 999                         amdgpu_dpm_powergate_uvd(adev, !enable);
1000                         mutex_unlock(&adev->pm.mutex);
1001                 } else {
1002                         if (enable) {
1003                                 mutex_lock(&adev->pm.mutex);
1004                                 adev->pm.dpm.uvd_active = true;
1005                                 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1006                                 mutex_unlock(&adev->pm.mutex);
1007                         } else {
1008                                 mutex_lock(&adev->pm.mutex);
1009                                 adev->pm.dpm.uvd_active = false;
1010                                 mutex_unlock(&adev->pm.mutex);
1011                         }
1012                         amdgpu_pm_compute_clocks(adev);
1013                 }
1014
1015         }
1016 }
1017
1018 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1019 {
1020         if (adev->pp_enabled)
1021                 amdgpu_dpm_powergate_vce(adev, !enable);
1022         else {
1023                 if (adev->pm.funcs->powergate_vce) {
1024                         mutex_lock(&adev->pm.mutex);
1025                         amdgpu_dpm_powergate_vce(adev, !enable);
1026                         mutex_unlock(&adev->pm.mutex);
1027                 } else {
1028                         if (enable) {
1029                                 mutex_lock(&adev->pm.mutex);
1030                                 adev->pm.dpm.vce_active = true;
1031                                 /* XXX select vce level based on ring/task */
1032                                 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
1033                                 mutex_unlock(&adev->pm.mutex);
1034                         } else {
1035                                 mutex_lock(&adev->pm.mutex);
1036                                 adev->pm.dpm.vce_active = false;
1037                                 mutex_unlock(&adev->pm.mutex);
1038                         }
1039                         amdgpu_pm_compute_clocks(adev);
1040                 }
1041         }
1042 }
1043
1044 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1045 {
1046         int i;
1047
1048         if (adev->pp_enabled)
1049                 /* TO DO */
1050                 return;
1051
1052         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1053                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1054
1055 }
1056
1057 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1058 {
1059         int ret;
1060
1061         if (adev->pm.sysfs_initialized)
1062                 return 0;
1063
1064         if (!adev->pp_enabled) {
1065                 if (adev->pm.funcs->get_temperature == NULL)
1066                         return 0;
1067         }
1068
1069         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1070                                                                    DRIVER_NAME, adev,
1071                                                                    hwmon_groups);
1072         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1073                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1074                 dev_err(adev->dev,
1075                         "Unable to register hwmon device: %d\n", ret);
1076                 return ret;
1077         }
1078
1079         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1080         if (ret) {
1081                 DRM_ERROR("failed to create device file for dpm state\n");
1082                 return ret;
1083         }
1084         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1085         if (ret) {
1086                 DRM_ERROR("failed to create device file for dpm state\n");
1087                 return ret;
1088         }
1089
1090         if (adev->pp_enabled) {
1091                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1092                 if (ret) {
1093                         DRM_ERROR("failed to create device file pp_num_states\n");
1094                         return ret;
1095                 }
1096                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1097                 if (ret) {
1098                         DRM_ERROR("failed to create device file pp_cur_state\n");
1099                         return ret;
1100                 }
1101                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1102                 if (ret) {
1103                         DRM_ERROR("failed to create device file pp_force_state\n");
1104                         return ret;
1105                 }
1106                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1107                 if (ret) {
1108                         DRM_ERROR("failed to create device file pp_table\n");
1109                         return ret;
1110                 }
1111                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1112                 if (ret) {
1113                         DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1114                         return ret;
1115                 }
1116                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1117                 if (ret) {
1118                         DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1119                         return ret;
1120                 }
1121                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1122                 if (ret) {
1123                         DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1124                         return ret;
1125                 }
1126         }
1127         ret = amdgpu_debugfs_pm_init(adev);
1128         if (ret) {
1129                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1130                 return ret;
1131         }
1132
1133         adev->pm.sysfs_initialized = true;
1134
1135         return 0;
1136 }
1137
1138 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1139 {
1140         if (adev->pm.int_hwmon_dev)
1141                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1142         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1143         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1144         if (adev->pp_enabled) {
1145                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1146                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1147                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1148                 device_remove_file(adev->dev, &dev_attr_pp_table);
1149                 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1150                 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1151                 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1152         }
1153 }
1154
1155 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1156 {
1157         struct drm_device *ddev = adev->ddev;
1158         struct drm_crtc *crtc;
1159         struct amdgpu_crtc *amdgpu_crtc;
1160
1161         if (!adev->pm.dpm_enabled)
1162                 return;
1163
1164         if (adev->pp_enabled) {
1165                 int i = 0;
1166
1167                 amdgpu_display_bandwidth_update(adev);
1168                 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1169                         struct amdgpu_ring *ring = adev->rings[i];
1170                         if (ring && ring->ready)
1171                                 amdgpu_fence_wait_empty(ring);
1172                 }
1173
1174                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1175         } else {
1176                 mutex_lock(&adev->pm.mutex);
1177                 adev->pm.dpm.new_active_crtcs = 0;
1178                 adev->pm.dpm.new_active_crtc_count = 0;
1179                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1180                         list_for_each_entry(crtc,
1181                                             &ddev->mode_config.crtc_list, head) {
1182                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1183                                 if (crtc->enabled) {
1184                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1185                                         adev->pm.dpm.new_active_crtc_count++;
1186                                 }
1187                         }
1188                 }
1189                 /* update battery/ac status */
1190                 if (power_supply_is_system_supplied() > 0)
1191                         adev->pm.dpm.ac_power = true;
1192                 else
1193                         adev->pm.dpm.ac_power = false;
1194
1195                 amdgpu_dpm_change_power_state_locked(adev);
1196
1197                 mutex_unlock(&adev->pm.mutex);
1198         }
1199 }
1200
1201 /*
1202  * Debugfs info
1203  */
1204 #if defined(CONFIG_DEBUG_FS)
1205
1206 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1207 {
1208         struct drm_info_node *node = (struct drm_info_node *) m->private;
1209         struct drm_device *dev = node->minor->dev;
1210         struct amdgpu_device *adev = dev->dev_private;
1211         struct drm_device *ddev = adev->ddev;
1212
1213         if (!adev->pm.dpm_enabled) {
1214                 seq_printf(m, "dpm not enabled\n");
1215                 return 0;
1216         }
1217         if  ((adev->flags & AMD_IS_PX) &&
1218              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1219                 seq_printf(m, "PX asic powered off\n");
1220         } else if (adev->pp_enabled) {
1221                 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1222         } else {
1223                 mutex_lock(&adev->pm.mutex);
1224                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1225                         amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1226                 else
1227                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1228                 mutex_unlock(&adev->pm.mutex);
1229         }
1230
1231         return 0;
1232 }
1233
1234 static const struct drm_info_list amdgpu_pm_info_list[] = {
1235         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1236 };
1237 #endif
1238
1239 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1240 {
1241 #if defined(CONFIG_DEBUG_FS)
1242         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1243 #else
1244         return 0;
1245 #endif
1246 }