drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <ttm/ttm_memory.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "bif/bif_4_1_d.h"
  48
  49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  50
  51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  53
  54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  55 {
  56         struct amdgpu_mman *mman;
  57         struct amdgpu_device *adev;
  58
  59         mman = container_of(bdev, struct amdgpu_mman, bdev);
  60         adev = container_of(mman, struct amdgpu_device, mman);
  61         return adev;
  62 }
  63
  64
  65 /*
  66  * Global memory.
  67  */
  68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  69 {
  70         return ttm_mem_global_init(ref->object);
  71 }
  72
  73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  74 {
  75         ttm_mem_global_release(ref->object);
  76 }
  77
  78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  79 {
  80         struct drm_global_reference *global_ref;
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         int r;
  84
  85         adev->mman.mem_global_referenced = false;
  86         global_ref = &adev->mman.mem_global_ref;
  87         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  88         global_ref->size = sizeof(struct ttm_mem_global);
  89         global_ref->init = &amdgpu_ttm_mem_global_init;
  90         global_ref->release = &amdgpu_ttm_mem_global_release;
  91         r = drm_global_item_ref(global_ref);
  92         if (r != 0) {
  93                 DRM_ERROR("Failed setting up TTM memory accounting "
  94                           "subsystem.\n");
  95                 return r;
  96         }
  97
  98         adev->mman.bo_global_ref.mem_glob =
  99                 adev->mman.mem_global_ref.object;
 100         global_ref = &adev->mman.bo_global_ref.ref;
 101         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 102         global_ref->size = sizeof(struct ttm_bo_global);
 103         global_ref->init = &ttm_bo_global_init;
 104         global_ref->release = &ttm_bo_global_release;
 105         r = drm_global_item_ref(global_ref);
 106         if (r != 0) {
 107                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 108                 drm_global_item_unref(&adev->mman.mem_global_ref);
 109                 return r;
 110         }
 111
 112         ring = adev->mman.buffer_funcs_ring;
 113         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 114         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 115                                   rq, amdgpu_sched_jobs);
 116         if (r != 0) {
 117                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 118                 drm_global_item_unref(&adev->mman.mem_global_ref);
 119                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 120                 return r;
 121         }
 122
 123         adev->mman.mem_global_referenced = true;
 124
 125         return 0;
 126 }
 127
 128 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 129 {
 130         if (adev->mman.mem_global_referenced) {
 131                 amd_sched_entity_fini(adev->mman.entity.sched,
 132                                       &adev->mman.entity);
 133                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 134                 drm_global_item_unref(&adev->mman.mem_global_ref);
 135                 adev->mman.mem_global_referenced = false;
 136         }
 137 }
 138
 139 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 140 {
 141         return 0;
 142 }
 143
 144 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 145                                 struct ttm_mem_type_manager *man)
 146 {
 147         struct amdgpu_device *adev;
 148
 149         adev = amdgpu_get_adev(bdev);
 150
 151         switch (type) {
 152         case TTM_PL_SYSTEM:
 153                 /* System memory */
 154                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 155                 man->available_caching = TTM_PL_MASK_CACHING;
 156                 man->default_caching = TTM_PL_FLAG_CACHED;
 157                 break;
 158         case TTM_PL_TT:
 159                 man->func = &ttm_bo_manager_func;
 160                 man->gpu_offset = adev->mc.gtt_start;
 161                 man->available_caching = TTM_PL_MASK_CACHING;
 162                 man->default_caching = TTM_PL_FLAG_CACHED;
 163                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 164                 break;
 165         case TTM_PL_VRAM:
 166                 /* "On-card" video ram */
 167                 man->func = &ttm_bo_manager_func;
 168                 man->gpu_offset = adev->mc.vram_start;
 169                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 170                              TTM_MEMTYPE_FLAG_MAPPABLE;
 171                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 172                 man->default_caching = TTM_PL_FLAG_WC;
 173                 break;
 174         case AMDGPU_PL_GDS:
 175         case AMDGPU_PL_GWS:
 176         case AMDGPU_PL_OA:
 177                 /* On-chip GDS memory*/
 178                 man->func = &ttm_bo_manager_func;
 179                 man->gpu_offset = 0;
 180                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 181                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 182                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 183                 break;
 184         default:
 185                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 186                 return -EINVAL;
 187         }
 188         return 0;
 189 }
 190
 191 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 192                                 struct ttm_placement *placement)
 193 {
 194         struct amdgpu_bo *rbo;
 195         static struct ttm_place placements = {
 196                 .fpfn = 0,
 197                 .lpfn = 0,
 198                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 199         };
 200
 201         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 202                 placement->placement = &placements;
 203                 placement->busy_placement = &placements;
 204                 placement->num_placement = 1;
 205                 placement->num_busy_placement = 1;
 206                 return;
 207         }
 208         rbo = container_of(bo, struct amdgpu_bo, tbo);
 209         switch (bo->mem.mem_type) {
 210         case TTM_PL_VRAM:
 211                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 212                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 213                 else
 214                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 215                 break;
 216         case TTM_PL_TT:
 217         default:
 218                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 219         }
 220         *placement = rbo->placement;
 221 }
 222
 223 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 224 {
 225         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 226
 227         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 228                 return -EPERM;
 229         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 230 }
 231
 232 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 233                              struct ttm_mem_reg *new_mem)
 234 {
 235         struct ttm_mem_reg *old_mem = &bo->mem;
 236
 237         BUG_ON(old_mem->mm_node != NULL);
 238         *old_mem = *new_mem;
 239         new_mem->mm_node = NULL;
 240 }
 241
 242 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 243                         bool evict, bool no_wait_gpu,
 244                         struct ttm_mem_reg *new_mem,
 245                         struct ttm_mem_reg *old_mem)
 246 {
 247         struct amdgpu_device *adev;
 248         struct amdgpu_ring *ring;
 249         uint64_t old_start, new_start;
 250         struct fence *fence;
 251         int r;
 252
 253         adev = amdgpu_get_adev(bo->bdev);
 254         ring = adev->mman.buffer_funcs_ring;
 255         old_start = old_mem->start << PAGE_SHIFT;
 256         new_start = new_mem->start << PAGE_SHIFT;
 257
 258         switch (old_mem->mem_type) {
 259         case TTM_PL_VRAM:
 260         case TTM_PL_TT:
 261                 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
 262                 break;
 263         default:
 264                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 265                 return -EINVAL;
 266         }
 267         switch (new_mem->mem_type) {
 268         case TTM_PL_VRAM:
 269         case TTM_PL_TT:
 270                 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
 271                 break;
 272         default:
 273                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 274                 return -EINVAL;
 275         }
 276         if (!ring->ready) {
 277                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 278                 return -EINVAL;
 279         }
 280
 281         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 282
 283         r = amdgpu_copy_buffer(ring, old_start, new_start,
 284                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 285                                bo->resv, &fence);
 286         if (r)
 287                 return r;
 288
 289         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 290         fence_put(fence);
 291         return r;
 292 }
 293
 294 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 295                                 bool evict, bool interruptible,
 296                                 bool no_wait_gpu,
 297                                 struct ttm_mem_reg *new_mem)
 298 {
 299         struct amdgpu_device *adev;
 300         struct ttm_mem_reg *old_mem = &bo->mem;
 301         struct ttm_mem_reg tmp_mem;
 302         struct ttm_place placements;
 303         struct ttm_placement placement;
 304         int r;
 305
 306         adev = amdgpu_get_adev(bo->bdev);
 307         tmp_mem = *new_mem;
 308         tmp_mem.mm_node = NULL;
 309         placement.num_placement = 1;
 310         placement.placement = &placements;
 311         placement.num_busy_placement = 1;
 312         placement.busy_placement = &placements;
 313         placements.fpfn = 0;
 314         placements.lpfn = 0;
 315         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 316         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 317                              interruptible, no_wait_gpu);
 318         if (unlikely(r)) {
 319                 return r;
 320         }
 321
 322         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 323         if (unlikely(r)) {
 324                 goto out_cleanup;
 325         }
 326
 327         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 328         if (unlikely(r)) {
 329                 goto out_cleanup;
 330         }
 331         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 332         if (unlikely(r)) {
 333                 goto out_cleanup;
 334         }
 335         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 336 out_cleanup:
 337         ttm_bo_mem_put(bo, &tmp_mem);
 338         return r;
 339 }
 340
 341 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 342                                 bool evict, bool interruptible,
 343                                 bool no_wait_gpu,
 344                                 struct ttm_mem_reg *new_mem)
 345 {
 346         struct amdgpu_device *adev;
 347         struct ttm_mem_reg *old_mem = &bo->mem;
 348         struct ttm_mem_reg tmp_mem;
 349         struct ttm_placement placement;
 350         struct ttm_place placements;
 351         int r;
 352
 353         adev = amdgpu_get_adev(bo->bdev);
 354         tmp_mem = *new_mem;
 355         tmp_mem.mm_node = NULL;
 356         placement.num_placement = 1;
 357         placement.placement = &placements;
 358         placement.num_busy_placement = 1;
 359         placement.busy_placement = &placements;
 360         placements.fpfn = 0;
 361         placements.lpfn = 0;
 362         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 363         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 364                              interruptible, no_wait_gpu);
 365         if (unlikely(r)) {
 366                 return r;
 367         }
 368         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 369         if (unlikely(r)) {
 370                 goto out_cleanup;
 371         }
 372         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 373         if (unlikely(r)) {
 374                 goto out_cleanup;
 375         }
 376 out_cleanup:
 377         ttm_bo_mem_put(bo, &tmp_mem);
 378         return r;
 379 }
 380
 381 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 382                         bool evict, bool interruptible,
 383                         bool no_wait_gpu,
 384                         struct ttm_mem_reg *new_mem)
 385 {
 386         struct amdgpu_device *adev;
 387         struct amdgpu_bo *abo;
 388         struct ttm_mem_reg *old_mem = &bo->mem;
 389         int r;
 390
 391         /* Can't move a pinned BO */
 392         abo = container_of(bo, struct amdgpu_bo, tbo);
 393         if (WARN_ON_ONCE(abo->pin_count > 0))
 394                 return -EINVAL;
 395
 396         adev = amdgpu_get_adev(bo->bdev);
 397
 398         /* remember the eviction */
 399         if (evict)
 400                 atomic64_inc(&adev->num_evictions);
 401
 402         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 403                 amdgpu_move_null(bo, new_mem);
 404                 return 0;
 405         }
 406         if ((old_mem->mem_type == TTM_PL_TT &&
 407              new_mem->mem_type == TTM_PL_SYSTEM) ||
 408             (old_mem->mem_type == TTM_PL_SYSTEM &&
 409              new_mem->mem_type == TTM_PL_TT)) {
 410                 /* bind is enough */
 411                 amdgpu_move_null(bo, new_mem);
 412                 return 0;
 413         }
 414         if (adev->mman.buffer_funcs == NULL ||
 415             adev->mman.buffer_funcs_ring == NULL ||
 416             !adev->mman.buffer_funcs_ring->ready) {
 417                 /* use memcpy */
 418                 goto memcpy;
 419         }
 420
 421         if (old_mem->mem_type == TTM_PL_VRAM &&
 422             new_mem->mem_type == TTM_PL_SYSTEM) {
 423                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 424                                         no_wait_gpu, new_mem);
 425         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 426                    new_mem->mem_type == TTM_PL_VRAM) {
 427                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 428                                             no_wait_gpu, new_mem);
 429         } else {
 430                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 431         }
 432
 433         if (r) {
 434 memcpy:
 435                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 436                 if (r) {
 437                         return r;
 438                 }
 439         }
 440
 441         /* update statistics */
 442         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 443         return 0;
 444 }
 445
 446 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 447 {
 448         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 449         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 450
 451         mem->bus.addr = NULL;
 452         mem->bus.offset = 0;
 453         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 454         mem->bus.base = 0;
 455         mem->bus.is_iomem = false;
 456         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 457                 return -EINVAL;
 458         switch (mem->mem_type) {
 459         case TTM_PL_SYSTEM:
 460                 /* system memory */
 461                 return 0;
 462         case TTM_PL_TT:
 463                 break;
 464         case TTM_PL_VRAM:
 465                 mem->bus.offset = mem->start << PAGE_SHIFT;
 466                 /* check if it's visible */
 467                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 468                         return -EINVAL;
 469                 mem->bus.base = adev->mc.aper_base;
 470                 mem->bus.is_iomem = true;
 471 #ifdef __alpha__
 472                 /*
 473                  * Alpha: use bus.addr to hold the ioremap() return,
 474                  * so we can modify bus.base below.
 475                  */
 476                 if (mem->placement & TTM_PL_FLAG_WC)
 477                         mem->bus.addr =
 478                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 479                                            mem->bus.size);
 480                 else
 481                         mem->bus.addr =
 482                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 483                                                 mem->bus.size);
 484
 485                 /*
 486                  * Alpha: Use just the bus offset plus
 487                  * the hose/domain memory base for bus.base.
 488                  * It then can be used to build PTEs for VRAM
 489                  * access, as done in ttm_bo_vm_fault().
 490                  */
 491                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 492                         adev->ddev->hose->dense_mem_base;
 493 #endif
 494                 break;
 495         default:
 496                 return -EINVAL;
 497         }
 498         return 0;
 499 }
 500
 501 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 502 {
 503 }
 504
 505 /*
 506  * TTM backend functions.
 507  */
 508 struct amdgpu_ttm_gup_task_list {
 509         struct list_head        list;
 510         struct task_struct      *task;
 511 };
 512
 513 struct amdgpu_ttm_tt {
 514         struct ttm_dma_tt       ttm;
 515         struct amdgpu_device    *adev;
 516         u64                     offset;
 517         uint64_t                userptr;
 518         struct mm_struct        *usermm;
 519         uint32_t                userflags;
 520         spinlock_t              guptasklock;
 521         struct list_head        guptasks;
 522         atomic_t                mmu_invalidations;
 523 };
 524
 525 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 526 {
 527         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 528         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 529         unsigned pinned = 0;
 530         int r;
 531
 532         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 533                 /* check that we only use anonymous memory
 534                    to prevent problems with writeback */
 535                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 536                 struct vm_area_struct *vma;
 537
 538                 vma = find_vma(gtt->usermm, gtt->userptr);
 539                 if (!vma || vma->vm_file || vma->vm_end < end)
 540                         return -EPERM;
 541         }
 542
 543         do {
 544                 unsigned num_pages = ttm->num_pages - pinned;
 545                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 546                 struct page **p = pages + pinned;
 547                 struct amdgpu_ttm_gup_task_list guptask;
 548
 549                 guptask.task = current;
 550                 spin_lock(&gtt->guptasklock);
 551                 list_add(&guptask.list, &gtt->guptasks);
 552                 spin_unlock(&gtt->guptasklock);
 553
 554                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
 555
 556                 spin_lock(&gtt->guptasklock);
 557                 list_del(&guptask.list);
 558                 spin_unlock(&gtt->guptasklock);
 559
 560                 if (r < 0)
 561                         goto release_pages;
 562
 563                 pinned += r;
 564
 565         } while (pinned < ttm->num_pages);
 566
 567         return 0;
 568
 569 release_pages:
 570         release_pages(pages, pinned, 0);
 571         return r;
 572 }
 573
 574 /* prepare the sg table with the user pages */
 575 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 576 {
 577         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 578         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 579         unsigned nents;
 580         int r;
 581
 582         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 583         enum dma_data_direction direction = write ?
 584                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 585
 586         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 587                                       ttm->num_pages << PAGE_SHIFT,
 588                                       GFP_KERNEL);
 589         if (r)
 590                 goto release_sg;
 591
 592         r = -ENOMEM;
 593         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 594         if (nents != ttm->sg->nents)
 595                 goto release_sg;
 596
 597         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 598                                          gtt->ttm.dma_address, ttm->num_pages);
 599
 600         return 0;
 601
 602 release_sg:
 603         kfree(ttm->sg);
 604         return r;
 605 }
 606
 607 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 608 {
 609         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 610         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 611         struct sg_page_iter sg_iter;
 612
 613         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 614         enum dma_data_direction direction = write ?
 615                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 616
 617         /* double check that we don't free the table twice */
 618         if (!ttm->sg->sgl)
 619                 return;
 620
 621         /* free the sg table and pages again */
 622         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 623
 624         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 625                 struct page *page = sg_page_iter_page(&sg_iter);
 626                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 627                         set_page_dirty(page);
 628
 629                 mark_page_accessed(page);
 630                 put_page(page);
 631         }
 632
 633         sg_free_table(ttm->sg);
 634 }
 635
 636 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 637                                    struct ttm_mem_reg *bo_mem)
 638 {
 639         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 640         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 641         int r;
 642
 643         if (gtt->userptr) {
 644                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 645                 if (r) {
 646                         DRM_ERROR("failed to pin userptr\n");
 647                         return r;
 648                 }
 649         }
 650         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 651         if (!ttm->num_pages) {
 652                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 653                      ttm->num_pages, bo_mem, ttm);
 654         }
 655
 656         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 657             bo_mem->mem_type == AMDGPU_PL_GWS ||
 658             bo_mem->mem_type == AMDGPU_PL_OA)
 659                 return -EINVAL;
 660
 661         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 662                 ttm->pages, gtt->ttm.dma_address, flags);
 663
 664         if (r) {
 665                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 666                           ttm->num_pages, (unsigned)gtt->offset);
 667                 return r;
 668         }
 669         return 0;
 670 }
 671
 672 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 673 {
 674         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 675
 676         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 677         if (gtt->adev->gart.ready)
 678                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 679
 680         if (gtt->userptr)
 681                 amdgpu_ttm_tt_unpin_userptr(ttm);
 682
 683         return 0;
 684 }
 685
 686 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 687 {
 688         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 689
 690         ttm_dma_tt_fini(&gtt->ttm);
 691         kfree(gtt);
 692 }
 693
 694 static struct ttm_backend_func amdgpu_backend_func = {
 695         .bind = &amdgpu_ttm_backend_bind,
 696         .unbind = &amdgpu_ttm_backend_unbind,
 697         .destroy = &amdgpu_ttm_backend_destroy,
 698 };
 699
 700 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 701                                     unsigned long size, uint32_t page_flags,
 702                                     struct page *dummy_read_page)
 703 {
 704         struct amdgpu_device *adev;
 705         struct amdgpu_ttm_tt *gtt;
 706
 707         adev = amdgpu_get_adev(bdev);
 708
 709         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 710         if (gtt == NULL) {
 711                 return NULL;
 712         }
 713         gtt->ttm.ttm.func = &amdgpu_backend_func;
 714         gtt->adev = adev;
 715         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 716                 kfree(gtt);
 717                 return NULL;
 718         }
 719         return &gtt->ttm.ttm;
 720 }
 721
 722 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 723 {
 724         struct amdgpu_device *adev;
 725         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 726         unsigned i;
 727         int r;
 728         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 729
 730         if (ttm->state != tt_unpopulated)
 731                 return 0;
 732
 733         if (gtt && gtt->userptr) {
 734                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 735                 if (!ttm->sg)
 736                         return -ENOMEM;
 737
 738                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 739                 ttm->state = tt_unbound;
 740                 return 0;
 741         }
 742
 743         if (slave && ttm->sg) {
 744                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 745                                                  gtt->ttm.dma_address, ttm->num_pages);
 746                 ttm->state = tt_unbound;
 747                 return 0;
 748         }
 749
 750         adev = amdgpu_get_adev(ttm->bdev);
 751
 752 #ifdef CONFIG_SWIOTLB
 753         if (swiotlb_nr_tbl()) {
 754                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 755         }
 756 #endif
 757
 758         r = ttm_pool_populate(ttm);
 759         if (r) {
 760                 return r;
 761         }
 762
 763         for (i = 0; i < ttm->num_pages; i++) {
 764                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 765                                                        0, PAGE_SIZE,
 766                                                        PCI_DMA_BIDIRECTIONAL);
 767                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 768                         while (i--) {
 769                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 770                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 771                                 gtt->ttm.dma_address[i] = 0;
 772                         }
 773                         ttm_pool_unpopulate(ttm);
 774                         return -EFAULT;
 775                 }
 776         }
 777         return 0;
 778 }
 779
 780 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 781 {
 782         struct amdgpu_device *adev;
 783         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 784         unsigned i;
 785         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 786
 787         if (gtt && gtt->userptr) {
 788                 kfree(ttm->sg);
 789                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 790                 return;
 791         }
 792
 793         if (slave)
 794                 return;
 795
 796         adev = amdgpu_get_adev(ttm->bdev);
 797
 798 #ifdef CONFIG_SWIOTLB
 799         if (swiotlb_nr_tbl()) {
 800                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 801                 return;
 802         }
 803 #endif
 804
 805         for (i = 0; i < ttm->num_pages; i++) {
 806                 if (gtt->ttm.dma_address[i]) {
 807                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 808                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 809                 }
 810         }
 811
 812         ttm_pool_unpopulate(ttm);
 813 }
 814
 815 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 816                               uint32_t flags)
 817 {
 818         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 819
 820         if (gtt == NULL)
 821                 return -EINVAL;
 822
 823         gtt->userptr = addr;
 824         gtt->usermm = current->mm;
 825         gtt->userflags = flags;
 826         spin_lock_init(&gtt->guptasklock);
 827         INIT_LIST_HEAD(&gtt->guptasks);
 828         atomic_set(&gtt->mmu_invalidations, 0);
 829
 830         return 0;
 831 }
 832
 833 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 834 {
 835         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 836
 837         if (gtt == NULL)
 838                 return NULL;
 839
 840         return gtt->usermm;
 841 }
 842
 843 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 844                                   unsigned long end)
 845 {
 846         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 847         struct amdgpu_ttm_gup_task_list *entry;
 848         unsigned long size;
 849
 850         if (gtt == NULL || !gtt->userptr)
 851                 return false;
 852
 853         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 854         if (gtt->userptr > end || gtt->userptr + size <= start)
 855                 return false;
 856
 857         spin_lock(&gtt->guptasklock);
 858         list_for_each_entry(entry, &gtt->guptasks, list) {
 859                 if (entry->task == current) {
 860                         spin_unlock(&gtt->guptasklock);
 861                         return false;
 862                 }
 863         }
 864         spin_unlock(&gtt->guptasklock);
 865
 866         atomic_inc(&gtt->mmu_invalidations);
 867
 868         return true;
 869 }
 870
 871 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 872                                        int *last_invalidated)
 873 {
 874         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 875         int prev_invalidated = *last_invalidated;
 876
 877         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 878         return prev_invalidated != *last_invalidated;
 879 }
 880
 881 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 882 {
 883         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 884
 885         if (gtt == NULL)
 886                 return false;
 887
 888         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 889 }
 890
 891 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 892                                  struct ttm_mem_reg *mem)
 893 {
 894         uint32_t flags = 0;
 895
 896         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 897                 flags |= AMDGPU_PTE_VALID;
 898
 899         if (mem && mem->mem_type == TTM_PL_TT) {
 900                 flags |= AMDGPU_PTE_SYSTEM;
 901
 902                 if (ttm->caching_state == tt_cached)
 903                         flags |= AMDGPU_PTE_SNOOPED;
 904         }
 905
 906         if (adev->asic_type >= CHIP_TONGA)
 907                 flags |= AMDGPU_PTE_EXECUTABLE;
 908
 909         flags |= AMDGPU_PTE_READABLE;
 910
 911         if (!amdgpu_ttm_tt_is_readonly(ttm))
 912                 flags |= AMDGPU_PTE_WRITEABLE;
 913
 914         return flags;
 915 }
 916
 917 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
 918 {
 919         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 920         unsigned i, j;
 921
 922         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
 923                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
 924
 925                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
 926                         if (&tbo->lru == lru->lru[j])
 927                                 lru->lru[j] = tbo->lru.prev;
 928
 929                 if (&tbo->swap == lru->swap_lru)
 930                         lru->swap_lru = tbo->swap.prev;
 931         }
 932 }
 933
 934 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
 935 {
 936         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 937         unsigned log2_size = min(ilog2(tbo->num_pages),
 938                                  AMDGPU_TTM_LRU_SIZE - 1);
 939
 940         return &adev->mman.log2_size[log2_size];
 941 }
 942
 943 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
 944 {
 945         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
 946         struct list_head *res = lru->lru[tbo->mem.mem_type];
 947
 948         lru->lru[tbo->mem.mem_type] = &tbo->lru;
 949
 950         return res;
 951 }
 952
 953 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
 954 {
 955         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
 956         struct list_head *res = lru->swap_lru;
 957
 958         lru->swap_lru = &tbo->swap;
 959
 960         return res;
 961 }
 962
 963 static struct ttm_bo_driver amdgpu_bo_driver = {
 964         .ttm_tt_create = &amdgpu_ttm_tt_create,
 965         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 966         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 967         .invalidate_caches = &amdgpu_invalidate_caches,
 968         .init_mem_type = &amdgpu_init_mem_type,
 969         .evict_flags = &amdgpu_evict_flags,
 970         .move = &amdgpu_bo_move,
 971         .verify_access = &amdgpu_verify_access,
 972         .move_notify = &amdgpu_bo_move_notify,
 973         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 974         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 975         .io_mem_free = &amdgpu_ttm_io_mem_free,
 976         .lru_removal = &amdgpu_ttm_lru_removal,
 977         .lru_tail = &amdgpu_ttm_lru_tail,
 978         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
 979 };
 980
 981 int amdgpu_ttm_init(struct amdgpu_device *adev)
 982 {
 983         unsigned i, j;
 984         int r;
 985
 986         /* No others user of address space so set it to 0 */
 987         r = ttm_bo_device_init(&adev->mman.bdev,
 988                                adev->mman.bo_global_ref.ref.object,
 989                                &amdgpu_bo_driver,
 990                                adev->ddev->anon_inode->i_mapping,
 991                                DRM_FILE_PAGE_OFFSET,
 992                                adev->need_dma32);
 993         if (r) {
 994                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 995                 return r;
 996         }
 997
 998         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
 999                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1000
1001                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1002                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1003                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1004         }
1005
1006         adev->mman.initialized = true;
1007         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1008                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1009         if (r) {
1010                 DRM_ERROR("Failed initializing VRAM heap.\n");
1011                 return r;
1012         }
1013         /* Change the size here instead of the init above so only lpfn is affected */
1014         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1015
1016         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1017                              AMDGPU_GEM_DOMAIN_VRAM,
1018                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1019                              NULL, NULL, &adev->stollen_vga_memory);
1020         if (r) {
1021                 return r;
1022         }
1023         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1024         if (r)
1025                 return r;
1026         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1027         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1028         if (r) {
1029                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1030                 return r;
1031         }
1032         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1033                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1034         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1035                                 adev->mc.gtt_size >> PAGE_SHIFT);
1036         if (r) {
1037                 DRM_ERROR("Failed initializing GTT heap.\n");
1038                 return r;
1039         }
1040         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1041                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1042
1043         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1044         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1045         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1046         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1047         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1048         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1049         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1050         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1051         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1052         /* GDS Memory */
1053         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1054                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1055         if (r) {
1056                 DRM_ERROR("Failed initializing GDS heap.\n");
1057                 return r;
1058         }
1059
1060         /* GWS */
1061         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1062                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1063         if (r) {
1064                 DRM_ERROR("Failed initializing gws heap.\n");
1065                 return r;
1066         }
1067
1068         /* OA */
1069         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1070                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1071         if (r) {
1072                 DRM_ERROR("Failed initializing oa heap.\n");
1073                 return r;
1074         }
1075
1076         r = amdgpu_ttm_debugfs_init(adev);
1077         if (r) {
1078                 DRM_ERROR("Failed to init debugfs\n");
1079                 return r;
1080         }
1081         return 0;
1082 }
1083
1084 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1085 {
1086         int r;
1087
1088         if (!adev->mman.initialized)
1089                 return;
1090         amdgpu_ttm_debugfs_fini(adev);
1091         if (adev->stollen_vga_memory) {
1092                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1093                 if (r == 0) {
1094                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1095                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1096                 }
1097                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1098         }
1099         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1100         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1101         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1102         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1103         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1104         ttm_bo_device_release(&adev->mman.bdev);
1105         amdgpu_gart_fini(adev);
1106         amdgpu_ttm_global_fini(adev);
1107         adev->mman.initialized = false;
1108         DRM_INFO("amdgpu: ttm finalized\n");
1109 }
1110
1111 /* this should only be called at bootup or when userspace
1112  * isn't running */
1113 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1114 {
1115         struct ttm_mem_type_manager *man;
1116
1117         if (!adev->mman.initialized)
1118                 return;
1119
1120         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1121         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1122         man->size = size >> PAGE_SHIFT;
1123 }
1124
1125 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1126 {
1127         struct drm_file *file_priv;
1128         struct amdgpu_device *adev;
1129
1130         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1131                 return -EINVAL;
1132
1133         file_priv = filp->private_data;
1134         adev = file_priv->minor->dev->dev_private;
1135         if (adev == NULL)
1136                 return -EINVAL;
1137
1138         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1139 }
1140
1141 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1142                        uint64_t src_offset,
1143                        uint64_t dst_offset,
1144                        uint32_t byte_count,
1145                        struct reservation_object *resv,
1146                        struct fence **fence)
1147 {
1148         struct amdgpu_device *adev = ring->adev;
1149         struct amdgpu_job *job;
1150
1151         uint32_t max_bytes;
1152         unsigned num_loops, num_dw;
1153         unsigned i;
1154         int r;
1155
1156         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1157         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1158         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1159
1160         /* for IB padding */
1161         while (num_dw & 0x7)
1162                 num_dw++;
1163
1164         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1165         if (r)
1166                 return r;
1167
1168         if (resv) {
1169                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1170                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1171                 if (r) {
1172                         DRM_ERROR("sync failed (%d).\n", r);
1173                         goto error_free;
1174                 }
1175         }
1176
1177         for (i = 0; i < num_loops; i++) {
1178                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1179
1180                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1181                                         dst_offset, cur_size_in_bytes);
1182
1183                 src_offset += cur_size_in_bytes;
1184                 dst_offset += cur_size_in_bytes;
1185                 byte_count -= cur_size_in_bytes;
1186         }
1187
1188         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1189         WARN_ON(job->ibs[0].length_dw > num_dw);
1190         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1191                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1192         if (r)
1193                 goto error_free;
1194
1195         return 0;
1196
1197 error_free:
1198         amdgpu_job_free(job);
1199         return r;
1200 }
1201
1202 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1203                 uint32_t src_data,
1204                 struct reservation_object *resv,
1205                 struct fence **fence)
1206 {
1207         struct amdgpu_device *adev = bo->adev;
1208         struct amdgpu_job *job;
1209         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1210
1211         uint32_t max_bytes, byte_count;
1212         uint64_t dst_offset;
1213         unsigned int num_loops, num_dw;
1214         unsigned int i;
1215         int r;
1216
1217         byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1218         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1219         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1220         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1221
1222         /* for IB padding */
1223         while (num_dw & 0x7)
1224                 num_dw++;
1225
1226         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1227         if (r)
1228                 return r;
1229
1230         if (resv) {
1231                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1232                                 AMDGPU_FENCE_OWNER_UNDEFINED);
1233                 if (r) {
1234                         DRM_ERROR("sync failed (%d).\n", r);
1235                         goto error_free;
1236                 }
1237         }
1238
1239         dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1240         for (i = 0; i < num_loops; i++) {
1241                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1242
1243                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1244                                 dst_offset, cur_size_in_bytes);
1245
1246                 dst_offset += cur_size_in_bytes;
1247                 byte_count -= cur_size_in_bytes;
1248         }
1249
1250         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1251         WARN_ON(job->ibs[0].length_dw > num_dw);
1252         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1253                         AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1254         if (r)
1255                 goto error_free;
1256
1257         return 0;
1258
1259 error_free:
1260         amdgpu_job_free(job);
1261         return r;
1262 }
1263
1264 #if defined(CONFIG_DEBUG_FS)
1265
1266 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1267 {
1268         struct drm_info_node *node = (struct drm_info_node *)m->private;
1269         unsigned ttm_pl = *(int *)node->info_ent->data;
1270         struct drm_device *dev = node->minor->dev;
1271         struct amdgpu_device *adev = dev->dev_private;
1272         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1273         int ret;
1274         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1275
1276         spin_lock(&glob->lru_lock);
1277         ret = drm_mm_dump_table(m, mm);
1278         spin_unlock(&glob->lru_lock);
1279         if (ttm_pl == TTM_PL_VRAM)
1280                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1281                            adev->mman.bdev.man[ttm_pl].size,
1282                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1283                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1284         return ret;
1285 }
1286
1287 static int ttm_pl_vram = TTM_PL_VRAM;
1288 static int ttm_pl_tt = TTM_PL_TT;
1289
1290 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1291         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1292         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1293         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1294 #ifdef CONFIG_SWIOTLB
1295         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1296 #endif
1297 };
1298
1299 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1300                                     size_t size, loff_t *pos)
1301 {
1302         struct amdgpu_device *adev = f->f_inode->i_private;
1303         ssize_t result = 0;
1304         int r;
1305
1306         if (size & 0x3 || *pos & 0x3)
1307                 return -EINVAL;
1308
1309         while (size) {
1310                 unsigned long flags;
1311                 uint32_t value;
1312
1313                 if (*pos >= adev->mc.mc_vram_size)
1314                         return result;
1315
1316                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1317                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1318                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1319                 value = RREG32(mmMM_DATA);
1320                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1321
1322                 r = put_user(value, (uint32_t *)buf);
1323                 if (r)
1324                         return r;
1325
1326                 result += 4;
1327                 buf += 4;
1328                 *pos += 4;
1329                 size -= 4;
1330         }
1331
1332         return result;
1333 }
1334
1335 static const struct file_operations amdgpu_ttm_vram_fops = {
1336         .owner = THIS_MODULE,
1337         .read = amdgpu_ttm_vram_read,
1338         .llseek = default_llseek
1339 };
1340
1341 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1342
1343 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1344                                    size_t size, loff_t *pos)
1345 {
1346         struct amdgpu_device *adev = f->f_inode->i_private;
1347         ssize_t result = 0;
1348         int r;
1349
1350         while (size) {
1351                 loff_t p = *pos / PAGE_SIZE;
1352                 unsigned off = *pos & ~PAGE_MASK;
1353                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1354                 struct page *page;
1355                 void *ptr;
1356
1357                 if (p >= adev->gart.num_cpu_pages)
1358                         return result;
1359
1360                 page = adev->gart.pages[p];
1361                 if (page) {
1362                         ptr = kmap(page);
1363                         ptr += off;
1364
1365                         r = copy_to_user(buf, ptr, cur_size);
1366                         kunmap(adev->gart.pages[p]);
1367                 } else
1368                         r = clear_user(buf, cur_size);
1369
1370                 if (r)
1371                         return -EFAULT;
1372
1373                 result += cur_size;
1374                 buf += cur_size;
1375                 *pos += cur_size;
1376                 size -= cur_size;
1377         }
1378
1379         return result;
1380 }
1381
1382 static const struct file_operations amdgpu_ttm_gtt_fops = {
1383         .owner = THIS_MODULE,
1384         .read = amdgpu_ttm_gtt_read,
1385         .llseek = default_llseek
1386 };
1387
1388 #endif
1389
1390 #endif
1391
1392 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1393 {
1394 #if defined(CONFIG_DEBUG_FS)
1395         unsigned count;
1396
1397         struct drm_minor *minor = adev->ddev->primary;
1398         struct dentry *ent, *root = minor->debugfs_root;
1399
1400         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1401                                   adev, &amdgpu_ttm_vram_fops);
1402         if (IS_ERR(ent))
1403                 return PTR_ERR(ent);
1404         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1405         adev->mman.vram = ent;
1406
1407 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1408         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1409                                   adev, &amdgpu_ttm_gtt_fops);
1410         if (IS_ERR(ent))
1411                 return PTR_ERR(ent);
1412         i_size_write(ent->d_inode, adev->mc.gtt_size);
1413         adev->mman.gtt = ent;
1414
1415 #endif
1416         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1417
1418 #ifdef CONFIG_SWIOTLB
1419         if (!swiotlb_nr_tbl())
1420                 --count;
1421 #endif
1422
1423         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1424 #else
1425
1426         return 0;
1427 #endif
1428 }
1429
1430 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1431 {
1432 #if defined(CONFIG_DEBUG_FS)
1433
1434         debugfs_remove(adev->mman.vram);
1435         adev->mman.vram = NULL;
1436
1437 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1438         debugfs_remove(adev->mman.gtt);
1439         adev->mman.gtt = NULL;
1440 #endif
1441
1442 #endif
1443 }
1444
1445 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1446 {
1447         return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1448 }