drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v6_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gmc/gmc_6_0_d.h"
  34 #include "gmc/gmc_6_0_sh_mask.h"
  35 #include "dce/dce_6_0_d.h"
  36 #include "dce/dce_6_0_sh_mask.h"
  37 #include "si_enums.h"
  38
  39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
  40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int gmc_v6_0_wait_for_idle(void *handle);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
  44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
  45 MODULE_FIRMWARE("radeon/verde_mc.bin");
  46 MODULE_FIRMWARE("radeon/oland_mc.bin");
  47 MODULE_FIRMWARE("radeon/si58_mc.bin");
  48
  49 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  50 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  51 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  52 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  53 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  54 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  55 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  56 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  57
  58
  59 static const u32 crtc_offsets[6] =
  60 {
  61         SI_CRTC0_REGISTER_OFFSET,
  62         SI_CRTC1_REGISTER_OFFSET,
  63         SI_CRTC2_REGISTER_OFFSET,
  64         SI_CRTC3_REGISTER_OFFSET,
  65         SI_CRTC4_REGISTER_OFFSET,
  66         SI_CRTC5_REGISTER_OFFSET
  67 };
  68
  69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
  70                              struct amdgpu_mode_mc_save *save)
  71 {
  72         u32 blackout;
  73
  74         if (adev->mode_info.num_crtc)
  75                 amdgpu_display_stop_mc_access(adev, save);
  76
  77         gmc_v6_0_wait_for_idle((void *)adev);
  78
  79         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  80         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  81                 /* Block CPU access */
  82                 WREG32(mmBIF_FB_EN, 0);
  83                 /* blackout the MC */
  84                 blackout = REG_SET_FIELD(blackout,
  85                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  86                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  87         }
  88         /* wait for the MC to settle */
  89         udelay(100);
  90
  91 }
  92
  93 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
  94                                struct amdgpu_mode_mc_save *save)
  95 {
  96         u32 tmp;
  97
  98         /* unblackout the MC */
  99         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 100         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 101         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 102         /* allow CPU access */
 103         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 104         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 105         WREG32(mmBIF_FB_EN, tmp);
 106
 107         if (adev->mode_info.num_crtc)
 108                 amdgpu_display_resume_mc_access(adev, save);
 109
 110 }
 111
 112 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 113 {
 114         const char *chip_name;
 115         char fw_name[30];
 116         int err;
 117         bool is_58_fw = false;
 118
 119         DRM_DEBUG("\n");
 120
 121         switch (adev->asic_type) {
 122         case CHIP_TAHITI:
 123                 chip_name = "tahiti";
 124                 break;
 125         case CHIP_PITCAIRN:
 126                 chip_name = "pitcairn";
 127                 break;
 128         case CHIP_VERDE:
 129                 chip_name = "verde";
 130                 break;
 131         case CHIP_OLAND:
 132                 chip_name = "oland";
 133                 break;
 134         case CHIP_HAINAN:
 135                 chip_name = "hainan";
 136                 break;
 137         default: BUG();
 138         }
 139
 140         /* this memory configuration requires special firmware */
 141         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 142                 is_58_fw = true;
 143
 144         if (is_58_fw)
 145                 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
 146         else
 147                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 148         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 149         if (err)
 150                 goto out;
 151
 152         err = amdgpu_ucode_validate(adev->mc.fw);
 153
 154 out:
 155         if (err) {
 156                 dev_err(adev->dev,
 157                        "si_mc: Failed to load firmware \"%s\"\n",
 158                        fw_name);
 159                 release_firmware(adev->mc.fw);
 160                 adev->mc.fw = NULL;
 161         }
 162         return err;
 163 }
 164
 165 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 166 {
 167         const __le32 *new_fw_data = NULL;
 168         u32 running;
 169         const __le32 *new_io_mc_regs = NULL;
 170         int i, regs_size, ucode_size;
 171         const struct mc_firmware_header_v1_0 *hdr;
 172
 173         if (!adev->mc.fw)
 174                 return -EINVAL;
 175
 176         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 177
 178         amdgpu_ucode_print_mc_hdr(&hdr->header);
 179
 180         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 181         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 182         new_io_mc_regs = (const __le32 *)
 183                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 184         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 185         new_fw_data = (const __le32 *)
 186                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 187
 188         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 189
 190         if (running == 0) {
 191
 192                 /* reset the engine and set to writable */
 193                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 194                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 195
 196                 /* load mc io regs */
 197                 for (i = 0; i < regs_size; i++) {
 198                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 199                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 200                 }
 201                 /* load the MC ucode */
 202                 for (i = 0; i < ucode_size; i++) {
 203                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 204                 }
 205
 206                 /* put the engine back into the active state */
 207                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 208                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 209                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 210
 211                 /* wait for training to complete */
 212                 for (i = 0; i < adev->usec_timeout; i++) {
 213                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 214                                 break;
 215                         udelay(1);
 216                 }
 217                 for (i = 0; i < adev->usec_timeout; i++) {
 218                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 219                                 break;
 220                         udelay(1);
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 229                                        struct amdgpu_mc *mc)
 230 {
 231         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 232                 dev_warn(adev->dev, "limiting VRAM\n");
 233                 mc->real_vram_size = 0xFFC0000000ULL;
 234                 mc->mc_vram_size = 0xFFC0000000ULL;
 235         }
 236         amdgpu_vram_location(adev, &adev->mc, 0);
 237         adev->mc.gtt_base_align = 0;
 238         amdgpu_gtt_location(adev, mc);
 239 }
 240
 241 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 242 {
 243         struct amdgpu_mode_mc_save save;
 244         u32 tmp;
 245         int i, j;
 246
 247         /* Initialize HDP */
 248         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 249                 WREG32((0xb05 + j), 0x00000000);
 250                 WREG32((0xb06 + j), 0x00000000);
 251                 WREG32((0xb07 + j), 0x00000000);
 252                 WREG32((0xb08 + j), 0x00000000);
 253                 WREG32((0xb09 + j), 0x00000000);
 254         }
 255         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 256
 257         gmc_v6_0_mc_stop(adev, &save);
 258
 259         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 260                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 261         }
 262
 263         WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
 264         /* Update configuration */
 265         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 266                adev->mc.vram_start >> 12);
 267         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 268                adev->mc.vram_end >> 12);
 269         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 270                adev->vram_scratch.gpu_addr >> 12);
 271         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 272         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 273         WREG32(mmMC_VM_FB_LOCATION, tmp);
 274         /* XXX double check these! */
 275         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 276         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 277         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 278         WREG32(mmMC_VM_AGP_BASE, 0);
 279         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 280         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 281
 282         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 283                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 284         }
 285         gmc_v6_0_mc_resume(adev, &save);
 286         amdgpu_display_set_vga_render_state(adev, false);
 287 }
 288
 289 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 290 {
 291
 292         u32 tmp;
 293         int chansize, numchan;
 294
 295         tmp = RREG32(mmMC_ARB_RAMCFG);
 296         if (tmp & (1 << 11)) {
 297                 chansize = 16;
 298         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 299                 chansize = 64;
 300         } else {
 301                 chansize = 32;
 302         }
 303         tmp = RREG32(mmMC_SHARED_CHMAP);
 304         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 305         case 0:
 306         default:
 307                 numchan = 1;
 308                 break;
 309         case 1:
 310                 numchan = 2;
 311                 break;
 312         case 2:
 313                 numchan = 4;
 314                 break;
 315         case 3:
 316                 numchan = 8;
 317                 break;
 318         case 4:
 319                 numchan = 3;
 320                 break;
 321         case 5:
 322                 numchan = 6;
 323                 break;
 324         case 6:
 325                 numchan = 10;
 326                 break;
 327         case 7:
 328                 numchan = 12;
 329                 break;
 330         case 8:
 331                 numchan = 16;
 332                 break;
 333         }
 334         adev->mc.vram_width = numchan * chansize;
 335         /* Could aper size report 0 ? */
 336         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 337         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 338         /* size in MB on si */
 339         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 340         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 341         adev->mc.visible_vram_size = adev->mc.aper_size;
 342
 343         /* unless the user had overridden it, set the gart
 344          * size equal to the 1024 or vram, whichever is larger.
 345          */
 346         if (amdgpu_gart_size == -1)
 347                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 348         else
 349                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 350
 351         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 352
 353         return 0;
 354 }
 355
 356 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 357                                         uint32_t vmid)
 358 {
 359         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 360
 361         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 362 }
 363
 364 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 365                                      void *cpu_pt_addr,
 366                                      uint32_t gpu_page_idx,
 367                                      uint64_t addr,
 368                                      uint32_t flags)
 369 {
 370         void __iomem *ptr = (void *)cpu_pt_addr;
 371         uint64_t value;
 372
 373         value = addr & 0xFFFFFFFFFFFFF000ULL;
 374         value |= flags;
 375         writeq(value, ptr + (gpu_page_idx * 8));
 376
 377         return 0;
 378 }
 379
 380 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 381                                               bool value)
 382 {
 383         u32 tmp;
 384
 385         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 386         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 387                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 388         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 389                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 390         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 391                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 392         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 393                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 394         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 395                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 396         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 397                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 398         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 399 }
 400
 401 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 402 {
 403         int r, i;
 404
 405         if (adev->gart.robj == NULL) {
 406                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 407                 return -EINVAL;
 408         }
 409         r = amdgpu_gart_table_vram_pin(adev);
 410         if (r)
 411                 return r;
 412         /* Setup TLB control */
 413         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 414                (0xA << 7) |
 415                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 416                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 417                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 418                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 419                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 420         /* Setup L2 cache */
 421         WREG32(mmVM_L2_CNTL,
 422                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 423                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 424                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 425                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 426                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 427                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 428         WREG32(mmVM_L2_CNTL2,
 429                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 430                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 431         WREG32(mmVM_L2_CNTL3,
 432                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 433                (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 434                (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 435         /* setup context0 */
 436         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 437         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 438         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 439         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 440                         (u32)(adev->dummy_page.addr >> 12));
 441         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 442         WREG32(mmVM_CONTEXT0_CNTL,
 443                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 444                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 445                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 446
 447         WREG32(0x575, 0);
 448         WREG32(0x576, 0);
 449         WREG32(0x577, 0);
 450
 451         /* empty context1-15 */
 452         /* set vm size, must be a multiple of 4 */
 453         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 454         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 455         /* Assign the pt base to something valid for now; the pts used for
 456          * the VMs are determined by the application and setup and assigned
 457          * on the fly in the vm part of radeon_gart.c
 458          */
 459         for (i = 1; i < 16; i++) {
 460                 if (i < 8)
 461                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 462                                adev->gart.table_addr >> 12);
 463                 else
 464                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 465                                adev->gart.table_addr >> 12);
 466         }
 467
 468         /* enable context1-15 */
 469         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 470                (u32)(adev->dummy_page.addr >> 12));
 471         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 472         WREG32(mmVM_CONTEXT1_CNTL,
 473                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 474                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 475                ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 476         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 477                 gmc_v6_0_set_fault_enable_default(adev, false);
 478         else
 479                 gmc_v6_0_set_fault_enable_default(adev, true);
 480
 481         gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
 482         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 483                  (unsigned)(adev->mc.gtt_size >> 20),
 484                  (unsigned long long)adev->gart.table_addr);
 485         adev->gart.ready = true;
 486         return 0;
 487 }
 488
 489 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 490 {
 491         int r;
 492
 493         if (adev->gart.robj) {
 494                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 495                 return 0;
 496         }
 497         r = amdgpu_gart_init(adev);
 498         if (r)
 499                 return r;
 500         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 501         return amdgpu_gart_table_vram_alloc(adev);
 502 }
 503
 504 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 505 {
 506         /*unsigned i;
 507
 508         for (i = 1; i < 16; ++i) {
 509                 uint32_t reg;
 510                 if (i < 8)
 511                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 512                 else
 513                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 514                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 515         }*/
 516
 517         /* Disable all tables */
 518         WREG32(mmVM_CONTEXT0_CNTL, 0);
 519         WREG32(mmVM_CONTEXT1_CNTL, 0);
 520         /* Setup TLB control */
 521         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 522                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 523                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 524         /* Setup L2 cache */
 525         WREG32(mmVM_L2_CNTL,
 526                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 527                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 528                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 529                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 530         WREG32(mmVM_L2_CNTL2, 0);
 531         WREG32(mmVM_L2_CNTL3,
 532                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 533                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 534         amdgpu_gart_table_vram_unpin(adev);
 535 }
 536
 537 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
 538 {
 539         amdgpu_gart_table_vram_free(adev);
 540         amdgpu_gart_fini(adev);
 541 }
 542
 543 static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
 544 {
 545         /*
 546          * number of VMs
 547          * VMID 0 is reserved for System
 548          * amdgpu graphics/compute will use VMIDs 1-7
 549          * amdkfd will use VMIDs 8-15
 550          */
 551         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 552         amdgpu_vm_manager_init(adev);
 553
 554         /* base offset of vram pages */
 555         if (adev->flags & AMD_IS_APU) {
 556                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 557                 tmp <<= 22;
 558                 adev->vm_manager.vram_base_offset = tmp;
 559         } else
 560                 adev->vm_manager.vram_base_offset = 0;
 561
 562         return 0;
 563 }
 564
 565 static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
 566 {
 567 }
 568
 569 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 570                                      u32 status, u32 addr, u32 mc_client)
 571 {
 572         u32 mc_id;
 573         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 574         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 575                                         PROTECTIONS);
 576         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 577                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 578
 579         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 580                               MEMORY_CLIENT_ID);
 581
 582         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 583                protections, vmid, addr,
 584                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 585                              MEMORY_CLIENT_RW) ?
 586                "write" : "read", block, mc_client, mc_id);
 587 }
 588
 589 /*
 590 static const u32 mc_cg_registers[] = {
 591         MC_HUB_MISC_HUB_CG,
 592         MC_HUB_MISC_SIP_CG,
 593         MC_HUB_MISC_VM_CG,
 594         MC_XPB_CLK_GAT,
 595         ATC_MISC_CG,
 596         MC_CITF_MISC_WR_CG,
 597         MC_CITF_MISC_RD_CG,
 598         MC_CITF_MISC_VM_CG,
 599         VM_L2_CG,
 600 };
 601
 602 static const u32 mc_cg_ls_en[] = {
 603         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 604         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 605         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 606         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 607         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 608         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 609         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 610         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 611         VM_L2_CG__MEM_LS_ENABLE_MASK,
 612 };
 613
 614 static const u32 mc_cg_en[] = {
 615         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 616         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 617         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 618         MC_XPB_CLK_GAT__ENABLE_MASK,
 619         ATC_MISC_CG__ENABLE_MASK,
 620         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 621         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 622         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 623         VM_L2_CG__ENABLE_MASK,
 624 };
 625
 626 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 627                                   bool enable)
 628 {
 629         int i;
 630         u32 orig, data;
 631
 632         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 633                 orig = data = RREG32(mc_cg_registers[i]);
 634                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 635                         data |= mc_cg_ls_en[i];
 636                 else
 637                         data &= ~mc_cg_ls_en[i];
 638                 if (data != orig)
 639                         WREG32(mc_cg_registers[i], data);
 640         }
 641 }
 642
 643 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 644                                     bool enable)
 645 {
 646         int i;
 647         u32 orig, data;
 648
 649         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 650                 orig = data = RREG32(mc_cg_registers[i]);
 651                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 652                         data |= mc_cg_en[i];
 653                 else
 654                         data &= ~mc_cg_en[i];
 655                 if (data != orig)
 656                         WREG32(mc_cg_registers[i], data);
 657         }
 658 }
 659
 660 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 661                                      bool enable)
 662 {
 663         u32 orig, data;
 664
 665         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 666
 667         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 668                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 669                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 670                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 671                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 672         } else {
 673                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 674                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 675                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 676                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 677         }
 678
 679         if (orig != data)
 680                 WREG32_PCIE(ixPCIE_CNTL2, data);
 681 }
 682
 683 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 684                                      bool enable)
 685 {
 686         u32 orig, data;
 687
 688         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 689
 690         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 691                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 692         else
 693                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 694
 695         if (orig != data)
 696                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 697 }
 698
 699 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 700                                    bool enable)
 701 {
 702         u32 orig, data;
 703
 704         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 705
 706         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 707                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 708         else
 709                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 710
 711         if (orig != data)
 712                 WREG32(mmHDP_MEM_POWER_LS, data);
 713 }
 714 */
 715
 716 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 717 {
 718         switch (mc_seq_vram_type) {
 719         case MC_SEQ_MISC0__MT__GDDR1:
 720                 return AMDGPU_VRAM_TYPE_GDDR1;
 721         case MC_SEQ_MISC0__MT__DDR2:
 722                 return AMDGPU_VRAM_TYPE_DDR2;
 723         case MC_SEQ_MISC0__MT__GDDR3:
 724                 return AMDGPU_VRAM_TYPE_GDDR3;
 725         case MC_SEQ_MISC0__MT__GDDR4:
 726                 return AMDGPU_VRAM_TYPE_GDDR4;
 727         case MC_SEQ_MISC0__MT__GDDR5:
 728                 return AMDGPU_VRAM_TYPE_GDDR5;
 729         case MC_SEQ_MISC0__MT__DDR3:
 730                 return AMDGPU_VRAM_TYPE_DDR3;
 731         default:
 732                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 733         }
 734 }
 735
 736 static int gmc_v6_0_early_init(void *handle)
 737 {
 738         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 739
 740         gmc_v6_0_set_gart_funcs(adev);
 741         gmc_v6_0_set_irq_funcs(adev);
 742
 743         if (adev->flags & AMD_IS_APU) {
 744                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 745         } else {
 746                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 747                 tmp &= MC_SEQ_MISC0__MT__MASK;
 748                 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int gmc_v6_0_late_init(void *handle)
 755 {
 756         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 757
 758         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 759                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 760         else
 761                 return 0;
 762 }
 763
 764 static int gmc_v6_0_sw_init(void *handle)
 765 {
 766         int r;
 767         int dma_bits;
 768         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 769
 770         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 771         if (r)
 772                 return r;
 773
 774         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 775         if (r)
 776                 return r;
 777
 778         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 779
 780         adev->mc.mc_mask = 0xffffffffffULL;
 781
 782         adev->need_dma32 = false;
 783         dma_bits = adev->need_dma32 ? 32 : 40;
 784         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 785         if (r) {
 786                 adev->need_dma32 = true;
 787                 dma_bits = 32;
 788                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 789         }
 790         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 791         if (r) {
 792                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 793                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 794         }
 795
 796         r = gmc_v6_0_init_microcode(adev);
 797         if (r) {
 798                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 799                 return r;
 800         }
 801
 802         r = gmc_v6_0_mc_init(adev);
 803         if (r)
 804                 return r;
 805
 806         r = amdgpu_bo_init(adev);
 807         if (r)
 808                 return r;
 809
 810         r = gmc_v6_0_gart_init(adev);
 811         if (r)
 812                 return r;
 813
 814         if (!adev->vm_manager.enabled) {
 815                 r = gmc_v6_0_vm_init(adev);
 816                 if (r) {
 817                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 818                         return r;
 819                 }
 820                 adev->vm_manager.enabled = true;
 821         }
 822
 823         return r;
 824 }
 825
 826 static int gmc_v6_0_sw_fini(void *handle)
 827 {
 828         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 829
 830         if (adev->vm_manager.enabled) {
 831                 gmc_v6_0_vm_fini(adev);
 832                 adev->vm_manager.enabled = false;
 833         }
 834         gmc_v6_0_gart_fini(adev);
 835         amdgpu_gem_force_release(adev);
 836         amdgpu_bo_fini(adev);
 837
 838         return 0;
 839 }
 840
 841 static int gmc_v6_0_hw_init(void *handle)
 842 {
 843         int r;
 844         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 845
 846         gmc_v6_0_mc_program(adev);
 847
 848         if (!(adev->flags & AMD_IS_APU)) {
 849                 r = gmc_v6_0_mc_load_microcode(adev);
 850                 if (r) {
 851                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 852                         return r;
 853                 }
 854         }
 855
 856         r = gmc_v6_0_gart_enable(adev);
 857         if (r)
 858                 return r;
 859
 860         return r;
 861 }
 862
 863 static int gmc_v6_0_hw_fini(void *handle)
 864 {
 865         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 866
 867         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 868         gmc_v6_0_gart_disable(adev);
 869
 870         return 0;
 871 }
 872
 873 static int gmc_v6_0_suspend(void *handle)
 874 {
 875         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 876
 877         if (adev->vm_manager.enabled) {
 878                 gmc_v6_0_vm_fini(adev);
 879                 adev->vm_manager.enabled = false;
 880         }
 881         gmc_v6_0_hw_fini(adev);
 882
 883         return 0;
 884 }
 885
 886 static int gmc_v6_0_resume(void *handle)
 887 {
 888         int r;
 889         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 890
 891         r = gmc_v6_0_hw_init(adev);
 892         if (r)
 893                 return r;
 894
 895         if (!adev->vm_manager.enabled) {
 896                 r = gmc_v6_0_vm_init(adev);
 897                 if (r) {
 898                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 899                         return r;
 900                 }
 901                 adev->vm_manager.enabled = true;
 902         }
 903
 904         return r;
 905 }
 906
 907 static bool gmc_v6_0_is_idle(void *handle)
 908 {
 909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 910         u32 tmp = RREG32(mmSRBM_STATUS);
 911
 912         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 913                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 914                 return false;
 915
 916         return true;
 917 }
 918
 919 static int gmc_v6_0_wait_for_idle(void *handle)
 920 {
 921         unsigned i;
 922         u32 tmp;
 923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 924
 925         for (i = 0; i < adev->usec_timeout; i++) {
 926                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
 927                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 928                                                SRBM_STATUS__MCC_BUSY_MASK |
 929                                                SRBM_STATUS__MCD_BUSY_MASK |
 930                                                SRBM_STATUS__VMC_BUSY_MASK);
 931                 if (!tmp)
 932                         return 0;
 933                 udelay(1);
 934         }
 935         return -ETIMEDOUT;
 936
 937 }
 938
 939 static int gmc_v6_0_soft_reset(void *handle)
 940 {
 941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 942         struct amdgpu_mode_mc_save save;
 943         u32 srbm_soft_reset = 0;
 944         u32 tmp = RREG32(mmSRBM_STATUS);
 945
 946         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 947                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 948                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 949
 950         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 951                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
 952                 if (!(adev->flags & AMD_IS_APU))
 953                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 954                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 955         }
 956
 957         if (srbm_soft_reset) {
 958                 gmc_v6_0_mc_stop(adev, &save);
 959                 if (gmc_v6_0_wait_for_idle(adev)) {
 960                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
 961                 }
 962
 963
 964                 tmp = RREG32(mmSRBM_SOFT_RESET);
 965                 tmp |= srbm_soft_reset;
 966                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 967                 WREG32(mmSRBM_SOFT_RESET, tmp);
 968                 tmp = RREG32(mmSRBM_SOFT_RESET);
 969
 970                 udelay(50);
 971
 972                 tmp &= ~srbm_soft_reset;
 973                 WREG32(mmSRBM_SOFT_RESET, tmp);
 974                 tmp = RREG32(mmSRBM_SOFT_RESET);
 975
 976                 udelay(50);
 977
 978                 gmc_v6_0_mc_resume(adev, &save);
 979                 udelay(50);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 986                                              struct amdgpu_irq_src *src,
 987                                              unsigned type,
 988                                              enum amdgpu_interrupt_state state)
 989 {
 990         u32 tmp;
 991         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 992                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 993                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 994                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 995                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 996                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
 997
 998         switch (state) {
 999         case AMDGPU_IRQ_STATE_DISABLE:
1000                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1001                 tmp &= ~bits;
1002                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1003                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1004                 tmp &= ~bits;
1005                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1006                 break;
1007         case AMDGPU_IRQ_STATE_ENABLE:
1008                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1009                 tmp |= bits;
1010                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1011                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1012                 tmp |= bits;
1013                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1014                 break;
1015         default:
1016                 break;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1023                                       struct amdgpu_irq_src *source,
1024                                       struct amdgpu_iv_entry *entry)
1025 {
1026         u32 addr, status;
1027
1028         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1029         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1030         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1031
1032         if (!addr && !status)
1033                 return 0;
1034
1035         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1036                 gmc_v6_0_set_fault_enable_default(adev, false);
1037
1038         if (printk_ratelimit()) {
1039                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1040                         entry->src_id, entry->src_data);
1041                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1042                         addr);
1043                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1044                         status);
1045                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1046         }
1047
1048         return 0;
1049 }
1050
1051 static int gmc_v6_0_set_clockgating_state(void *handle,
1052                                           enum amd_clockgating_state state)
1053 {
1054         return 0;
1055 }
1056
1057 static int gmc_v6_0_set_powergating_state(void *handle,
1058                                           enum amd_powergating_state state)
1059 {
1060         return 0;
1061 }
1062
1063 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1064         .name = "gmc_v6_0",
1065         .early_init = gmc_v6_0_early_init,
1066         .late_init = gmc_v6_0_late_init,
1067         .sw_init = gmc_v6_0_sw_init,
1068         .sw_fini = gmc_v6_0_sw_fini,
1069         .hw_init = gmc_v6_0_hw_init,
1070         .hw_fini = gmc_v6_0_hw_fini,
1071         .suspend = gmc_v6_0_suspend,
1072         .resume = gmc_v6_0_resume,
1073         .is_idle = gmc_v6_0_is_idle,
1074         .wait_for_idle = gmc_v6_0_wait_for_idle,
1075         .soft_reset = gmc_v6_0_soft_reset,
1076         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1077         .set_powergating_state = gmc_v6_0_set_powergating_state,
1078 };
1079
1080 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1081         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1082         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1083 };
1084
1085 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1086         .set = gmc_v6_0_vm_fault_interrupt_state,
1087         .process = gmc_v6_0_process_interrupt,
1088 };
1089
1090 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1091 {
1092         if (adev->gart.gart_funcs == NULL)
1093                 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1094 }
1095
1096 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1097 {
1098         adev->mc.vm_fault.num_types = 1;
1099         adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1100 }
1101
1102 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1103 {
1104         .type = AMD_IP_BLOCK_TYPE_GMC,
1105         .major = 6,
1106         .minor = 0,
1107         .rev = 0,
1108         .funcs = &gmc_v6_0_ip_funcs,
1109 };