drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include "linux/delay.h"
  27
  28 #include "hwmgr.h"
  29 #include "fiji_smumgr.h"
  30 #include "atombios.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomctrl.h"
  33 #include "atombios.h"
  34 #include "cgs_common.h"
  35 #include "fiji_dyn_defaults.h"
  36 #include "fiji_powertune.h"
  37 #include "smu73.h"
  38 #include "smu/smu_7_1_3_d.h"
  39 #include "smu/smu_7_1_3_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44 #include "dce/dce_10_0_d.h"
  45 #include "dce/dce_10_0_sh_mask.h"
  46 #include "pppcielanes.h"
  47 #include "fiji_hwmgr.h"
  48 #include "tonga_processpptables.h"
  49 #include "tonga_pptable.h"
  50 #include "pp_debug.h"
  51 #include "pp_acpi.h"
  52 #include "amd_pcie_helpers.h"
  53 #include "cgs_linux.h"
  54 #include "ppinterrupt.h"
  55
  56 #include "fiji_clockpowergating.h"
  57 #include "fiji_thermal.h"
  58
  59 #define VOLTAGE_SCALE   4
  60 #define SMC_RAM_END             0x40000
  61 #define VDDC_VDDCI_DELTA        300
  62
  63 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  64 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  65 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  66
  67 #define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
  68 #define MC_CG_ARB_FREQ_F1           0x0b
  69 #define MC_CG_ARB_FREQ_F2           0x0c
  70 #define MC_CG_ARB_FREQ_F3           0x0d
  71
  72 /* From smc_reg.h */
  73 #define SMC_CG_IND_START            0xc0030000
  74 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */
  75
  76 #define VOLTAGE_SCALE               4
  77 #define VOLTAGE_VID_OFFSET_SCALE1   625
  78 #define VOLTAGE_VID_OFFSET_SCALE2   100
  79
  80 #define VDDC_VDDCI_DELTA            300
  81
  82 #define ixSWRST_COMMAND_1           0x1400103
  83 #define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000
  84
  85 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  86 enum DPM_EVENT_SRC {
  87     DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
  88     DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
  89     DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
  90     DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
  91     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
  92 };
  93
  94
  95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
  96  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
  97  */
  98 static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
  99 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 100
 101 /* [FF, SS] type, [] 4 voltage ranges, and
 102  * [Floor Freq, Boundary Freq, VID min , VID max]
 103  */
 104 static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
 105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 106   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 107
 108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
 109  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
 110  */
 111 static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
 115
 116 struct fiji_power_state *cast_phw_fiji_power_state(
 117                                   struct pp_hw_power_state *hw_ps)
 118 {
 119         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 120                                 "Invalid Powerstate Type!",
 121                                  return NULL;);
 122
 123         return (struct fiji_power_state *)hw_ps;
 124 }
 125
 126 const struct fiji_power_state *cast_const_phw_fiji_power_state(
 127                                  const struct pp_hw_power_state *hw_ps)
 128 {
 129         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 130                                 "Invalid Powerstate Type!",
 131                                  return NULL;);
 132
 133         return (const struct fiji_power_state *)hw_ps;
 134 }
 135
 136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
 137 {
 138         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 139                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 140                         ? true : false;
 141 }
 142
 143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 144 {
 145         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 146         struct fiji_ulv_parm *ulv = &data->ulv;
 147
 148         ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
 149         data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
 150         data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
 151         data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
 152         data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
 153         data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
 154         data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
 155         data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
 156         data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
 157
 158         data->static_screen_threshold_unit =
 159                         PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
 160         data->static_screen_threshold =
 161                         PPFIJI_STATICSCREENTHRESHOLD_DFLT;
 162
 163         /* Unset ABM cap as it moved to DAL.
 164          * Add PHM_PlatformCaps_NonABMSupportInPPLib
 165          * for re-direct ABM related request to DAL
 166          */
 167         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 168                         PHM_PlatformCaps_ABM);
 169         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 170                         PHM_PlatformCaps_NonABMSupportInPPLib);
 171
 172         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 173                         PHM_PlatformCaps_DynamicACTiming);
 174
 175         fiji_initialize_power_tune_defaults(hwmgr);
 176
 177         data->mclk_stutter_mode_threshold = 60000;
 178         data->pcie_gen_performance.max = PP_PCIEGen1;
 179         data->pcie_gen_performance.min = PP_PCIEGen3;
 180         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 181         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 182         data->pcie_lane_performance.max = 0;
 183         data->pcie_lane_performance.min = 16;
 184         data->pcie_lane_power_saving.max = 0;
 185         data->pcie_lane_power_saving.min = 16;
 186
 187         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 188                         PHM_PlatformCaps_DynamicUVDState);
 189 }
 190
 191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 192         phm_ppt_v1_voltage_lookup_table *lookup_table,
 193         uint16_t virtual_voltage_id, int32_t *sclk)
 194 {
 195         uint8_t entryId;
 196         uint8_t voltageId;
 197         struct phm_ppt_v1_information *table_info =
 198                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 199
 200         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
 201
 202         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 203         for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
 204                 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 205                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 206                         break;
 207         }
 208
 209         PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
 210                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 211                         return -EINVAL;
 212                         );
 213
 214         *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
 215
 216         return 0;
 217 }
 218
 219 /**
 220 * Get Leakage VDDC based on leakage ID.
 221 *
 222 * @param    hwmgr  the address of the powerplay hardware manager.
 223 * @return   always 0
 224 */
 225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
 226 {
 227         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 228         uint16_t    vv_id;
 229         uint16_t    vddc = 0;
 230         uint16_t    evv_default = 1150;
 231         uint16_t    i, j;
 232         uint32_t  sclk = 0;
 233         struct phm_ppt_v1_information *table_info =
 234                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 235         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 236                         table_info->vdd_dep_on_sclk;
 237         int result;
 238
 239         for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
 240                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 241                 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
 242                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 243                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 244                                         PHM_PlatformCaps_ClockStretcher)) {
 245                                 for (j = 1; j < sclk_table->count; j++) {
 246                                         if (sclk_table->entries[j].clk == sclk &&
 247                                                         sclk_table->entries[j].cks_enable == 0) {
 248                                                 sclk += 5000;
 249                                                 break;
 250                                         }
 251                                 }
 252                         }
 253
 254                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 255                                         PHM_PlatformCaps_EnableDriverEVV))
 256                                 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
 257                                                 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
 258                         else
 259                                 result = -EINVAL;
 260
 261                         if (result)
 262                                 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
 263                                                 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
 264
 265                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 266                         PP_ASSERT_WITH_CODE((vddc < 2000),
 267                                         "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
 268
 269                         if (result)
 270                                 /* 1.15V is the default safe value for Fiji */
 271                                 vddc = evv_default;
 272
 273                         /* the voltage should not be zero nor equal to leakage ID */
 274                         if (vddc != 0 && vddc != vv_id) {
 275                                 data->vddc_leakage.actual_voltage
 276                                 [data->vddc_leakage.count] = vddc;
 277                                 data->vddc_leakage.leakage_id
 278                                 [data->vddc_leakage.count] = vv_id;
 279                                 data->vddc_leakage.count++;
 280                         }
 281                 }
 282         }
 283         return 0;
 284 }
 285
 286 /**
 287  * Change virtual leakage voltage to actual value.
 288  *
 289  * @param     hwmgr  the address of the powerplay hardware manager.
 290  * @param     pointer to changing voltage
 291  * @param     pointer to leakage table
 292  */
 293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 294                 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
 295 {
 296         uint32_t index;
 297
 298         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 299         for (index = 0; index < leakage_table->count; index++) {
 300                 /* if this voltage matches a leakage voltage ID */
 301                 /* patch with actual leakage voltage */
 302                 if (leakage_table->leakage_id[index] == *voltage) {
 303                         *voltage = leakage_table->actual_voltage[index];
 304                         break;
 305                 }
 306         }
 307
 308         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 309                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
 310 }
 311
 312 /**
 313 * Patch voltage lookup table by EVV leakages.
 314 *
 315 * @param     hwmgr  the address of the powerplay hardware manager.
 316 * @param     pointer to voltage lookup table
 317 * @param     pointer to leakage table
 318 * @return     always 0
 319 */
 320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 321                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 322                 struct fiji_leakage_voltage *leakage_table)
 323 {
 324         uint32_t i;
 325
 326         for (i = 0; i < lookup_table->count; i++)
 327                 fiji_patch_with_vdd_leakage(hwmgr,
 328                                 &lookup_table->entries[i].us_vdd, leakage_table);
 329
 330         return 0;
 331 }
 332
 333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
 334                 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
 335                 uint16_t *vddc)
 336 {
 337         struct phm_ppt_v1_information *table_info =
 338                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 339         fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 340         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
 341                         table_info->max_clock_voltage_on_dc.vddc;
 342         return 0;
 343 }
 344
 345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
 346                 struct pp_hwmgr *hwmgr)
 347 {
 348         uint8_t entryId;
 349         uint8_t voltageId;
 350         struct phm_ppt_v1_information *table_info =
 351                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 352
 353         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 354                         table_info->vdd_dep_on_sclk;
 355         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 356                         table_info->vdd_dep_on_mclk;
 357         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 358                         table_info->mm_dep_table;
 359
 360         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
 361                 voltageId = sclk_table->entries[entryId].vddInd;
 362                 sclk_table->entries[entryId].vddc =
 363                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 364         }
 365
 366         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
 367                 voltageId = mclk_table->entries[entryId].vddInd;
 368                 mclk_table->entries[entryId].vddc =
 369                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 370         }
 371
 372         for (entryId = 0; entryId < mm_table->count; ++entryId) {
 373                 voltageId = mm_table->entries[entryId].vddcInd;
 374                 mm_table->entries[entryId].vddc =
 375                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 376         }
 377
 378         return 0;
 379
 380 }
 381
 382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
 383 {
 384         /* Need to determine if we need calculated voltage. */
 385         return 0;
 386 }
 387
 388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
 389 {
 390         /* Need to determine if we need calculated voltage from mm table. */
 391         return 0;
 392 }
 393
 394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
 395                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 396 {
 397         uint32_t table_size, i, j;
 398         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 399         table_size = lookup_table->count;
 400
 401         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
 402                 "Lookup table is empty", return -EINVAL);
 403
 404         /* Sorting voltages */
 405         for (i = 0; i < table_size - 1; i++) {
 406                 for (j = i + 1; j > 0; j--) {
 407                         if (lookup_table->entries[j].us_vdd <
 408                                         lookup_table->entries[j - 1].us_vdd) {
 409                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 410                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 411                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 412                         }
 413                 }
 414         }
 415
 416         return 0;
 417 }
 418
 419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 420 {
 421         int result = 0;
 422         int tmp_result;
 423         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 424         struct phm_ppt_v1_information *table_info =
 425                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 426
 427         tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
 428                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 429         if (tmp_result)
 430                 result = tmp_result;
 431
 432         tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 433                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 434         if (tmp_result)
 435                 result = tmp_result;
 436
 437         tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 438         if (tmp_result)
 439                 result = tmp_result;
 440
 441         tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
 442         if (tmp_result)
 443                 result = tmp_result;
 444
 445         tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
 446         if (tmp_result)
 447                 result = tmp_result;
 448
 449         tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 450         if(tmp_result)
 451                 result = tmp_result;
 452
 453         return result;
 454 }
 455
 456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 457 {
 458         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 459         struct phm_ppt_v1_information *table_info =
 460                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 461
 462         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 463                         table_info->vdd_dep_on_sclk;
 464         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 465                         table_info->vdd_dep_on_mclk;
 466
 467         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
 468                 "VDD dependency on SCLK table is missing.       \
 469                 This table is mandatory", return -EINVAL);
 470         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 471                 "VDD dependency on SCLK table has to have is missing.   \
 472                 This table is mandatory", return -EINVAL);
 473
 474         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
 475                 "VDD dependency on MCLK table is missing.       \
 476                 This table is mandatory", return -EINVAL);
 477         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 478                 "VDD dependency on MCLK table has to have is missing.    \
 479                 This table is mandatory", return -EINVAL);
 480
 481         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
 482         data->max_vddc_in_pptable =     (uint16_t)allowed_sclk_vdd_table->
 483                         entries[allowed_sclk_vdd_table->count - 1].vddc;
 484
 485         table_info->max_clock_voltage_on_ac.sclk =
 486                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 487         table_info->max_clock_voltage_on_ac.mclk =
 488                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 489         table_info->max_clock_voltage_on_ac.vddc =
 490                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 491         table_info->max_clock_voltage_on_ac.vddci =
 492                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 493
 494         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 495                 table_info->max_clock_voltage_on_ac.sclk;
 496         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 497                 table_info->max_clock_voltage_on_ac.mclk;
 498         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 499                 table_info->max_clock_voltage_on_ac.vddc;
 500         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 501                 table_info->max_clock_voltage_on_ac.vddci;
 502
 503         return 0;
 504 }
 505
 506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 507 {
 508         uint32_t speedCntl = 0;
 509
 510         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 511         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 512                         ixPCIE_LC_SPEED_CNTL);
 513         return((uint16_t)PHM_GET_FIELD(speedCntl,
 514                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 515 }
 516
 517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 518 {
 519         uint32_t link_width;
 520
 521         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 522         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 523                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 524
 525         PP_ASSERT_WITH_CODE((7 >= link_width),
 526                         "Invalid PCIe lane width!", return 0);
 527
 528         return decode_pcie_lane_width(link_width);
 529 }
 530
 531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
 532 *
 533 * @param hwmgr Pointer to the hardware manager.
 534 * @param pPowerState The address of the PowerState instance being created.
 535 *
 536 */
 537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
 538                 struct pp_hw_power_state *hw_ps)
 539 {
 540         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 541         struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
 542         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
 543         uint16_t size;
 544         uint8_t frev, crev;
 545         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 546
 547         /* First retrieve the Boot clocks and VDDC from the firmware info table.
 548          * We assume here that fw_info is unchanged if this call fails.
 549          */
 550         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
 551                         hwmgr->device, index,
 552                         &size, &frev, &crev);
 553         if (!fw_info)
 554                 /* During a test, there is no firmware info table. */
 555                 return 0;
 556
 557         /* Patch the state. */
 558         data->vbios_boot_state.sclk_bootup_value =
 559                         le32_to_cpu(fw_info->ulDefaultEngineClock);
 560         data->vbios_boot_state.mclk_bootup_value =
 561                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
 562         data->vbios_boot_state.mvdd_bootup_value =
 563                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
 564         data->vbios_boot_state.vddc_bootup_value =
 565                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
 566         data->vbios_boot_state.vddci_bootup_value =
 567                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
 568         data->vbios_boot_state.pcie_gen_bootup_value =
 569                         fiji_get_current_pcie_speed(hwmgr);
 570         data->vbios_boot_state.pcie_lane_bootup_value =
 571                         (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
 572
 573         /* set boot power state */
 574         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
 575         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
 576         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
 577         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
 578
 579         return 0;
 580 }
 581
 582 static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 583 {
 584         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 585
 586         if (data->soft_pp_table) {
 587                 kfree(data->soft_pp_table);
 588                 data->soft_pp_table = NULL;
 589         }
 590
 591         return phm_hwmgr_backend_fini(hwmgr);
 592 }
 593
 594 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 595 {
 596         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 597         uint32_t i;
 598         struct phm_ppt_v1_information *table_info =
 599                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 600         bool stay_in_boot;
 601         int result;
 602
 603         data->dll_default_on = false;
 604         data->sram_end = SMC_RAM_END;
 605
 606         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 607                 data->activity_target[i] = FIJI_AT_DFLT;
 608
 609         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
 610
 611         data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
 612         data->mclk_dpm0_activity_target = 0xa;
 613
 614         data->sclk_dpm_key_disabled = 0;
 615         data->mclk_dpm_key_disabled = 0;
 616         data->pcie_dpm_key_disabled = 0;
 617
 618         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 619                         PHM_PlatformCaps_UnTabledHardwareInterface);
 620         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 621                         PHM_PlatformCaps_TablelessHardwareInterface);
 622
 623         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 624                         PHM_PlatformCaps_SclkDeepSleep);
 625
 626         data->gpio_debug = 0;
 627
 628         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 629                         PHM_PlatformCaps_DynamicPatchPowerState);
 630
 631         /* need to set voltage control types before EVV patching */
 632         data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
 633         data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
 634         data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
 635
 636         data->force_pcie_gen = PP_PCIEGenInvalid;
 637
 638         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 639                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
 640                 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 641
 642         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 643                         PHM_PlatformCaps_EnableMVDDControl))
 644                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 645                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
 646                         data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 647
 648         if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
 649                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 650                         PHM_PlatformCaps_EnableMVDDControl);
 651
 652         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 653                         PHM_PlatformCaps_ControlVDDCI)) {
 654                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 655                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 656                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 657                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 658                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
 659                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 660         }
 661
 662         if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
 663                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 664                                 PHM_PlatformCaps_ControlVDDCI);
 665
 666         if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
 667                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 668                                 PHM_PlatformCaps_ClockStretcher);
 669
 670         fiji_init_dpm_defaults(hwmgr);
 671
 672         /* Get leakage voltage based on leakage ID. */
 673         fiji_get_evv_voltages(hwmgr);
 674
 675         /* Patch our voltage dependency table with actual leakage voltage
 676          * We need to perform leakage translation before it's used by other functions
 677          */
 678         fiji_complete_dependency_tables(hwmgr);
 679
 680         /* Parse pptable data read from VBIOS */
 681         fiji_set_private_data_based_on_pptable(hwmgr);
 682
 683         /* ULV Support */
 684         data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
 685
 686         /* Initalize Dynamic State Adjustment Rule Settings */
 687         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
 688
 689         if (!result) {
 690                 data->uvd_enabled = false;
 691                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 692                                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 693                 data->vddc_phase_shed_control = false;
 694         }
 695
 696         stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 697                         PHM_PlatformCaps_StayInBootState);
 698
 699         if (0 == result) {
 700                 struct cgs_system_info sys_info = {0};
 701
 702                 data->is_tlu_enabled = 0;
 703                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 704                                 FIJI_MAX_HARDWARE_POWERLEVELS;
 705                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 706                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
 707
 708                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 709                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 710
 711                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
 712                                 hwmgr->thermal_controller.
 713                                 advanceFanControlParameters.ucFanControlMode) {
 714                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
 715                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
 716                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
 717                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
 718                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
 719                                         table_info->cac_dtp_table->usOperatingTempMinLimit;
 720                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
 721                                         table_info->cac_dtp_table->usOperatingTempMaxLimit;
 722                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
 723                                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
 724                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
 725                                         table_info->cac_dtp_table->usOperatingTempStep;
 726                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
 727                                         table_info->cac_dtp_table->usTargetOperatingTemp;
 728
 729                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 730                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 731                 }
 732
 733                 sys_info.size = sizeof(struct cgs_system_info);
 734                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
 735                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 736                 if (result)
 737                         data->pcie_gen_cap = 0x30007;
 738                 else
 739                         data->pcie_gen_cap = (uint32_t)sys_info.value;
 740                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 741                         data->pcie_spc_cap = 20;
 742                 sys_info.size = sizeof(struct cgs_system_info);
 743                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
 744                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 745                 if (result)
 746                         data->pcie_lane_cap = 0x2f0000;
 747                 else
 748                         data->pcie_lane_cap = (uint32_t)sys_info.value;
 749         } else {
 750                 /* Ignore return value in here, we are cleaning up a mess. */
 751                 fiji_hwmgr_backend_fini(hwmgr);
 752         }
 753
 754         return 0;
 755 }
 756
 757 /**
 758  * Read clock related registers.
 759  *
 760  * @param    hwmgr  the address of the powerplay hardware manager.
 761  * @return   always 0
 762  */
 763 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
 764 {
 765         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 766
 767         data->clock_registers.vCG_SPLL_FUNC_CNTL =
 768                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 769                                 ixCG_SPLL_FUNC_CNTL);
 770         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
 771                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 772                                 ixCG_SPLL_FUNC_CNTL_2);
 773         data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
 774                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 775                                 ixCG_SPLL_FUNC_CNTL_3);
 776         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
 777                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 778                                 ixCG_SPLL_FUNC_CNTL_4);
 779         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
 780                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 781                                 ixCG_SPLL_SPREAD_SPECTRUM);
 782         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 783                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 784                                 ixCG_SPLL_SPREAD_SPECTRUM_2);
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * Find out if memory is GDDR5.
 791  *
 792  * @param    hwmgr  the address of the powerplay hardware manager.
 793  * @return   always 0
 794  */
 795 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
 796 {
 797         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 798         uint32_t temp;
 799
 800         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 801
 802         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 803                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 804                          MC_SEQ_MISC0_GDDR5_SHIFT));
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * Enables Dynamic Power Management by SMC
 811  *
 812  * @param    hwmgr  the address of the powerplay hardware manager.
 813  * @return   always 0
 814  */
 815 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 816 {
 817         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 818                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
 819
 820         return 0;
 821 }
 822
 823 /**
 824  * Initialize PowerGating States for different engines
 825  *
 826  * @param    hwmgr  the address of the powerplay hardware manager.
 827  * @return   always 0
 828  */
 829 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
 830 {
 831         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 832
 833         data->uvd_power_gated = false;
 834         data->vce_power_gated = false;
 835         data->samu_power_gated = false;
 836         data->acp_power_gated = false;
 837         data->pg_acp_init = true;
 838
 839         return 0;
 840 }
 841
 842 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 843 {
 844         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 845         data->low_sclk_interrupt_threshold = 0;
 846
 847         return 0;
 848 }
 849
 850 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
 851 {
 852         int tmp_result, result = 0;
 853
 854         tmp_result = fiji_read_clock_registers(hwmgr);
 855         PP_ASSERT_WITH_CODE((0 == tmp_result),
 856                         "Failed to read clock registers!", result = tmp_result);
 857
 858         tmp_result = fiji_get_memory_type(hwmgr);
 859         PP_ASSERT_WITH_CODE((0 == tmp_result),
 860                         "Failed to get memory type!", result = tmp_result);
 861
 862         tmp_result = fiji_enable_acpi_power_management(hwmgr);
 863         PP_ASSERT_WITH_CODE((0 == tmp_result),
 864                         "Failed to enable ACPI power management!", result = tmp_result);
 865
 866         tmp_result = fiji_init_power_gate_state(hwmgr);
 867         PP_ASSERT_WITH_CODE((0 == tmp_result),
 868                         "Failed to init power gate state!", result = tmp_result);
 869
 870         tmp_result = tonga_get_mc_microcode_version(hwmgr);
 871         PP_ASSERT_WITH_CODE((0 == tmp_result),
 872                         "Failed to get MC microcode version!", result = tmp_result);
 873
 874         tmp_result = fiji_init_sclk_threshold(hwmgr);
 875         PP_ASSERT_WITH_CODE((0 == tmp_result),
 876                         "Failed to init sclk threshold!", result = tmp_result);
 877
 878         return result;
 879 }
 880
 881 /**
 882 * Checks if we want to support voltage control
 883 *
 884 * @param    hwmgr  the address of the powerplay hardware manager.
 885 */
 886 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
 887 {
 888         const struct fiji_hwmgr *data =
 889                         (const struct fiji_hwmgr *)(hwmgr->backend);
 890
 891         return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
 892 }
 893
 894 /**
 895 * Enable voltage control
 896 *
 897 * @param    hwmgr  the address of the powerplay hardware manager.
 898 * @return   always 0
 899 */
 900 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
 901 {
 902         /* enable voltage control */
 903         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 904                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 905
 906         return 0;
 907 }
 908
 909 /**
 910 * Remove repeated voltage values and create table with unique values.
 911 *
 912 * @param    hwmgr  the address of the powerplay hardware manager.
 913 * @param    vol_table  the pointer to changing voltage table
 914 * @return    0 in success
 915 */
 916
 917 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
 918                 struct pp_atomctrl_voltage_table *vol_table)
 919 {
 920         uint32_t i, j;
 921         uint16_t vvalue;
 922         bool found = false;
 923         struct pp_atomctrl_voltage_table *table;
 924
 925         PP_ASSERT_WITH_CODE((NULL != vol_table),
 926                         "Voltage Table empty.", return -EINVAL);
 927         table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
 928                         GFP_KERNEL);
 929
 930         if (NULL == table)
 931                 return -ENOMEM;
 932
 933         table->mask_low = vol_table->mask_low;
 934         table->phase_delay = vol_table->phase_delay;
 935
 936         for (i = 0; i < vol_table->count; i++) {
 937                 vvalue = vol_table->entries[i].value;
 938                 found = false;
 939
 940                 for (j = 0; j < table->count; j++) {
 941                         if (vvalue == table->entries[j].value) {
 942                                 found = true;
 943                                 break;
 944                         }
 945                 }
 946
 947                 if (!found) {
 948                         table->entries[table->count].value = vvalue;
 949                         table->entries[table->count].smio_low =
 950                                         vol_table->entries[i].smio_low;
 951                         table->count++;
 952                 }
 953         }
 954
 955         memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
 956         kfree(table);
 957
 958         return 0;
 959 }
 960
 961 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
 962                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 963 {
 964         uint32_t i;
 965         int result;
 966         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 967         struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
 968
 969         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 970                         "Voltage Dependency Table empty.", return -EINVAL);
 971
 972         vol_table->mask_low = 0;
 973         vol_table->phase_delay = 0;
 974         vol_table->count = dep_table->count;
 975
 976         for (i = 0; i < dep_table->count; i++) {
 977                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
 978                 vol_table->entries[i].smio_low = 0;
 979         }
 980
 981         result = fiji_trim_voltage_table(hwmgr, vol_table);
 982         PP_ASSERT_WITH_CODE((0 == result),
 983                         "Failed to trim MVDD table.", return result);
 984
 985         return 0;
 986 }
 987
 988 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
 989                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 990 {
 991         uint32_t i;
 992         int result;
 993         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 994         struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
 995
 996         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 997                         "Voltage Dependency Table empty.", return -EINVAL);
 998
 999         vol_table->mask_low = 0;
1000         vol_table->phase_delay = 0;
1001         vol_table->count = dep_table->count;
1002
1003         for (i = 0; i < dep_table->count; i++) {
1004                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1005                 vol_table->entries[i].smio_low = 0;
1006         }
1007
1008         result = fiji_trim_voltage_table(hwmgr, vol_table);
1009         PP_ASSERT_WITH_CODE((0 == result),
1010                         "Failed to trim VDDCI table.", return result);
1011
1012         return 0;
1013 }
1014
1015 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1016                 phm_ppt_v1_voltage_lookup_table *lookup_table)
1017 {
1018         int i = 0;
1019         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1020         struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
1021
1022         PP_ASSERT_WITH_CODE((0 != lookup_table->count),
1023                         "Voltage Lookup Table empty.", return -EINVAL);
1024
1025         vol_table->mask_low = 0;
1026         vol_table->phase_delay = 0;
1027
1028         vol_table->count = lookup_table->count;
1029
1030         for (i = 0; i < vol_table->count; i++) {
1031                 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
1032                 vol_table->entries[i].smio_low = 0;
1033         }
1034
1035         return 0;
1036 }
1037
1038 /* ---- Voltage Tables ----
1039  * If the voltage table would be bigger than
1040  * what will fit into the state table on
1041  * the SMC keep only the higher entries.
1042  */
1043 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1044                 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1045 {
1046         unsigned int i, diff;
1047
1048         if (vol_table->count <= max_vol_steps)
1049                 return;
1050
1051         diff = vol_table->count - max_vol_steps;
1052
1053         for (i = 0; i < max_vol_steps; i++)
1054                 vol_table->entries[i] = vol_table->entries[i + diff];
1055
1056         vol_table->count = max_vol_steps;
1057
1058         return;
1059 }
1060
1061 /**
1062 * Create Voltage Tables.
1063 *
1064 * @param    hwmgr  the address of the powerplay hardware manager.
1065 * @return   always 0
1066 */
1067 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1068 {
1069         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1070         struct phm_ppt_v1_information *table_info =
1071                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1072         int result;
1073
1074         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1075                 result = atomctrl_get_voltage_table_v3(hwmgr,
1076                                 VOLTAGE_TYPE_MVDDC,     VOLTAGE_OBJ_GPIO_LUT,
1077                                 &(data->mvdd_voltage_table));
1078                 PP_ASSERT_WITH_CODE((0 == result),
1079                                 "Failed to retrieve MVDD table.",
1080                                 return result);
1081         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1082                 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1083                                 table_info->vdd_dep_on_mclk);
1084                 PP_ASSERT_WITH_CODE((0 == result),
1085                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1086                                 return result;);
1087         }
1088
1089         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1090                 result = atomctrl_get_voltage_table_v3(hwmgr,
1091                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1092                                 &(data->vddci_voltage_table));
1093                 PP_ASSERT_WITH_CODE((0 == result),
1094                                 "Failed to retrieve VDDCI table.",
1095                                 return result);
1096         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1097                 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1098                                 table_info->vdd_dep_on_mclk);
1099                 PP_ASSERT_WITH_CODE((0 == result),
1100                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1101                                 return result);
1102         }
1103
1104         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1105                 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1106                                 table_info->vddc_lookup_table);
1107                 PP_ASSERT_WITH_CODE((0 == result),
1108                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
1109                                 return result);
1110         }
1111
1112         PP_ASSERT_WITH_CODE(
1113                         (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1114                         "Too many voltage values for VDDC. Trimming to fit state table.",
1115                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1116                                         SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1117
1118         PP_ASSERT_WITH_CODE(
1119                         (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1120                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1121                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1122                                         SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1123
1124         PP_ASSERT_WITH_CODE(
1125                         (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1126                         "Too many voltage values for MVDD. Trimming to fit state table.",
1127                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1128                                         SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1129
1130         return 0;
1131 }
1132
1133 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1134 {
1135         /* Program additional LP registers
1136          * that are no longer programmed by VBIOS
1137          */
1138         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1139                         cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1140         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1141                         cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1142         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1143                         cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1144         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1145                         cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1146         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1147                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1148         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1149                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1150         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1151                         cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1152
1153         return 0;
1154 }
1155
1156 /**
1157 * Programs static screed detection parameters
1158 *
1159 * @param    hwmgr  the address of the powerplay hardware manager.
1160 * @return   always 0
1161 */
1162 static int fiji_program_static_screen_threshold_parameters(
1163                 struct pp_hwmgr *hwmgr)
1164 {
1165         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1166
1167         /* Set static screen threshold unit */
1168         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1169                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1170                         data->static_screen_threshold_unit);
1171         /* Set static screen threshold */
1172         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1173                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1174                         data->static_screen_threshold);
1175
1176         return 0;
1177 }
1178
1179 /**
1180 * Setup display gap for glitch free memory clock switching.
1181 *
1182 * @param    hwmgr  the address of the powerplay hardware manager.
1183 * @return   always  0
1184 */
1185 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1186 {
1187         uint32_t displayGap =
1188                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1189                                         ixCG_DISPLAY_GAP_CNTL);
1190
1191         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1192                         DISP_GAP, DISPLAY_GAP_IGNORE);
1193
1194         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1195                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1196
1197         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1198                         ixCG_DISPLAY_GAP_CNTL, displayGap);
1199
1200         return 0;
1201 }
1202
1203 /**
1204 * Programs activity state transition voting clients
1205 *
1206 * @param    hwmgr  the address of the powerplay hardware manager.
1207 * @return   always  0
1208 */
1209 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1210 {
1211         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1212
1213         /* Clear reset for voting clients before enabling DPM */
1214         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1215                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1216         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1217                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1218
1219         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1220                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1221         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1222                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1223         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1224                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1225         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1226                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1227         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1228                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1229         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1230                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1231         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1232                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1233         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1234                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1235
1236         return 0;
1237 }
1238
1239 /**
1240 * Get the location of various tables inside the FW image.
1241 *
1242 * @param    hwmgr  the address of the powerplay hardware manager.
1243 * @return   always  0
1244 */
1245 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1246 {
1247         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1248         struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1249         uint32_t tmp;
1250         int result;
1251         bool error = false;
1252
1253         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1254                         SMU7_FIRMWARE_HEADER_LOCATION +
1255                         offsetof(SMU73_Firmware_Header, DpmTable),
1256                         &tmp, data->sram_end);
1257
1258         if (0 == result)
1259                 data->dpm_table_start = tmp;
1260
1261         error |= (0 != result);
1262
1263         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1264                         SMU7_FIRMWARE_HEADER_LOCATION +
1265                         offsetof(SMU73_Firmware_Header, SoftRegisters),
1266                         &tmp, data->sram_end);
1267
1268         if (!result) {
1269                 data->soft_regs_start = tmp;
1270                 smu_data->soft_regs_start = tmp;
1271         }
1272
1273         error |= (0 != result);
1274
1275         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1276                         SMU7_FIRMWARE_HEADER_LOCATION +
1277                         offsetof(SMU73_Firmware_Header, mcRegisterTable),
1278                         &tmp, data->sram_end);
1279
1280         if (!result)
1281                 data->mc_reg_table_start = tmp;
1282
1283         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1284                         SMU7_FIRMWARE_HEADER_LOCATION +
1285                         offsetof(SMU73_Firmware_Header, FanTable),
1286                         &tmp, data->sram_end);
1287
1288         if (!result)
1289                 data->fan_table_start = tmp;
1290
1291         error |= (0 != result);
1292
1293         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1294                         SMU7_FIRMWARE_HEADER_LOCATION +
1295                         offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1296                         &tmp, data->sram_end);
1297
1298         if (!result)
1299                 data->arb_table_start = tmp;
1300
1301         error |= (0 != result);
1302
1303         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1304                         SMU7_FIRMWARE_HEADER_LOCATION +
1305                         offsetof(SMU73_Firmware_Header, Version),
1306                         &tmp, data->sram_end);
1307
1308         if (!result)
1309                 hwmgr->microcode_version_info.SMC = tmp;
1310
1311         error |= (0 != result);
1312
1313         return error ? -1 : 0;
1314 }
1315
1316 /* Copy one arb setting to another and then switch the active set.
1317  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1318  */
1319 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1320                 uint32_t arb_src, uint32_t arb_dest)
1321 {
1322         uint32_t mc_arb_dram_timing;
1323         uint32_t mc_arb_dram_timing2;
1324         uint32_t burst_time;
1325         uint32_t mc_cg_config;
1326
1327         switch (arb_src) {
1328         case MC_CG_ARB_FREQ_F0:
1329                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1330                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1331                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1332                 break;
1333         case MC_CG_ARB_FREQ_F1:
1334                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1335                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1336                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1337                 break;
1338         default:
1339                 return -EINVAL;
1340         }
1341
1342         switch (arb_dest) {
1343         case MC_CG_ARB_FREQ_F0:
1344                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1345                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1346                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1347                 break;
1348         case MC_CG_ARB_FREQ_F1:
1349                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1350                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1351                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1352                 break;
1353         default:
1354                 return -EINVAL;
1355         }
1356
1357         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1358         mc_cg_config |= 0x0000000F;
1359         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1360         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1361
1362         return 0;
1363 }
1364
1365 /**
1366 * Initial switch from ARB F0->F1
1367 *
1368 * @param    hwmgr  the address of the powerplay hardware manager.
1369 * @return   always 0
1370 * This function is to be called from the SetPowerState table.
1371 */
1372 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1373 {
1374         return fiji_copy_and_switch_arb_sets(hwmgr,
1375                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1376 }
1377
1378 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1379                 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1380 {
1381         int i;
1382         PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1383                         "Fatal error, can not set up single DPM table entries "
1384                         "to exceed max number!",);
1385
1386         dpm_table->count = count;
1387         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1388                 dpm_table->dpm_levels[i].enabled = false;
1389
1390         return 0;
1391 }
1392
1393 static void fiji_setup_pcie_table_entry(
1394         struct fiji_single_dpm_table *dpm_table,
1395         uint32_t index, uint32_t pcie_gen,
1396         uint32_t pcie_lanes)
1397 {
1398         dpm_table->dpm_levels[index].value = pcie_gen;
1399         dpm_table->dpm_levels[index].param1 = pcie_lanes;
1400         dpm_table->dpm_levels[index].enabled = 1;
1401 }
1402
1403 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1404 {
1405         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1406         struct phm_ppt_v1_information *table_info =
1407                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1408         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1409         uint32_t i, max_entry;
1410
1411         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1412                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
1413                         return -EINVAL);
1414
1415         if (data->use_pcie_performance_levels &&
1416                         !data->use_pcie_power_saving_levels) {
1417                 data->pcie_gen_power_saving = data->pcie_gen_performance;
1418                 data->pcie_lane_power_saving = data->pcie_lane_performance;
1419         } else if (!data->use_pcie_performance_levels &&
1420                         data->use_pcie_power_saving_levels) {
1421                 data->pcie_gen_performance = data->pcie_gen_power_saving;
1422                 data->pcie_lane_performance = data->pcie_lane_power_saving;
1423         }
1424
1425         fiji_reset_single_dpm_table(hwmgr,
1426                         &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1427
1428         if (pcie_table != NULL) {
1429                 /* max_entry is used to make sure we reserve one PCIE level
1430                  * for boot level (fix for A+A PSPP issue).
1431                  * If PCIE table from PPTable have ULV entry + 8 entries,
1432                  * then ignore the last entry.*/
1433                 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1434                                 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1435                 for (i = 1; i < max_entry; i++) {
1436                         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1437                                         get_pcie_gen_support(data->pcie_gen_cap,
1438                                                         pcie_table->entries[i].gen_speed),
1439                                         get_pcie_lane_support(data->pcie_lane_cap,
1440                                                         pcie_table->entries[i].lane_width));
1441                 }
1442                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1443         } else {
1444                 /* Hardcode Pcie Table */
1445                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1446                                 get_pcie_gen_support(data->pcie_gen_cap,
1447                                                 PP_Min_PCIEGen),
1448                                 get_pcie_lane_support(data->pcie_lane_cap,
1449                                                 PP_Max_PCIELane));
1450                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1451                                 get_pcie_gen_support(data->pcie_gen_cap,
1452                                                 PP_Min_PCIEGen),
1453                                 get_pcie_lane_support(data->pcie_lane_cap,
1454                                                 PP_Max_PCIELane));
1455                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1456                                 get_pcie_gen_support(data->pcie_gen_cap,
1457                                                 PP_Max_PCIEGen),
1458                                 get_pcie_lane_support(data->pcie_lane_cap,
1459                                                 PP_Max_PCIELane));
1460                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1461                                 get_pcie_gen_support(data->pcie_gen_cap,
1462                                                 PP_Max_PCIEGen),
1463                                 get_pcie_lane_support(data->pcie_lane_cap,
1464                                                 PP_Max_PCIELane));
1465                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1466                                 get_pcie_gen_support(data->pcie_gen_cap,
1467                                                 PP_Max_PCIEGen),
1468                                 get_pcie_lane_support(data->pcie_lane_cap,
1469                                                 PP_Max_PCIELane));
1470                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1471                                 get_pcie_gen_support(data->pcie_gen_cap,
1472                                                 PP_Max_PCIEGen),
1473                                 get_pcie_lane_support(data->pcie_lane_cap,
1474                                                 PP_Max_PCIELane));
1475
1476                 data->dpm_table.pcie_speed_table.count = 6;
1477         }
1478         /* Populate last level for boot PCIE level, but do not increment count. */
1479         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1480                         data->dpm_table.pcie_speed_table.count,
1481                         get_pcie_gen_support(data->pcie_gen_cap,
1482                                         PP_Min_PCIEGen),
1483                         get_pcie_lane_support(data->pcie_lane_cap,
1484                                         PP_Max_PCIELane));
1485
1486         return 0;
1487 }
1488
1489 /*
1490  * This function is to initalize all DPM state tables
1491  * for SMU7 based on the dependency table.
1492  * Dynamic state patching function will then trim these
1493  * state tables to the allowed range based
1494  * on the power policy or external client requests,
1495  * such as UVD request, etc.
1496  */
1497 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1498 {
1499         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1500         struct phm_ppt_v1_information *table_info =
1501                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1502         uint32_t i;
1503
1504         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1505                         table_info->vdd_dep_on_sclk;
1506         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1507                         table_info->vdd_dep_on_mclk;
1508
1509         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1510                         "SCLK dependency table is missing. This table is mandatory",
1511                         return -EINVAL);
1512         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1513                         "SCLK dependency table has to have is missing. "
1514                         "This table is mandatory",
1515                         return -EINVAL);
1516
1517         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1518                         "MCLK dependency table is missing. This table is mandatory",
1519                         return -EINVAL);
1520         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1521                         "MCLK dependency table has to have is missing. "
1522                         "This table is mandatory",
1523                         return -EINVAL);
1524
1525         /* clear the state table to reset everything to default */
1526         fiji_reset_single_dpm_table(hwmgr,
1527                         &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1528         fiji_reset_single_dpm_table(hwmgr,
1529                         &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1530
1531         /* Initialize Sclk DPM table based on allow Sclk values */
1532         data->dpm_table.sclk_table.count = 0;
1533         for (i = 0; i < dep_sclk_table->count; i++) {
1534                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1535                                 [data->dpm_table.sclk_table.count - 1].value !=
1536                                                 dep_sclk_table->entries[i].clk) {
1537                         data->dpm_table.sclk_table.dpm_levels
1538                         [data->dpm_table.sclk_table.count].value =
1539                                         dep_sclk_table->entries[i].clk;
1540                         data->dpm_table.sclk_table.dpm_levels
1541                         [data->dpm_table.sclk_table.count].enabled =
1542                                         (i == 0) ? true : false;
1543                         data->dpm_table.sclk_table.count++;
1544                 }
1545         }
1546
1547         /* Initialize Mclk DPM table based on allow Mclk values */
1548         data->dpm_table.mclk_table.count = 0;
1549         for (i=0; i<dep_mclk_table->count; i++) {
1550                 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1551                                 [data->dpm_table.mclk_table.count - 1].value !=
1552                                                 dep_mclk_table->entries[i].clk) {
1553                         data->dpm_table.mclk_table.dpm_levels
1554                         [data->dpm_table.mclk_table.count].value =
1555                                         dep_mclk_table->entries[i].clk;
1556                         data->dpm_table.mclk_table.dpm_levels
1557                         [data->dpm_table.mclk_table.count].enabled =
1558                                         (i == 0) ? true : false;
1559                         data->dpm_table.mclk_table.count++;
1560                 }
1561         }
1562
1563         /* setup PCIE gen speed levels */
1564         fiji_setup_default_pcie_table(hwmgr);
1565
1566         /* save a copy of the default DPM table */
1567         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1568                         sizeof(struct fiji_dpm_table));
1569
1570         return 0;
1571 }
1572
1573 /**
1574  * @brief PhwFiji_GetVoltageOrder
1575  *  Returns index of requested voltage record in lookup(table)
1576  * @param lookup_table - lookup list to search in
1577  * @param voltage - voltage to look for
1578  * @return 0 on success
1579  */
1580 uint8_t fiji_get_voltage_index(
1581                 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1582 {
1583         uint8_t count = (uint8_t) (lookup_table->count);
1584         uint8_t i;
1585
1586         PP_ASSERT_WITH_CODE((NULL != lookup_table),
1587                         "Lookup Table empty.", return 0);
1588         PP_ASSERT_WITH_CODE((0 != count),
1589                         "Lookup Table empty.", return 0);
1590
1591         for (i = 0; i < lookup_table->count; i++) {
1592                 /* find first voltage equal or bigger than requested */
1593                 if (lookup_table->entries[i].us_vdd >= voltage)
1594                         return i;
1595         }
1596         /* voltage is bigger than max voltage in the table */
1597         return i - 1;
1598 }
1599
1600 /**
1601 * Preparation of vddc and vddgfx CAC tables for SMC.
1602 *
1603 * @param    hwmgr  the address of the hardware manager
1604 * @param    table  the SMC DPM table structure to be populated
1605 * @return   always 0
1606 */
1607 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1608                 struct SMU73_Discrete_DpmTable *table)
1609 {
1610         uint32_t count;
1611         uint8_t index;
1612         int result = 0;
1613         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1614         struct phm_ppt_v1_information *table_info =
1615                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1616         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1617                         table_info->vddc_lookup_table;
1618         /* tables is already swapped, so in order to use the value from it,
1619          * we need to swap it back.
1620          * We are populating vddc CAC data to BapmVddc table
1621          * in split and merged mode
1622          */
1623         for( count = 0; count<lookup_table->count; count++) {
1624                 index = fiji_get_voltage_index(lookup_table,
1625                                 data->vddc_voltage_table.entries[count].value);
1626                 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1627                                 (lookup_table->entries[index].us_cac_low *
1628                                                 VOLTAGE_SCALE)) / 25);
1629                 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1630                                 (lookup_table->entries[index].us_cac_high *
1631                                                 VOLTAGE_SCALE)) / 25);
1632         }
1633
1634         return result;
1635 }
1636
1637 /**
1638 * Preparation of voltage tables for SMC.
1639 *
1640 * @param    hwmgr   the address of the hardware manager
1641 * @param    table   the SMC DPM table structure to be populated
1642 * @return   always  0
1643 */
1644
1645 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1646                 struct SMU73_Discrete_DpmTable *table)
1647 {
1648         int result;
1649
1650         result = fiji_populate_cac_table(hwmgr, table);
1651         PP_ASSERT_WITH_CODE(0 == result,
1652                         "can not populate CAC voltage tables to SMC",
1653                         return -EINVAL);
1654
1655         return 0;
1656 }
1657
1658 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1659                 struct SMU73_Discrete_Ulv *state)
1660 {
1661         int result = 0;
1662         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1663         struct phm_ppt_v1_information *table_info =
1664                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1665
1666         state->CcPwrDynRm = 0;
1667         state->CcPwrDynRm1 = 0;
1668
1669         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1670         state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1671                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1672
1673         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1674
1675         if (!result) {
1676                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1677                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1678                 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1679         }
1680         return result;
1681 }
1682
1683 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1684                 struct SMU73_Discrete_DpmTable *table)
1685 {
1686         return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1687 }
1688
1689 static int32_t fiji_get_dpm_level_enable_mask_value(
1690                 struct fiji_single_dpm_table* dpm_table)
1691 {
1692         int32_t i;
1693         int32_t mask = 0;
1694
1695         for (i = dpm_table->count; i > 0; i--) {
1696                 mask = mask << 1;
1697                 if (dpm_table->dpm_levels[i - 1].enabled)
1698                         mask |= 0x1;
1699                 else
1700                         mask &= 0xFFFFFFFE;
1701         }
1702         return mask;
1703 }
1704
1705 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1706                 struct SMU73_Discrete_DpmTable *table)
1707 {
1708         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1709         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1710         int i;
1711
1712         /* Index (dpm_table->pcie_speed_table.count)
1713          * is reserved for PCIE boot level. */
1714         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1715                 table->LinkLevel[i].PcieGenSpeed  =
1716                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1717                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1718                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1719                 table->LinkLevel[i].EnabledForActivity = 1;
1720                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1721                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1722                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1723         }
1724
1725         data->smc_state_table.LinkLevelCount =
1726                         (uint8_t)dpm_table->pcie_speed_table.count;
1727         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1728                         fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1729
1730         return 0;
1731 }
1732
1733 /**
1734 * Calculates the SCLK dividers using the provided engine clock
1735 *
1736 * @param    hwmgr  the address of the hardware manager
1737 * @param    clock  the engine clock to use to populate the structure
1738 * @param    sclk   the SMC SCLK structure to be populated
1739 */
1740 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1741                 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1742 {
1743         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1744         struct pp_atomctrl_clock_dividers_vi dividers;
1745         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1746         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1747         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1748         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1749         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1750         uint32_t ref_clock;
1751         uint32_t ref_divider;
1752         uint32_t fbdiv;
1753         int result;
1754
1755         /* get the engine clock dividers for this clock value */
1756         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
1757
1758         PP_ASSERT_WITH_CODE(result == 0,
1759                         "Error retrieving Engine Clock dividers from VBIOS.",
1760                         return result);
1761
1762         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1763         ref_clock = atomctrl_get_reference_clock(hwmgr);
1764         ref_divider = 1 + dividers.uc_pll_ref_div;
1765
1766         /* low 14 bits is fraction and high 12 bits is divider */
1767         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1768
1769         /* SPLL_FUNC_CNTL setup */
1770         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1771                         SPLL_REF_DIV, dividers.uc_pll_ref_div);
1772         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1773                         SPLL_PDIV_A,  dividers.uc_pll_post_div);
1774
1775         /* SPLL_FUNC_CNTL_3 setup*/
1776         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1777                         SPLL_FB_DIV, fbdiv);
1778
1779         /* set to use fractional accumulation*/
1780         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1781                         SPLL_DITHEN, 1);
1782
1783         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1784                                 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1785                 struct pp_atomctrl_internal_ss_info ssInfo;
1786
1787                 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1788                 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1789                                 vco_freq, &ssInfo)) {
1790                         /*
1791                          * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1792                          * ss_info.speed_spectrum_rate -- in unit of khz
1793                          *
1794                          * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1795                          */
1796                         uint32_t clk_s = ref_clock * 5 /
1797                                         (ref_divider * ssInfo.speed_spectrum_rate);
1798                         /* clkv = 2 * D * fbdiv / NS */
1799                         uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1800                                         fbdiv / (clk_s * 10000);
1801
1802                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1803                                         CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1804                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1805                                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1806                         cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1807                                         CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1808                 }
1809         }
1810
1811         sclk->SclkFrequency        = clock;
1812         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
1813         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
1814         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
1815         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
1816         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
1817
1818         return 0;
1819 }
1820
1821 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1822 {
1823         uint32_t  i;
1824         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1825         struct pp_atomctrl_voltage_table *vddci_table =
1826                         &(data->vddci_voltage_table);
1827
1828         for (i = 0; i < vddci_table->count; i++) {
1829                 if (vddci_table->entries[i].value >= vddci)
1830                         return vddci_table->entries[i].value;
1831         }
1832
1833         PP_ASSERT_WITH_CODE(false,
1834                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1835                         return vddci_table->entries[i-1].value);
1836 }
1837
1838 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1839                 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1840                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1841 {
1842         uint32_t i;
1843         uint16_t vddci;
1844         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1845
1846         *voltage = *mvdd = 0;
1847
1848         /* clock - voltage dependency table is empty table */
1849         if (dep_table->count == 0)
1850                 return -EINVAL;
1851
1852         for (i = 0; i < dep_table->count; i++) {
1853                 /* find first sclk bigger than request */
1854                 if (dep_table->entries[i].clk >= clock) {
1855                         *voltage |= (dep_table->entries[i].vddc *
1856                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1857                         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1858                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1859                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1860                         else if (dep_table->entries[i].vddci)
1861                                 *voltage |= (dep_table->entries[i].vddci *
1862                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1863                         else {
1864                                 vddci = fiji_find_closest_vddci(hwmgr,
1865                                                 (dep_table->entries[i].vddc -
1866                                                                 (uint16_t)data->vddc_vddci_delta));
1867                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1868                         }
1869
1870                         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1871                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1872                                         VOLTAGE_SCALE;
1873                         else if (dep_table->entries[i].mvdd)
1874                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1875                                         VOLTAGE_SCALE;
1876
1877                         *voltage |= 1 << PHASES_SHIFT;
1878                         return 0;
1879                 }
1880         }
1881
1882         /* sclk is bigger than max sclk in the dependence table */
1883         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1884
1885         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1886                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1887                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1888         else if (dep_table->entries[i-1].vddci) {
1889                 vddci = fiji_find_closest_vddci(hwmgr,
1890                                 (dep_table->entries[i].vddc -
1891                                                 (uint16_t)data->vddc_vddci_delta));
1892                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1893         }
1894
1895         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1896                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1897         else if (dep_table->entries[i].mvdd)
1898                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1899
1900         return 0;
1901 }
1902
1903 static uint8_t fiji_get_sleep_divider_id_from_clock(uint32_t clock,
1904                 uint32_t clock_insr)
1905 {
1906         uint8_t i;
1907         uint32_t temp;
1908         uint32_t min = max(clock_insr, (uint32_t)FIJI_MINIMUM_ENGINE_CLOCK);
1909
1910         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
1911         for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1912                 temp = clock >> i;
1913
1914                 if (temp >= min || i == 0)
1915                         break;
1916         }
1917         return i;
1918 }
1919 /**
1920 * Populates single SMC SCLK structure using the provided engine clock
1921 *
1922 * @param    hwmgr      the address of the hardware manager
1923 * @param    clock the engine clock to use to populate the structure
1924 * @param    sclk        the SMC SCLK structure to be populated
1925 */
1926
1927 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1928                 uint32_t clock, uint16_t sclk_al_threshold,
1929                 struct SMU73_Discrete_GraphicsLevel *level)
1930 {
1931         int result;
1932         /* PP_Clocks minClocks; */
1933         uint32_t threshold, mvdd;
1934         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1935         struct phm_ppt_v1_information *table_info =
1936                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1937
1938         result = fiji_calculate_sclk_params(hwmgr, clock, level);
1939
1940         /* populate graphics levels */
1941         result = fiji_get_dependency_volt_by_clk(hwmgr,
1942                         table_info->vdd_dep_on_sclk, clock,
1943                         &level->MinVoltage, &mvdd);
1944         PP_ASSERT_WITH_CODE((0 == result),
1945                         "can not find VDDC voltage value for "
1946                         "VDDC engine clock dependency table",
1947                         return result);
1948
1949         level->SclkFrequency = clock;
1950         level->ActivityLevel = sclk_al_threshold;
1951         level->CcPwrDynRm = 0;
1952         level->CcPwrDynRm1 = 0;
1953         level->EnabledForActivity = 0;
1954         level->EnabledForThrottle = 1;
1955         level->UpHyst = 10;
1956         level->DownHyst = 0;
1957         level->VoltageDownHyst = 0;
1958         level->PowerThrottle = 0;
1959
1960         threshold = clock * data->fast_watermark_threshold / 100;
1961
1962
1963         data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
1964
1965         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1966                 level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(clock,
1967                                                                 hwmgr->display_config.min_core_set_clock_in_sr);
1968
1969
1970         /* Default to slow, highest DPM level will be
1971          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1972          */
1973         level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1974
1975         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1976         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1977         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1978         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1979         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1980         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1981         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1982         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1983         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1984
1985         return 0;
1986 }
1987 /**
1988 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1989 *
1990 * @param    hwmgr      the address of the hardware manager
1991 */
1992 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1993 {
1994         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1995         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1996         struct phm_ppt_v1_information *table_info =
1997                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1998         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1999         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
2000         int result = 0;
2001         uint32_t array = data->dpm_table_start +
2002                         offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
2003         uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
2004                         SMU73_MAX_LEVELS_GRAPHICS;
2005         struct SMU73_Discrete_GraphicsLevel *levels =
2006                         data->smc_state_table.GraphicsLevel;
2007         uint32_t i, max_entry;
2008         uint8_t hightest_pcie_level_enabled = 0,
2009                         lowest_pcie_level_enabled = 0,
2010                         mid_pcie_level_enabled = 0,
2011                         count = 0;
2012
2013         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2014                 result = fiji_populate_single_graphic_level(hwmgr,
2015                                 dpm_table->sclk_table.dpm_levels[i].value,
2016                                 (uint16_t)data->activity_target[i],
2017                                 &levels[i]);
2018                 if (result)
2019                         return result;
2020
2021                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2022                 if (i > 1)
2023                         levels[i].DeepSleepDivId = 0;
2024         }
2025
2026         /* Only enable level 0 for now.*/
2027         levels[0].EnabledForActivity = 1;
2028
2029         /* set highest level watermark to high */
2030         levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
2031                         PPSMC_DISPLAY_WATERMARK_HIGH;
2032
2033         data->smc_state_table.GraphicsDpmLevelCount =
2034                         (uint8_t)dpm_table->sclk_table.count;
2035         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2036                         fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2037
2038         if (pcie_table != NULL) {
2039                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
2040                                 "There must be 1 or more PCIE levels defined in PPTable.",
2041                                 return -EINVAL);
2042                 max_entry = pcie_entry_cnt - 1;
2043                 for (i = 0; i < dpm_table->sclk_table.count; i++)
2044                         levels[i].pcieDpmLevel =
2045                                         (uint8_t) ((i < max_entry)? i : max_entry);
2046         } else {
2047                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2048                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2049                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2050                         hightest_pcie_level_enabled++;
2051
2052                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2053                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2054                                                 (1 << lowest_pcie_level_enabled)) == 0 ))
2055                         lowest_pcie_level_enabled++;
2056
2057                 while ((count < hightest_pcie_level_enabled) &&
2058                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2059                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2060                         count++;
2061
2062                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2063                                 hightest_pcie_level_enabled?
2064                                                 (lowest_pcie_level_enabled + 1 + count) :
2065                                                 hightest_pcie_level_enabled;
2066
2067                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2068                 for(i = 2; i < dpm_table->sclk_table.count; i++)
2069                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2070
2071                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2072                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2073
2074                 /* set pcieDpmLevel to mid_pcie_level_enabled */
2075                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2076         }
2077         /* level count will send to smc once at init smc table and never change */
2078         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2079                         (uint32_t)array_size, data->sram_end);
2080
2081         return result;
2082 }
2083
2084 /**
2085  * MCLK Frequency Ratio
2086  * SEQ_CG_RESP  Bit[31:24] - 0x0
2087  * Bit[27:24] \96 DDR3 Frequency ratio
2088  * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
2089  * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
2090  * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
2091  * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
2092  * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
2093  * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
2094  * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
2095  * 400 < 0x7 <= 450MHz,       800 < 0xF
2096  */
2097 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2098 {
2099         if (mem_clock <= 10000) return 0x0;
2100         if (mem_clock <= 15000) return 0x1;
2101         if (mem_clock <= 20000) return 0x2;
2102         if (mem_clock <= 25000) return 0x3;
2103         if (mem_clock <= 30000) return 0x4;
2104         if (mem_clock <= 35000) return 0x5;
2105         if (mem_clock <= 40000) return 0x6;
2106         if (mem_clock <= 45000) return 0x7;
2107         if (mem_clock <= 50000) return 0x8;
2108         if (mem_clock <= 55000) return 0x9;
2109         if (mem_clock <= 60000) return 0xa;
2110         if (mem_clock <= 65000) return 0xb;
2111         if (mem_clock <= 70000) return 0xc;
2112         if (mem_clock <= 75000) return 0xd;
2113         if (mem_clock <= 80000) return 0xe;
2114         /* mem_clock > 800MHz */
2115         return 0xf;
2116 }
2117
2118 /**
2119 * Populates the SMC MCLK structure using the provided memory clock
2120 *
2121 * @param    hwmgr   the address of the hardware manager
2122 * @param    clock   the memory clock to use to populate the structure
2123 * @param    sclk    the SMC SCLK structure to be populated
2124 */
2125 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2126     uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2127 {
2128         struct pp_atomctrl_memory_clock_param mem_param;
2129         int result;
2130
2131         result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2132         PP_ASSERT_WITH_CODE((0 == result),
2133                         "Failed to get Memory PLL Dividers.",);
2134
2135         /* Save the result data to outpupt memory level structure */
2136         mclk->MclkFrequency   = clock;
2137         mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
2138         mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
2139
2140         return result;
2141 }
2142
2143 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2144                 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2145 {
2146         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2147         struct phm_ppt_v1_information *table_info =
2148                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2149         int result = 0;
2150
2151         if (table_info->vdd_dep_on_mclk) {
2152                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2153                                 table_info->vdd_dep_on_mclk, clock,
2154                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
2155                 PP_ASSERT_WITH_CODE((0 == result),
2156                                 "can not find MinVddc voltage value from memory "
2157                                 "VDDC voltage dependency table", return result);
2158         }
2159
2160         mem_level->EnabledForThrottle = 1;
2161         mem_level->EnabledForActivity = 0;
2162         mem_level->UpHyst = 0;
2163         mem_level->DownHyst = 100;
2164         mem_level->VoltageDownHyst = 0;
2165         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2166         mem_level->StutterEnable = false;
2167
2168         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2169
2170         /* enable stutter mode if all the follow condition applied
2171          * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2172          * &(data->DisplayTiming.numExistingDisplays));
2173          */
2174         data->display_timing.num_existing_displays = 1;
2175
2176         if ((data->mclk_stutter_mode_threshold) &&
2177                 (clock <= data->mclk_stutter_mode_threshold) &&
2178                 (!data->is_uvd_enabled) &&
2179                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2180                                 STUTTER_ENABLE) & 0x1))
2181                 mem_level->StutterEnable = true;
2182
2183         result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2184         if (!result) {
2185                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2186                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2187                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2188                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2189         }
2190         return result;
2191 }
2192
2193 /**
2194 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2195 *
2196 * @param    hwmgr      the address of the hardware manager
2197 */
2198 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2199 {
2200         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2201         struct fiji_dpm_table *dpm_table = &data->dpm_table;
2202         int result;
2203         /* populate MCLK dpm table to SMU7 */
2204         uint32_t array = data->dpm_table_start +
2205                         offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2206         uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2207                         SMU73_MAX_LEVELS_MEMORY;
2208         struct SMU73_Discrete_MemoryLevel *levels =
2209                         data->smc_state_table.MemoryLevel;
2210         uint32_t i;
2211
2212         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2213                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2214                                 "can not populate memory level as memory clock is zero",
2215                                 return -EINVAL);
2216                 result = fiji_populate_single_memory_level(hwmgr,
2217                                 dpm_table->mclk_table.dpm_levels[i].value,
2218                                 &levels[i]);
2219                 if (result)
2220                         return result;
2221         }
2222
2223         /* Only enable level 0 for now. */
2224         levels[0].EnabledForActivity = 1;
2225
2226         /* in order to prevent MC activity from stutter mode to push DPM up.
2227          * the UVD change complements this by putting the MCLK in
2228          * a higher state by default such that we are not effected by
2229          * up threshold or and MCLK DPM latency.
2230          */
2231         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2232         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2233
2234         data->smc_state_table.MemoryDpmLevelCount =
2235                         (uint8_t)dpm_table->mclk_table.count;
2236         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2237                         fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2238         /* set highest level watermark to high */
2239         levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2240                         PPSMC_DISPLAY_WATERMARK_HIGH;
2241
2242         /* level count will send to smc once at init smc table and never change */
2243         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2244                         (uint32_t)array_size, data->sram_end);
2245
2246         return result;
2247 }
2248
2249 /**
2250 * Populates the SMC MVDD structure using the provided memory clock.
2251 *
2252 * @param    hwmgr      the address of the hardware manager
2253 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2254 * @param    voltage     the SMC VOLTAGE structure to be populated
2255 */
2256 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2257                 uint32_t mclk, SMIO_Pattern *smio_pat)
2258 {
2259         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2260         struct phm_ppt_v1_information *table_info =
2261                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2262         uint32_t i = 0;
2263
2264         if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2265                 /* find mvdd value which clock is more than request */
2266                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2267                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2268                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2269                                 break;
2270                         }
2271                 }
2272                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2273                                 "MVDD Voltage is outside the supported range.",
2274                                 return -EINVAL);
2275         } else
2276                 return -EINVAL;
2277
2278         return 0;
2279 }
2280
2281 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2282                 SMU73_Discrete_DpmTable *table)
2283 {
2284         int result = 0;
2285         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2286         struct phm_ppt_v1_information *table_info =
2287                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2288         struct pp_atomctrl_clock_dividers_vi dividers;
2289         SMIO_Pattern vol_level;
2290         uint32_t mvdd;
2291         uint16_t us_mvdd;
2292         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2293         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2294
2295         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2296
2297         if (!data->sclk_dpm_key_disabled) {
2298                 /* Get MinVoltage and Frequency from DPM0,
2299                  * already converted to SMC_UL */
2300                 table->ACPILevel.SclkFrequency =
2301                                 data->dpm_table.sclk_table.dpm_levels[0].value;
2302                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2303                                 table_info->vdd_dep_on_sclk,
2304                                 table->ACPILevel.SclkFrequency,
2305                                 &table->ACPILevel.MinVoltage, &mvdd);
2306                 PP_ASSERT_WITH_CODE((0 == result),
2307                                 "Cannot find ACPI VDDC voltage value "
2308                                 "in Clock Dependency Table",);
2309         } else {
2310                 table->ACPILevel.SclkFrequency =
2311                                 data->vbios_boot_state.sclk_bootup_value;
2312                 table->ACPILevel.MinVoltage =
2313                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2314         }
2315
2316         /* get the engine clock dividers for this clock value */
2317         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2318                         table->ACPILevel.SclkFrequency,  &dividers);
2319         PP_ASSERT_WITH_CODE(result == 0,
2320                         "Error retrieving Engine Clock dividers from VBIOS.",
2321                         return result);
2322
2323         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2324         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2325         table->ACPILevel.DeepSleepDivId = 0;
2326
2327         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2328                         SPLL_PWRON, 0);
2329         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2330                         SPLL_RESET, 1);
2331         spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2332                         SCLK_MUX_SEL, 4);
2333
2334         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2335         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2336         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2337         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2338         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2339         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2340         table->ACPILevel.CcPwrDynRm = 0;
2341         table->ACPILevel.CcPwrDynRm1 = 0;
2342
2343         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2344         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2345         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2346         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2347         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2348         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2349         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2350         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2351         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2352         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2353         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2354
2355         if (!data->mclk_dpm_key_disabled) {
2356                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2357                 table->MemoryACPILevel.MclkFrequency =
2358                                 data->dpm_table.mclk_table.dpm_levels[0].value;
2359                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2360                                 table_info->vdd_dep_on_mclk,
2361                                 table->MemoryACPILevel.MclkFrequency,
2362                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
2363                 PP_ASSERT_WITH_CODE((0 == result),
2364                                 "Cannot find ACPI VDDCI voltage value "
2365                                 "in Clock Dependency Table",);
2366         } else {
2367                 table->MemoryACPILevel.MclkFrequency =
2368                                 data->vbios_boot_state.mclk_bootup_value;
2369                 table->MemoryACPILevel.MinVoltage =
2370                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2371         }
2372
2373         us_mvdd = 0;
2374         if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2375                         (data->mclk_dpm_key_disabled))
2376                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2377         else {
2378                 if (!fiji_populate_mvdd_value(hwmgr,
2379                                 data->dpm_table.mclk_table.dpm_levels[0].value,
2380                                 &vol_level))
2381                         us_mvdd = vol_level.Voltage;
2382         }
2383
2384         table->MemoryACPILevel.MinMvdd =
2385                         PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2386
2387         table->MemoryACPILevel.EnabledForThrottle = 0;
2388         table->MemoryACPILevel.EnabledForActivity = 0;
2389         table->MemoryACPILevel.UpHyst = 0;
2390         table->MemoryACPILevel.DownHyst = 100;
2391         table->MemoryACPILevel.VoltageDownHyst = 0;
2392         table->MemoryACPILevel.ActivityLevel =
2393                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2394
2395         table->MemoryACPILevel.StutterEnable = false;
2396         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2397         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2398
2399         return result;
2400 }
2401
2402 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2403                 SMU73_Discrete_DpmTable *table)
2404 {
2405         int result = -EINVAL;
2406         uint8_t count;
2407         struct pp_atomctrl_clock_dividers_vi dividers;
2408         struct phm_ppt_v1_information *table_info =
2409                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2410         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2411                         table_info->mm_dep_table;
2412         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2413
2414         table->VceLevelCount = (uint8_t)(mm_table->count);
2415         table->VceBootLevel = 0;
2416
2417         for(count = 0; count < table->VceLevelCount; count++) {
2418                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2419                 table->VceLevel[count].MinVoltage = 0;
2420                 table->VceLevel[count].MinVoltage |=
2421                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2422                 table->VceLevel[count].MinVoltage |=
2423                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2424                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
2425                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2426
2427                 /*retrieve divider value for VBIOS */
2428                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2429                                 table->VceLevel[count].Frequency, &dividers);
2430                 PP_ASSERT_WITH_CODE((0 == result),
2431                                 "can not find divide id for VCE engine clock",
2432                                 return result);
2433
2434                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2435
2436                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2437                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2438         }
2439         return result;
2440 }
2441
2442 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2443                 SMU73_Discrete_DpmTable *table)
2444 {
2445         int result = -EINVAL;
2446         uint8_t count;
2447         struct pp_atomctrl_clock_dividers_vi dividers;
2448         struct phm_ppt_v1_information *table_info =
2449                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2450         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2451                         table_info->mm_dep_table;
2452         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2453
2454         table->AcpLevelCount = (uint8_t)(mm_table->count);
2455         table->AcpBootLevel = 0;
2456
2457         for (count = 0; count < table->AcpLevelCount; count++) {
2458                 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2459                 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2460                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2461                 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2462                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2463                 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2464
2465                 /* retrieve divider value for VBIOS */
2466                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2467                                 table->AcpLevel[count].Frequency, &dividers);
2468                 PP_ASSERT_WITH_CODE((0 == result),
2469                                 "can not find divide id for engine clock", return result);
2470
2471                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2472
2473                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2474                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2475         }
2476         return result;
2477 }
2478
2479 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2480                 SMU73_Discrete_DpmTable *table)
2481 {
2482         int result = -EINVAL;
2483         uint8_t count;
2484         struct pp_atomctrl_clock_dividers_vi dividers;
2485         struct phm_ppt_v1_information *table_info =
2486                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2487         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2488                         table_info->mm_dep_table;
2489         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2490
2491         table->SamuBootLevel = 0;
2492         table->SamuLevelCount = (uint8_t)(mm_table->count);
2493
2494         for (count = 0; count < table->SamuLevelCount; count++) {
2495                 /* not sure whether we need evclk or not */
2496                 table->SamuLevel[count].MinVoltage = 0;
2497                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2498                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2499                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2500                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2501                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2502                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2503
2504                 /* retrieve divider value for VBIOS */
2505                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2506                                 table->SamuLevel[count].Frequency, &dividers);
2507                 PP_ASSERT_WITH_CODE((0 == result),
2508                                 "can not find divide id for samu clock", return result);
2509
2510                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2511
2512                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2513                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2514         }
2515         return result;
2516 }
2517
2518 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2519                 int32_t eng_clock, int32_t mem_clock,
2520                 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2521 {
2522         uint32_t dram_timing;
2523         uint32_t dram_timing2;
2524         uint32_t burstTime;
2525         ULONG state, trrds, trrdl;
2526         int result;
2527
2528         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2529                         eng_clock, mem_clock);
2530         PP_ASSERT_WITH_CODE(result == 0,
2531                         "Error calling VBIOS to set DRAM_TIMING.", return result);
2532
2533         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2534         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2535         burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2536
2537         state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2538         trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2539         trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2540
2541         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
2542         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2543         arb_regs->McArbBurstTime   = (uint8_t)burstTime;
2544         arb_regs->TRRDS            = (uint8_t)trrds;
2545         arb_regs->TRRDL            = (uint8_t)trrdl;
2546
2547         return 0;
2548 }
2549
2550 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2551 {
2552         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2553         struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2554         uint32_t i, j;
2555         int result = 0;
2556
2557         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2558                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2559                         result = fiji_populate_memory_timing_parameters(hwmgr,
2560                                         data->dpm_table.sclk_table.dpm_levels[i].value,
2561                                         data->dpm_table.mclk_table.dpm_levels[j].value,
2562                                         &arb_regs.entries[i][j]);
2563                         if (result)
2564                                 break;
2565                 }
2566         }
2567
2568         if (!result)
2569                 result = fiji_copy_bytes_to_smc(
2570                                 hwmgr->smumgr,
2571                                 data->arb_table_start,
2572                                 (uint8_t *)&arb_regs,
2573                                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2574                                 data->sram_end);
2575         return result;
2576 }
2577
2578 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2579                 struct SMU73_Discrete_DpmTable *table)
2580 {
2581         int result = -EINVAL;
2582         uint8_t count;
2583         struct pp_atomctrl_clock_dividers_vi dividers;
2584         struct phm_ppt_v1_information *table_info =
2585                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2586         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2587                         table_info->mm_dep_table;
2588         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2589
2590         table->UvdLevelCount = (uint8_t)(mm_table->count);
2591         table->UvdBootLevel = 0;
2592
2593         for (count = 0; count < table->UvdLevelCount; count++) {
2594                 table->UvdLevel[count].MinVoltage = 0;
2595                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2596                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2597                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2598                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2599                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2600                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2601                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2602
2603                 /* retrieve divider value for VBIOS */
2604                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2605                                 table->UvdLevel[count].VclkFrequency, &dividers);
2606                 PP_ASSERT_WITH_CODE((0 == result),
2607                                 "can not find divide id for Vclk clock", return result);
2608
2609                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2610
2611                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2612                                 table->UvdLevel[count].DclkFrequency, &dividers);
2613                 PP_ASSERT_WITH_CODE((0 == result),
2614                                 "can not find divide id for Dclk clock", return result);
2615
2616                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2617
2618                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2619                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2620                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2621
2622         }
2623         return result;
2624 }
2625
2626 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2627                 uint32_t value, uint32_t *boot_level)
2628 {
2629         int result = -EINVAL;
2630         uint32_t i;
2631
2632         for (i = 0; i < table->count; i++) {
2633                 if (value == table->dpm_levels[i].value) {
2634                         *boot_level = i;
2635                         result = 0;
2636                 }
2637         }
2638         return result;
2639 }
2640
2641 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2642                 struct SMU73_Discrete_DpmTable *table)
2643 {
2644         int result = 0;
2645         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2646
2647         table->GraphicsBootLevel = 0;
2648         table->MemoryBootLevel = 0;
2649
2650         /* find boot level from dpm table */
2651         result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2652                         data->vbios_boot_state.sclk_bootup_value,
2653                         (uint32_t *)&(table->GraphicsBootLevel));
2654
2655         result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2656                         data->vbios_boot_state.mclk_bootup_value,
2657                         (uint32_t *)&(table->MemoryBootLevel));
2658
2659         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
2660                         VOLTAGE_SCALE;
2661         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2662                         VOLTAGE_SCALE;
2663         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
2664                         VOLTAGE_SCALE;
2665
2666         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2667         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2668         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2669
2670         return 0;
2671 }
2672
2673 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2674 {
2675         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2676         struct phm_ppt_v1_information *table_info =
2677                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2678         uint8_t count, level;
2679
2680         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2681         for (level = 0; level < count; level++) {
2682                 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2683                                 data->vbios_boot_state.sclk_bootup_value) {
2684                         data->smc_state_table.GraphicsBootLevel = level;
2685                         break;
2686                 }
2687         }
2688
2689         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2690         for (level = 0; level < count; level++) {
2691                 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2692                                 data->vbios_boot_state.mclk_bootup_value) {
2693                         data->smc_state_table.MemoryBootLevel = level;
2694                         break;
2695                 }
2696         }
2697
2698         return 0;
2699 }
2700
2701 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2702 {
2703         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2704                         volt_with_cks, value;
2705         uint16_t clock_freq_u16;
2706         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2707         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2708                         volt_offset = 0;
2709         struct phm_ppt_v1_information *table_info =
2710                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2711         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2712                         table_info->vdd_dep_on_sclk;
2713
2714         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2715
2716         /* Read SMU_Eefuse to read and calculate RO and determine
2717          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2718          */
2719         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2720                         ixSMU_EFUSE_0 + (146 * 4));
2721         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2722                         ixSMU_EFUSE_0 + (148 * 4));
2723         efuse &= 0xFF000000;
2724         efuse = efuse >> 24;
2725         efuse2 &= 0xF;
2726
2727         if (efuse2 == 1)
2728                 ro = (2300 - 1350) * efuse / 255 + 1350;
2729         else
2730                 ro = (2500 - 1000) * efuse / 255 + 1000;
2731
2732         if (ro >= 1660)
2733                 type = 0;
2734         else
2735                 type = 1;
2736
2737         /* Populate Stretch amount */
2738         data->smc_state_table.ClockStretcherAmount = stretch_amount;
2739
2740         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2741         for (i = 0; i < sclk_table->count; i++) {
2742                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2743                                 sclk_table->entries[i].cks_enable << i;
2744                 volt_without_cks = (uint32_t)((14041 *
2745                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2746                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2747                 volt_with_cks = (uint32_t)((13946 *
2748                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2749                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2750                 if (volt_without_cks >= volt_with_cks)
2751                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2752                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2753                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2754         }
2755
2756         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2757                         STRETCH_ENABLE, 0x0);
2758         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2759                         masterReset, 0x1);
2760         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2761                         staticEnable, 0x1);
2762         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2763                         masterReset, 0x0);
2764
2765         /* Populate CKS Lookup Table */
2766         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2767                 stretch_amount2 = 0;
2768         else if (stretch_amount == 3 || stretch_amount == 4)
2769                 stretch_amount2 = 1;
2770         else {
2771                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2772                                 PHM_PlatformCaps_ClockStretcher);
2773                 PP_ASSERT_WITH_CODE(false,
2774                                 "Stretch Amount in PPTable not supported\n",
2775                                 return -EINVAL);
2776         }
2777
2778         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2779                         ixPWR_CKS_CNTL);
2780         value &= 0xFFC2FF87;
2781         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2782                         fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2783         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2784                         fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2785         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2786                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2787                         SclkFrequency) / 100);
2788         if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2789                         clock_freq_u16 &&
2790             fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2791                         clock_freq_u16) {
2792                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2793                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2794                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2795                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2796                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2797                 value |= (fiji_clock_stretch_amount_conversion
2798                                 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2799                                  [stretch_amount]) << 3;
2800         }
2801         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2802                         CKS_LOOKUPTableEntry[0].minFreq);
2803         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2804                         CKS_LOOKUPTableEntry[0].maxFreq);
2805         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2806                         fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2807         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2808                         (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2809
2810         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2811                         ixPWR_CKS_CNTL, value);
2812
2813         /* Populate DDT Lookup Table */
2814         for (i = 0; i < 4; i++) {
2815                 /* Assign the minimum and maximum VID stored
2816                  * in the last row of Clock Stretcher Voltage Table.
2817                  */
2818                 data->smc_state_table.ClockStretcherDataTable.
2819                 ClockStretcherDataTableEntry[i].minVID =
2820                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2821                 data->smc_state_table.ClockStretcherDataTable.
2822                 ClockStretcherDataTableEntry[i].maxVID =
2823                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2824                 /* Loop through each SCLK and check the frequency
2825                  * to see if it lies within the frequency for clock stretcher.
2826                  */
2827                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2828                         cks_setting = 0;
2829                         clock_freq = PP_SMC_TO_HOST_UL(
2830                                         data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2831                         /* Check the allowed frequency against the sclk level[j].
2832                          *  Sclk's endianness has already been converted,
2833                          *  and it's in 10Khz unit,
2834                          *  as opposed to Data table, which is in Mhz unit.
2835                          */
2836                         if (clock_freq >=
2837                                         (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2838                                 cks_setting |= 0x2;
2839                                 if (clock_freq <
2840                                                 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2841                                         cks_setting |= 0x1;
2842                         }
2843                         data->smc_state_table.ClockStretcherDataTable.
2844                         ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2845                 }
2846                 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2847                                 ClockStretcherDataTable.
2848                                 ClockStretcherDataTableEntry[i].setting);
2849         }
2850
2851         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2852         value &= 0xFFFFFFFE;
2853         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2854
2855         return 0;
2856 }
2857
2858 /**
2859 * Populates the SMC VRConfig field in DPM table.
2860 *
2861 * @param    hwmgr   the address of the hardware manager
2862 * @param    table   the SMC DPM table structure to be populated
2863 * @return   always 0
2864 */
2865 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2866                 struct SMU73_Discrete_DpmTable *table)
2867 {
2868         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2869         uint16_t config;
2870
2871         config = VR_MERGED_WITH_VDDC;
2872         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2873
2874         /* Set Vddc Voltage Controller */
2875         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2876                 config = VR_SVI2_PLANE_1;
2877                 table->VRConfig |= config;
2878         } else {
2879                 PP_ASSERT_WITH_CODE(false,
2880                                 "VDDC should be on SVI2 control in merged mode!",);
2881         }
2882         /* Set Vddci Voltage Controller */
2883         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2884                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
2885                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2886         } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2887                 config = VR_SMIO_PATTERN_1;
2888                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2889         } else {
2890                 config = VR_STATIC_VOLTAGE;
2891                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2892         }
2893         /* Set Mvdd Voltage Controller */
2894         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2895                 config = VR_SVI2_PLANE_2;
2896                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2897         } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2898                 config = VR_SMIO_PATTERN_2;
2899                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2900         } else {
2901                 config = VR_STATIC_VOLTAGE;
2902                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2903         }
2904
2905         return 0;
2906 }
2907
2908 /**
2909 * Initializes the SMC table and uploads it
2910 *
2911 * @param    hwmgr  the address of the powerplay hardware manager.
2912 * @param    pInput  the pointer to input data (PowerState)
2913 * @return   always 0
2914 */
2915 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2916 {
2917         int result;
2918         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2919         struct phm_ppt_v1_information *table_info =
2920                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2921         struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2922         const struct fiji_ulv_parm *ulv = &(data->ulv);
2923         uint8_t i;
2924         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2925
2926         result = fiji_setup_default_dpm_tables(hwmgr);
2927         PP_ASSERT_WITH_CODE(0 == result,
2928                         "Failed to setup default DPM tables!", return result);
2929
2930         if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2931                 fiji_populate_smc_voltage_tables(hwmgr, table);
2932
2933         table->SystemFlags = 0;
2934
2935         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2936                         PHM_PlatformCaps_AutomaticDCTransition))
2937                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2938
2939         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2940                         PHM_PlatformCaps_StepVddc))
2941                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2942
2943         if (data->is_memory_gddr5)
2944                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2945
2946         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2947                 result = fiji_populate_ulv_state(hwmgr, table);
2948                 PP_ASSERT_WITH_CODE(0 == result,
2949                                 "Failed to initialize ULV state!", return result);
2950                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2951                                 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2952         }
2953
2954         result = fiji_populate_smc_link_level(hwmgr, table);
2955         PP_ASSERT_WITH_CODE(0 == result,
2956                         "Failed to initialize Link Level!", return result);
2957
2958         result = fiji_populate_all_graphic_levels(hwmgr);
2959         PP_ASSERT_WITH_CODE(0 == result,
2960                         "Failed to initialize Graphics Level!", return result);
2961
2962         result = fiji_populate_all_memory_levels(hwmgr);
2963         PP_ASSERT_WITH_CODE(0 == result,
2964                         "Failed to initialize Memory Level!", return result);
2965
2966         result = fiji_populate_smc_acpi_level(hwmgr, table);
2967         PP_ASSERT_WITH_CODE(0 == result,
2968                         "Failed to initialize ACPI Level!", return result);
2969
2970         result = fiji_populate_smc_vce_level(hwmgr, table);
2971         PP_ASSERT_WITH_CODE(0 == result,
2972                         "Failed to initialize VCE Level!", return result);
2973
2974         result = fiji_populate_smc_acp_level(hwmgr, table);
2975         PP_ASSERT_WITH_CODE(0 == result,
2976                         "Failed to initialize ACP Level!", return result);
2977
2978         result = fiji_populate_smc_samu_level(hwmgr, table);
2979         PP_ASSERT_WITH_CODE(0 == result,
2980                         "Failed to initialize SAMU Level!", return result);
2981
2982         /* Since only the initial state is completely set up at this point
2983          * (the other states are just copies of the boot state) we only
2984          * need to populate the  ARB settings for the initial state.
2985          */
2986         result = fiji_program_memory_timing_parameters(hwmgr);
2987         PP_ASSERT_WITH_CODE(0 == result,
2988                         "Failed to Write ARB settings for the initial state.", return result);
2989
2990         result = fiji_populate_smc_uvd_level(hwmgr, table);
2991         PP_ASSERT_WITH_CODE(0 == result,
2992                         "Failed to initialize UVD Level!", return result);
2993
2994         result = fiji_populate_smc_boot_level(hwmgr, table);
2995         PP_ASSERT_WITH_CODE(0 == result,
2996                         "Failed to initialize Boot Level!", return result);
2997
2998         result = fiji_populate_smc_initailial_state(hwmgr);
2999         PP_ASSERT_WITH_CODE(0 == result,
3000                         "Failed to initialize Boot State!", return result);
3001
3002         result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
3003         PP_ASSERT_WITH_CODE(0 == result,
3004                         "Failed to populate BAPM Parameters!", return result);
3005
3006         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3007                         PHM_PlatformCaps_ClockStretcher)) {
3008                 result = fiji_populate_clock_stretcher_data_table(hwmgr);
3009                 PP_ASSERT_WITH_CODE(0 == result,
3010                                 "Failed to populate Clock Stretcher Data Table!",
3011                                 return result);
3012         }
3013
3014         table->GraphicsVoltageChangeEnable  = 1;
3015         table->GraphicsThermThrottleEnable  = 1;
3016         table->GraphicsInterval = 1;
3017         table->VoltageInterval  = 1;
3018         table->ThermalInterval  = 1;
3019         table->TemperatureLimitHigh =
3020                         table_info->cac_dtp_table->usTargetOperatingTemp *
3021                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3022         table->TemperatureLimitLow  =
3023                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3024                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3025         table->MemoryVoltageChangeEnable = 1;
3026         table->MemoryInterval = 1;
3027         table->VoltageResponseTime = 0;
3028         table->PhaseResponseTime = 0;
3029         table->MemoryThermThrottleEnable = 1;
3030         table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
3031         table->PCIeGenInterval = 1;
3032         table->VRConfig = 0;
3033
3034         result = fiji_populate_vr_config(hwmgr, table);
3035         PP_ASSERT_WITH_CODE(0 == result,
3036                         "Failed to populate VRConfig setting!", return result);
3037
3038         table->ThermGpio = 17;
3039         table->SclkStepSize = 0x4000;
3040
3041         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
3042                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
3043                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3044                                 PHM_PlatformCaps_RegulatorHot);
3045         } else {
3046                 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
3047                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3048                                 PHM_PlatformCaps_RegulatorHot);
3049         }
3050
3051         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3052                         &gpio_pin)) {
3053                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
3054                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3055                                 PHM_PlatformCaps_AutomaticDCTransition);
3056         } else {
3057                 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3058                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3059                                 PHM_PlatformCaps_AutomaticDCTransition);
3060         }
3061
3062         /* Thermal Output GPIO */
3063         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3064                         &gpio_pin)) {
3065                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3066                                 PHM_PlatformCaps_ThermalOutGPIO);
3067
3068                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3069
3070                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3071                  * since VBIOS will program this register to set 'inactive state',
3072                  * driver can then determine 'active state' from this and
3073                  * program SMU with correct polarity
3074                  */
3075                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3076                                 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3077                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3078
3079                 /* if required, combine VRHot/PCC with thermal out GPIO */
3080                 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3081                                 PHM_PlatformCaps_RegulatorHot) &&
3082                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3083                                         PHM_PlatformCaps_CombinePCCWithThermalSignal))
3084                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3085         } else {
3086                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3087                                 PHM_PlatformCaps_ThermalOutGPIO);
3088                 table->ThermOutGpio = 17;
3089                 table->ThermOutPolarity = 1;
3090                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3091         }
3092
3093         for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3094                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3095
3096         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3097         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3098         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3099         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3100         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3101         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3102         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3103         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3104         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3105
3106         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3107         result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3108                         data->dpm_table_start +
3109                         offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3110                         (uint8_t *)&(table->SystemFlags),
3111                         sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3112                         data->sram_end);
3113         PP_ASSERT_WITH_CODE(0 == result,
3114                         "Failed to upload dpm data to SMC memory!", return result);
3115
3116         return 0;
3117 }
3118
3119 /**
3120 * Initialize the ARB DRAM timing table's index field.
3121 *
3122 * @param    hwmgr  the address of the powerplay hardware manager.
3123 * @return   always 0
3124 */
3125 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3126 {
3127         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3128         uint32_t tmp;
3129         int result;
3130
3131         /* This is a read-modify-write on the first byte of the ARB table.
3132          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3133          * is the field 'current'.
3134          * This solution is ugly, but we never write the whole table only
3135          * individual fields in it.
3136          * In reality this field should not be in that structure
3137          * but in a soft register.
3138          */
3139         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3140                         data->arb_table_start, &tmp, data->sram_end);
3141
3142         if (result)
3143                 return result;
3144
3145         tmp &= 0x00FFFFFF;
3146         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3147
3148         return fiji_write_smc_sram_dword(hwmgr->smumgr,
3149                         data->arb_table_start,  tmp, data->sram_end);
3150 }
3151
3152 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3153 {
3154         if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3155                         PHM_PlatformCaps_RegulatorHot))
3156                 return smum_send_msg_to_smc(hwmgr->smumgr,
3157                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3158
3159         return 0;
3160 }
3161
3162 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3163 {
3164         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3165                         SCLK_PWRMGT_OFF, 0);
3166         return 0;
3167 }
3168
3169 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3170 {
3171         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3172         struct fiji_ulv_parm *ulv = &(data->ulv);
3173
3174         if (ulv->ulv_supported)
3175                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3176
3177         return 0;
3178 }
3179
3180 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3181 {
3182         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3183                         PHM_PlatformCaps_SclkDeepSleep)) {
3184                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3185                         PP_ASSERT_WITH_CODE(false,
3186                                         "Attempt to enable Master Deep Sleep switch failed!",
3187                                         return -1);
3188         } else {
3189                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3190                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3191                         PP_ASSERT_WITH_CODE(false,
3192                                         "Attempt to disable Master Deep Sleep switch failed!",
3193                                         return -1);
3194                 }
3195         }
3196
3197         return 0;
3198 }
3199
3200 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3201 {
3202         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3203         uint32_t   val, val0, val2;
3204         uint32_t   i, cpl_cntl, cpl_threshold, mc_threshold;
3205
3206         /* enable SCLK dpm */
3207         if(!data->sclk_dpm_key_disabled)
3208                 PP_ASSERT_WITH_CODE(
3209                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3210                 "Failed to enable SCLK DPM during DPM Start Function!",
3211                 return -1);
3212
3213         /* enable MCLK dpm */
3214         if(0 == data->mclk_dpm_key_disabled) {
3215                 cpl_threshold = 0;
3216                 mc_threshold = 0;
3217
3218                 /* Read per MCD tile (0 - 7) */
3219                 for (i = 0; i < 8; i++) {
3220                         PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3221                         val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3222                         if (0xf0000000 != val) {
3223                                 /* count number of MCQ that has channel(s) enabled */
3224                                 cpl_threshold++;
3225                                 /* only harvest 3 or full 4 supported */
3226                                 mc_threshold = val ? 3 : 4;
3227                         }
3228                 }
3229                 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3230                                 "Number of MCQ is zero!", return -EINVAL;);
3231
3232                 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3233                                 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3234                                                 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3235                 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3236                                 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3237                                                 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3238                 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3239                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3240                                 ixLCAC_MC0_CNTL, mc_threshold);
3241                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3242                                 ixLCAC_MC1_CNTL, mc_threshold);
3243                 if (8 == cpl_threshold) {
3244                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3245                                         ixLCAC_MC2_CNTL, mc_threshold);
3246                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3247                                         ixLCAC_MC3_CNTL, mc_threshold);
3248                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3249                                         ixLCAC_MC4_CNTL, mc_threshold);
3250                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3251                                         ixLCAC_MC5_CNTL, mc_threshold);
3252                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3253                                         ixLCAC_MC6_CNTL, mc_threshold);
3254                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3255                                         ixLCAC_MC7_CNTL, mc_threshold);
3256                 }
3257                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3258                                 ixLCAC_CPL_CNTL, cpl_cntl);
3259
3260                 udelay(5);
3261
3262                 mc_threshold = mc_threshold |
3263                                 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3264                 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3265                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3266                                 ixLCAC_MC0_CNTL, mc_threshold);
3267                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3268                                 ixLCAC_MC1_CNTL, mc_threshold);
3269                 if (8 == cpl_threshold) {
3270                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3271                                         ixLCAC_MC2_CNTL, mc_threshold);
3272                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3273                                         ixLCAC_MC3_CNTL, mc_threshold);
3274                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3275                                         ixLCAC_MC4_CNTL, mc_threshold);
3276                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3277                                         ixLCAC_MC5_CNTL, mc_threshold);
3278                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3279                                         ixLCAC_MC6_CNTL, mc_threshold);
3280                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3281                                         ixLCAC_MC7_CNTL, mc_threshold);
3282                 }
3283                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3284                                 ixLCAC_CPL_CNTL, cpl_cntl);
3285
3286                 /* Program CAC_EN per MCD (0-7) Tile */
3287                 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3288                 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3289                                 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3290                                 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3291                                 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3292                                 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3293                                 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3294                                 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3295                                 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3296                                 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3297
3298                 for (i = 0; i < 8; i++) {
3299                         /* Enable MCD i Tile read & write */
3300                         val2  = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3301                                         (1 << i));
3302                         cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3303                         /* Enbale CAC_ON MCD i Tile */
3304                         val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3305                         val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3306                         cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3307                 }
3308                 /* Set MC_CONFIG_MCD back to its default setting val0 */
3309                 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3310
3311                 PP_ASSERT_WITH_CODE(
3312                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3313                                                 PPSMC_MSG_MCLKDPM_Enable)),
3314                                 "Failed to enable MCLK DPM during DPM Start Function!",
3315                                 return -1);
3316         }
3317         return 0;
3318 }
3319
3320 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3321 {
3322         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3323
3324         /*enable general power management */
3325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3326                         GLOBAL_PWRMGT_EN, 1);
3327         /* enable sclk deep sleep */
3328         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3329                         DYNAMIC_PM_EN, 1);
3330         /* prepare for PCIE DPM */
3331         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3332                         data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3333                                         VoltageChangeTimeout), 0x1000);
3334         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3335                         SWRST_COMMAND_1, RESETLC, 0x0);
3336
3337         PP_ASSERT_WITH_CODE(
3338                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3339                                         PPSMC_MSG_Voltage_Cntl_Enable)),
3340                         "Failed to enable voltage DPM during DPM Start Function!",
3341                         return -1);
3342
3343         if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3344                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3345                 return -1;
3346         }
3347
3348         /* enable PCIE dpm */
3349         if(!data->pcie_dpm_key_disabled) {
3350                 PP_ASSERT_WITH_CODE(
3351                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3352                                                 PPSMC_MSG_PCIeDPM_Enable)),
3353                                 "Failed to enable pcie DPM during DPM Start Function!",
3354                                 return -1);
3355         }
3356
3357         return 0;
3358 }
3359
3360 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3361                 uint32_t sources)
3362 {
3363         bool protection;
3364         enum DPM_EVENT_SRC src;
3365
3366         switch (sources) {
3367         default:
3368                 printk(KERN_ERR "Unknown throttling event sources.");
3369                 /* fall through */
3370         case 0:
3371                 protection = false;
3372                 /* src is unused */
3373                 break;
3374         case (1 << PHM_AutoThrottleSource_Thermal):
3375                 protection = true;
3376                 src = DPM_EVENT_SRC_DIGITAL;
3377                 break;
3378         case (1 << PHM_AutoThrottleSource_External):
3379                 protection = true;
3380                 src = DPM_EVENT_SRC_EXTERNAL;
3381                 break;
3382         case (1 << PHM_AutoThrottleSource_External) |
3383                         (1 << PHM_AutoThrottleSource_Thermal):
3384                 protection = true;
3385                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3386                 break;
3387         }
3388         /* Order matters - don't enable thermal protection for the wrong source. */
3389         if (protection) {
3390                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3391                                 DPM_EVENT_SRC, src);
3392                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3393                                 THERMAL_PROTECTION_DIS,
3394                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3395                                                 PHM_PlatformCaps_ThermalController));
3396         } else
3397                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3398                                 THERMAL_PROTECTION_DIS, 1);
3399 }
3400
3401 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3402                 PHM_AutoThrottleSource source)
3403 {
3404         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3405
3406         if (!(data->active_auto_throttle_sources & (1 << source))) {
3407                 data->active_auto_throttle_sources |= 1 << source;
3408                 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3409         }
3410         return 0;
3411 }
3412
3413 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3414 {
3415         return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3416 }
3417
3418 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3419 {
3420         int tmp_result, result = 0;
3421
3422         tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3423         PP_ASSERT_WITH_CODE(result == 0,
3424                         "DPM is already running right now, no need to enable DPM!",
3425                         return 0);
3426
3427         if (fiji_voltage_control(hwmgr)) {
3428                 tmp_result = fiji_enable_voltage_control(hwmgr);
3429                 PP_ASSERT_WITH_CODE(tmp_result == 0,
3430                                 "Failed to enable voltage control!",
3431                                 result = tmp_result);
3432         }
3433
3434         if (fiji_voltage_control(hwmgr)) {
3435                 tmp_result = fiji_construct_voltage_tables(hwmgr);
3436                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3437                                 "Failed to contruct voltage tables!",
3438                                 result = tmp_result);
3439         }
3440
3441         tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3442         PP_ASSERT_WITH_CODE((0 == tmp_result),
3443                         "Failed to initialize MC reg table!", result = tmp_result);
3444
3445         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3446                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3447                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3448                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3449
3450         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3451                         PHM_PlatformCaps_ThermalController))
3452                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3453                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3454
3455         tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3456         PP_ASSERT_WITH_CODE((0 == tmp_result),
3457                         "Failed to program static screen threshold parameters!",
3458                         result = tmp_result);
3459
3460         tmp_result = fiji_enable_display_gap(hwmgr);
3461         PP_ASSERT_WITH_CODE((0 == tmp_result),
3462                         "Failed to enable display gap!", result = tmp_result);
3463
3464         tmp_result = fiji_program_voting_clients(hwmgr);
3465         PP_ASSERT_WITH_CODE((0 == tmp_result),
3466                         "Failed to program voting clients!", result = tmp_result);
3467
3468         tmp_result = fiji_process_firmware_header(hwmgr);
3469         PP_ASSERT_WITH_CODE((0 == tmp_result),
3470                         "Failed to process firmware header!", result = tmp_result);
3471
3472         tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3473         PP_ASSERT_WITH_CODE((0 == tmp_result),
3474                         "Failed to initialize switch from ArbF0 to F1!",
3475                         result = tmp_result);
3476
3477         tmp_result = fiji_init_smc_table(hwmgr);
3478         PP_ASSERT_WITH_CODE((0 == tmp_result),
3479                         "Failed to initialize SMC table!", result = tmp_result);
3480
3481         tmp_result = fiji_init_arb_table_index(hwmgr);
3482         PP_ASSERT_WITH_CODE((0 == tmp_result),
3483                         "Failed to initialize ARB table index!", result = tmp_result);
3484
3485         tmp_result = fiji_populate_pm_fuses(hwmgr);
3486         PP_ASSERT_WITH_CODE((0 == tmp_result),
3487                         "Failed to populate PM fuses!", result = tmp_result);
3488
3489         tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3490         PP_ASSERT_WITH_CODE((0 == tmp_result),
3491                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3492
3493         tmp_result = tonga_notify_smc_display_change(hwmgr, false);
3494         PP_ASSERT_WITH_CODE((0 == tmp_result),
3495                         "Failed to notify no display!", result = tmp_result);
3496
3497         tmp_result = fiji_enable_sclk_control(hwmgr);
3498         PP_ASSERT_WITH_CODE((0 == tmp_result),
3499                         "Failed to enable SCLK control!", result = tmp_result);
3500
3501         tmp_result = fiji_enable_ulv(hwmgr);
3502         PP_ASSERT_WITH_CODE((0 == tmp_result),
3503                         "Failed to enable ULV!", result = tmp_result);
3504
3505         tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3506         PP_ASSERT_WITH_CODE((0 == tmp_result),
3507                         "Failed to enable deep sleep master switch!", result = tmp_result);
3508
3509         tmp_result = fiji_start_dpm(hwmgr);
3510         PP_ASSERT_WITH_CODE((0 == tmp_result),
3511                         "Failed to start DPM!", result = tmp_result);
3512
3513         tmp_result = fiji_enable_smc_cac(hwmgr);
3514         PP_ASSERT_WITH_CODE((0 == tmp_result),
3515                         "Failed to enable SMC CAC!", result = tmp_result);
3516
3517         tmp_result = fiji_enable_power_containment(hwmgr);
3518         PP_ASSERT_WITH_CODE((0 == tmp_result),
3519                         "Failed to enable power containment!", result = tmp_result);
3520
3521         tmp_result = fiji_power_control_set_level(hwmgr);
3522         PP_ASSERT_WITH_CODE((0 == tmp_result),
3523                         "Failed to power control set level!", result = tmp_result);
3524
3525         tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3526         PP_ASSERT_WITH_CODE((0 == tmp_result),
3527                         "Failed to enable thermal auto throttle!", result = tmp_result);
3528
3529         return result;
3530 }
3531
3532 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3533 {
3534         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3535         uint32_t level, tmp;
3536
3537         if (!data->sclk_dpm_key_disabled) {
3538                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3539                         level = 0;
3540                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3541                         while (tmp >>= 1)
3542                                 level++;
3543                         if (level)
3544                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3545                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3546                                                 (1 << level));
3547                 }
3548         }
3549
3550         if (!data->mclk_dpm_key_disabled) {
3551                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3552                         level = 0;
3553                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3554                         while (tmp >>= 1)
3555                                 level++;
3556                         if (level)
3557                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3558                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3559                                                 (1 << level));
3560                 }
3561         }
3562
3563         if (!data->pcie_dpm_key_disabled) {
3564                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3565                         level = 0;
3566                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3567                         while (tmp >>= 1)
3568                                 level++;
3569                         if (level)
3570                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3571                                                 PPSMC_MSG_PCIeDPM_ForceLevel,
3572                                                 (1 << level));
3573                 }
3574         }
3575         return 0;
3576 }
3577
3578 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3579 {
3580         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3581
3582         phm_apply_dal_min_voltage_request(hwmgr);
3583
3584         if (!data->sclk_dpm_key_disabled) {
3585                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3586                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3587                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3588                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3589         }
3590         return 0;
3591 }
3592
3593 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3594 {
3595         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3596
3597         if (!fiji_is_dpm_running(hwmgr))
3598                 return -EINVAL;
3599
3600         if (!data->pcie_dpm_key_disabled) {
3601                 smum_send_msg_to_smc(hwmgr->smumgr,
3602                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3603         }
3604
3605         return fiji_upload_dpmlevel_enable_mask(hwmgr);
3606 }
3607
3608 static uint32_t fiji_get_lowest_enabled_level(
3609                 struct pp_hwmgr *hwmgr, uint32_t mask)
3610 {
3611         uint32_t level = 0;
3612
3613         while(0 == (mask & (1 << level)))
3614                 level++;
3615
3616         return level;
3617 }
3618
3619 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3620 {
3621         struct fiji_hwmgr *data =
3622                         (struct fiji_hwmgr *)(hwmgr->backend);
3623         uint32_t level;
3624
3625         if (!data->sclk_dpm_key_disabled)
3626                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3627                         level = fiji_get_lowest_enabled_level(hwmgr,
3628                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3629                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3630                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3631                                                             (1 << level));
3632
3633         }
3634
3635         if (!data->mclk_dpm_key_disabled) {
3636                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3637                         level = fiji_get_lowest_enabled_level(hwmgr,
3638                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3639                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3640                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3641                                                             (1 << level));
3642                 }
3643         }
3644
3645         if (!data->pcie_dpm_key_disabled) {
3646                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3647                         level = fiji_get_lowest_enabled_level(hwmgr,
3648                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3649                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3650                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3651                                                             (1 << level));
3652                 }
3653         }
3654
3655         return 0;
3656
3657 }
3658 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3659                                 enum amd_dpm_forced_level level)
3660 {
3661         int ret = 0;
3662
3663         switch (level) {
3664         case AMD_DPM_FORCED_LEVEL_HIGH:
3665                 ret = fiji_force_dpm_highest(hwmgr);
3666                 if (ret)
3667                         return ret;
3668                 break;
3669         case AMD_DPM_FORCED_LEVEL_LOW:
3670                 ret = fiji_force_dpm_lowest(hwmgr);
3671                 if (ret)
3672                         return ret;
3673                 break;
3674         case AMD_DPM_FORCED_LEVEL_AUTO:
3675                 ret = fiji_unforce_dpm_levels(hwmgr);
3676                 if (ret)
3677                         return ret;
3678                 break;
3679         default:
3680                 break;
3681         }
3682
3683         hwmgr->dpm_level = level;
3684
3685         return ret;
3686 }
3687
3688 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3689 {
3690         return sizeof(struct fiji_power_state);
3691 }
3692
3693 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3694                 void *state, struct pp_power_state *power_state,
3695                 void *pp_table, uint32_t classification_flag)
3696 {
3697         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3698         struct fiji_power_state  *fiji_power_state =
3699                         (struct fiji_power_state *)(&(power_state->hardware));
3700         struct fiji_performance_level *performance_level;
3701         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3702         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3703                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3704         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3705                         (ATOM_Tonga_SCLK_Dependency_Table *)
3706                         (((unsigned long)powerplay_table) +
3707                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3708         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3709                         (ATOM_Tonga_MCLK_Dependency_Table *)
3710                         (((unsigned long)powerplay_table) +
3711                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3712
3713         /* The following fields are not initialized here: id orderedList allStatesList */
3714         power_state->classification.ui_label =
3715                         (le16_to_cpu(state_entry->usClassification) &
3716                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3717                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3718         power_state->classification.flags = classification_flag;
3719         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3720
3721         power_state->classification.temporary_state = false;
3722         power_state->classification.to_be_deleted = false;
3723
3724         power_state->validation.disallowOnDC =
3725                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3726                                         ATOM_Tonga_DISALLOW_ON_DC));
3727
3728         power_state->pcie.lanes = 0;
3729
3730         power_state->display.disableFrameModulation = false;
3731         power_state->display.limitRefreshrate = false;
3732         power_state->display.enableVariBright =
3733                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3734                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3735
3736         power_state->validation.supportedPowerLevels = 0;
3737         power_state->uvd_clocks.VCLK = 0;
3738         power_state->uvd_clocks.DCLK = 0;
3739         power_state->temperatures.min = 0;
3740         power_state->temperatures.max = 0;
3741
3742         performance_level = &(fiji_power_state->performance_levels
3743                         [fiji_power_state->performance_level_count++]);
3744
3745         PP_ASSERT_WITH_CODE(
3746                         (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3747                         "Performance levels exceeds SMC limit!",
3748                         return -1);
3749
3750         PP_ASSERT_WITH_CODE(
3751                         (fiji_power_state->performance_level_count <=
3752                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3753                         "Performance levels exceeds Driver limit!",
3754                         return -1);
3755
3756         /* Performance levels are arranged from low to high. */
3757         performance_level->memory_clock = mclk_dep_table->entries
3758                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3759         performance_level->engine_clock = sclk_dep_table->entries
3760                         [state_entry->ucEngineClockIndexLow].ulSclk;
3761         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3762                         state_entry->ucPCIEGenLow);
3763         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3764                         state_entry->ucPCIELaneHigh);
3765
3766         performance_level = &(fiji_power_state->performance_levels
3767                         [fiji_power_state->performance_level_count++]);
3768         performance_level->memory_clock = mclk_dep_table->entries
3769                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3770         performance_level->engine_clock = sclk_dep_table->entries
3771                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3772         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3773                         state_entry->ucPCIEGenHigh);
3774         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3775                         state_entry->ucPCIELaneHigh);
3776
3777         return 0;
3778 }
3779
3780 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3781                 unsigned long entry_index, struct pp_power_state *state)
3782 {
3783         int result;
3784         struct fiji_power_state *ps;
3785         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3786         struct phm_ppt_v1_information *table_info =
3787                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3788         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3789                         table_info->vdd_dep_on_mclk;
3790
3791         state->hardware.magic = PHM_VIslands_Magic;
3792
3793         ps = (struct fiji_power_state *)(&state->hardware);
3794
3795         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3796                         fiji_get_pp_table_entry_callback_func);
3797
3798         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3799          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3800          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3801          */
3802         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3803                 if (dep_mclk_table->entries[0].clk !=
3804                                 data->vbios_boot_state.mclk_bootup_value)
3805                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3806                                         "does not match VBIOS boot MCLK level");
3807                 if (dep_mclk_table->entries[0].vddci !=
3808                                 data->vbios_boot_state.vddci_bootup_value)
3809                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3810                                         "does not match VBIOS boot VDDCI level");
3811         }
3812
3813         /* set DC compatible flag if this state supports DC */
3814         if (!state->validation.disallowOnDC)
3815                 ps->dc_compatible = true;
3816
3817         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3818                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3819
3820         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3821         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3822
3823         if (!result) {
3824                 uint32_t i;
3825
3826                 switch (state->classification.ui_label) {
3827                 case PP_StateUILabel_Performance:
3828                         data->use_pcie_performance_levels = true;
3829
3830                         for (i = 0; i < ps->performance_level_count; i++) {
3831                                 if (data->pcie_gen_performance.max <
3832                                                 ps->performance_levels[i].pcie_gen)
3833                                         data->pcie_gen_performance.max =
3834                                                         ps->performance_levels[i].pcie_gen;
3835
3836                                 if (data->pcie_gen_performance.min >
3837                                                 ps->performance_levels[i].pcie_gen)
3838                                         data->pcie_gen_performance.min =
3839                                                         ps->performance_levels[i].pcie_gen;
3840
3841                                 if (data->pcie_lane_performance.max <
3842                                                 ps->performance_levels[i].pcie_lane)
3843                                         data->pcie_lane_performance.max =
3844                                                         ps->performance_levels[i].pcie_lane;
3845
3846                                 if (data->pcie_lane_performance.min >
3847                                                 ps->performance_levels[i].pcie_lane)
3848                                         data->pcie_lane_performance.min =
3849                                                         ps->performance_levels[i].pcie_lane;
3850                         }
3851                         break;
3852                 case PP_StateUILabel_Battery:
3853                         data->use_pcie_power_saving_levels = true;
3854
3855                         for (i = 0; i < ps->performance_level_count; i++) {
3856                                 if (data->pcie_gen_power_saving.max <
3857                                                 ps->performance_levels[i].pcie_gen)
3858                                         data->pcie_gen_power_saving.max =
3859                                                         ps->performance_levels[i].pcie_gen;
3860
3861                                 if (data->pcie_gen_power_saving.min >
3862                                                 ps->performance_levels[i].pcie_gen)
3863                                         data->pcie_gen_power_saving.min =
3864                                                         ps->performance_levels[i].pcie_gen;
3865
3866                                 if (data->pcie_lane_power_saving.max <
3867                                                 ps->performance_levels[i].pcie_lane)
3868                                         data->pcie_lane_power_saving.max =
3869                                                         ps->performance_levels[i].pcie_lane;
3870
3871                                 if (data->pcie_lane_power_saving.min >
3872                                                 ps->performance_levels[i].pcie_lane)
3873                                         data->pcie_lane_power_saving.min =
3874                                                         ps->performance_levels[i].pcie_lane;
3875                         }
3876                         break;
3877                 default:
3878                         break;
3879                 }
3880         }
3881         return 0;
3882 }
3883
3884 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3885                                 struct pp_power_state  *request_ps,
3886                         const struct pp_power_state *current_ps)
3887 {
3888         struct fiji_power_state *fiji_ps =
3889                                 cast_phw_fiji_power_state(&request_ps->hardware);
3890         uint32_t sclk;
3891         uint32_t mclk;
3892         struct PP_Clocks minimum_clocks = {0};
3893         bool disable_mclk_switching;
3894         bool disable_mclk_switching_for_frame_lock;
3895         struct cgs_display_info info = {0};
3896         const struct phm_clock_and_voltage_limits *max_limits;
3897         uint32_t i;
3898         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3899         struct phm_ppt_v1_information *table_info =
3900                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3901         int32_t count;
3902         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3903
3904         data->battery_state = (PP_StateUILabel_Battery ==
3905                         request_ps->classification.ui_label);
3906
3907         PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3908                                  "VI should always have 2 performance levels",);
3909
3910         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3911                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3912                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3913
3914         /* Cap clock DPM tables at DC MAX if it is in DC. */
3915         if (PP_PowerSource_DC == hwmgr->power_source) {
3916                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3917                         if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3918                                 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3919                         if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3920                                 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3921                 }
3922         }
3923
3924         fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3925         fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3926
3927         fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3928
3929         cgs_get_active_displays_info(hwmgr->device, &info);
3930
3931         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3932
3933         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3934
3935         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3936                         PHM_PlatformCaps_StablePState)) {
3937                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3938                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3939
3940                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3941                                 count >= 0; count--) {
3942                         if (stable_pstate_sclk >=
3943                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3944                                 stable_pstate_sclk =
3945                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3946                                 break;
3947                         }
3948                 }
3949
3950                 if (count < 0)
3951                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3952
3953                 stable_pstate_mclk = max_limits->mclk;
3954
3955                 minimum_clocks.engineClock = stable_pstate_sclk;
3956                 minimum_clocks.memoryClock = stable_pstate_mclk;
3957         }
3958
3959         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3960                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3961
3962         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3963                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3964
3965         fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3966
3967         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3968                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3969                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3970                                 "Overdrive sclk exceeds limit",
3971                                 hwmgr->gfx_arbiter.sclk_over_drive =
3972                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3973
3974                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3975                         fiji_ps->performance_levels[1].engine_clock =
3976                                         hwmgr->gfx_arbiter.sclk_over_drive;
3977         }
3978
3979         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3980                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3981                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3982                                 "Overdrive mclk exceeds limit",
3983                                 hwmgr->gfx_arbiter.mclk_over_drive =
3984                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3985
3986                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3987                         fiji_ps->performance_levels[1].memory_clock =
3988                                         hwmgr->gfx_arbiter.mclk_over_drive;
3989         }
3990
3991         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3992                                     hwmgr->platform_descriptor.platformCaps,
3993                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3994
3995         disable_mclk_switching = (1 < info.display_count) ||
3996                                     disable_mclk_switching_for_frame_lock;
3997
3998         sclk = fiji_ps->performance_levels[0].engine_clock;
3999         mclk = fiji_ps->performance_levels[0].memory_clock;
4000
4001         if (disable_mclk_switching)
4002                 mclk = fiji_ps->performance_levels
4003                 [fiji_ps->performance_level_count - 1].memory_clock;
4004
4005         if (sclk < minimum_clocks.engineClock)
4006                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
4007                                 max_limits->sclk : minimum_clocks.engineClock;
4008
4009         if (mclk < minimum_clocks.memoryClock)
4010                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
4011                                 max_limits->mclk : minimum_clocks.memoryClock;
4012
4013         fiji_ps->performance_levels[0].engine_clock = sclk;
4014         fiji_ps->performance_levels[0].memory_clock = mclk;
4015
4016         fiji_ps->performance_levels[1].engine_clock =
4017                 (fiji_ps->performance_levels[1].engine_clock >=
4018                                 fiji_ps->performance_levels[0].engine_clock) ?
4019                                                 fiji_ps->performance_levels[1].engine_clock :
4020                                                 fiji_ps->performance_levels[0].engine_clock;
4021
4022         if (disable_mclk_switching) {
4023                 if (mclk < fiji_ps->performance_levels[1].memory_clock)
4024                         mclk = fiji_ps->performance_levels[1].memory_clock;
4025
4026                 fiji_ps->performance_levels[0].memory_clock = mclk;
4027                 fiji_ps->performance_levels[1].memory_clock = mclk;
4028         } else {
4029                 if (fiji_ps->performance_levels[1].memory_clock <
4030                                 fiji_ps->performance_levels[0].memory_clock)
4031                         fiji_ps->performance_levels[1].memory_clock =
4032                                         fiji_ps->performance_levels[0].memory_clock;
4033         }
4034
4035         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4036                         PHM_PlatformCaps_StablePState)) {
4037                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4038                         fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4039                         fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4040                         fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4041                         fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4042                 }
4043         }
4044
4045         return 0;
4046 }
4047
4048 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4049 {
4050         const struct phm_set_power_state_input *states =
4051                         (const struct phm_set_power_state_input *)input;
4052         const struct fiji_power_state *fiji_ps =
4053                         cast_const_phw_fiji_power_state(states->pnew_state);
4054         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4055         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4056         uint32_t sclk = fiji_ps->performance_levels
4057                         [fiji_ps->performance_level_count - 1].engine_clock;
4058         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4059         uint32_t mclk = fiji_ps->performance_levels
4060                         [fiji_ps->performance_level_count - 1].memory_clock;
4061         uint32_t i;
4062         struct cgs_display_info info = {0};
4063
4064         data->need_update_smu7_dpm_table = 0;
4065
4066         for (i = 0; i < sclk_table->count; i++) {
4067                 if (sclk == sclk_table->dpm_levels[i].value)
4068                         break;
4069         }
4070
4071         if (i >= sclk_table->count)
4072                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4073         else {
4074                 if(data->display_timing.min_clock_in_sr !=
4075                         hwmgr->display_config.min_core_set_clock_in_sr)
4076                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4077         }
4078
4079         for (i = 0; i < mclk_table->count; i++) {
4080                 if (mclk == mclk_table->dpm_levels[i].value)
4081                         break;
4082         }
4083
4084         if (i >= mclk_table->count)
4085                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4086
4087         cgs_get_active_displays_info(hwmgr->device, &info);
4088
4089         if (data->display_timing.num_existing_displays != info.display_count)
4090                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4091
4092         return 0;
4093 }
4094
4095 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4096                 const struct fiji_power_state *fiji_ps)
4097 {
4098         uint32_t i;
4099         uint32_t sclk, max_sclk = 0;
4100         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4101         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4102
4103         for (i = 0; i < fiji_ps->performance_level_count; i++) {
4104                 sclk = fiji_ps->performance_levels[i].engine_clock;
4105                 if (max_sclk < sclk)
4106                         max_sclk = sclk;
4107         }
4108
4109         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4110                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4111                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4112                                         dpm_table->pcie_speed_table.dpm_levels
4113                                         [dpm_table->pcie_speed_table.count - 1].value :
4114                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4115         }
4116
4117         return 0;
4118 }
4119
4120 static int fiji_request_link_speed_change_before_state_change(
4121                 struct pp_hwmgr *hwmgr, const void *input)
4122 {
4123         const struct phm_set_power_state_input *states =
4124                         (const struct phm_set_power_state_input *)input;
4125         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4126         const struct fiji_power_state *fiji_nps =
4127                         cast_const_phw_fiji_power_state(states->pnew_state);
4128         const struct fiji_power_state *fiji_cps =
4129                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4130
4131         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4132         uint16_t current_link_speed;
4133
4134         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4135                 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4136         else
4137                 current_link_speed = data->force_pcie_gen;
4138
4139         data->force_pcie_gen = PP_PCIEGenInvalid;
4140         data->pspp_notify_required = false;
4141         if (target_link_speed > current_link_speed) {
4142                 switch(target_link_speed) {
4143                 case PP_PCIEGen3:
4144                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4145                                 break;
4146                         data->force_pcie_gen = PP_PCIEGen2;
4147                         if (current_link_speed == PP_PCIEGen2)
4148                                 break;
4149                 case PP_PCIEGen2:
4150                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4151                                 break;
4152                 default:
4153                         data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4154                         break;
4155                 }
4156         } else {
4157                 if (target_link_speed < current_link_speed)
4158                         data->pspp_notify_required = true;
4159         }
4160
4161         return 0;
4162 }
4163
4164 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4165 {
4166         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4167
4168         if (0 == data->need_update_smu7_dpm_table)
4169                 return 0;
4170
4171         if ((0 == data->sclk_dpm_key_disabled) &&
4172                 (data->need_update_smu7_dpm_table &
4173                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4174                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4175                                 "Trying to freeze SCLK DPM when DPM is disabled",);
4176                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4177                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4178                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4179                                 return -1);
4180         }
4181
4182         if ((0 == data->mclk_dpm_key_disabled) &&
4183                 (data->need_update_smu7_dpm_table &
4184                  DPMTABLE_OD_UPDATE_MCLK)) {
4185                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4186                                 "Trying to freeze MCLK DPM when DPM is disabled",);
4187                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4188                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4189                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4190                                 return -1);
4191         }
4192
4193         return 0;
4194 }
4195
4196 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4197                 struct pp_hwmgr *hwmgr, const void *input)
4198 {
4199         int result = 0;
4200         const struct phm_set_power_state_input *states =
4201                         (const struct phm_set_power_state_input *)input;
4202         const struct fiji_power_state *fiji_ps =
4203                         cast_const_phw_fiji_power_state(states->pnew_state);
4204         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4205         uint32_t sclk = fiji_ps->performance_levels
4206                         [fiji_ps->performance_level_count - 1].engine_clock;
4207         uint32_t mclk = fiji_ps->performance_levels
4208                         [fiji_ps->performance_level_count - 1].memory_clock;
4209         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4210
4211         struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4212         uint32_t dpm_count, clock_percent;
4213         uint32_t i;
4214
4215         if (0 == data->need_update_smu7_dpm_table)
4216                 return 0;
4217
4218         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4219                 dpm_table->sclk_table.dpm_levels
4220                 [dpm_table->sclk_table.count - 1].value = sclk;
4221
4222                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4223                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4224                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4225                                         PHM_PlatformCaps_OD6PlusinDCSupport)) {
4226                 /* Need to do calculation based on the golden DPM table
4227                  * as the Heatmap GPU Clock axis is also based on the default values
4228                  */
4229                         PP_ASSERT_WITH_CODE(
4230                                 (golden_dpm_table->sclk_table.dpm_levels
4231                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4232                                 "Divide by 0!",
4233                                 return -1);
4234                         dpm_count = dpm_table->sclk_table.count < 2 ?
4235                                         0 : dpm_table->sclk_table.count - 2;
4236                         for (i = dpm_count; i > 1; i--) {
4237                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4238                                                 [golden_dpm_table->sclk_table.count-1].value) {
4239                                         clock_percent =
4240                                                 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4241                                                         [golden_dpm_table->sclk_table.count-1].value) * 100) /
4242                                                 golden_dpm_table->sclk_table.dpm_levels
4243                                                         [golden_dpm_table->sclk_table.count-1].value;
4244
4245                                         dpm_table->sclk_table.dpm_levels[i].value =
4246                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4247                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4248                                                                 clock_percent)/100;
4249
4250                                 } else if (golden_dpm_table->sclk_table.dpm_levels
4251                                                 [dpm_table->sclk_table.count-1].value > sclk) {
4252                                         clock_percent =
4253                                                 ((golden_dpm_table->sclk_table.dpm_levels
4254                                                 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4255                                                                 100) /
4256                                                 golden_dpm_table->sclk_table.dpm_levels
4257                                                         [golden_dpm_table->sclk_table.count-1].value;
4258
4259                                         dpm_table->sclk_table.dpm_levels[i].value =
4260                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4261                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4262                                                                         clock_percent) / 100;
4263                                 } else
4264                                         dpm_table->sclk_table.dpm_levels[i].value =
4265                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4266                         }
4267                 }
4268         }
4269
4270         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4271                 dpm_table->mclk_table.dpm_levels
4272                         [dpm_table->mclk_table.count - 1].value = mclk;
4273                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4274                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4275                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4276                                 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4277
4278                         PP_ASSERT_WITH_CODE(
4279                                         (golden_dpm_table->mclk_table.dpm_levels
4280                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4281                                         "Divide by 0!",
4282                                         return -1);
4283                         dpm_count = dpm_table->mclk_table.count < 2 ?
4284                                         0 : dpm_table->mclk_table.count - 2;
4285                         for (i = dpm_count; i > 1; i--) {
4286                                 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4287                                                 [golden_dpm_table->mclk_table.count-1].value) {
4288                                         clock_percent = ((mclk -
4289                                                         golden_dpm_table->mclk_table.dpm_levels
4290                                                         [golden_dpm_table->mclk_table.count-1].value) * 100) /
4291                                                         golden_dpm_table->mclk_table.dpm_levels
4292                                                         [golden_dpm_table->mclk_table.count-1].value;
4293
4294                                         dpm_table->mclk_table.dpm_levels[i].value =
4295                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4296                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4297                                                                         clock_percent) / 100;
4298
4299                                 } else if (golden_dpm_table->mclk_table.dpm_levels
4300                                                 [dpm_table->mclk_table.count-1].value > mclk) {
4301                                         clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4302                                                         [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4303                                                                         golden_dpm_table->mclk_table.dpm_levels
4304                                                                         [golden_dpm_table->mclk_table.count-1].value;
4305
4306                                         dpm_table->mclk_table.dpm_levels[i].value =
4307                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4308                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4309                                                                         clock_percent) / 100;
4310                                 } else
4311                                         dpm_table->mclk_table.dpm_levels[i].value =
4312                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4313                         }
4314                 }
4315         }
4316
4317         if (data->need_update_smu7_dpm_table &
4318                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4319                 result = fiji_populate_all_graphic_levels(hwmgr);
4320                 PP_ASSERT_WITH_CODE((0 == result),
4321                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4322                                 return result);
4323         }
4324
4325         if (data->need_update_smu7_dpm_table &
4326                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4327                 /*populate MCLK dpm table to SMU7 */
4328                 result = fiji_populate_all_memory_levels(hwmgr);
4329                 PP_ASSERT_WITH_CODE((0 == result),
4330                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4331                                 return result);
4332         }
4333
4334         return result;
4335 }
4336
4337 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4338                           struct fiji_single_dpm_table * dpm_table,
4339                              uint32_t low_limit, uint32_t high_limit)
4340 {
4341         uint32_t i;
4342
4343         for (i = 0; i < dpm_table->count; i++) {
4344                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4345                     (dpm_table->dpm_levels[i].value > high_limit))
4346                         dpm_table->dpm_levels[i].enabled = false;
4347                 else
4348                         dpm_table->dpm_levels[i].enabled = true;
4349         }
4350         return 0;
4351 }
4352
4353 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4354                 const struct fiji_power_state *fiji_ps)
4355 {
4356         int result = 0;
4357         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4358         uint32_t high_limit_count;
4359
4360         PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4361                         "power state did not have any performance level",
4362                         return -1);
4363
4364         high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4365
4366         fiji_trim_single_dpm_states(hwmgr,
4367                         &(data->dpm_table.sclk_table),
4368                         fiji_ps->performance_levels[0].engine_clock,
4369                         fiji_ps->performance_levels[high_limit_count].engine_clock);
4370
4371         fiji_trim_single_dpm_states(hwmgr,
4372                         &(data->dpm_table.mclk_table),
4373                         fiji_ps->performance_levels[0].memory_clock,
4374                         fiji_ps->performance_levels[high_limit_count].memory_clock);
4375
4376         return result;
4377 }
4378
4379 static int fiji_generate_dpm_level_enable_mask(
4380                 struct pp_hwmgr *hwmgr, const void *input)
4381 {
4382         int result;
4383         const struct phm_set_power_state_input *states =
4384                         (const struct phm_set_power_state_input *)input;
4385         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4386         const struct fiji_power_state *fiji_ps =
4387                         cast_const_phw_fiji_power_state(states->pnew_state);
4388
4389         result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4390         if (result)
4391                 return result;
4392
4393         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4394                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4395         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4396                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4397         data->last_mclk_dpm_enable_mask =
4398                         data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4399
4400         if (data->uvd_enabled) {
4401                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4402                         data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4403         }
4404
4405         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4406                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4407
4408         return 0;
4409 }
4410
4411 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4412 {
4413         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4414                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4415                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4416 }
4417
4418 int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4419 {
4420         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4421                         PPSMC_MSG_VCEDPM_Enable :
4422                         PPSMC_MSG_VCEDPM_Disable);
4423 }
4424
4425 int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4426 {
4427         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4428                         PPSMC_MSG_SAMUDPM_Enable :
4429                         PPSMC_MSG_SAMUDPM_Disable);
4430 }
4431
4432 int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4433 {
4434         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4435                         PPSMC_MSG_ACPDPM_Enable :
4436                         PPSMC_MSG_ACPDPM_Disable);
4437 }
4438
4439 int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4440 {
4441         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4442         uint32_t mm_boot_level_offset, mm_boot_level_value;
4443         struct phm_ppt_v1_information *table_info =
4444                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4445
4446         if (!bgate) {
4447                 data->smc_state_table.UvdBootLevel = 0;
4448                 if (table_info->mm_dep_table->count > 0)
4449                         data->smc_state_table.UvdBootLevel =
4450                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4451                 mm_boot_level_offset = data->dpm_table_start +
4452                                 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4453                 mm_boot_level_offset /= 4;
4454                 mm_boot_level_offset *= 4;
4455                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4456                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4457                 mm_boot_level_value &= 0x00FFFFFF;
4458                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4459                 cgs_write_ind_register(hwmgr->device,
4460                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4461
4462                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4463                                 PHM_PlatformCaps_UVDDPM) ||
4464                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4465                                 PHM_PlatformCaps_StablePState))
4466                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4467                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4468                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4469         }
4470
4471         return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4472 }
4473
4474 int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4475 {
4476         const struct phm_set_power_state_input *states =
4477                         (const struct phm_set_power_state_input *)input;
4478         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4479         const struct fiji_power_state *fiji_nps =
4480                         cast_const_phw_fiji_power_state(states->pnew_state);
4481         const struct fiji_power_state *fiji_cps =
4482                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4483
4484         uint32_t mm_boot_level_offset, mm_boot_level_value;
4485         struct phm_ppt_v1_information *table_info =
4486                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4487
4488         if (fiji_nps->vce_clks.evclk >0 &&
4489         (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4490                 data->smc_state_table.VceBootLevel =
4491                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4492
4493                 mm_boot_level_offset = data->dpm_table_start +
4494                                 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4495                 mm_boot_level_offset /= 4;
4496                 mm_boot_level_offset *= 4;
4497                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4498                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4499                 mm_boot_level_value &= 0xFF00FFFF;
4500                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4501                 cgs_write_ind_register(hwmgr->device,
4502                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4503
4504                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4505                                 PHM_PlatformCaps_StablePState)) {
4506                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4507                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4508                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4509
4510                         fiji_enable_disable_vce_dpm(hwmgr, true);
4511                 } else if (fiji_nps->vce_clks.evclk == 0 &&
4512                                 fiji_cps != NULL &&
4513                                 fiji_cps->vce_clks.evclk > 0)
4514                         fiji_enable_disable_vce_dpm(hwmgr, false);
4515         }
4516
4517         return 0;
4518 }
4519
4520 int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4521 {
4522         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4523         uint32_t mm_boot_level_offset, mm_boot_level_value;
4524         struct phm_ppt_v1_information *table_info =
4525                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4526
4527         if (!bgate) {
4528                 data->smc_state_table.SamuBootLevel =
4529                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4530                 mm_boot_level_offset = data->dpm_table_start +
4531                                 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4532                 mm_boot_level_offset /= 4;
4533                 mm_boot_level_offset *= 4;
4534                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4535                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4536                 mm_boot_level_value &= 0xFFFFFF00;
4537                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4538                 cgs_write_ind_register(hwmgr->device,
4539                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4540
4541                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4542                                 PHM_PlatformCaps_StablePState))
4543                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4544                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4545                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4546         }
4547
4548         return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4549 }
4550
4551 int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4552 {
4553         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4554         uint32_t mm_boot_level_offset, mm_boot_level_value;
4555         struct phm_ppt_v1_information *table_info =
4556                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4557
4558         if (!bgate) {
4559                 data->smc_state_table.AcpBootLevel =
4560                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4561                 mm_boot_level_offset = data->dpm_table_start +
4562                                 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4563                 mm_boot_level_offset /= 4;
4564                 mm_boot_level_offset *= 4;
4565                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4566                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4567                 mm_boot_level_value &= 0xFFFF00FF;
4568                 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4569                 cgs_write_ind_register(hwmgr->device,
4570                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4571
4572                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4573                                 PHM_PlatformCaps_StablePState))
4574                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4575                                                 PPSMC_MSG_ACPDPM_SetEnabledMask,
4576                                                 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4577         }
4578
4579         return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4580 }
4581
4582 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4583 {
4584         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4585
4586         int result = 0;
4587         uint32_t low_sclk_interrupt_threshold = 0;
4588
4589         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4590                         PHM_PlatformCaps_SclkThrottleLowNotification)
4591                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4592                                 data->low_sclk_interrupt_threshold)) {
4593                 data->low_sclk_interrupt_threshold =
4594                                 hwmgr->gfx_arbiter.sclk_threshold;
4595                 low_sclk_interrupt_threshold =
4596                                 data->low_sclk_interrupt_threshold;
4597
4598                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4599
4600                 result = fiji_copy_bytes_to_smc(
4601                                 hwmgr->smumgr,
4602                                 data->dpm_table_start +
4603                                 offsetof(SMU73_Discrete_DpmTable,
4604                                         LowSclkInterruptThreshold),
4605                                 (uint8_t *)&low_sclk_interrupt_threshold,
4606                                 sizeof(uint32_t),
4607                                 data->sram_end);
4608         }
4609
4610         return result;
4611 }
4612
4613 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4614 {
4615         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4616
4617         if (data->need_update_smu7_dpm_table &
4618                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4619                 return fiji_program_memory_timing_parameters(hwmgr);
4620
4621         return 0;
4622 }
4623
4624 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4625 {
4626         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4627
4628         if (0 == data->need_update_smu7_dpm_table)
4629                 return 0;
4630
4631         if ((0 == data->sclk_dpm_key_disabled) &&
4632                 (data->need_update_smu7_dpm_table &
4633                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4634
4635                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4636                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4637                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4638                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4639                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4640                         return -1);
4641         }
4642
4643         if ((0 == data->mclk_dpm_key_disabled) &&
4644                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4645
4646                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4647                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4648                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4649                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4650                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4651                     return -1);
4652         }
4653
4654         data->need_update_smu7_dpm_table = 0;
4655
4656         return 0;
4657 }
4658
4659 /* Look up the voltaged based on DAL's requested level.
4660  * and then send the requested VDDC voltage to SMC
4661  */
4662 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4663 {
4664         return;
4665 }
4666
4667 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4668 {
4669         int result;
4670         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4671
4672         /* Apply minimum voltage based on DAL's request level */
4673         fiji_apply_dal_minimum_voltage_request(hwmgr);
4674
4675         if (0 == data->sclk_dpm_key_disabled) {
4676                 /* Checking if DPM is running.  If we discover hang because of this,
4677                  *  we should skip this message.
4678                  */
4679                 if (!fiji_is_dpm_running(hwmgr))
4680                         printk(KERN_ERR "[ powerplay ] "
4681                                         "Trying to set Enable Mask when DPM is disabled \n");
4682
4683                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4684                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4685                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4686                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4687                         PP_ASSERT_WITH_CODE((0 == result),
4688                                 "Set Sclk Dpm enable Mask failed", return -1);
4689                 }
4690         }
4691
4692         if (0 == data->mclk_dpm_key_disabled) {
4693                 /* Checking if DPM is running.  If we discover hang because of this,
4694                  *  we should skip this message.
4695                  */
4696                 if (!fiji_is_dpm_running(hwmgr))
4697                         printk(KERN_ERR "[ powerplay ]"
4698                                         " Trying to set Enable Mask when DPM is disabled \n");
4699
4700                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4701                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4702                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4703                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4704                         PP_ASSERT_WITH_CODE((0 == result),
4705                                 "Set Mclk Dpm enable Mask failed", return -1);
4706                 }
4707         }
4708
4709         return 0;
4710 }
4711
4712 static int fiji_notify_link_speed_change_after_state_change(
4713                 struct pp_hwmgr *hwmgr, const void *input)
4714 {
4715         const struct phm_set_power_state_input *states =
4716                         (const struct phm_set_power_state_input *)input;
4717         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4718         const struct fiji_power_state *fiji_ps =
4719                         cast_const_phw_fiji_power_state(states->pnew_state);
4720         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4721         uint8_t  request;
4722
4723         if (data->pspp_notify_required) {
4724                 if (target_link_speed == PP_PCIEGen3)
4725                         request = PCIE_PERF_REQ_GEN3;
4726                 else if (target_link_speed == PP_PCIEGen2)
4727                         request = PCIE_PERF_REQ_GEN2;
4728                 else
4729                         request = PCIE_PERF_REQ_GEN1;
4730
4731                 if(request == PCIE_PERF_REQ_GEN1 &&
4732                                 fiji_get_current_pcie_speed(hwmgr) > 0)
4733                         return 0;
4734
4735                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4736                         if (PP_PCIEGen2 == target_link_speed)
4737                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4738                         else
4739                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4740                 }
4741         }
4742
4743         return 0;
4744 }
4745
4746 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4747                 const void *input)
4748 {
4749         int tmp_result, result = 0;
4750
4751         tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4752         PP_ASSERT_WITH_CODE((0 == tmp_result),
4753                         "Failed to find DPM states clocks in DPM table!",
4754                         result = tmp_result);
4755
4756         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4757                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4758                 tmp_result =
4759                         fiji_request_link_speed_change_before_state_change(hwmgr, input);
4760                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4761                                 "Failed to request link speed change before state change!",
4762                                 result = tmp_result);
4763         }
4764
4765         tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4766         PP_ASSERT_WITH_CODE((0 == tmp_result),
4767                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4768
4769         tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4770         PP_ASSERT_WITH_CODE((0 == tmp_result),
4771                         "Failed to populate and upload SCLK MCLK DPM levels!",
4772                         result = tmp_result);
4773
4774         tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4775         PP_ASSERT_WITH_CODE((0 == tmp_result),
4776                         "Failed to generate DPM level enabled mask!",
4777                         result = tmp_result);
4778
4779         tmp_result = fiji_update_vce_dpm(hwmgr, input);
4780         PP_ASSERT_WITH_CODE((0 == tmp_result),
4781                         "Failed to update VCE DPM!",
4782                         result = tmp_result);
4783
4784         tmp_result = fiji_update_sclk_threshold(hwmgr);
4785         PP_ASSERT_WITH_CODE((0 == tmp_result),
4786                         "Failed to update SCLK threshold!",
4787                         result = tmp_result);
4788
4789         tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4790         PP_ASSERT_WITH_CODE((0 == tmp_result),
4791                         "Failed to program memory timing parameters!",
4792                         result = tmp_result);
4793
4794         tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4795         PP_ASSERT_WITH_CODE((0 == tmp_result),
4796                         "Failed to unfreeze SCLK MCLK DPM!",
4797                         result = tmp_result);
4798
4799         tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4800         PP_ASSERT_WITH_CODE((0 == tmp_result),
4801                         "Failed to upload DPM level enabled mask!",
4802                         result = tmp_result);
4803
4804         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4805                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4806                 tmp_result =
4807                         fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4808                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4809                                 "Failed to notify link speed change after state change!",
4810                                 result = tmp_result);
4811         }
4812
4813         return result;
4814 }
4815
4816 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4817 {
4818         struct pp_power_state  *ps;
4819         struct fiji_power_state  *fiji_ps;
4820
4821         if (hwmgr == NULL)
4822                 return -EINVAL;
4823
4824         ps = hwmgr->request_ps;
4825
4826         if (ps == NULL)
4827                 return -EINVAL;
4828
4829         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4830
4831         if (low)
4832                 return fiji_ps->performance_levels[0].engine_clock;
4833         else
4834                 return fiji_ps->performance_levels
4835                                 [fiji_ps->performance_level_count-1].engine_clock;
4836 }
4837
4838 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4839 {
4840         struct pp_power_state  *ps;
4841         struct fiji_power_state  *fiji_ps;
4842
4843         if (hwmgr == NULL)
4844                 return -EINVAL;
4845
4846         ps = hwmgr->request_ps;
4847
4848         if (ps == NULL)
4849                 return -EINVAL;
4850
4851         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4852
4853         if (low)
4854                 return fiji_ps->performance_levels[0].memory_clock;
4855         else
4856                 return fiji_ps->performance_levels
4857                                 [fiji_ps->performance_level_count-1].memory_clock;
4858 }
4859
4860 static void fiji_print_current_perforce_level(
4861                 struct pp_hwmgr *hwmgr, struct seq_file *m)
4862 {
4863         uint32_t sclk, mclk, activity_percent = 0;
4864         uint32_t offset;
4865         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4866
4867         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4868
4869         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4870
4871         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4872
4873         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4874         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
4875                         mclk / 100, sclk / 100);
4876
4877         offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
4878         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4879         activity_percent += 0x80;
4880         activity_percent >>= 8;
4881
4882         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4883
4884         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
4885
4886         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
4887 }
4888
4889 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
4890 {
4891         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4892         uint32_t num_active_displays = 0;
4893         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4894                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4895         uint32_t display_gap2;
4896         uint32_t pre_vbi_time_in_us;
4897         uint32_t frame_time_in_us;
4898         uint32_t ref_clock;
4899         uint32_t refresh_rate = 0;
4900         struct cgs_display_info info = {0};
4901         struct cgs_mode_info mode_info;
4902
4903         info.mode_info = &mode_info;
4904
4905         cgs_get_active_displays_info(hwmgr->device, &info);
4906         num_active_displays = info.display_count;
4907
4908         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
4909                         DISP_GAP, (num_active_displays > 0)?
4910                         DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4911         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4912                         ixCG_DISPLAY_GAP_CNTL, display_gap);
4913
4914         ref_clock = mode_info.ref_clock;
4915         refresh_rate = mode_info.refresh_rate;
4916
4917         if (refresh_rate == 0)
4918                 refresh_rate = 60;
4919
4920         frame_time_in_us = 1000000 / refresh_rate;
4921
4922         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4923         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4924
4925         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4926                         ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4927
4928         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4929                         data->soft_regs_start +
4930                         offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
4931
4932         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4933                         data->soft_regs_start +
4934                         offsetof(SMU73_SoftRegisters, VBlankTimeout),
4935                         (frame_time_in_us - pre_vbi_time_in_us));
4936
4937         if (num_active_displays == 1)
4938                 tonga_notify_smc_display_change(hwmgr, true);
4939
4940         return 0;
4941 }
4942
4943 int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4944 {
4945         return fiji_program_display_gap(hwmgr);
4946 }
4947
4948 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
4949                 uint16_t us_max_fan_pwm)
4950 {
4951         hwmgr->thermal_controller.
4952         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4953
4954         if (phm_is_hw_access_blocked(hwmgr))
4955                 return 0;
4956
4957         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4958                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4959 }
4960
4961 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
4962                 uint16_t us_max_fan_rpm)
4963 {
4964         hwmgr->thermal_controller.
4965         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4966
4967         if (phm_is_hw_access_blocked(hwmgr))
4968                 return 0;
4969
4970         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4971                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4972 }
4973
4974 int fiji_dpm_set_interrupt_state(void *private_data,
4975                                          unsigned src_id, unsigned type,
4976                                          int enabled)
4977 {
4978         uint32_t cg_thermal_int;
4979         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
4980
4981         if (hwmgr == NULL)
4982                 return -EINVAL;
4983
4984         switch (type) {
4985         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
4986                 if (enabled) {
4987                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
4988                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
4989                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
4990                         cgs_write_ind_register(hwmgr->device,
4991                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
4992                 } else {
4993                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
4994                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
4995                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
4996                         cgs_write_ind_register(hwmgr->device,
4997                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
4998                 }
4999                 break;
5000
5001         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5002                 if (enabled) {
5003                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5004                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5005                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5006                         cgs_write_ind_register(hwmgr->device,
5007                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5008                 } else {
5009                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5010                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5011                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5012                         cgs_write_ind_register(hwmgr->device,
5013                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5014                 }
5015                 break;
5016         default:
5017                 break;
5018         }
5019         return 0;
5020 }
5021
5022 int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5023                                         const void *thermal_interrupt_info)
5024 {
5025         int result;
5026         const struct pp_interrupt_registration_info *info =
5027                         (const struct pp_interrupt_registration_info *)
5028                         thermal_interrupt_info;
5029
5030         if (info == NULL)
5031                 return -EINVAL;
5032
5033         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5034                                 fiji_dpm_set_interrupt_state,
5035                                 info->call_back, info->context);
5036
5037         if (result)
5038                 return -EINVAL;
5039
5040         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5041                                 fiji_dpm_set_interrupt_state,
5042                                 info->call_back, info->context);
5043
5044         if (result)
5045                 return -EINVAL;
5046
5047         return 0;
5048 }
5049
5050 static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5051 {
5052         if (mode) {
5053                 /* stop auto-manage */
5054                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5055                                 PHM_PlatformCaps_MicrocodeFanControl))
5056                         fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
5057                 fiji_fan_ctrl_set_static_mode(hwmgr, mode);
5058         } else
5059                 /* restart auto-manage */
5060                 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5061
5062         return 0;
5063 }
5064
5065 static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5066 {
5067         if (hwmgr->fan_ctrl_is_in_default_mode)
5068                 return hwmgr->fan_ctrl_default_mode;
5069         else
5070                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5071                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5072 }
5073
5074 static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
5075 {
5076         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5077
5078         if (!data->soft_pp_table) {
5079                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
5080                                               hwmgr->soft_pp_table_size,
5081                                               GFP_KERNEL);
5082                 if (!data->soft_pp_table)
5083                         return -ENOMEM;
5084         }
5085
5086         *table = (char *)&data->soft_pp_table;
5087
5088         return hwmgr->soft_pp_table_size;
5089 }
5090
5091 static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
5092 {
5093         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5094
5095         if (!data->soft_pp_table) {
5096                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
5097                 if (!data->soft_pp_table)
5098                         return -ENOMEM;
5099         }
5100
5101         memcpy(data->soft_pp_table, buf, size);
5102
5103         hwmgr->soft_pp_table = data->soft_pp_table;
5104
5105         /* TODO: re-init powerplay to implement modified pptable */
5106
5107         return 0;
5108 }
5109
5110 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
5111                 enum pp_clock_type type, uint32_t mask)
5112 {
5113         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5114
5115         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5116                 return -EINVAL;
5117
5118         switch (type) {
5119         case PP_SCLK:
5120                 if (!data->sclk_dpm_key_disabled)
5121                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5122                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5123                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5124                 break;
5125
5126         case PP_MCLK:
5127                 if (!data->mclk_dpm_key_disabled)
5128                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5129                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5130                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5131                 break;
5132
5133         case PP_PCIE:
5134         {
5135                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5136                 uint32_t level = 0;
5137
5138                 while (tmp >>= 1)
5139                         level++;
5140
5141                 if (!data->pcie_dpm_key_disabled)
5142                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5143                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5144                                         level);
5145                 break;
5146         }
5147         default:
5148                 break;
5149         }
5150
5151         return 0;
5152 }
5153
5154 static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5155                 enum pp_clock_type type, char *buf)
5156 {
5157         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5158         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5159         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5160         struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5161         int i, now, size = 0;
5162         uint32_t clock, pcie_speed;
5163
5164         switch (type) {
5165         case PP_SCLK:
5166                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5167                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5168
5169                 for (i = 0; i < sclk_table->count; i++) {
5170                         if (clock > sclk_table->dpm_levels[i].value)
5171                                 continue;
5172                         break;
5173                 }
5174                 now = i;
5175
5176                 for (i = 0; i < sclk_table->count; i++)
5177                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5178                                         i, sclk_table->dpm_levels[i].value / 100,
5179                                         (i == now) ? "*" : "");
5180                 break;
5181         case PP_MCLK:
5182                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5183                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5184
5185                 for (i = 0; i < mclk_table->count; i++) {
5186                         if (clock > mclk_table->dpm_levels[i].value)
5187                                 continue;
5188                         break;
5189                 }
5190                 now = i;
5191
5192                 for (i = 0; i < mclk_table->count; i++)
5193                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5194                                         i, mclk_table->dpm_levels[i].value / 100,
5195                                         (i == now) ? "*" : "");
5196                 break;
5197         case PP_PCIE:
5198                 pcie_speed = fiji_get_current_pcie_speed(hwmgr);
5199                 for (i = 0; i < pcie_table->count; i++) {
5200                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5201                                 continue;
5202                         break;
5203                 }
5204                 now = i;
5205
5206                 for (i = 0; i < pcie_table->count; i++)
5207                         size += sprintf(buf + size, "%d: %s %s\n", i,
5208                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
5209                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5210                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5211                                         (i == now) ? "*" : "");
5212                 break;
5213         default:
5214                 break;
5215         }
5216         return size;
5217 }
5218
5219 static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5220                                                            const struct fiji_performance_level *pl2)
5221 {
5222         return ((pl1->memory_clock == pl2->memory_clock) &&
5223                   (pl1->engine_clock == pl2->engine_clock) &&
5224                   (pl1->pcie_gen == pl2->pcie_gen) &&
5225                   (pl1->pcie_lane == pl2->pcie_lane));
5226 }
5227
5228 int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5229 {
5230         const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5231         const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5232         int i;
5233
5234         if (equal == NULL || psa == NULL || psb == NULL)
5235                 return -EINVAL;
5236
5237         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5238         if (psa->performance_level_count != psb->performance_level_count) {
5239                 *equal = false;
5240                 return 0;
5241         }
5242
5243         for (i = 0; i < psa->performance_level_count; i++) {
5244                 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5245                         /* If we have found even one performance level pair that is different the states are different. */
5246                         *equal = false;
5247                         return 0;
5248                 }
5249         }
5250
5251         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5252         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5253         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5254         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5255         *equal &= (psa->acp_clk == psb->acp_clk);
5256
5257         return 0;
5258 }
5259
5260 bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5261 {
5262         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5263         bool is_update_required = false;
5264         struct cgs_display_info info = {0,0,NULL};
5265
5266         cgs_get_active_displays_info(hwmgr->device, &info);
5267
5268         if (data->display_timing.num_existing_displays != info.display_count)
5269                 is_update_required = true;
5270
5271         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5272                 if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
5273                         is_update_required = true;
5274         }
5275
5276         return is_update_required;
5277 }
5278
5279
5280 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5281         .backend_init = &fiji_hwmgr_backend_init,
5282         .backend_fini = &fiji_hwmgr_backend_fini,
5283         .asic_setup = &fiji_setup_asic_task,
5284         .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
5285         .force_dpm_level = &fiji_dpm_force_dpm_level,
5286         .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
5287         .get_power_state_size = &fiji_get_power_state_size,
5288         .get_pp_table_entry = &fiji_get_pp_table_entry,
5289         .patch_boot_state = &fiji_patch_boot_state,
5290         .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
5291         .power_state_set = &fiji_set_power_state_tasks,
5292         .get_sclk = &fiji_dpm_get_sclk,
5293         .get_mclk = &fiji_dpm_get_mclk,
5294         .print_current_perforce_level = &fiji_print_current_perforce_level,
5295         .powergate_uvd = &fiji_phm_powergate_uvd,
5296         .powergate_vce = &fiji_phm_powergate_vce,
5297         .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
5298         .notify_smc_display_config_after_ps_adjustment =
5299                         &tonga_notify_smc_display_config_after_ps_adjustment,
5300         .display_config_changed = &fiji_display_configuration_changed_task,
5301         .set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
5302         .set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
5303         .get_temperature = fiji_thermal_get_temperature,
5304         .stop_thermal_controller = fiji_thermal_stop_thermal_controller,
5305         .get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
5306         .get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
5307         .set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
5308         .reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
5309         .get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
5310         .set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
5311         .uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
5312         .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5313         .set_fan_control_mode = fiji_set_fan_control_mode,
5314         .get_fan_control_mode = fiji_get_fan_control_mode,
5315         .check_states_equal = fiji_check_states_equal,
5316         .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5317         .get_pp_table = fiji_get_pp_table,
5318         .set_pp_table = fiji_set_pp_table,
5319         .force_clock_level = fiji_force_clock_level,
5320         .print_clock_levels = fiji_print_clock_levels,
5321 };
5322
5323 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
5324 {
5325         struct fiji_hwmgr  *data;
5326         int ret = 0;
5327
5328         data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
5329         if (data == NULL)
5330                 return -ENOMEM;
5331
5332         hwmgr->backend = data;
5333         hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
5334         hwmgr->pptable_func = &tonga_pptable_funcs;
5335         pp_fiji_thermal_initialize(hwmgr);
5336         return ret;
5337 }