drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94
  95 static int
  96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  97 {
  98         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  99
 100         switch (max_link_bw) {
 101         case DP_LINK_BW_1_62:
 102         case DP_LINK_BW_2_7:
 103                 break;
 104         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 105                 max_link_bw = DP_LINK_BW_2_7;
 106                 break;
 107         default:
 108                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 109                      max_link_bw);
 110                 max_link_bw = DP_LINK_BW_1_62;
 111                 break;
 112         }
 113         return max_link_bw;
 114 }
 115
 116 /*
 117  * The units on the numbers in the next two are... bizarre.  Examples will
 118  * make it clearer; this one parallels an example in the eDP spec.
 119  *
 120  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 121  *
 122  *     270000 * 1 * 8 / 10 == 216000
 123  *
 124  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 125  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 126  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 127  * 119000.  At 18bpp that's 2142000 kilobits per second.
 128  *
 129  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 130  * get the result in decakilobits instead of kilobits.
 131  */
 132
 133 static int
 134 intel_dp_link_required(int pixel_clock, int bpp)
 135 {
 136         return (pixel_clock * bpp + 9) / 10;
 137 }
 138
 139 static int
 140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 141 {
 142         return (max_link_clock * max_lanes * 8) / 10;
 143 }
 144
 145 static int
 146 intel_dp_mode_valid(struct drm_connector *connector,
 147                     struct drm_display_mode *mode)
 148 {
 149         struct intel_dp *intel_dp = intel_attached_dp(connector);
 150         struct intel_connector *intel_connector = to_intel_connector(connector);
 151         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 152         int target_clock = mode->clock;
 153         int max_rate, mode_rate, max_lanes, max_link_clock;
 154
 155         if (is_edp(intel_dp) && fixed_mode) {
 156                 if (mode->hdisplay > fixed_mode->hdisplay)
 157                         return MODE_PANEL;
 158
 159                 if (mode->vdisplay > fixed_mode->vdisplay)
 160                         return MODE_PANEL;
 161
 162                 target_clock = fixed_mode->clock;
 163         }
 164
 165         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 166         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 167
 168         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 169         mode_rate = intel_dp_link_required(target_clock, 18);
 170
 171         if (mode_rate > max_rate)
 172                 return MODE_CLOCK_HIGH;
 173
 174         if (mode->clock < 10000)
 175                 return MODE_CLOCK_LOW;
 176
 177         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 178                 return MODE_H_ILLEGAL;
 179
 180         return MODE_OK;
 181 }
 182
 183 static uint32_t
 184 pack_aux(uint8_t *src, int src_bytes)
 185 {
 186         int     i;
 187         uint32_t v = 0;
 188
 189         if (src_bytes > 4)
 190                 src_bytes = 4;
 191         for (i = 0; i < src_bytes; i++)
 192                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 193         return v;
 194 }
 195
 196 static void
 197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 198 {
 199         int i;
 200         if (dst_bytes > 4)
 201                 dst_bytes = 4;
 202         for (i = 0; i < dst_bytes; i++)
 203                 dst[i] = src >> ((3-i) * 8);
 204 }
 205
 206 /* hrawclock is 1/4 the FSB frequency */
 207 static int
 208 intel_hrawclk(struct drm_device *dev)
 209 {
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         uint32_t clkcfg;
 212
 213         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 214         if (IS_VALLEYVIEW(dev))
 215                 return 200;
 216
 217         clkcfg = I915_READ(CLKCFG);
 218         switch (clkcfg & CLKCFG_FSB_MASK) {
 219         case CLKCFG_FSB_400:
 220                 return 100;
 221         case CLKCFG_FSB_533:
 222                 return 133;
 223         case CLKCFG_FSB_667:
 224                 return 166;
 225         case CLKCFG_FSB_800:
 226                 return 200;
 227         case CLKCFG_FSB_1067:
 228                 return 266;
 229         case CLKCFG_FSB_1333:
 230                 return 333;
 231         /* these two are just a guess; one of them might be right */
 232         case CLKCFG_FSB_1600:
 233         case CLKCFG_FSB_1600_ALT:
 234                 return 400;
 235         default:
 236                 return 133;
 237         }
 238 }
 239
 240 static void
 241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 242                                     struct intel_dp *intel_dp,
 243                                     struct edp_power_seq *out);
 244 static void
 245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 246                                               struct intel_dp *intel_dp,
 247                                               struct edp_power_seq *out);
 248
 249 static enum pipe
 250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 251 {
 252         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 253         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 254         struct drm_device *dev = intel_dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         enum port port = intel_dig_port->port;
 257         enum pipe pipe;
 258
 259         /* modeset should have pipe */
 260         if (crtc)
 261                 return to_intel_crtc(crtc)->pipe;
 262
 263         /* init time, try to find a pipe with this port selected */
 264         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 265                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 266                         PANEL_PORT_SELECT_MASK;
 267                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 268                         return pipe;
 269                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 270                         return pipe;
 271         }
 272
 273         /* shrug */
 274         return PIPE_A;
 275 }
 276
 277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 278 {
 279         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 280
 281         if (HAS_PCH_SPLIT(dev))
 282                 return PCH_PP_CONTROL;
 283         else
 284                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 285 }
 286
 287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 288 {
 289         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 290
 291         if (HAS_PCH_SPLIT(dev))
 292                 return PCH_PP_STATUS;
 293         else
 294                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 295 }
 296
 297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 298 {
 299         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301
 302         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 303 }
 304
 305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 306 {
 307         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 308         struct drm_i915_private *dev_priv = dev->dev_private;
 309
 310         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 311 }
 312
 313 static void
 314 intel_dp_check_edp(struct intel_dp *intel_dp)
 315 {
 316         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318
 319         if (!is_edp(intel_dp))
 320                 return;
 321
 322         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 323                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 324                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 325                               I915_READ(_pp_stat_reg(intel_dp)),
 326                               I915_READ(_pp_ctrl_reg(intel_dp)));
 327         }
 328 }
 329
 330 static uint32_t
 331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 332 {
 333         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 334         struct drm_device *dev = intel_dig_port->base.base.dev;
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 337         uint32_t status;
 338         bool done;
 339
 340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 341         if (has_aux_irq)
 342                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 343                                           msecs_to_jiffies_timeout(10));
 344         else
 345                 done = wait_for_atomic(C, 10) == 0;
 346         if (!done)
 347                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 348                           has_aux_irq);
 349 #undef C
 350
 351         return status;
 352 }
 353
 354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 355                                       int index)
 356 {
 357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 358         struct drm_device *dev = intel_dig_port->base.base.dev;
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360
 361         /* The clock divider is based off the hrawclk,
 362          * and would like to run at 2MHz. So, take the
 363          * hrawclk value and divide by 2 and use that
 364          *
 365          * Note that PCH attached eDP panels should use a 125MHz input
 366          * clock divider.
 367          */
 368         if (IS_VALLEYVIEW(dev)) {
 369                 return index ? 0 : 100;
 370         } else if (intel_dig_port->port == PORT_A) {
 371                 if (index)
 372                         return 0;
 373                 if (HAS_DDI(dev))
 374                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 375                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 376                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 377                 else
 378                         return 225; /* eDP input clock at 450Mhz */
 379         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 380                 /* Workaround for non-ULT HSW */
 381                 switch (index) {
 382                 case 0: return 63;
 383                 case 1: return 72;
 384                 default: return 0;
 385                 }
 386         } else if (HAS_PCH_SPLIT(dev)) {
 387                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 388         } else {
 389                 return index ? 0 :intel_hrawclk(dev) / 2;
 390         }
 391 }
 392
 393 static int
 394 intel_dp_aux_ch(struct intel_dp *intel_dp,
 395                 uint8_t *send, int send_bytes,
 396                 uint8_t *recv, int recv_size)
 397 {
 398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 399         struct drm_device *dev = intel_dig_port->base.base.dev;
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 402         uint32_t ch_data = ch_ctl + 4;
 403         uint32_t aux_clock_divider;
 404         int i, ret, recv_bytes;
 405         uint32_t status;
 406         int try, precharge, clock = 0;
 407         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 408
 409         /* dp aux is extremely sensitive to irq latency, hence request the
 410          * lowest possible wakeup latency and so prevent the cpu from going into
 411          * deep sleep states.
 412          */
 413         pm_qos_update_request(&dev_priv->pm_qos, 0);
 414
 415         intel_dp_check_edp(intel_dp);
 416
 417         if (IS_GEN6(dev))
 418                 precharge = 3;
 419         else
 420                 precharge = 5;
 421
 422         intel_aux_display_runtime_get(dev_priv);
 423
 424         /* Try to wait for any previous AUX channel activity */
 425         for (try = 0; try < 3; try++) {
 426                 status = I915_READ_NOTRACE(ch_ctl);
 427                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 428                         break;
 429                 msleep(1);
 430         }
 431
 432         if (try == 3) {
 433                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 434                      I915_READ(ch_ctl));
 435                 ret = -EBUSY;
 436                 goto out;
 437         }
 438
 439         /* Only 5 data registers! */
 440         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 441                 ret = -E2BIG;
 442                 goto out;
 443         }
 444
 445         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 446                 /* Must try at least 3 times according to DP spec */
 447                 for (try = 0; try < 5; try++) {
 448                         /* Load the send data into the aux channel data registers */
 449                         for (i = 0; i < send_bytes; i += 4)
 450                                 I915_WRITE(ch_data + i,
 451                                            pack_aux(send + i, send_bytes - i));
 452
 453                         /* Send the command and wait for it to complete */
 454                         I915_WRITE(ch_ctl,
 455                                    DP_AUX_CH_CTL_SEND_BUSY |
 456                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 457                                    DP_AUX_CH_CTL_TIME_OUT_400us |
 458                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 459                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 460                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 461                                    DP_AUX_CH_CTL_DONE |
 462                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 463                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 464
 465                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 466
 467                         /* Clear done status and any errors */
 468                         I915_WRITE(ch_ctl,
 469                                    status |
 470                                    DP_AUX_CH_CTL_DONE |
 471                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 472                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 473
 474                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 475                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 476                                 continue;
 477                         if (status & DP_AUX_CH_CTL_DONE)
 478                                 break;
 479                 }
 480                 if (status & DP_AUX_CH_CTL_DONE)
 481                         break;
 482         }
 483
 484         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 485                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 486                 ret = -EBUSY;
 487                 goto out;
 488         }
 489
 490         /* Check for timeout or receive error.
 491          * Timeouts occur when the sink is not connected
 492          */
 493         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 494                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 495                 ret = -EIO;
 496                 goto out;
 497         }
 498
 499         /* Timeouts occur when the device isn't connected, so they're
 500          * "normal" -- don't fill the kernel log with these */
 501         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 502                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 503                 ret = -ETIMEDOUT;
 504                 goto out;
 505         }
 506
 507         /* Unload any bytes sent back from the other side */
 508         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 509                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 510         if (recv_bytes > recv_size)
 511                 recv_bytes = recv_size;
 512
 513         for (i = 0; i < recv_bytes; i += 4)
 514                 unpack_aux(I915_READ(ch_data + i),
 515                            recv + i, recv_bytes - i);
 516
 517         ret = recv_bytes;
 518 out:
 519         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 520         intel_aux_display_runtime_put(dev_priv);
 521
 522         return ret;
 523 }
 524
 525 /* Write data to the aux channel in native mode */
 526 static int
 527 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 528                           uint16_t address, uint8_t *send, int send_bytes)
 529 {
 530         int ret;
 531         uint8_t msg[20];
 532         int msg_bytes;
 533         uint8_t ack;
 534
 535         if (WARN_ON(send_bytes > 16))
 536                 return -E2BIG;
 537
 538         intel_dp_check_edp(intel_dp);
 539         msg[0] = AUX_NATIVE_WRITE << 4;
 540         msg[1] = address >> 8;
 541         msg[2] = address & 0xff;
 542         msg[3] = send_bytes - 1;
 543         memcpy(&msg[4], send, send_bytes);
 544         msg_bytes = send_bytes + 4;
 545         for (;;) {
 546                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 547                 if (ret < 0)
 548                         return ret;
 549                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 550                         break;
 551                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 552                         udelay(100);
 553                 else
 554                         return -EIO;
 555         }
 556         return send_bytes;
 557 }
 558
 559 /* Write a single byte to the aux channel in native mode */
 560 static int
 561 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 562                             uint16_t address, uint8_t byte)
 563 {
 564         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 565 }
 566
 567 /* read bytes from a native aux channel */
 568 static int
 569 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 570                          uint16_t address, uint8_t *recv, int recv_bytes)
 571 {
 572         uint8_t msg[4];
 573         int msg_bytes;
 574         uint8_t reply[20];
 575         int reply_bytes;
 576         uint8_t ack;
 577         int ret;
 578
 579         if (WARN_ON(recv_bytes > 19))
 580                 return -E2BIG;
 581
 582         intel_dp_check_edp(intel_dp);
 583         msg[0] = AUX_NATIVE_READ << 4;
 584         msg[1] = address >> 8;
 585         msg[2] = address & 0xff;
 586         msg[3] = recv_bytes - 1;
 587
 588         msg_bytes = 4;
 589         reply_bytes = recv_bytes + 1;
 590
 591         for (;;) {
 592                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 593                                       reply, reply_bytes);
 594                 if (ret == 0)
 595                         return -EPROTO;
 596                 if (ret < 0)
 597                         return ret;
 598                 ack = reply[0];
 599                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 600                         memcpy(recv, reply + 1, ret - 1);
 601                         return ret - 1;
 602                 }
 603                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 604                         udelay(100);
 605                 else
 606                         return -EIO;
 607         }
 608 }
 609
 610 static int
 611 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 612                     uint8_t write_byte, uint8_t *read_byte)
 613 {
 614         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 615         struct intel_dp *intel_dp = container_of(adapter,
 616                                                 struct intel_dp,
 617                                                 adapter);
 618         uint16_t address = algo_data->address;
 619         uint8_t msg[5];
 620         uint8_t reply[2];
 621         unsigned retry;
 622         int msg_bytes;
 623         int reply_bytes;
 624         int ret;
 625
 626         intel_dp_check_edp(intel_dp);
 627         /* Set up the command byte */
 628         if (mode & MODE_I2C_READ)
 629                 msg[0] = AUX_I2C_READ << 4;
 630         else
 631                 msg[0] = AUX_I2C_WRITE << 4;
 632
 633         if (!(mode & MODE_I2C_STOP))
 634                 msg[0] |= AUX_I2C_MOT << 4;
 635
 636         msg[1] = address >> 8;
 637         msg[2] = address;
 638
 639         switch (mode) {
 640         case MODE_I2C_WRITE:
 641                 msg[3] = 0;
 642                 msg[4] = write_byte;
 643                 msg_bytes = 5;
 644                 reply_bytes = 1;
 645                 break;
 646         case MODE_I2C_READ:
 647                 msg[3] = 0;
 648                 msg_bytes = 4;
 649                 reply_bytes = 2;
 650                 break;
 651         default:
 652                 msg_bytes = 3;
 653                 reply_bytes = 1;
 654                 break;
 655         }
 656
 657         /*
 658          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 659          * required to retry at least seven times upon receiving AUX_DEFER
 660          * before giving up the AUX transaction.
 661          */
 662         for (retry = 0; retry < 7; retry++) {
 663                 ret = intel_dp_aux_ch(intel_dp,
 664                                       msg, msg_bytes,
 665                                       reply, reply_bytes);
 666                 if (ret < 0) {
 667                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 668                         return ret;
 669                 }
 670
 671                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 672                 case AUX_NATIVE_REPLY_ACK:
 673                         /* I2C-over-AUX Reply field is only valid
 674                          * when paired with AUX ACK.
 675                          */
 676                         break;
 677                 case AUX_NATIVE_REPLY_NACK:
 678                         DRM_DEBUG_KMS("aux_ch native nack\n");
 679                         return -EREMOTEIO;
 680                 case AUX_NATIVE_REPLY_DEFER:
 681                         /*
 682                          * For now, just give more slack to branch devices. We
 683                          * could check the DPCD for I2C bit rate capabilities,
 684                          * and if available, adjust the interval. We could also
 685                          * be more careful with DP-to-Legacy adapters where a
 686                          * long legacy cable may force very low I2C bit rates.
 687                          */
 688                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 689                             DP_DWN_STRM_PORT_PRESENT)
 690                                 usleep_range(500, 600);
 691                         else
 692                                 usleep_range(300, 400);
 693                         continue;
 694                 default:
 695                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 696                                   reply[0]);
 697                         return -EREMOTEIO;
 698                 }
 699
 700                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 701                 case AUX_I2C_REPLY_ACK:
 702                         if (mode == MODE_I2C_READ) {
 703                                 *read_byte = reply[1];
 704                         }
 705                         return reply_bytes - 1;
 706                 case AUX_I2C_REPLY_NACK:
 707                         DRM_DEBUG_KMS("aux_i2c nack\n");
 708                         return -EREMOTEIO;
 709                 case AUX_I2C_REPLY_DEFER:
 710                         DRM_DEBUG_KMS("aux_i2c defer\n");
 711                         udelay(100);
 712                         break;
 713                 default:
 714                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 715                         return -EREMOTEIO;
 716                 }
 717         }
 718
 719         DRM_ERROR("too many retries, giving up\n");
 720         return -EREMOTEIO;
 721 }
 722
 723 static int
 724 intel_dp_i2c_init(struct intel_dp *intel_dp,
 725                   struct intel_connector *intel_connector, const char *name)
 726 {
 727         int     ret;
 728
 729         DRM_DEBUG_KMS("i2c_init %s\n", name);
 730         intel_dp->algo.running = false;
 731         intel_dp->algo.address = 0;
 732         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 733
 734         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 735         intel_dp->adapter.owner = THIS_MODULE;
 736         intel_dp->adapter.class = I2C_CLASS_DDC;
 737         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 738         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 739         intel_dp->adapter.algo_data = &intel_dp->algo;
 740         intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 741
 742         ironlake_edp_panel_vdd_on(intel_dp);
 743         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 744         ironlake_edp_panel_vdd_off(intel_dp, false);
 745         return ret;
 746 }
 747
 748 static void
 749 intel_dp_set_clock(struct intel_encoder *encoder,
 750                    struct intel_crtc_config *pipe_config, int link_bw)
 751 {
 752         struct drm_device *dev = encoder->base.dev;
 753         const struct dp_link_dpll *divisor = NULL;
 754         int i, count = 0;
 755
 756         if (IS_G4X(dev)) {
 757                 divisor = gen4_dpll;
 758                 count = ARRAY_SIZE(gen4_dpll);
 759         } else if (IS_HASWELL(dev)) {
 760                 /* Haswell has special-purpose DP DDI clocks. */
 761         } else if (HAS_PCH_SPLIT(dev)) {
 762                 divisor = pch_dpll;
 763                 count = ARRAY_SIZE(pch_dpll);
 764         } else if (IS_VALLEYVIEW(dev)) {
 765                 divisor = vlv_dpll;
 766                 count = ARRAY_SIZE(vlv_dpll);
 767         }
 768
 769         if (divisor && count) {
 770                 for (i = 0; i < count; i++) {
 771                         if (link_bw == divisor[i].link_bw) {
 772                                 pipe_config->dpll = divisor[i].dpll;
 773                                 pipe_config->clock_set = true;
 774                                 break;
 775                         }
 776                 }
 777         }
 778 }
 779
 780 bool
 781 intel_dp_compute_config(struct intel_encoder *encoder,
 782                         struct intel_crtc_config *pipe_config)
 783 {
 784         struct drm_device *dev = encoder->base.dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 787         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 788         enum port port = dp_to_dig_port(intel_dp)->port;
 789         struct intel_crtc *intel_crtc = encoder->new_crtc;
 790         struct intel_connector *intel_connector = intel_dp->attached_connector;
 791         int lane_count, clock;
 792         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 793         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 794         int bpp, mode_rate;
 795         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 796         int link_avail, link_clock;
 797
 798         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 799                 pipe_config->has_pch_encoder = true;
 800
 801         pipe_config->has_dp_encoder = true;
 802
 803         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 804                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 805                                        adjusted_mode);
 806                 if (!HAS_PCH_SPLIT(dev))
 807                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 808                                                  intel_connector->panel.fitting_mode);
 809                 else
 810                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 811                                                 intel_connector->panel.fitting_mode);
 812         }
 813
 814         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 815                 return false;
 816
 817         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 818                       "max bw %02x pixel clock %iKHz\n",
 819                       max_lane_count, bws[max_clock],
 820                       adjusted_mode->crtc_clock);
 821
 822         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 823          * bpc in between. */
 824         bpp = pipe_config->pipe_bpp;
 825         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
 826                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 827                               dev_priv->vbt.edp_bpp);
 828                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 829         }
 830
 831         for (; bpp >= 6*3; bpp -= 2*3) {
 832                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 833                                                    bpp);
 834
 835                 for (clock = 0; clock <= max_clock; clock++) {
 836                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 837                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 838                                 link_avail = intel_dp_max_data_rate(link_clock,
 839                                                                     lane_count);
 840
 841                                 if (mode_rate <= link_avail) {
 842                                         goto found;
 843                                 }
 844                         }
 845                 }
 846         }
 847
 848         return false;
 849
 850 found:
 851         if (intel_dp->color_range_auto) {
 852                 /*
 853                  * See:
 854                  * CEA-861-E - 5.1 Default Encoding Parameters
 855                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 856                  */
 857                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 858                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 859                 else
 860                         intel_dp->color_range = 0;
 861         }
 862
 863         if (intel_dp->color_range)
 864                 pipe_config->limited_color_range = true;
 865
 866         intel_dp->link_bw = bws[clock];
 867         intel_dp->lane_count = lane_count;
 868         pipe_config->pipe_bpp = bpp;
 869         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 870
 871         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 872                       intel_dp->link_bw, intel_dp->lane_count,
 873                       pipe_config->port_clock, bpp);
 874         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 875                       mode_rate, link_avail);
 876
 877         intel_link_compute_m_n(bpp, lane_count,
 878                                adjusted_mode->crtc_clock,
 879                                pipe_config->port_clock,
 880                                &pipe_config->dp_m_n);
 881
 882         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 883
 884         return true;
 885 }
 886
 887 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 888 {
 889         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 890         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 891         struct drm_device *dev = crtc->base.dev;
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 dpa_ctl;
 894
 895         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 896         dpa_ctl = I915_READ(DP_A);
 897         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 898
 899         if (crtc->config.port_clock == 162000) {
 900                 /* For a long time we've carried around a ILK-DevA w/a for the
 901                  * 160MHz clock. If we're really unlucky, it's still required.
 902                  */
 903                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 904                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 905                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 906         } else {
 907                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 908                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 909         }
 910
 911         I915_WRITE(DP_A, dpa_ctl);
 912
 913         POSTING_READ(DP_A);
 914         udelay(500);
 915 }
 916
 917 static void intel_dp_mode_set(struct intel_encoder *encoder)
 918 {
 919         struct drm_device *dev = encoder->base.dev;
 920         struct drm_i915_private *dev_priv = dev->dev_private;
 921         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 922         enum port port = dp_to_dig_port(intel_dp)->port;
 923         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 924         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 925
 926         /*
 927          * There are four kinds of DP registers:
 928          *
 929          *      IBX PCH
 930          *      SNB CPU
 931          *      IVB CPU
 932          *      CPT PCH
 933          *
 934          * IBX PCH and CPU are the same for almost everything,
 935          * except that the CPU DP PLL is configured in this
 936          * register
 937          *
 938          * CPT PCH is quite different, having many bits moved
 939          * to the TRANS_DP_CTL register instead. That
 940          * configuration happens (oddly) in ironlake_pch_enable
 941          */
 942
 943         /* Preserve the BIOS-computed detected bit. This is
 944          * supposed to be read-only.
 945          */
 946         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 947
 948         /* Handle DP bits in common between all three register formats */
 949         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 950         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 951
 952         if (intel_dp->has_audio) {
 953                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 954                                  pipe_name(crtc->pipe));
 955                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 956                 intel_write_eld(&encoder->base, adjusted_mode);
 957         }
 958
 959         /* Split out the IBX/CPU vs CPT settings */
 960
 961         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 962                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 963                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 964                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 965                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 966                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 967
 968                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 969                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 970
 971                 intel_dp->DP |= crtc->pipe << 29;
 972         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 973                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 974                         intel_dp->DP |= intel_dp->color_range;
 975
 976                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 977                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 978                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 979                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 980                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 981
 982                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 983                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 984
 985                 if (crtc->pipe == 1)
 986                         intel_dp->DP |= DP_PIPEB_SELECT;
 987         } else {
 988                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 989         }
 990
 991         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 992                 ironlake_set_pll_cpu_edp(intel_dp);
 993 }
 994
 995 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 996 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 997
 998 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 999 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1000
1001 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1002 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1003
1004 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1005                                        u32 mask,
1006                                        u32 value)
1007 {
1008         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1009         struct drm_i915_private *dev_priv = dev->dev_private;
1010         u32 pp_stat_reg, pp_ctrl_reg;
1011
1012         pp_stat_reg = _pp_stat_reg(intel_dp);
1013         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1014
1015         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1016                         mask, value,
1017                         I915_READ(pp_stat_reg),
1018                         I915_READ(pp_ctrl_reg));
1019
1020         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1021                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022                                 I915_READ(pp_stat_reg),
1023                                 I915_READ(pp_ctrl_reg));
1024         }
1025 }
1026
1027 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1028 {
1029         DRM_DEBUG_KMS("Wait for panel power on\n");
1030         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1031 }
1032
1033 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1034 {
1035         DRM_DEBUG_KMS("Wait for panel power off time\n");
1036         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1037 }
1038
1039 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1040 {
1041         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1043 }
1044
1045
1046 /* Read the current pp_control value, unlocking the register if it
1047  * is locked
1048  */
1049
1050 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1051 {
1052         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054         u32 control;
1055
1056         control = I915_READ(_pp_ctrl_reg(intel_dp));
1057         control &= ~PANEL_UNLOCK_MASK;
1058         control |= PANEL_UNLOCK_REGS;
1059         return control;
1060 }
1061
1062 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1063 {
1064         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066         u32 pp;
1067         u32 pp_stat_reg, pp_ctrl_reg;
1068
1069         if (!is_edp(intel_dp))
1070                 return;
1071         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1072
1073         WARN(intel_dp->want_panel_vdd,
1074              "eDP VDD already requested on\n");
1075
1076         intel_dp->want_panel_vdd = true;
1077
1078         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1079                 DRM_DEBUG_KMS("eDP VDD already on\n");
1080                 return;
1081         }
1082
1083         if (!ironlake_edp_have_panel_power(intel_dp))
1084                 ironlake_wait_panel_power_cycle(intel_dp);
1085
1086         pp = ironlake_get_pp_control(intel_dp);
1087         pp |= EDP_FORCE_VDD;
1088
1089         pp_stat_reg = _pp_stat_reg(intel_dp);
1090         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1091
1092         I915_WRITE(pp_ctrl_reg, pp);
1093         POSTING_READ(pp_ctrl_reg);
1094         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1095                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1096         /*
1097          * If the panel wasn't on, delay before accessing aux channel
1098          */
1099         if (!ironlake_edp_have_panel_power(intel_dp)) {
1100                 DRM_DEBUG_KMS("eDP was not running\n");
1101                 msleep(intel_dp->panel_power_up_delay);
1102         }
1103 }
1104
1105 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1106 {
1107         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         u32 pp;
1110         u32 pp_stat_reg, pp_ctrl_reg;
1111
1112         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1113
1114         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1115                 pp = ironlake_get_pp_control(intel_dp);
1116                 pp &= ~EDP_FORCE_VDD;
1117
1118                 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1119                 pp_ctrl_reg = _pp_stat_reg(intel_dp);
1120
1121                 I915_WRITE(pp_ctrl_reg, pp);
1122                 POSTING_READ(pp_ctrl_reg);
1123
1124                 /* Make sure sequencer is idle before allowing subsequent activity */
1125                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1126                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1127                 msleep(intel_dp->panel_power_down_delay);
1128         }
1129 }
1130
1131 static void ironlake_panel_vdd_work(struct work_struct *__work)
1132 {
1133         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1134                                                  struct intel_dp, panel_vdd_work);
1135         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1136
1137         mutex_lock(&dev->mode_config.mutex);
1138         ironlake_panel_vdd_off_sync(intel_dp);
1139         mutex_unlock(&dev->mode_config.mutex);
1140 }
1141
1142 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1143 {
1144         if (!is_edp(intel_dp))
1145                 return;
1146
1147         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1148         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1149
1150         intel_dp->want_panel_vdd = false;
1151
1152         if (sync) {
1153                 ironlake_panel_vdd_off_sync(intel_dp);
1154         } else {
1155                 /*
1156                  * Queue the timer to fire a long
1157                  * time from now (relative to the power down delay)
1158                  * to keep the panel power up across a sequence of operations
1159                  */
1160                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1161                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1162         }
1163 }
1164
1165 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1166 {
1167         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         u32 pp;
1170         u32 pp_ctrl_reg;
1171
1172         if (!is_edp(intel_dp))
1173                 return;
1174
1175         DRM_DEBUG_KMS("Turn eDP power on\n");
1176
1177         if (ironlake_edp_have_panel_power(intel_dp)) {
1178                 DRM_DEBUG_KMS("eDP power already on\n");
1179                 return;
1180         }
1181
1182         ironlake_wait_panel_power_cycle(intel_dp);
1183
1184         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1185         pp = ironlake_get_pp_control(intel_dp);
1186         if (IS_GEN5(dev)) {
1187                 /* ILK workaround: disable reset around power sequence */
1188                 pp &= ~PANEL_POWER_RESET;
1189                 I915_WRITE(pp_ctrl_reg, pp);
1190                 POSTING_READ(pp_ctrl_reg);
1191         }
1192
1193         pp |= POWER_TARGET_ON;
1194         if (!IS_GEN5(dev))
1195                 pp |= PANEL_POWER_RESET;
1196
1197         I915_WRITE(pp_ctrl_reg, pp);
1198         POSTING_READ(pp_ctrl_reg);
1199
1200         ironlake_wait_panel_on(intel_dp);
1201
1202         if (IS_GEN5(dev)) {
1203                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1204                 I915_WRITE(pp_ctrl_reg, pp);
1205                 POSTING_READ(pp_ctrl_reg);
1206         }
1207 }
1208
1209 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1210 {
1211         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         u32 pp;
1214         u32 pp_ctrl_reg;
1215
1216         if (!is_edp(intel_dp))
1217                 return;
1218
1219         DRM_DEBUG_KMS("Turn eDP power off\n");
1220
1221         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1222
1223         pp = ironlake_get_pp_control(intel_dp);
1224         /* We need to switch off panel power _and_ force vdd, for otherwise some
1225          * panels get very unhappy and cease to work. */
1226         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1227
1228         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1229
1230         I915_WRITE(pp_ctrl_reg, pp);
1231         POSTING_READ(pp_ctrl_reg);
1232
1233         intel_dp->want_panel_vdd = false;
1234
1235         ironlake_wait_panel_off(intel_dp);
1236 }
1237
1238 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1239 {
1240         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241         struct drm_device *dev = intel_dig_port->base.base.dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1244         u32 pp;
1245         u32 pp_ctrl_reg;
1246
1247         if (!is_edp(intel_dp))
1248                 return;
1249
1250         DRM_DEBUG_KMS("\n");
1251         /*
1252          * If we enable the backlight right away following a panel power
1253          * on, we may see slight flicker as the panel syncs with the eDP
1254          * link.  So delay a bit to make sure the image is solid before
1255          * allowing it to appear.
1256          */
1257         msleep(intel_dp->backlight_on_delay);
1258         pp = ironlake_get_pp_control(intel_dp);
1259         pp |= EDP_BLC_ENABLE;
1260
1261         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1262
1263         I915_WRITE(pp_ctrl_reg, pp);
1264         POSTING_READ(pp_ctrl_reg);
1265
1266         intel_panel_enable_backlight(dev, pipe);
1267 }
1268
1269 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1270 {
1271         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 pp;
1274         u32 pp_ctrl_reg;
1275
1276         if (!is_edp(intel_dp))
1277                 return;
1278
1279         intel_panel_disable_backlight(dev);
1280
1281         DRM_DEBUG_KMS("\n");
1282         pp = ironlake_get_pp_control(intel_dp);
1283         pp &= ~EDP_BLC_ENABLE;
1284
1285         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1286
1287         I915_WRITE(pp_ctrl_reg, pp);
1288         POSTING_READ(pp_ctrl_reg);
1289         msleep(intel_dp->backlight_off_delay);
1290 }
1291
1292 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1293 {
1294         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1295         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1296         struct drm_device *dev = crtc->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         u32 dpa_ctl;
1299
1300         assert_pipe_disabled(dev_priv,
1301                              to_intel_crtc(crtc)->pipe);
1302
1303         DRM_DEBUG_KMS("\n");
1304         dpa_ctl = I915_READ(DP_A);
1305         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1306         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1307
1308         /* We don't adjust intel_dp->DP while tearing down the link, to
1309          * facilitate link retraining (e.g. after hotplug). Hence clear all
1310          * enable bits here to ensure that we don't enable too much. */
1311         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1312         intel_dp->DP |= DP_PLL_ENABLE;
1313         I915_WRITE(DP_A, intel_dp->DP);
1314         POSTING_READ(DP_A);
1315         udelay(200);
1316 }
1317
1318 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1319 {
1320         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1321         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1322         struct drm_device *dev = crtc->dev;
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         u32 dpa_ctl;
1325
1326         assert_pipe_disabled(dev_priv,
1327                              to_intel_crtc(crtc)->pipe);
1328
1329         dpa_ctl = I915_READ(DP_A);
1330         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1331              "dp pll off, should be on\n");
1332         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1333
1334         /* We can't rely on the value tracked for the DP register in
1335          * intel_dp->DP because link_down must not change that (otherwise link
1336          * re-training will fail. */
1337         dpa_ctl &= ~DP_PLL_ENABLE;
1338         I915_WRITE(DP_A, dpa_ctl);
1339         POSTING_READ(DP_A);
1340         udelay(200);
1341 }
1342
1343 /* If the sink supports it, try to set the power state appropriately */
1344 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1345 {
1346         int ret, i;
1347
1348         /* Should have a valid DPCD by this point */
1349         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1350                 return;
1351
1352         if (mode != DRM_MODE_DPMS_ON) {
1353                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1354                                                   DP_SET_POWER_D3);
1355                 if (ret != 1)
1356                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1357         } else {
1358                 /*
1359                  * When turning on, we need to retry for 1ms to give the sink
1360                  * time to wake up.
1361                  */
1362                 for (i = 0; i < 3; i++) {
1363                         ret = intel_dp_aux_native_write_1(intel_dp,
1364                                                           DP_SET_POWER,
1365                                                           DP_SET_POWER_D0);
1366                         if (ret == 1)
1367                                 break;
1368                         msleep(1);
1369                 }
1370         }
1371 }
1372
1373 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1374                                   enum pipe *pipe)
1375 {
1376         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1377         enum port port = dp_to_dig_port(intel_dp)->port;
1378         struct drm_device *dev = encoder->base.dev;
1379         struct drm_i915_private *dev_priv = dev->dev_private;
1380         u32 tmp = I915_READ(intel_dp->output_reg);
1381
1382         if (!(tmp & DP_PORT_EN))
1383                 return false;
1384
1385         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1386                 *pipe = PORT_TO_PIPE_CPT(tmp);
1387         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1388                 *pipe = PORT_TO_PIPE(tmp);
1389         } else {
1390                 u32 trans_sel;
1391                 u32 trans_dp;
1392                 int i;
1393
1394                 switch (intel_dp->output_reg) {
1395                 case PCH_DP_B:
1396                         trans_sel = TRANS_DP_PORT_SEL_B;
1397                         break;
1398                 case PCH_DP_C:
1399                         trans_sel = TRANS_DP_PORT_SEL_C;
1400                         break;
1401                 case PCH_DP_D:
1402                         trans_sel = TRANS_DP_PORT_SEL_D;
1403                         break;
1404                 default:
1405                         return true;
1406                 }
1407
1408                 for_each_pipe(i) {
1409                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1410                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1411                                 *pipe = i;
1412                                 return true;
1413                         }
1414                 }
1415
1416                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1417                               intel_dp->output_reg);
1418         }
1419
1420         return true;
1421 }
1422
1423 static void intel_dp_get_config(struct intel_encoder *encoder,
1424                                 struct intel_crtc_config *pipe_config)
1425 {
1426         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1427         u32 tmp, flags = 0;
1428         struct drm_device *dev = encoder->base.dev;
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         enum port port = dp_to_dig_port(intel_dp)->port;
1431         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1432         int dotclock;
1433
1434         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1435                 tmp = I915_READ(intel_dp->output_reg);
1436                 if (tmp & DP_SYNC_HS_HIGH)
1437                         flags |= DRM_MODE_FLAG_PHSYNC;
1438                 else
1439                         flags |= DRM_MODE_FLAG_NHSYNC;
1440
1441                 if (tmp & DP_SYNC_VS_HIGH)
1442                         flags |= DRM_MODE_FLAG_PVSYNC;
1443                 else
1444                         flags |= DRM_MODE_FLAG_NVSYNC;
1445         } else {
1446                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1447                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1448                         flags |= DRM_MODE_FLAG_PHSYNC;
1449                 else
1450                         flags |= DRM_MODE_FLAG_NHSYNC;
1451
1452                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1453                         flags |= DRM_MODE_FLAG_PVSYNC;
1454                 else
1455                         flags |= DRM_MODE_FLAG_NVSYNC;
1456         }
1457
1458         pipe_config->adjusted_mode.flags |= flags;
1459
1460         pipe_config->has_dp_encoder = true;
1461
1462         intel_dp_get_m_n(crtc, pipe_config);
1463
1464         if (port == PORT_A) {
1465                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1466                         pipe_config->port_clock = 162000;
1467                 else
1468                         pipe_config->port_clock = 270000;
1469         }
1470
1471         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1472             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1473                 /*
1474                  * This is a big fat ugly hack.
1475                  *
1476                  * Some machines in UEFI boot mode provide us a VBT that has 18
1477                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1478                  * unknown we fail to light up. Yet the same BIOS boots up with
1479                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1480                  * max, not what it tells us to use.
1481                  *
1482                  * Note: This will still be broken if the eDP panel is not lit
1483                  * up by the BIOS, and thus we can't get the mode at module
1484                  * load.
1485                  */
1486                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1487                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1488                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1489         }
1490
1491         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1492                                             &pipe_config->dp_m_n);
1493
1494         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1495                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1496
1497         pipe_config->adjusted_mode.crtc_clock = dotclock;
1498 }
1499
1500 static bool is_edp_psr(struct drm_device *dev)
1501 {
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503
1504         return dev_priv->psr.sink_support;
1505 }
1506
1507 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510
1511         if (!HAS_PSR(dev))
1512                 return false;
1513
1514         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1515 }
1516
1517 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1518                                     struct edp_vsc_psr *vsc_psr)
1519 {
1520         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1521         struct drm_device *dev = dig_port->base.base.dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1524         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1525         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1526         uint32_t *data = (uint32_t *) vsc_psr;
1527         unsigned int i;
1528
1529         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1530            the video DIP being updated before program video DIP data buffer
1531            registers for DIP being updated. */
1532         I915_WRITE(ctl_reg, 0);
1533         POSTING_READ(ctl_reg);
1534
1535         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1536                 if (i < sizeof(struct edp_vsc_psr))
1537                         I915_WRITE(data_reg + i, *data++);
1538                 else
1539                         I915_WRITE(data_reg + i, 0);
1540         }
1541
1542         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1543         POSTING_READ(ctl_reg);
1544 }
1545
1546 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1547 {
1548         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1549         struct drm_i915_private *dev_priv = dev->dev_private;
1550         struct edp_vsc_psr psr_vsc;
1551
1552         if (intel_dp->psr_setup_done)
1553                 return;
1554
1555         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1556         memset(&psr_vsc, 0, sizeof(psr_vsc));
1557         psr_vsc.sdp_header.HB0 = 0;
1558         psr_vsc.sdp_header.HB1 = 0x7;
1559         psr_vsc.sdp_header.HB2 = 0x2;
1560         psr_vsc.sdp_header.HB3 = 0x8;
1561         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1562
1563         /* Avoid continuous PSR exit by masking memup and hpd */
1564         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1565                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1566
1567         intel_dp->psr_setup_done = true;
1568 }
1569
1570 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1571 {
1572         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1575         int precharge = 0x3;
1576         int msg_size = 5;       /* Header(4) + Message(1) */
1577
1578         /* Enable PSR in sink */
1579         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1580                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1581                                             DP_PSR_ENABLE &
1582                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1583         else
1584                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1585                                             DP_PSR_ENABLE |
1586                                             DP_PSR_MAIN_LINK_ACTIVE);
1587
1588         /* Setup AUX registers */
1589         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1590         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1591         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1592                    DP_AUX_CH_CTL_TIME_OUT_400us |
1593                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1594                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1595                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1596 }
1597
1598 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1599 {
1600         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         uint32_t max_sleep_time = 0x1f;
1603         uint32_t idle_frames = 1;
1604         uint32_t val = 0x0;
1605
1606         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1607                 val |= EDP_PSR_LINK_STANDBY;
1608                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1609                 val |= EDP_PSR_TP1_TIME_0us;
1610                 val |= EDP_PSR_SKIP_AUX_EXIT;
1611         } else
1612                 val |= EDP_PSR_LINK_DISABLE;
1613
1614         I915_WRITE(EDP_PSR_CTL(dev), val |
1615                    EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1616                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1617                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1618                    EDP_PSR_ENABLE);
1619 }
1620
1621 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1622 {
1623         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1624         struct drm_device *dev = dig_port->base.base.dev;
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         struct drm_crtc *crtc = dig_port->base.base.crtc;
1627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1629         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1630
1631         dev_priv->psr.source_ok = false;
1632
1633         if (!HAS_PSR(dev)) {
1634                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1635                 return false;
1636         }
1637
1638         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1639             (dig_port->port != PORT_A)) {
1640                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1641                 return false;
1642         }
1643
1644         if (!i915_enable_psr) {
1645                 DRM_DEBUG_KMS("PSR disable by flag\n");
1646                 return false;
1647         }
1648
1649         crtc = dig_port->base.base.crtc;
1650         if (crtc == NULL) {
1651                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1652                 return false;
1653         }
1654
1655         intel_crtc = to_intel_crtc(crtc);
1656         if (!intel_crtc_active(crtc)) {
1657                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1658                 return false;
1659         }
1660
1661         obj = to_intel_framebuffer(crtc->fb)->obj;
1662         if (obj->tiling_mode != I915_TILING_X ||
1663             obj->fence_reg == I915_FENCE_REG_NONE) {
1664                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1665                 return false;
1666         }
1667
1668         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1669                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1670                 return false;
1671         }
1672
1673         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1674             S3D_ENABLE) {
1675                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1676                 return false;
1677         }
1678
1679         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1680                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1681                 return false;
1682         }
1683
1684         dev_priv->psr.source_ok = true;
1685         return true;
1686 }
1687
1688 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1689 {
1690         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1691
1692         if (!intel_edp_psr_match_conditions(intel_dp) ||
1693             intel_edp_is_psr_enabled(dev))
1694                 return;
1695
1696         /* Setup PSR once */
1697         intel_edp_psr_setup(intel_dp);
1698
1699         /* Enable PSR on the panel */
1700         intel_edp_psr_enable_sink(intel_dp);
1701
1702         /* Enable PSR on the host */
1703         intel_edp_psr_enable_source(intel_dp);
1704 }
1705
1706 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1707 {
1708         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709
1710         if (intel_edp_psr_match_conditions(intel_dp) &&
1711             !intel_edp_is_psr_enabled(dev))
1712                 intel_edp_psr_do_enable(intel_dp);
1713 }
1714
1715 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1716 {
1717         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719
1720         if (!intel_edp_is_psr_enabled(dev))
1721                 return;
1722
1723         I915_WRITE(EDP_PSR_CTL(dev),
1724                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1725
1726         /* Wait till PSR is idle */
1727         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1728                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1729                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1730 }
1731
1732 void intel_edp_psr_update(struct drm_device *dev)
1733 {
1734         struct intel_encoder *encoder;
1735         struct intel_dp *intel_dp = NULL;
1736
1737         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1738                 if (encoder->type == INTEL_OUTPUT_EDP) {
1739                         intel_dp = enc_to_intel_dp(&encoder->base);
1740
1741                         if (!is_edp_psr(dev))
1742                                 return;
1743
1744                         if (!intel_edp_psr_match_conditions(intel_dp))
1745                                 intel_edp_psr_disable(intel_dp);
1746                         else
1747                                 if (!intel_edp_is_psr_enabled(dev))
1748                                         intel_edp_psr_do_enable(intel_dp);
1749                 }
1750 }
1751
1752 static void intel_disable_dp(struct intel_encoder *encoder)
1753 {
1754         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1755         enum port port = dp_to_dig_port(intel_dp)->port;
1756         struct drm_device *dev = encoder->base.dev;
1757
1758         /* Make sure the panel is off before trying to change the mode. But also
1759          * ensure that we have vdd while we switch off the panel. */
1760         ironlake_edp_panel_vdd_on(intel_dp);
1761         ironlake_edp_backlight_off(intel_dp);
1762         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1763         ironlake_edp_panel_off(intel_dp);
1764
1765         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1766         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1767                 intel_dp_link_down(intel_dp);
1768 }
1769
1770 static void intel_post_disable_dp(struct intel_encoder *encoder)
1771 {
1772         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1773         enum port port = dp_to_dig_port(intel_dp)->port;
1774         struct drm_device *dev = encoder->base.dev;
1775
1776         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1777                 intel_dp_link_down(intel_dp);
1778                 if (!IS_VALLEYVIEW(dev))
1779                         ironlake_edp_pll_off(intel_dp);
1780         }
1781 }
1782
1783 static void intel_enable_dp(struct intel_encoder *encoder)
1784 {
1785         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1786         struct drm_device *dev = encoder->base.dev;
1787         struct drm_i915_private *dev_priv = dev->dev_private;
1788         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1789
1790         if (WARN_ON(dp_reg & DP_PORT_EN))
1791                 return;
1792
1793         ironlake_edp_panel_vdd_on(intel_dp);
1794         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1795         intel_dp_start_link_train(intel_dp);
1796         ironlake_edp_panel_on(intel_dp);
1797         ironlake_edp_panel_vdd_off(intel_dp, true);
1798         intel_dp_complete_link_train(intel_dp);
1799         intel_dp_stop_link_train(intel_dp);
1800 }
1801
1802 static void g4x_enable_dp(struct intel_encoder *encoder)
1803 {
1804         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1805
1806         intel_enable_dp(encoder);
1807         ironlake_edp_backlight_on(intel_dp);
1808 }
1809
1810 static void vlv_enable_dp(struct intel_encoder *encoder)
1811 {
1812         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1813
1814         ironlake_edp_backlight_on(intel_dp);
1815 }
1816
1817 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1818 {
1819         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1820         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1821
1822         if (dport->port == PORT_A)
1823                 ironlake_edp_pll_on(intel_dp);
1824 }
1825
1826 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1827 {
1828         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1830         struct drm_device *dev = encoder->base.dev;
1831         struct drm_i915_private *dev_priv = dev->dev_private;
1832         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1833         int port = vlv_dport_to_channel(dport);
1834         int pipe = intel_crtc->pipe;
1835         struct edp_power_seq power_seq;
1836         u32 val;
1837
1838         mutex_lock(&dev_priv->dpio_lock);
1839
1840         val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1841         val = 0;
1842         if (pipe)
1843                 val |= (1<<21);
1844         else
1845                 val &= ~(1<<21);
1846         val |= 0x001000c4;
1847         vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1848         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1849         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1850
1851         mutex_unlock(&dev_priv->dpio_lock);
1852
1853         /* init power sequencer on this pipe and port */
1854         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1855         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1856                                                       &power_seq);
1857
1858         intel_enable_dp(encoder);
1859
1860         vlv_wait_port_ready(dev_priv, port);
1861 }
1862
1863 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1864 {
1865         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1866         struct drm_device *dev = encoder->base.dev;
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         struct intel_crtc *intel_crtc =
1869                 to_intel_crtc(encoder->base.crtc);
1870         int port = vlv_dport_to_channel(dport);
1871         int pipe = intel_crtc->pipe;
1872
1873         /* Program Tx lane resets to default */
1874         mutex_lock(&dev_priv->dpio_lock);
1875         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1876                          DPIO_PCS_TX_LANE2_RESET |
1877                          DPIO_PCS_TX_LANE1_RESET);
1878         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1879                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1880                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1881                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1882                                  DPIO_PCS_CLK_SOFT_RESET);
1883
1884         /* Fix up inter-pair skew failure */
1885         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1886         vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1887         vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1888         mutex_unlock(&dev_priv->dpio_lock);
1889 }
1890
1891 /*
1892  * Native read with retry for link status and receiver capability reads for
1893  * cases where the sink may still be asleep.
1894  */
1895 static bool
1896 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1897                                uint8_t *recv, int recv_bytes)
1898 {
1899         int ret, i;
1900
1901         /*
1902          * Sinks are *supposed* to come up within 1ms from an off state,
1903          * but we're also supposed to retry 3 times per the spec.
1904          */
1905         for (i = 0; i < 3; i++) {
1906                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1907                                                recv_bytes);
1908                 if (ret == recv_bytes)
1909                         return true;
1910                 msleep(1);
1911         }
1912
1913         return false;
1914 }
1915
1916 /*
1917  * Fetch AUX CH registers 0x202 - 0x207 which contain
1918  * link status information
1919  */
1920 static bool
1921 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1922 {
1923         return intel_dp_aux_native_read_retry(intel_dp,
1924                                               DP_LANE0_1_STATUS,
1925                                               link_status,
1926                                               DP_LINK_STATUS_SIZE);
1927 }
1928
1929 #if 0
1930 static char     *voltage_names[] = {
1931         "0.4V", "0.6V", "0.8V", "1.2V"
1932 };
1933 static char     *pre_emph_names[] = {
1934         "0dB", "3.5dB", "6dB", "9.5dB"
1935 };
1936 static char     *link_train_names[] = {
1937         "pattern 1", "pattern 2", "idle", "off"
1938 };
1939 #endif
1940
1941 /*
1942  * These are source-specific values; current Intel hardware supports
1943  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1944  */
1945
1946 static uint8_t
1947 intel_dp_voltage_max(struct intel_dp *intel_dp)
1948 {
1949         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1950         enum port port = dp_to_dig_port(intel_dp)->port;
1951
1952         if (IS_VALLEYVIEW(dev))
1953                 return DP_TRAIN_VOLTAGE_SWING_1200;
1954         else if (IS_GEN7(dev) && port == PORT_A)
1955                 return DP_TRAIN_VOLTAGE_SWING_800;
1956         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1957                 return DP_TRAIN_VOLTAGE_SWING_1200;
1958         else
1959                 return DP_TRAIN_VOLTAGE_SWING_800;
1960 }
1961
1962 static uint8_t
1963 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1964 {
1965         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1966         enum port port = dp_to_dig_port(intel_dp)->port;
1967
1968         if (HAS_DDI(dev)) {
1969                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1970                 case DP_TRAIN_VOLTAGE_SWING_400:
1971                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1972                 case DP_TRAIN_VOLTAGE_SWING_600:
1973                         return DP_TRAIN_PRE_EMPHASIS_6;
1974                 case DP_TRAIN_VOLTAGE_SWING_800:
1975                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1976                 case DP_TRAIN_VOLTAGE_SWING_1200:
1977                 default:
1978                         return DP_TRAIN_PRE_EMPHASIS_0;
1979                 }
1980         } else if (IS_VALLEYVIEW(dev)) {
1981                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1982                 case DP_TRAIN_VOLTAGE_SWING_400:
1983                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1984                 case DP_TRAIN_VOLTAGE_SWING_600:
1985                         return DP_TRAIN_PRE_EMPHASIS_6;
1986                 case DP_TRAIN_VOLTAGE_SWING_800:
1987                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1988                 case DP_TRAIN_VOLTAGE_SWING_1200:
1989                 default:
1990                         return DP_TRAIN_PRE_EMPHASIS_0;
1991                 }
1992         } else if (IS_GEN7(dev) && port == PORT_A) {
1993                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1994                 case DP_TRAIN_VOLTAGE_SWING_400:
1995                         return DP_TRAIN_PRE_EMPHASIS_6;
1996                 case DP_TRAIN_VOLTAGE_SWING_600:
1997                 case DP_TRAIN_VOLTAGE_SWING_800:
1998                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1999                 default:
2000                         return DP_TRAIN_PRE_EMPHASIS_0;
2001                 }
2002         } else {
2003                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2004                 case DP_TRAIN_VOLTAGE_SWING_400:
2005                         return DP_TRAIN_PRE_EMPHASIS_6;
2006                 case DP_TRAIN_VOLTAGE_SWING_600:
2007                         return DP_TRAIN_PRE_EMPHASIS_6;
2008                 case DP_TRAIN_VOLTAGE_SWING_800:
2009                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2010                 case DP_TRAIN_VOLTAGE_SWING_1200:
2011                 default:
2012                         return DP_TRAIN_PRE_EMPHASIS_0;
2013                 }
2014         }
2015 }
2016
2017 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2018 {
2019         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2022         struct intel_crtc *intel_crtc =
2023                 to_intel_crtc(dport->base.base.crtc);
2024         unsigned long demph_reg_value, preemph_reg_value,
2025                 uniqtranscale_reg_value;
2026         uint8_t train_set = intel_dp->train_set[0];
2027         int port = vlv_dport_to_channel(dport);
2028         int pipe = intel_crtc->pipe;
2029
2030         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2031         case DP_TRAIN_PRE_EMPHASIS_0:
2032                 preemph_reg_value = 0x0004000;
2033                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2034                 case DP_TRAIN_VOLTAGE_SWING_400:
2035                         demph_reg_value = 0x2B405555;
2036                         uniqtranscale_reg_value = 0x552AB83A;
2037                         break;
2038                 case DP_TRAIN_VOLTAGE_SWING_600:
2039                         demph_reg_value = 0x2B404040;
2040                         uniqtranscale_reg_value = 0x5548B83A;
2041                         break;
2042                 case DP_TRAIN_VOLTAGE_SWING_800:
2043                         demph_reg_value = 0x2B245555;
2044                         uniqtranscale_reg_value = 0x5560B83A;
2045                         break;
2046                 case DP_TRAIN_VOLTAGE_SWING_1200:
2047                         demph_reg_value = 0x2B405555;
2048                         uniqtranscale_reg_value = 0x5598DA3A;
2049                         break;
2050                 default:
2051                         return 0;
2052                 }
2053                 break;
2054         case DP_TRAIN_PRE_EMPHASIS_3_5:
2055                 preemph_reg_value = 0x0002000;
2056                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2057                 case DP_TRAIN_VOLTAGE_SWING_400:
2058                         demph_reg_value = 0x2B404040;
2059                         uniqtranscale_reg_value = 0x5552B83A;
2060                         break;
2061                 case DP_TRAIN_VOLTAGE_SWING_600:
2062                         demph_reg_value = 0x2B404848;
2063                         uniqtranscale_reg_value = 0x5580B83A;
2064                         break;
2065                 case DP_TRAIN_VOLTAGE_SWING_800:
2066                         demph_reg_value = 0x2B404040;
2067                         uniqtranscale_reg_value = 0x55ADDA3A;
2068                         break;
2069                 default:
2070                         return 0;
2071                 }
2072                 break;
2073         case DP_TRAIN_PRE_EMPHASIS_6:
2074                 preemph_reg_value = 0x0000000;
2075                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2076                 case DP_TRAIN_VOLTAGE_SWING_400:
2077                         demph_reg_value = 0x2B305555;
2078                         uniqtranscale_reg_value = 0x5570B83A;
2079                         break;
2080                 case DP_TRAIN_VOLTAGE_SWING_600:
2081                         demph_reg_value = 0x2B2B4040;
2082                         uniqtranscale_reg_value = 0x55ADDA3A;
2083                         break;
2084                 default:
2085                         return 0;
2086                 }
2087                 break;
2088         case DP_TRAIN_PRE_EMPHASIS_9_5:
2089                 preemph_reg_value = 0x0006000;
2090                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2091                 case DP_TRAIN_VOLTAGE_SWING_400:
2092                         demph_reg_value = 0x1B405555;
2093                         uniqtranscale_reg_value = 0x55ADDA3A;
2094                         break;
2095                 default:
2096                         return 0;
2097                 }
2098                 break;
2099         default:
2100                 return 0;
2101         }
2102
2103         mutex_lock(&dev_priv->dpio_lock);
2104         vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2105         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2106         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
2107                          uniqtranscale_reg_value);
2108         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2109         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2110         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2111         vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
2112         mutex_unlock(&dev_priv->dpio_lock);
2113
2114         return 0;
2115 }
2116
2117 static void
2118 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2119 {
2120         uint8_t v = 0;
2121         uint8_t p = 0;
2122         int lane;
2123         uint8_t voltage_max;
2124         uint8_t preemph_max;
2125
2126         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2127                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2128                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2129
2130                 if (this_v > v)
2131                         v = this_v;
2132                 if (this_p > p)
2133                         p = this_p;
2134         }
2135
2136         voltage_max = intel_dp_voltage_max(intel_dp);
2137         if (v >= voltage_max)
2138                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2139
2140         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2141         if (p >= preemph_max)
2142                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2143
2144         for (lane = 0; lane < 4; lane++)
2145                 intel_dp->train_set[lane] = v | p;
2146 }
2147
2148 static uint32_t
2149 intel_gen4_signal_levels(uint8_t train_set)
2150 {
2151         uint32_t        signal_levels = 0;
2152
2153         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2154         case DP_TRAIN_VOLTAGE_SWING_400:
2155         default:
2156                 signal_levels |= DP_VOLTAGE_0_4;
2157                 break;
2158         case DP_TRAIN_VOLTAGE_SWING_600:
2159                 signal_levels |= DP_VOLTAGE_0_6;
2160                 break;
2161         case DP_TRAIN_VOLTAGE_SWING_800:
2162                 signal_levels |= DP_VOLTAGE_0_8;
2163                 break;
2164         case DP_TRAIN_VOLTAGE_SWING_1200:
2165                 signal_levels |= DP_VOLTAGE_1_2;
2166                 break;
2167         }
2168         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2169         case DP_TRAIN_PRE_EMPHASIS_0:
2170         default:
2171                 signal_levels |= DP_PRE_EMPHASIS_0;
2172                 break;
2173         case DP_TRAIN_PRE_EMPHASIS_3_5:
2174                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2175                 break;
2176         case DP_TRAIN_PRE_EMPHASIS_6:
2177                 signal_levels |= DP_PRE_EMPHASIS_6;
2178                 break;
2179         case DP_TRAIN_PRE_EMPHASIS_9_5:
2180                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2181                 break;
2182         }
2183         return signal_levels;
2184 }
2185
2186 /* Gen6's DP voltage swing and pre-emphasis control */
2187 static uint32_t
2188 intel_gen6_edp_signal_levels(uint8_t train_set)
2189 {
2190         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2191                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2192         switch (signal_levels) {
2193         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2194         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2195                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2196         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2197                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2198         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2199         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2200                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2201         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2202         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2203                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2204         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2205         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2206                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2207         default:
2208                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2209                               "0x%x\n", signal_levels);
2210                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2211         }
2212 }
2213
2214 /* Gen7's DP voltage swing and pre-emphasis control */
2215 static uint32_t
2216 intel_gen7_edp_signal_levels(uint8_t train_set)
2217 {
2218         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2219                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2220         switch (signal_levels) {
2221         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2222                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2223         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2224                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2225         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2226                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2227
2228         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2229                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2230         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2231                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2232
2233         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2234                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2235         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2236                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2237
2238         default:
2239                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2240                               "0x%x\n", signal_levels);
2241                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2242         }
2243 }
2244
2245 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2246 static uint32_t
2247 intel_hsw_signal_levels(uint8_t train_set)
2248 {
2249         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2250                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2251         switch (signal_levels) {
2252         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2253                 return DDI_BUF_EMP_400MV_0DB_HSW;
2254         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2256         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2257                 return DDI_BUF_EMP_400MV_6DB_HSW;
2258         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2259                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2260
2261         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2262                 return DDI_BUF_EMP_600MV_0DB_HSW;
2263         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2264                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2265         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2266                 return DDI_BUF_EMP_600MV_6DB_HSW;
2267
2268         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2269                 return DDI_BUF_EMP_800MV_0DB_HSW;
2270         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2271                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2272         default:
2273                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2274                               "0x%x\n", signal_levels);
2275                 return DDI_BUF_EMP_400MV_0DB_HSW;
2276         }
2277 }
2278
2279 /* Properly updates "DP" with the correct signal levels. */
2280 static void
2281 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2282 {
2283         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2284         enum port port = intel_dig_port->port;
2285         struct drm_device *dev = intel_dig_port->base.base.dev;
2286         uint32_t signal_levels, mask;
2287         uint8_t train_set = intel_dp->train_set[0];
2288
2289         if (HAS_DDI(dev)) {
2290                 signal_levels = intel_hsw_signal_levels(train_set);
2291                 mask = DDI_BUF_EMP_MASK;
2292         } else if (IS_VALLEYVIEW(dev)) {
2293                 signal_levels = intel_vlv_signal_levels(intel_dp);
2294                 mask = 0;
2295         } else if (IS_GEN7(dev) && port == PORT_A) {
2296                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2297                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2298         } else if (IS_GEN6(dev) && port == PORT_A) {
2299                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2300                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2301         } else {
2302                 signal_levels = intel_gen4_signal_levels(train_set);
2303                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2304         }
2305
2306         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2307
2308         *DP = (*DP & ~mask) | signal_levels;
2309 }
2310
2311 static bool
2312 intel_dp_set_link_train(struct intel_dp *intel_dp,
2313                         uint32_t *DP,
2314                         uint8_t dp_train_pat)
2315 {
2316         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2317         struct drm_device *dev = intel_dig_port->base.base.dev;
2318         struct drm_i915_private *dev_priv = dev->dev_private;
2319         enum port port = intel_dig_port->port;
2320         int ret;
2321
2322         if (HAS_DDI(dev)) {
2323                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2324
2325                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2326                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2327                 else
2328                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2329
2330                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2331                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2332                 case DP_TRAINING_PATTERN_DISABLE:
2333                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2334
2335                         break;
2336                 case DP_TRAINING_PATTERN_1:
2337                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2338                         break;
2339                 case DP_TRAINING_PATTERN_2:
2340                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2341                         break;
2342                 case DP_TRAINING_PATTERN_3:
2343                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2344                         break;
2345                 }
2346                 I915_WRITE(DP_TP_CTL(port), temp);
2347
2348         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2349                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2350
2351                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2352                 case DP_TRAINING_PATTERN_DISABLE:
2353                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2354                         break;
2355                 case DP_TRAINING_PATTERN_1:
2356                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2357                         break;
2358                 case DP_TRAINING_PATTERN_2:
2359                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2360                         break;
2361                 case DP_TRAINING_PATTERN_3:
2362                         DRM_ERROR("DP training pattern 3 not supported\n");
2363                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2364                         break;
2365                 }
2366
2367         } else {
2368                 *DP &= ~DP_LINK_TRAIN_MASK;
2369
2370                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2371                 case DP_TRAINING_PATTERN_DISABLE:
2372                         *DP |= DP_LINK_TRAIN_OFF;
2373                         break;
2374                 case DP_TRAINING_PATTERN_1:
2375                         *DP |= DP_LINK_TRAIN_PAT_1;
2376                         break;
2377                 case DP_TRAINING_PATTERN_2:
2378                         *DP |= DP_LINK_TRAIN_PAT_2;
2379                         break;
2380                 case DP_TRAINING_PATTERN_3:
2381                         DRM_ERROR("DP training pattern 3 not supported\n");
2382                         *DP |= DP_LINK_TRAIN_PAT_2;
2383                         break;
2384                 }
2385         }
2386
2387         I915_WRITE(intel_dp->output_reg, *DP);
2388         POSTING_READ(intel_dp->output_reg);
2389
2390         ret = intel_dp_aux_native_write_1(intel_dp, DP_TRAINING_PATTERN_SET,
2391                                           dp_train_pat);
2392         if (ret != 1)
2393                 return false;
2394
2395         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2396             DP_TRAINING_PATTERN_DISABLE) {
2397                 ret = intel_dp_aux_native_write(intel_dp,
2398                                                 DP_TRAINING_LANE0_SET,
2399                                                 intel_dp->train_set,
2400                                                 intel_dp->lane_count);
2401                 if (ret != intel_dp->lane_count)
2402                         return false;
2403         }
2404
2405         return true;
2406 }
2407
2408 static bool
2409 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2410                         uint8_t dp_train_pat)
2411 {
2412         memset(intel_dp->train_set, 0, 4);
2413         intel_dp_set_signal_levels(intel_dp, DP);
2414         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2415 }
2416
2417 static bool
2418 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2419                            uint8_t link_status[DP_LINK_STATUS_SIZE])
2420 {
2421         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2422         struct drm_device *dev = intel_dig_port->base.base.dev;
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         int ret;
2425
2426         intel_get_adjust_train(intel_dp, link_status);
2427         intel_dp_set_signal_levels(intel_dp, DP);
2428
2429         I915_WRITE(intel_dp->output_reg, *DP);
2430         POSTING_READ(intel_dp->output_reg);
2431
2432         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2433                                         intel_dp->train_set,
2434                                         intel_dp->lane_count);
2435
2436         return ret == intel_dp->lane_count;
2437 }
2438
2439 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2440 {
2441         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2442         struct drm_device *dev = intel_dig_port->base.base.dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         enum port port = intel_dig_port->port;
2445         uint32_t val;
2446
2447         if (!HAS_DDI(dev))
2448                 return;
2449
2450         val = I915_READ(DP_TP_CTL(port));
2451         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2452         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2453         I915_WRITE(DP_TP_CTL(port), val);
2454
2455         /*
2456          * On PORT_A we can have only eDP in SST mode. There the only reason
2457          * we need to set idle transmission mode is to work around a HW issue
2458          * where we enable the pipe while not in idle link-training mode.
2459          * In this case there is requirement to wait for a minimum number of
2460          * idle patterns to be sent.
2461          */
2462         if (port == PORT_A)
2463                 return;
2464
2465         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2466                      1))
2467                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2468 }
2469
2470 /* Enable corresponding port and start training pattern 1 */
2471 void
2472 intel_dp_start_link_train(struct intel_dp *intel_dp)
2473 {
2474         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2475         struct drm_device *dev = encoder->dev;
2476         int i;
2477         uint8_t voltage;
2478         int voltage_tries, loop_tries;
2479         uint32_t DP = intel_dp->DP;
2480         uint8_t link_config[2];
2481
2482         if (HAS_DDI(dev))
2483                 intel_ddi_prepare_link_retrain(encoder);
2484
2485         /* Write the link configuration data */
2486         link_config[0] = intel_dp->link_bw;
2487         link_config[1] = intel_dp->lane_count;
2488         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2489                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2490         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2491
2492         link_config[0] = 0;
2493         link_config[1] = DP_SET_ANSI_8B10B;
2494         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2495
2496         DP |= DP_PORT_EN;
2497
2498         /* clock recovery */
2499         if (!intel_dp_reset_link_train(intel_dp, &DP,
2500                                        DP_TRAINING_PATTERN_1 |
2501                                        DP_LINK_SCRAMBLING_DISABLE)) {
2502                 DRM_ERROR("failed to enable link training\n");
2503                 return;
2504         }
2505
2506         voltage = 0xff;
2507         voltage_tries = 0;
2508         loop_tries = 0;
2509         for (;;) {
2510                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2511
2512                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2513                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2514                         DRM_ERROR("failed to get link status\n");
2515                         break;
2516                 }
2517
2518                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2519                         DRM_DEBUG_KMS("clock recovery OK\n");
2520                         break;
2521                 }
2522
2523                 /* Check to see if we've tried the max voltage */
2524                 for (i = 0; i < intel_dp->lane_count; i++)
2525                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2526                                 break;
2527                 if (i == intel_dp->lane_count) {
2528                         ++loop_tries;
2529                         if (loop_tries == 5) {
2530                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2531                                 break;
2532                         }
2533                         intel_dp_reset_link_train(intel_dp, &DP,
2534                                                   DP_TRAINING_PATTERN_1 |
2535                                                   DP_LINK_SCRAMBLING_DISABLE);
2536                         voltage_tries = 0;
2537                         continue;
2538                 }
2539
2540                 /* Check to see if we've tried the same voltage 5 times */
2541                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2542                         ++voltage_tries;
2543                         if (voltage_tries == 5) {
2544                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2545                                 break;
2546                         }
2547                 } else
2548                         voltage_tries = 0;
2549                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2550
2551                 /* Update training set as requested by target */
2552                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2553                         DRM_ERROR("failed to update link training\n");
2554                         break;
2555                 }
2556         }
2557
2558         intel_dp->DP = DP;
2559 }
2560
2561 void
2562 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2563 {
2564         bool channel_eq = false;
2565         int tries, cr_tries;
2566         uint32_t DP = intel_dp->DP;
2567
2568         /* channel equalization */
2569         if (!intel_dp_set_link_train(intel_dp, &DP,
2570                                      DP_TRAINING_PATTERN_2 |
2571                                      DP_LINK_SCRAMBLING_DISABLE)) {
2572                 DRM_ERROR("failed to start channel equalization\n");
2573                 return;
2574         }
2575
2576         tries = 0;
2577         cr_tries = 0;
2578         channel_eq = false;
2579         for (;;) {
2580                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2581
2582                 if (cr_tries > 5) {
2583                         DRM_ERROR("failed to train DP, aborting\n");
2584                         intel_dp_link_down(intel_dp);
2585                         break;
2586                 }
2587
2588                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2589                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2590                         DRM_ERROR("failed to get link status\n");
2591                         break;
2592                 }
2593
2594                 /* Make sure clock is still ok */
2595                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2596                         intel_dp_start_link_train(intel_dp);
2597                         intel_dp_set_link_train(intel_dp, &DP,
2598                                                 DP_TRAINING_PATTERN_2 |
2599                                                 DP_LINK_SCRAMBLING_DISABLE);
2600                         cr_tries++;
2601                         continue;
2602                 }
2603
2604                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2605                         channel_eq = true;
2606                         break;
2607                 }
2608
2609                 /* Try 5 times, then try clock recovery if that fails */
2610                 if (tries > 5) {
2611                         intel_dp_link_down(intel_dp);
2612                         intel_dp_start_link_train(intel_dp);
2613                         intel_dp_set_link_train(intel_dp, &DP,
2614                                                 DP_TRAINING_PATTERN_2 |
2615                                                 DP_LINK_SCRAMBLING_DISABLE);
2616                         tries = 0;
2617                         cr_tries++;
2618                         continue;
2619                 }
2620
2621                 /* Update training set as requested by target */
2622                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2623                         DRM_ERROR("failed to update link training\n");
2624                         break;
2625                 }
2626                 ++tries;
2627         }
2628
2629         intel_dp_set_idle_link_train(intel_dp);
2630
2631         intel_dp->DP = DP;
2632
2633         if (channel_eq)
2634                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2635
2636 }
2637
2638 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2639 {
2640         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2641                                 DP_TRAINING_PATTERN_DISABLE);
2642 }
2643
2644 static void
2645 intel_dp_link_down(struct intel_dp *intel_dp)
2646 {
2647         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2648         enum port port = intel_dig_port->port;
2649         struct drm_device *dev = intel_dig_port->base.base.dev;
2650         struct drm_i915_private *dev_priv = dev->dev_private;
2651         struct intel_crtc *intel_crtc =
2652                 to_intel_crtc(intel_dig_port->base.base.crtc);
2653         uint32_t DP = intel_dp->DP;
2654
2655         /*
2656          * DDI code has a strict mode set sequence and we should try to respect
2657          * it, otherwise we might hang the machine in many different ways. So we
2658          * really should be disabling the port only on a complete crtc_disable
2659          * sequence. This function is just called under two conditions on DDI
2660          * code:
2661          * - Link train failed while doing crtc_enable, and on this case we
2662          *   really should respect the mode set sequence and wait for a
2663          *   crtc_disable.
2664          * - Someone turned the monitor off and intel_dp_check_link_status
2665          *   called us. We don't need to disable the whole port on this case, so
2666          *   when someone turns the monitor on again,
2667          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2668          *   train.
2669          */
2670         if (HAS_DDI(dev))
2671                 return;
2672
2673         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2674                 return;
2675
2676         DRM_DEBUG_KMS("\n");
2677
2678         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2679                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2680                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2681         } else {
2682                 DP &= ~DP_LINK_TRAIN_MASK;
2683                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2684         }
2685         POSTING_READ(intel_dp->output_reg);
2686
2687         /* We don't really know why we're doing this */
2688         intel_wait_for_vblank(dev, intel_crtc->pipe);
2689
2690         if (HAS_PCH_IBX(dev) &&
2691             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2692                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2693
2694                 /* Hardware workaround: leaving our transcoder select
2695                  * set to transcoder B while it's off will prevent the
2696                  * corresponding HDMI output on transcoder A.
2697                  *
2698                  * Combine this with another hardware workaround:
2699                  * transcoder select bit can only be cleared while the
2700                  * port is enabled.
2701                  */
2702                 DP &= ~DP_PIPEB_SELECT;
2703                 I915_WRITE(intel_dp->output_reg, DP);
2704
2705                 /* Changes to enable or select take place the vblank
2706                  * after being written.
2707                  */
2708                 if (WARN_ON(crtc == NULL)) {
2709                         /* We should never try to disable a port without a crtc
2710                          * attached. For paranoia keep the code around for a
2711                          * bit. */
2712                         POSTING_READ(intel_dp->output_reg);
2713                         msleep(50);
2714                 } else
2715                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2716         }
2717
2718         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2719         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2720         POSTING_READ(intel_dp->output_reg);
2721         msleep(intel_dp->panel_power_down_delay);
2722 }
2723
2724 static bool
2725 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2726 {
2727         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2728         struct drm_device *dev = dig_port->base.base.dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730
2731         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2732
2733         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2734                                            sizeof(intel_dp->dpcd)) == 0)
2735                 return false; /* aux transfer failed */
2736
2737         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2738                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2739         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2740
2741         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2742                 return false; /* DPCD not present */
2743
2744         /* Check if the panel supports PSR */
2745         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2746         if (is_edp(intel_dp)) {
2747                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2748                                                intel_dp->psr_dpcd,
2749                                                sizeof(intel_dp->psr_dpcd));
2750                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2751                         dev_priv->psr.sink_support = true;
2752                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2753                 }
2754         }
2755
2756         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2757               DP_DWN_STRM_PORT_PRESENT))
2758                 return true; /* native DP sink */
2759
2760         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2761                 return true; /* no per-port downstream info */
2762
2763         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2764                                            intel_dp->downstream_ports,
2765                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2766                 return false; /* downstream port status fetch failed */
2767
2768         return true;
2769 }
2770
2771 static void
2772 intel_dp_probe_oui(struct intel_dp *intel_dp)
2773 {
2774         u8 buf[3];
2775
2776         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2777                 return;
2778
2779         ironlake_edp_panel_vdd_on(intel_dp);
2780
2781         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2782                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2783                               buf[0], buf[1], buf[2]);
2784
2785         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2786                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2787                               buf[0], buf[1], buf[2]);
2788
2789         ironlake_edp_panel_vdd_off(intel_dp, false);
2790 }
2791
2792 static bool
2793 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2794 {
2795         int ret;
2796
2797         ret = intel_dp_aux_native_read_retry(intel_dp,
2798                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2799                                              sink_irq_vector, 1);
2800         if (!ret)
2801                 return false;
2802
2803         return true;
2804 }
2805
2806 static void
2807 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2808 {
2809         /* NAK by default */
2810         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2811 }
2812
2813 /*
2814  * According to DP spec
2815  * 5.1.2:
2816  *  1. Read DPCD
2817  *  2. Configure link according to Receiver Capabilities
2818  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2819  *  4. Check link status on receipt of hot-plug interrupt
2820  */
2821
2822 void
2823 intel_dp_check_link_status(struct intel_dp *intel_dp)
2824 {
2825         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2826         u8 sink_irq_vector;
2827         u8 link_status[DP_LINK_STATUS_SIZE];
2828
2829         if (!intel_encoder->connectors_active)
2830                 return;
2831
2832         if (WARN_ON(!intel_encoder->base.crtc))
2833                 return;
2834
2835         /* Try to read receiver status if the link appears to be up */
2836         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2837                 intel_dp_link_down(intel_dp);
2838                 return;
2839         }
2840
2841         /* Now read the DPCD to see if it's actually running */
2842         if (!intel_dp_get_dpcd(intel_dp)) {
2843                 intel_dp_link_down(intel_dp);
2844                 return;
2845         }
2846
2847         /* Try to read the source of the interrupt */
2848         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2849             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2850                 /* Clear interrupt source */
2851                 intel_dp_aux_native_write_1(intel_dp,
2852                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2853                                             sink_irq_vector);
2854
2855                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2856                         intel_dp_handle_test_request(intel_dp);
2857                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2858                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2859         }
2860
2861         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2862                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2863                               drm_get_encoder_name(&intel_encoder->base));
2864                 intel_dp_start_link_train(intel_dp);
2865                 intel_dp_complete_link_train(intel_dp);
2866                 intel_dp_stop_link_train(intel_dp);
2867         }
2868 }
2869
2870 /* XXX this is probably wrong for multiple downstream ports */
2871 static enum drm_connector_status
2872 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2873 {
2874         uint8_t *dpcd = intel_dp->dpcd;
2875         uint8_t type;
2876
2877         if (!intel_dp_get_dpcd(intel_dp))
2878                 return connector_status_disconnected;
2879
2880         /* if there's no downstream port, we're done */
2881         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2882                 return connector_status_connected;
2883
2884         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2885         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2886             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2887                 uint8_t reg;
2888                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2889                                                     &reg, 1))
2890                         return connector_status_unknown;
2891                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2892                                               : connector_status_disconnected;
2893         }
2894
2895         /* If no HPD, poke DDC gently */
2896         if (drm_probe_ddc(&intel_dp->adapter))
2897                 return connector_status_connected;
2898
2899         /* Well we tried, say unknown for unreliable port types */
2900         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2901                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2902                 if (type == DP_DS_PORT_TYPE_VGA ||
2903                     type == DP_DS_PORT_TYPE_NON_EDID)
2904                         return connector_status_unknown;
2905         } else {
2906                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2907                         DP_DWN_STRM_PORT_TYPE_MASK;
2908                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2909                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2910                         return connector_status_unknown;
2911         }
2912
2913         /* Anything else is out of spec, warn and ignore */
2914         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2915         return connector_status_disconnected;
2916 }
2917
2918 static enum drm_connector_status
2919 ironlake_dp_detect(struct intel_dp *intel_dp)
2920 {
2921         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2922         struct drm_i915_private *dev_priv = dev->dev_private;
2923         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2924         enum drm_connector_status status;
2925
2926         /* Can't disconnect eDP, but you can close the lid... */
2927         if (is_edp(intel_dp)) {
2928                 status = intel_panel_detect(dev);
2929                 if (status == connector_status_unknown)
2930                         status = connector_status_connected;
2931                 return status;
2932         }
2933
2934         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2935                 return connector_status_disconnected;
2936
2937         return intel_dp_detect_dpcd(intel_dp);
2938 }
2939
2940 static enum drm_connector_status
2941 g4x_dp_detect(struct intel_dp *intel_dp)
2942 {
2943         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2946         uint32_t bit;
2947
2948         /* Can't disconnect eDP, but you can close the lid... */
2949         if (is_edp(intel_dp)) {
2950                 enum drm_connector_status status;
2951
2952                 status = intel_panel_detect(dev);
2953                 if (status == connector_status_unknown)
2954                         status = connector_status_connected;
2955                 return status;
2956         }
2957
2958         switch (intel_dig_port->port) {
2959         case PORT_B:
2960                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2961                 break;
2962         case PORT_C:
2963                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2964                 break;
2965         case PORT_D:
2966                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2967                 break;
2968         default:
2969                 return connector_status_unknown;
2970         }
2971
2972         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2973                 return connector_status_disconnected;
2974
2975         return intel_dp_detect_dpcd(intel_dp);
2976 }
2977
2978 static struct edid *
2979 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2980 {
2981         struct intel_connector *intel_connector = to_intel_connector(connector);
2982
2983         /* use cached edid if we have one */
2984         if (intel_connector->edid) {
2985                 /* invalid edid */
2986                 if (IS_ERR(intel_connector->edid))
2987                         return NULL;
2988
2989                 return drm_edid_duplicate(intel_connector->edid);
2990         }
2991
2992         return drm_get_edid(connector, adapter);
2993 }
2994
2995 static int
2996 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2997 {
2998         struct intel_connector *intel_connector = to_intel_connector(connector);
2999
3000         /* use cached edid if we have one */
3001         if (intel_connector->edid) {
3002                 /* invalid edid */
3003                 if (IS_ERR(intel_connector->edid))
3004                         return 0;
3005
3006                 return intel_connector_update_modes(connector,
3007                                                     intel_connector->edid);
3008         }
3009
3010         return intel_ddc_get_modes(connector, adapter);
3011 }
3012
3013 static enum drm_connector_status
3014 intel_dp_detect(struct drm_connector *connector, bool force)
3015 {
3016         struct intel_dp *intel_dp = intel_attached_dp(connector);
3017         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3018         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3019         struct drm_device *dev = connector->dev;
3020         enum drm_connector_status status;
3021         struct edid *edid = NULL;
3022
3023         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3024                       connector->base.id, drm_get_connector_name(connector));
3025
3026         intel_dp->has_audio = false;
3027
3028         if (HAS_PCH_SPLIT(dev))
3029                 status = ironlake_dp_detect(intel_dp);
3030         else
3031                 status = g4x_dp_detect(intel_dp);
3032
3033         if (status != connector_status_connected)
3034                 return status;
3035
3036         intel_dp_probe_oui(intel_dp);
3037
3038         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3039                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3040         } else {
3041                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3042                 if (edid) {
3043                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3044                         kfree(edid);
3045                 }
3046         }
3047
3048         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3049                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3050         return connector_status_connected;
3051 }
3052
3053 static int intel_dp_get_modes(struct drm_connector *connector)
3054 {
3055         struct intel_dp *intel_dp = intel_attached_dp(connector);
3056         struct intel_connector *intel_connector = to_intel_connector(connector);
3057         struct drm_device *dev = connector->dev;
3058         int ret;
3059
3060         /* We should parse the EDID data and find out if it has an audio sink
3061          */
3062
3063         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3064         if (ret)
3065                 return ret;
3066
3067         /* if eDP has no EDID, fall back to fixed mode */
3068         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3069                 struct drm_display_mode *mode;
3070                 mode = drm_mode_duplicate(dev,
3071                                           intel_connector->panel.fixed_mode);
3072                 if (mode) {
3073                         drm_mode_probed_add(connector, mode);
3074                         return 1;
3075                 }
3076         }
3077         return 0;
3078 }
3079
3080 static bool
3081 intel_dp_detect_audio(struct drm_connector *connector)
3082 {
3083         struct intel_dp *intel_dp = intel_attached_dp(connector);
3084         struct edid *edid;
3085         bool has_audio = false;
3086
3087         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3088         if (edid) {
3089                 has_audio = drm_detect_monitor_audio(edid);
3090                 kfree(edid);
3091         }
3092
3093         return has_audio;
3094 }
3095
3096 static int
3097 intel_dp_set_property(struct drm_connector *connector,
3098                       struct drm_property *property,
3099                       uint64_t val)
3100 {
3101         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3102         struct intel_connector *intel_connector = to_intel_connector(connector);
3103         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3104         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3105         int ret;
3106
3107         ret = drm_object_property_set_value(&connector->base, property, val);
3108         if (ret)
3109                 return ret;
3110
3111         if (property == dev_priv->force_audio_property) {
3112                 int i = val;
3113                 bool has_audio;
3114
3115                 if (i == intel_dp->force_audio)
3116                         return 0;
3117
3118                 intel_dp->force_audio = i;
3119
3120                 if (i == HDMI_AUDIO_AUTO)
3121                         has_audio = intel_dp_detect_audio(connector);
3122                 else
3123                         has_audio = (i == HDMI_AUDIO_ON);
3124
3125                 if (has_audio == intel_dp->has_audio)
3126                         return 0;
3127
3128                 intel_dp->has_audio = has_audio;
3129                 goto done;
3130         }
3131
3132         if (property == dev_priv->broadcast_rgb_property) {
3133                 bool old_auto = intel_dp->color_range_auto;
3134                 uint32_t old_range = intel_dp->color_range;
3135
3136                 switch (val) {
3137                 case INTEL_BROADCAST_RGB_AUTO:
3138                         intel_dp->color_range_auto = true;
3139                         break;
3140                 case INTEL_BROADCAST_RGB_FULL:
3141                         intel_dp->color_range_auto = false;
3142                         intel_dp->color_range = 0;
3143                         break;
3144                 case INTEL_BROADCAST_RGB_LIMITED:
3145                         intel_dp->color_range_auto = false;
3146                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3147                         break;
3148                 default:
3149                         return -EINVAL;
3150                 }
3151
3152                 if (old_auto == intel_dp->color_range_auto &&
3153                     old_range == intel_dp->color_range)
3154                         return 0;
3155
3156                 goto done;
3157         }
3158
3159         if (is_edp(intel_dp) &&
3160             property == connector->dev->mode_config.scaling_mode_property) {
3161                 if (val == DRM_MODE_SCALE_NONE) {
3162                         DRM_DEBUG_KMS("no scaling not supported\n");
3163                         return -EINVAL;
3164                 }
3165
3166                 if (intel_connector->panel.fitting_mode == val) {
3167                         /* the eDP scaling property is not changed */
3168                         return 0;
3169                 }
3170                 intel_connector->panel.fitting_mode = val;
3171
3172                 goto done;
3173         }
3174
3175         return -EINVAL;
3176
3177 done:
3178         if (intel_encoder->base.crtc)
3179                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3180
3181         return 0;
3182 }
3183
3184 static void
3185 intel_dp_connector_destroy(struct drm_connector *connector)
3186 {
3187         struct intel_connector *intel_connector = to_intel_connector(connector);
3188
3189         if (!IS_ERR_OR_NULL(intel_connector->edid))
3190                 kfree(intel_connector->edid);
3191
3192         /* Can't call is_edp() since the encoder may have been destroyed
3193          * already. */
3194         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3195                 intel_panel_fini(&intel_connector->panel);
3196
3197         drm_connector_cleanup(connector);
3198         kfree(connector);
3199 }
3200
3201 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3202 {
3203         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3204         struct intel_dp *intel_dp = &intel_dig_port->dp;
3205         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3206
3207         i2c_del_adapter(&intel_dp->adapter);
3208         drm_encoder_cleanup(encoder);
3209         if (is_edp(intel_dp)) {
3210                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3211                 mutex_lock(&dev->mode_config.mutex);
3212                 ironlake_panel_vdd_off_sync(intel_dp);
3213                 mutex_unlock(&dev->mode_config.mutex);
3214         }
3215         kfree(intel_dig_port);
3216 }
3217
3218 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3219         .dpms = intel_connector_dpms,
3220         .detect = intel_dp_detect,
3221         .fill_modes = drm_helper_probe_single_connector_modes,
3222         .set_property = intel_dp_set_property,
3223         .destroy = intel_dp_connector_destroy,
3224 };
3225
3226 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3227         .get_modes = intel_dp_get_modes,
3228         .mode_valid = intel_dp_mode_valid,
3229         .best_encoder = intel_best_encoder,
3230 };
3231
3232 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3233         .destroy = intel_dp_encoder_destroy,
3234 };
3235
3236 static void
3237 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3238 {
3239         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3240
3241         intel_dp_check_link_status(intel_dp);
3242 }
3243
3244 /* Return which DP Port should be selected for Transcoder DP control */
3245 int
3246 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3247 {
3248         struct drm_device *dev = crtc->dev;
3249         struct intel_encoder *intel_encoder;
3250         struct intel_dp *intel_dp;
3251
3252         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3253                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3254
3255                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3256                     intel_encoder->type == INTEL_OUTPUT_EDP)
3257                         return intel_dp->output_reg;
3258         }
3259
3260         return -1;
3261 }
3262
3263 /* check the VBT to see whether the eDP is on DP-D port */
3264 bool intel_dpd_is_edp(struct drm_device *dev)
3265 {
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         union child_device_config *p_child;
3268         int i;
3269
3270         if (!dev_priv->vbt.child_dev_num)
3271                 return false;
3272
3273         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3274                 p_child = dev_priv->vbt.child_dev + i;
3275
3276                 if (p_child->common.dvo_port == PORT_IDPD &&
3277                     p_child->common.device_type == DEVICE_TYPE_eDP)
3278                         return true;
3279         }
3280         return false;
3281 }
3282
3283 static void
3284 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3285 {
3286         struct intel_connector *intel_connector = to_intel_connector(connector);
3287
3288         intel_attach_force_audio_property(connector);
3289         intel_attach_broadcast_rgb_property(connector);
3290         intel_dp->color_range_auto = true;
3291
3292         if (is_edp(intel_dp)) {
3293                 drm_mode_create_scaling_mode_property(connector->dev);
3294                 drm_object_attach_property(
3295                         &connector->base,
3296                         connector->dev->mode_config.scaling_mode_property,
3297                         DRM_MODE_SCALE_ASPECT);
3298                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3299         }
3300 }
3301
3302 static void
3303 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3304                                     struct intel_dp *intel_dp,
3305                                     struct edp_power_seq *out)
3306 {
3307         struct drm_i915_private *dev_priv = dev->dev_private;
3308         struct edp_power_seq cur, vbt, spec, final;
3309         u32 pp_on, pp_off, pp_div, pp;
3310         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3311
3312         if (HAS_PCH_SPLIT(dev)) {
3313                 pp_ctrl_reg = PCH_PP_CONTROL;
3314                 pp_on_reg = PCH_PP_ON_DELAYS;
3315                 pp_off_reg = PCH_PP_OFF_DELAYS;
3316                 pp_div_reg = PCH_PP_DIVISOR;
3317         } else {
3318                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3319
3320                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3321                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3322                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3323                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3324         }
3325
3326         /* Workaround: Need to write PP_CONTROL with the unlock key as
3327          * the very first thing. */
3328         pp = ironlake_get_pp_control(intel_dp);
3329         I915_WRITE(pp_ctrl_reg, pp);
3330
3331         pp_on = I915_READ(pp_on_reg);
3332         pp_off = I915_READ(pp_off_reg);
3333         pp_div = I915_READ(pp_div_reg);
3334
3335         /* Pull timing values out of registers */
3336         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3337                 PANEL_POWER_UP_DELAY_SHIFT;
3338
3339         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3340                 PANEL_LIGHT_ON_DELAY_SHIFT;
3341
3342         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3343                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3344
3345         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3346                 PANEL_POWER_DOWN_DELAY_SHIFT;
3347
3348         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3349                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3350
3351         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3352                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3353
3354         vbt = dev_priv->vbt.edp_pps;
3355
3356         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3357          * our hw here, which are all in 100usec. */
3358         spec.t1_t3 = 210 * 10;
3359         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3360         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3361         spec.t10 = 500 * 10;
3362         /* This one is special and actually in units of 100ms, but zero
3363          * based in the hw (so we need to add 100 ms). But the sw vbt
3364          * table multiplies it with 1000 to make it in units of 100usec,
3365          * too. */
3366         spec.t11_t12 = (510 + 100) * 10;
3367
3368         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3369                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3370
3371         /* Use the max of the register settings and vbt. If both are
3372          * unset, fall back to the spec limits. */
3373 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3374                                        spec.field : \
3375                                        max(cur.field, vbt.field))
3376         assign_final(t1_t3);
3377         assign_final(t8);
3378         assign_final(t9);
3379         assign_final(t10);
3380         assign_final(t11_t12);
3381 #undef assign_final
3382
3383 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3384         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3385         intel_dp->backlight_on_delay = get_delay(t8);
3386         intel_dp->backlight_off_delay = get_delay(t9);
3387         intel_dp->panel_power_down_delay = get_delay(t10);
3388         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3389 #undef get_delay
3390
3391         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3392                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3393                       intel_dp->panel_power_cycle_delay);
3394
3395         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3396                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3397
3398         if (out)
3399                 *out = final;
3400 }
3401
3402 static void
3403 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3404                                               struct intel_dp *intel_dp,
3405                                               struct edp_power_seq *seq)
3406 {
3407         struct drm_i915_private *dev_priv = dev->dev_private;
3408         u32 pp_on, pp_off, pp_div, port_sel = 0;
3409         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3410         int pp_on_reg, pp_off_reg, pp_div_reg;
3411
3412         if (HAS_PCH_SPLIT(dev)) {
3413                 pp_on_reg = PCH_PP_ON_DELAYS;
3414                 pp_off_reg = PCH_PP_OFF_DELAYS;
3415                 pp_div_reg = PCH_PP_DIVISOR;
3416         } else {
3417                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3418
3419                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3420                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3421                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3422         }
3423
3424         /* And finally store the new values in the power sequencer. */
3425         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3426                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3427         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3428                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3429         /* Compute the divisor for the pp clock, simply match the Bspec
3430          * formula. */
3431         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3432         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3433                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3434
3435         /* Haswell doesn't have any port selection bits for the panel
3436          * power sequencer any more. */
3437         if (IS_VALLEYVIEW(dev)) {
3438                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3439                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3440                 else
3441                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3442         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3443                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3444                         port_sel = PANEL_PORT_SELECT_DPA;
3445                 else
3446                         port_sel = PANEL_PORT_SELECT_DPD;
3447         }
3448
3449         pp_on |= port_sel;
3450
3451         I915_WRITE(pp_on_reg, pp_on);
3452         I915_WRITE(pp_off_reg, pp_off);
3453         I915_WRITE(pp_div_reg, pp_div);
3454
3455         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3456                       I915_READ(pp_on_reg),
3457                       I915_READ(pp_off_reg),
3458                       I915_READ(pp_div_reg));
3459 }
3460
3461 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3462                                      struct intel_connector *intel_connector)
3463 {
3464         struct drm_connector *connector = &intel_connector->base;
3465         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3466         struct drm_device *dev = intel_dig_port->base.base.dev;
3467         struct drm_i915_private *dev_priv = dev->dev_private;
3468         struct drm_display_mode *fixed_mode = NULL;
3469         struct edp_power_seq power_seq = { 0 };
3470         bool has_dpcd;
3471         struct drm_display_mode *scan;
3472         struct edid *edid;
3473
3474         if (!is_edp(intel_dp))
3475                 return true;
3476
3477         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3478
3479         /* Cache DPCD and EDID for edp. */
3480         ironlake_edp_panel_vdd_on(intel_dp);
3481         has_dpcd = intel_dp_get_dpcd(intel_dp);
3482         ironlake_edp_panel_vdd_off(intel_dp, false);
3483
3484         if (has_dpcd) {
3485                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3486                         dev_priv->no_aux_handshake =
3487                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3488                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3489         } else {
3490                 /* if this fails, presume the device is a ghost */
3491                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3492                 return false;
3493         }
3494
3495         /* We now know it's not a ghost, init power sequence regs. */
3496         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3497                                                       &power_seq);
3498
3499         ironlake_edp_panel_vdd_on(intel_dp);
3500         edid = drm_get_edid(connector, &intel_dp->adapter);
3501         if (edid) {
3502                 if (drm_add_edid_modes(connector, edid)) {
3503                         drm_mode_connector_update_edid_property(connector,
3504                                                                 edid);
3505                         drm_edid_to_eld(connector, edid);
3506                 } else {
3507                         kfree(edid);
3508                         edid = ERR_PTR(-EINVAL);
3509                 }
3510         } else {
3511                 edid = ERR_PTR(-ENOENT);
3512         }
3513         intel_connector->edid = edid;
3514
3515         /* prefer fixed mode from EDID if available */
3516         list_for_each_entry(scan, &connector->probed_modes, head) {
3517                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3518                         fixed_mode = drm_mode_duplicate(dev, scan);
3519                         break;
3520                 }
3521         }
3522
3523         /* fallback to VBT if available for eDP */
3524         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3525                 fixed_mode = drm_mode_duplicate(dev,
3526                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3527                 if (fixed_mode)
3528                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3529         }
3530
3531         ironlake_edp_panel_vdd_off(intel_dp, false);
3532
3533         intel_panel_init(&intel_connector->panel, fixed_mode);
3534         intel_panel_setup_backlight(connector);
3535
3536         return true;
3537 }
3538
3539 bool
3540 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3541                         struct intel_connector *intel_connector)
3542 {
3543         struct drm_connector *connector = &intel_connector->base;
3544         struct intel_dp *intel_dp = &intel_dig_port->dp;
3545         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3546         struct drm_device *dev = intel_encoder->base.dev;
3547         struct drm_i915_private *dev_priv = dev->dev_private;
3548         enum port port = intel_dig_port->port;
3549         const char *name = NULL;
3550         int type, error;
3551
3552         /* Preserve the current hw state. */
3553         intel_dp->DP = I915_READ(intel_dp->output_reg);
3554         intel_dp->attached_connector = intel_connector;
3555
3556         type = DRM_MODE_CONNECTOR_DisplayPort;
3557         /*
3558          * FIXME : We need to initialize built-in panels before external panels.
3559          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3560          */
3561         switch (port) {
3562         case PORT_A:
3563                 type = DRM_MODE_CONNECTOR_eDP;
3564                 break;
3565         case PORT_C:
3566                 if (IS_VALLEYVIEW(dev))
3567                         type = DRM_MODE_CONNECTOR_eDP;
3568                 break;
3569         case PORT_D:
3570                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3571                         type = DRM_MODE_CONNECTOR_eDP;
3572                 break;
3573         default:        /* silence GCC warning */
3574                 break;
3575         }
3576
3577         /*
3578          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3579          * for DP the encoder type can be set by the caller to
3580          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3581          */
3582         if (type == DRM_MODE_CONNECTOR_eDP)
3583                 intel_encoder->type = INTEL_OUTPUT_EDP;
3584
3585         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3586                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3587                         port_name(port));
3588
3589         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3590         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3591
3592         connector->interlace_allowed = true;
3593         connector->doublescan_allowed = 0;
3594
3595         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3596                           ironlake_panel_vdd_work);
3597
3598         intel_connector_attach_encoder(intel_connector, intel_encoder);
3599         drm_sysfs_connector_add(connector);
3600
3601         if (HAS_DDI(dev))
3602                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3603         else
3604                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3605
3606         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3607         if (HAS_DDI(dev)) {
3608                 switch (intel_dig_port->port) {
3609                 case PORT_A:
3610                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3611                         break;
3612                 case PORT_B:
3613                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3614                         break;
3615                 case PORT_C:
3616                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3617                         break;
3618                 case PORT_D:
3619                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3620                         break;
3621                 default:
3622                         BUG();
3623                 }
3624         }
3625
3626         /* Set up the DDC bus. */
3627         switch (port) {
3628         case PORT_A:
3629                 intel_encoder->hpd_pin = HPD_PORT_A;
3630                 name = "DPDDC-A";
3631                 break;
3632         case PORT_B:
3633                 intel_encoder->hpd_pin = HPD_PORT_B;
3634                 name = "DPDDC-B";
3635                 break;
3636         case PORT_C:
3637                 intel_encoder->hpd_pin = HPD_PORT_C;
3638                 name = "DPDDC-C";
3639                 break;
3640         case PORT_D:
3641                 intel_encoder->hpd_pin = HPD_PORT_D;
3642                 name = "DPDDC-D";
3643                 break;
3644         default:
3645                 BUG();
3646         }
3647
3648         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3649         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3650              error, port_name(port));
3651
3652         intel_dp->psr_setup_done = false;
3653
3654         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3655                 i2c_del_adapter(&intel_dp->adapter);
3656                 if (is_edp(intel_dp)) {
3657                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3658                         mutex_lock(&dev->mode_config.mutex);
3659                         ironlake_panel_vdd_off_sync(intel_dp);
3660                         mutex_unlock(&dev->mode_config.mutex);
3661                 }
3662                 drm_sysfs_connector_remove(connector);
3663                 drm_connector_cleanup(connector);
3664                 return false;
3665         }
3666
3667         intel_dp_add_properties(intel_dp, connector);
3668
3669         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3670          * 0xd.  Failure to do so will result in spurious interrupts being
3671          * generated on the port when a cable is not attached.
3672          */
3673         if (IS_G4X(dev) && !IS_GM45(dev)) {
3674                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3675                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3676         }
3677
3678         return true;
3679 }
3680
3681 void
3682 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3683 {
3684         struct intel_digital_port *intel_dig_port;
3685         struct intel_encoder *intel_encoder;
3686         struct drm_encoder *encoder;
3687         struct intel_connector *intel_connector;
3688
3689         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3690         if (!intel_dig_port)
3691                 return;
3692
3693         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3694         if (!intel_connector) {
3695                 kfree(intel_dig_port);
3696                 return;
3697         }
3698
3699         intel_encoder = &intel_dig_port->base;
3700         encoder = &intel_encoder->base;
3701
3702         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3703                          DRM_MODE_ENCODER_TMDS);
3704
3705         intel_encoder->compute_config = intel_dp_compute_config;
3706         intel_encoder->mode_set = intel_dp_mode_set;
3707         intel_encoder->disable = intel_disable_dp;
3708         intel_encoder->post_disable = intel_post_disable_dp;
3709         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3710         intel_encoder->get_config = intel_dp_get_config;
3711         if (IS_VALLEYVIEW(dev)) {
3712                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3713                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3714                 intel_encoder->enable = vlv_enable_dp;
3715         } else {
3716                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3717                 intel_encoder->enable = g4x_enable_dp;
3718         }
3719
3720         intel_dig_port->port = port;
3721         intel_dig_port->dp.output_reg = output_reg;
3722
3723         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3724         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3725         intel_encoder->cloneable = false;
3726         intel_encoder->hot_plug = intel_dp_hot_plug;
3727
3728         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3729                 drm_encoder_cleanup(encoder);
3730                 kfree(intel_dig_port);
3731                 kfree(intel_connector);
3732         }
3733 }