drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 /**
  69  * intel_pipe_update_start() - start update of a set of display registers
  70  * @crtc: the crtc of which the registers are going to be updated
  71  * @start_vbl_count: vblank counter return pointer used for error checking
  72  *
  73  * Mark the start of an update to pipe registers that should be updated
  74  * atomically regarding vblank. If the next vblank will happens within
  75  * the next 100 us, this function waits until the vblank passes.
  76  *
  77  * After a successful call to this function, interrupts will be disabled
  78  * until a subsequent call to intel_pipe_update_end(). That is done to
  79  * avoid random delays. The value written to @start_vbl_count should be
  80  * supplied to intel_pipe_update_end() for error checking.
  81  */
  82 void intel_pipe_update_start(struct intel_crtc *crtc)
  83 {
  84         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85         long timeout = msecs_to_jiffies_timeout(1);
  86         int scanline, min, max, vblank_start;
  87         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  88         DEFINE_WAIT(wait);
  89
  90         vblank_start = adjusted_mode->crtc_vblank_start;
  91         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  92                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  93
  94         /* FIXME needs to be calibrated sensibly */
  95         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
  96         max = vblank_start - 1;
  97
  98         local_irq_disable();
  99
 100         if (min <= 0 || max <= 0)
 101                 return;
 102
 103         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 104                 return;
 105
 106         crtc->debug.min_vbl = min;
 107         crtc->debug.max_vbl = max;
 108         trace_i915_pipe_update_start(crtc);
 109
 110         for (;;) {
 111                 /*
 112                  * prepare_to_wait() has a memory barrier, which guarantees
 113                  * other CPUs can see the task state update by the time we
 114                  * read the scanline.
 115                  */
 116                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 117
 118                 scanline = intel_get_crtc_scanline(crtc);
 119                 if (scanline < min || scanline > max)
 120                         break;
 121
 122                 if (timeout <= 0) {
 123                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 124                                   pipe_name(crtc->pipe));
 125                         break;
 126                 }
 127
 128                 local_irq_enable();
 129
 130                 timeout = schedule_timeout(timeout);
 131
 132                 local_irq_disable();
 133         }
 134
 135         finish_wait(wq, &wait);
 136
 137         drm_crtc_vblank_put(&crtc->base);
 138
 139         crtc->debug.scanline_start = scanline;
 140         crtc->debug.start_vbl_time = ktime_get();
 141         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 142
 143         trace_i915_pipe_update_vblank_evaded(crtc);
 144 }
 145
 146 /**
 147  * intel_pipe_update_end() - end update of a set of display registers
 148  * @crtc: the crtc of which the registers were updated
 149  * @start_vbl_count: start vblank counter (used for error checking)
 150  *
 151  * Mark the end of an update started with intel_pipe_update_start(). This
 152  * re-enables interrupts and verifies the update was actually completed
 153  * before a vblank using the value of @start_vbl_count.
 154  */
 155 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 156 {
 157         enum pipe pipe = crtc->pipe;
 158         int scanline_end = intel_get_crtc_scanline(crtc);
 159         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 160         ktime_t end_vbl_time = ktime_get();
 161
 162         if (work) {
 163                 work->flip_queued_vblank = end_vbl_count;
 164                 smp_mb__before_atomic();
 165                 atomic_set(&work->pending, 1);
 166         }
 167
 168         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 169
 170         /* We're still in the vblank-evade critical section, this can't race.
 171          * Would be slightly nice to just grab the vblank count and arm the
 172          * event outside of the critical section - the spinlock might spin for a
 173          * while ... */
 174         if (crtc->base.state->event) {
 175                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 176
 177                 spin_lock(&crtc->base.dev->event_lock);
 178                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 179                 spin_unlock(&crtc->base.dev->event_lock);
 180
 181                 crtc->base.state->event = NULL;
 182         }
 183
 184         local_irq_enable();
 185
 186         if (crtc->debug.start_vbl_count &&
 187             crtc->debug.start_vbl_count != end_vbl_count) {
 188                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 189                           pipe_name(pipe), crtc->debug.start_vbl_count,
 190                           end_vbl_count,
 191                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 192                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 193                           crtc->debug.scanline_start, scanline_end);
 194         }
 195 }
 196
 197 static void
 198 skl_update_plane(struct drm_plane *drm_plane,
 199                  const struct intel_crtc_state *crtc_state,
 200                  const struct intel_plane_state *plane_state)
 201 {
 202         struct drm_device *dev = drm_plane->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 205         struct drm_framebuffer *fb = plane_state->base.fb;
 206         enum plane_id plane_id = intel_plane->id;
 207         enum pipe pipe = intel_plane->pipe;
 208         u32 plane_ctl;
 209         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 210         u32 surf_addr = plane_state->main.offset;
 211         unsigned int rotation = plane_state->base.rotation;
 212         u32 stride = skl_plane_stride(fb, 0, rotation);
 213         int crtc_x = plane_state->base.dst.x1;
 214         int crtc_y = plane_state->base.dst.y1;
 215         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 216         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 217         uint32_t x = plane_state->main.x;
 218         uint32_t y = plane_state->main.y;
 219         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 220         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 221
 222         plane_ctl = PLANE_CTL_ENABLE;
 223
 224         if (IS_GEMINILAKE(dev_priv)) {
 225                 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
 226                            PLANE_COLOR_PIPE_GAMMA_ENABLE |
 227                            PLANE_COLOR_PIPE_CSC_ENABLE |
 228                            PLANE_COLOR_PLANE_GAMMA_DISABLE);
 229         } else {
 230                 plane_ctl |=
 231                         PLANE_CTL_PIPE_GAMMA_ENABLE |
 232                         PLANE_CTL_PIPE_CSC_ENABLE |
 233                         PLANE_CTL_PLANE_GAMMA_DISABLE;
 234         }
 235
 236         plane_ctl |= skl_plane_ctl_format(fb->format->format);
 237         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 238         plane_ctl |= skl_plane_ctl_rotation(rotation);
 239
 240         if (key->flags) {
 241                 I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 242                 I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 243                 I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 244         }
 245
 246         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 247                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 248         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 249                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 250
 251         /* Sizes are 0 based */
 252         src_w--;
 253         src_h--;
 254         crtc_w--;
 255         crtc_h--;
 256
 257         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 258         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
 259         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 260
 261         /* program plane scaler */
 262         if (plane_state->scaler_id >= 0) {
 263                 int scaler_id = plane_state->scaler_id;
 264                 const struct intel_scaler *scaler;
 265
 266                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n",
 267                               plane_id, PS_PLANE_SEL(plane_id));
 268
 269                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 270
 271                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 272                            PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 273                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 274                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 275                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 276                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 277
 278                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
 279         } else {
 280                 I915_WRITE(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 281         }
 282
 283         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
 284         I915_WRITE(PLANE_SURF(pipe, plane_id),
 285                    intel_plane_ggtt_offset(plane_state) + surf_addr);
 286         POSTING_READ(PLANE_SURF(pipe, plane_id));
 287 }
 288
 289 static void
 290 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 291 {
 292         struct drm_device *dev = dplane->dev;
 293         struct drm_i915_private *dev_priv = to_i915(dev);
 294         struct intel_plane *intel_plane = to_intel_plane(dplane);
 295         enum plane_id plane_id = intel_plane->id;
 296         enum pipe pipe = intel_plane->pipe;
 297
 298         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
 299
 300         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
 301         POSTING_READ(PLANE_SURF(pipe, plane_id));
 302 }
 303
 304 static void
 305 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 306 {
 307         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 308         enum plane_id plane_id = intel_plane->id;
 309
 310         /* Seems RGB data bypasses the CSC always */
 311         if (!format_is_yuv(format))
 312                 return;
 313
 314         /*
 315          * BT.601 limited range YCbCr -> full range RGB
 316          *
 317          * |r|   | 6537 4769     0|   |cr  |
 318          * |g| = |-3330 4769 -1605| x |y-64|
 319          * |b|   |    0 4769  8263|   |cb  |
 320          *
 321          * Cb and Cr apparently come in as signed already, so no
 322          * need for any offset. For Y we need to remove the offset.
 323          */
 324         I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 325         I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 326         I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 327
 328         I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 329         I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 330         I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 331         I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 332         I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
 333
 334         I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 335         I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 336         I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 337
 338         I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 339         I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 340         I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 341 }
 342
 343 static void
 344 vlv_update_plane(struct drm_plane *dplane,
 345                  const struct intel_crtc_state *crtc_state,
 346                  const struct intel_plane_state *plane_state)
 347 {
 348         struct drm_device *dev = dplane->dev;
 349         struct drm_i915_private *dev_priv = to_i915(dev);
 350         struct intel_plane *intel_plane = to_intel_plane(dplane);
 351         struct drm_framebuffer *fb = plane_state->base.fb;
 352         enum pipe pipe = intel_plane->pipe;
 353         enum plane_id plane_id = intel_plane->id;
 354         u32 sprctl;
 355         u32 sprsurf_offset, linear_offset;
 356         unsigned int rotation = plane_state->base.rotation;
 357         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 358         int crtc_x = plane_state->base.dst.x1;
 359         int crtc_y = plane_state->base.dst.y1;
 360         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 361         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 362         uint32_t x = plane_state->base.src.x1 >> 16;
 363         uint32_t y = plane_state->base.src.y1 >> 16;
 364         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 365         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 366
 367         sprctl = SP_ENABLE;
 368
 369         switch (fb->format->format) {
 370         case DRM_FORMAT_YUYV:
 371                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 372                 break;
 373         case DRM_FORMAT_YVYU:
 374                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 375                 break;
 376         case DRM_FORMAT_UYVY:
 377                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 378                 break;
 379         case DRM_FORMAT_VYUY:
 380                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 381                 break;
 382         case DRM_FORMAT_RGB565:
 383                 sprctl |= SP_FORMAT_BGR565;
 384                 break;
 385         case DRM_FORMAT_XRGB8888:
 386                 sprctl |= SP_FORMAT_BGRX8888;
 387                 break;
 388         case DRM_FORMAT_ARGB8888:
 389                 sprctl |= SP_FORMAT_BGRA8888;
 390                 break;
 391         case DRM_FORMAT_XBGR2101010:
 392                 sprctl |= SP_FORMAT_RGBX1010102;
 393                 break;
 394         case DRM_FORMAT_ABGR2101010:
 395                 sprctl |= SP_FORMAT_RGBA1010102;
 396                 break;
 397         case DRM_FORMAT_XBGR8888:
 398                 sprctl |= SP_FORMAT_RGBX8888;
 399                 break;
 400         case DRM_FORMAT_ABGR8888:
 401                 sprctl |= SP_FORMAT_RGBA8888;
 402                 break;
 403         default:
 404                 /*
 405                  * If we get here one of the upper layers failed to filter
 406                  * out the unsupported plane formats
 407                  */
 408                 BUG();
 409                 break;
 410         }
 411
 412         /*
 413          * Enable gamma to match primary/cursor plane behaviour.
 414          * FIXME should be user controllable via propertiesa.
 415          */
 416         sprctl |= SP_GAMMA_ENABLE;
 417
 418         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 419                 sprctl |= SP_TILED;
 420
 421         if (rotation & DRM_ROTATE_180)
 422                 sprctl |= SP_ROTATE_180;
 423
 424         if (rotation & DRM_REFLECT_X)
 425                 sprctl |= SP_MIRROR;
 426
 427         /* Sizes are 0 based */
 428         src_w--;
 429         src_h--;
 430         crtc_w--;
 431         crtc_h--;
 432
 433         intel_add_fb_offsets(&x, &y, plane_state, 0);
 434         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 435
 436         if (rotation & DRM_ROTATE_180) {
 437                 x += src_w;
 438                 y += src_h;
 439         } else if (rotation & DRM_REFLECT_X) {
 440                 x += src_w;
 441         }
 442
 443         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 444
 445         if (key->flags) {
 446                 I915_WRITE(SPKEYMINVAL(pipe, plane_id), key->min_value);
 447                 I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 448                 I915_WRITE(SPKEYMSK(pipe, plane_id), key->channel_mask);
 449         }
 450
 451         if (key->flags & I915_SET_COLORKEY_SOURCE)
 452                 sprctl |= SP_SOURCE_KEY;
 453
 454         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 455                 chv_update_csc(intel_plane, fb->format->format);
 456
 457         I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 458         I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 459
 460         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 461                 I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 462         else
 463                 I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
 464
 465         I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
 466
 467         I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 468         I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
 469         I915_WRITE(SPSURF(pipe, plane_id),
 470                    intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 471         POSTING_READ(SPSURF(pipe, plane_id));
 472 }
 473
 474 static void
 475 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 476 {
 477         struct drm_device *dev = dplane->dev;
 478         struct drm_i915_private *dev_priv = to_i915(dev);
 479         struct intel_plane *intel_plane = to_intel_plane(dplane);
 480         enum pipe pipe = intel_plane->pipe;
 481         enum plane_id plane_id = intel_plane->id;
 482
 483         I915_WRITE(SPCNTR(pipe, plane_id), 0);
 484
 485         I915_WRITE(SPSURF(pipe, plane_id), 0);
 486         POSTING_READ(SPSURF(pipe, plane_id));
 487 }
 488
 489 static void
 490 ivb_update_plane(struct drm_plane *plane,
 491                  const struct intel_crtc_state *crtc_state,
 492                  const struct intel_plane_state *plane_state)
 493 {
 494         struct drm_device *dev = plane->dev;
 495         struct drm_i915_private *dev_priv = to_i915(dev);
 496         struct intel_plane *intel_plane = to_intel_plane(plane);
 497         struct drm_framebuffer *fb = plane_state->base.fb;
 498         enum pipe pipe = intel_plane->pipe;
 499         u32 sprctl, sprscale = 0;
 500         u32 sprsurf_offset, linear_offset;
 501         unsigned int rotation = plane_state->base.rotation;
 502         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 503         int crtc_x = plane_state->base.dst.x1;
 504         int crtc_y = plane_state->base.dst.y1;
 505         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 506         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 507         uint32_t x = plane_state->base.src.x1 >> 16;
 508         uint32_t y = plane_state->base.src.y1 >> 16;
 509         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 510         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 511
 512         sprctl = SPRITE_ENABLE;
 513
 514         switch (fb->format->format) {
 515         case DRM_FORMAT_XBGR8888:
 516                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 517                 break;
 518         case DRM_FORMAT_XRGB8888:
 519                 sprctl |= SPRITE_FORMAT_RGBX888;
 520                 break;
 521         case DRM_FORMAT_YUYV:
 522                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 523                 break;
 524         case DRM_FORMAT_YVYU:
 525                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 526                 break;
 527         case DRM_FORMAT_UYVY:
 528                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 529                 break;
 530         case DRM_FORMAT_VYUY:
 531                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 532                 break;
 533         default:
 534                 BUG();
 535         }
 536
 537         /*
 538          * Enable gamma to match primary/cursor plane behaviour.
 539          * FIXME should be user controllable via propertiesa.
 540          */
 541         sprctl |= SPRITE_GAMMA_ENABLE;
 542
 543         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 544                 sprctl |= SPRITE_TILED;
 545
 546         if (rotation & DRM_ROTATE_180)
 547                 sprctl |= SPRITE_ROTATE_180;
 548
 549         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 550                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 551         else
 552                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 553
 554         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 555                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 556
 557         /* Sizes are 0 based */
 558         src_w--;
 559         src_h--;
 560         crtc_w--;
 561         crtc_h--;
 562
 563         if (crtc_w != src_w || crtc_h != src_h)
 564                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 565
 566         intel_add_fb_offsets(&x, &y, plane_state, 0);
 567         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 568
 569         /* HSW+ does this automagically in hardware */
 570         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
 571             rotation & DRM_ROTATE_180) {
 572                 x += src_w;
 573                 y += src_h;
 574         }
 575
 576         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 577
 578         if (key->flags) {
 579                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 580                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 581                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 582         }
 583
 584         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 585                 sprctl |= SPRITE_DEST_KEY;
 586         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 587                 sprctl |= SPRITE_SOURCE_KEY;
 588
 589         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 590         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 591
 592         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 593          * register */
 594         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 595                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 596         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 597                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 598         else
 599                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 600
 601         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 602         if (intel_plane->can_scale)
 603                 I915_WRITE(SPRSCALE(pipe), sprscale);
 604         I915_WRITE(SPRCTL(pipe), sprctl);
 605         I915_WRITE(SPRSURF(pipe),
 606                    intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 607         POSTING_READ(SPRSURF(pipe));
 608 }
 609
 610 static void
 611 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 612 {
 613         struct drm_device *dev = plane->dev;
 614         struct drm_i915_private *dev_priv = to_i915(dev);
 615         struct intel_plane *intel_plane = to_intel_plane(plane);
 616         int pipe = intel_plane->pipe;
 617
 618         I915_WRITE(SPRCTL(pipe), 0);
 619         /* Can't leave the scaler enabled... */
 620         if (intel_plane->can_scale)
 621                 I915_WRITE(SPRSCALE(pipe), 0);
 622
 623         I915_WRITE(SPRSURF(pipe), 0);
 624         POSTING_READ(SPRSURF(pipe));
 625 }
 626
 627 static void
 628 ilk_update_plane(struct drm_plane *plane,
 629                  const struct intel_crtc_state *crtc_state,
 630                  const struct intel_plane_state *plane_state)
 631 {
 632         struct drm_device *dev = plane->dev;
 633         struct drm_i915_private *dev_priv = to_i915(dev);
 634         struct intel_plane *intel_plane = to_intel_plane(plane);
 635         struct drm_framebuffer *fb = plane_state->base.fb;
 636         int pipe = intel_plane->pipe;
 637         u32 dvscntr, dvsscale;
 638         u32 dvssurf_offset, linear_offset;
 639         unsigned int rotation = plane_state->base.rotation;
 640         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 641         int crtc_x = plane_state->base.dst.x1;
 642         int crtc_y = plane_state->base.dst.y1;
 643         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 644         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 645         uint32_t x = plane_state->base.src.x1 >> 16;
 646         uint32_t y = plane_state->base.src.y1 >> 16;
 647         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 648         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 649
 650         dvscntr = DVS_ENABLE;
 651
 652         switch (fb->format->format) {
 653         case DRM_FORMAT_XBGR8888:
 654                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 655                 break;
 656         case DRM_FORMAT_XRGB8888:
 657                 dvscntr |= DVS_FORMAT_RGBX888;
 658                 break;
 659         case DRM_FORMAT_YUYV:
 660                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 661                 break;
 662         case DRM_FORMAT_YVYU:
 663                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 664                 break;
 665         case DRM_FORMAT_UYVY:
 666                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 667                 break;
 668         case DRM_FORMAT_VYUY:
 669                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 670                 break;
 671         default:
 672                 BUG();
 673         }
 674
 675         /*
 676          * Enable gamma to match primary/cursor plane behaviour.
 677          * FIXME should be user controllable via propertiesa.
 678          */
 679         dvscntr |= DVS_GAMMA_ENABLE;
 680
 681         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 682                 dvscntr |= DVS_TILED;
 683
 684         if (rotation & DRM_ROTATE_180)
 685                 dvscntr |= DVS_ROTATE_180;
 686
 687         if (IS_GEN6(dev_priv))
 688                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 689
 690         /* Sizes are 0 based */
 691         src_w--;
 692         src_h--;
 693         crtc_w--;
 694         crtc_h--;
 695
 696         dvsscale = 0;
 697         if (crtc_w != src_w || crtc_h != src_h)
 698                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 699
 700         intel_add_fb_offsets(&x, &y, plane_state, 0);
 701         dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 702
 703         if (rotation & DRM_ROTATE_180) {
 704                 x += src_w;
 705                 y += src_h;
 706         }
 707
 708         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 709
 710         if (key->flags) {
 711                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 712                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 713                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 714         }
 715
 716         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 717                 dvscntr |= DVS_DEST_KEY;
 718         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 719                 dvscntr |= DVS_SOURCE_KEY;
 720
 721         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 722         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 723
 724         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 725                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 726         else
 727                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 728
 729         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 730         I915_WRITE(DVSSCALE(pipe), dvsscale);
 731         I915_WRITE(DVSCNTR(pipe), dvscntr);
 732         I915_WRITE(DVSSURF(pipe),
 733                    intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 734         POSTING_READ(DVSSURF(pipe));
 735 }
 736
 737 static void
 738 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 739 {
 740         struct drm_device *dev = plane->dev;
 741         struct drm_i915_private *dev_priv = to_i915(dev);
 742         struct intel_plane *intel_plane = to_intel_plane(plane);
 743         int pipe = intel_plane->pipe;
 744
 745         I915_WRITE(DVSCNTR(pipe), 0);
 746         /* Disable the scaler */
 747         I915_WRITE(DVSSCALE(pipe), 0);
 748
 749         I915_WRITE(DVSSURF(pipe), 0);
 750         POSTING_READ(DVSSURF(pipe));
 751 }
 752
 753 static int
 754 intel_check_sprite_plane(struct drm_plane *plane,
 755                          struct intel_crtc_state *crtc_state,
 756                          struct intel_plane_state *state)
 757 {
 758         struct drm_i915_private *dev_priv = to_i915(plane->dev);
 759         struct drm_crtc *crtc = state->base.crtc;
 760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 761         struct intel_plane *intel_plane = to_intel_plane(plane);
 762         struct drm_framebuffer *fb = state->base.fb;
 763         int crtc_x, crtc_y;
 764         unsigned int crtc_w, crtc_h;
 765         uint32_t src_x, src_y, src_w, src_h;
 766         struct drm_rect *src = &state->base.src;
 767         struct drm_rect *dst = &state->base.dst;
 768         const struct drm_rect *clip = &state->clip;
 769         int hscale, vscale;
 770         int max_scale, min_scale;
 771         bool can_scale;
 772         int ret;
 773
 774         *src = drm_plane_state_src(&state->base);
 775         *dst = drm_plane_state_dest(&state->base);
 776
 777         if (!fb) {
 778                 state->base.visible = false;
 779                 return 0;
 780         }
 781
 782         /* Don't modify another pipe's plane */
 783         if (intel_plane->pipe != intel_crtc->pipe) {
 784                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 785                 return -EINVAL;
 786         }
 787
 788         /* FIXME check all gen limits */
 789         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 790                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 791                 return -EINVAL;
 792         }
 793
 794         /* setup can_scale, min_scale, max_scale */
 795         if (INTEL_GEN(dev_priv) >= 9) {
 796                 /* use scaler when colorkey is not required */
 797                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 798                         can_scale = 1;
 799                         min_scale = 1;
 800                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 801                 } else {
 802                         can_scale = 0;
 803                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 804                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 805                 }
 806         } else {
 807                 can_scale = intel_plane->can_scale;
 808                 max_scale = intel_plane->max_downscale << 16;
 809                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 810         }
 811
 812         /*
 813          * FIXME the following code does a bunch of fuzzy adjustments to the
 814          * coordinates and sizes. We probably need some way to decide whether
 815          * more strict checking should be done instead.
 816          */
 817         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 818                         state->base.rotation);
 819
 820         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 821         BUG_ON(hscale < 0);
 822
 823         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 824         BUG_ON(vscale < 0);
 825
 826         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 827
 828         crtc_x = dst->x1;
 829         crtc_y = dst->y1;
 830         crtc_w = drm_rect_width(dst);
 831         crtc_h = drm_rect_height(dst);
 832
 833         if (state->base.visible) {
 834                 /* check again in case clipping clamped the results */
 835                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 836                 if (hscale < 0) {
 837                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 838                         drm_rect_debug_print("src: ", src, true);
 839                         drm_rect_debug_print("dst: ", dst, false);
 840
 841                         return hscale;
 842                 }
 843
 844                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 845                 if (vscale < 0) {
 846                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 847                         drm_rect_debug_print("src: ", src, true);
 848                         drm_rect_debug_print("dst: ", dst, false);
 849
 850                         return vscale;
 851                 }
 852
 853                 /* Make the source viewport size an exact multiple of the scaling factors. */
 854                 drm_rect_adjust_size(src,
 855                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 856                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 857
 858                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 859                                     state->base.rotation);
 860
 861                 /* sanity check to make sure the src viewport wasn't enlarged */
 862                 WARN_ON(src->x1 < (int) state->base.src_x ||
 863                         src->y1 < (int) state->base.src_y ||
 864                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 865                         src->y2 > (int) state->base.src_y + state->base.src_h);
 866
 867                 /*
 868                  * Hardware doesn't handle subpixel coordinates.
 869                  * Adjust to (macro)pixel boundary, but be careful not to
 870                  * increase the source viewport size, because that could
 871                  * push the downscaling factor out of bounds.
 872                  */
 873                 src_x = src->x1 >> 16;
 874                 src_w = drm_rect_width(src) >> 16;
 875                 src_y = src->y1 >> 16;
 876                 src_h = drm_rect_height(src) >> 16;
 877
 878                 if (format_is_yuv(fb->format->format)) {
 879                         src_x &= ~1;
 880                         src_w &= ~1;
 881
 882                         /*
 883                          * Must keep src and dst the
 884                          * same if we can't scale.
 885                          */
 886                         if (!can_scale)
 887                                 crtc_w &= ~1;
 888
 889                         if (crtc_w == 0)
 890                                 state->base.visible = false;
 891                 }
 892         }
 893
 894         /* Check size restrictions when scaling */
 895         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 896                 unsigned int width_bytes;
 897                 int cpp = fb->format->cpp[0];
 898
 899                 WARN_ON(!can_scale);
 900
 901                 /* FIXME interlacing min height is 6 */
 902
 903                 if (crtc_w < 3 || crtc_h < 3)
 904                         state->base.visible = false;
 905
 906                 if (src_w < 3 || src_h < 3)
 907                         state->base.visible = false;
 908
 909                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 910
 911                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 912                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 913                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 914                         return -EINVAL;
 915                 }
 916         }
 917
 918         if (state->base.visible) {
 919                 src->x1 = src_x << 16;
 920                 src->x2 = (src_x + src_w) << 16;
 921                 src->y1 = src_y << 16;
 922                 src->y2 = (src_y + src_h) << 16;
 923         }
 924
 925         dst->x1 = crtc_x;
 926         dst->x2 = crtc_x + crtc_w;
 927         dst->y1 = crtc_y;
 928         dst->y2 = crtc_y + crtc_h;
 929
 930         if (INTEL_GEN(dev_priv) >= 9) {
 931                 ret = skl_check_plane_surface(state);
 932                 if (ret)
 933                         return ret;
 934         }
 935
 936         return 0;
 937 }
 938
 939 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 940                               struct drm_file *file_priv)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(dev);
 943         struct drm_intel_sprite_colorkey *set = data;
 944         struct drm_plane *plane;
 945         struct drm_plane_state *plane_state;
 946         struct drm_atomic_state *state;
 947         struct drm_modeset_acquire_ctx ctx;
 948         int ret = 0;
 949
 950         /* Make sure we don't try to enable both src & dest simultaneously */
 951         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 952                 return -EINVAL;
 953
 954         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 955             set->flags & I915_SET_COLORKEY_DESTINATION)
 956                 return -EINVAL;
 957
 958         plane = drm_plane_find(dev, set->plane_id);
 959         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 960                 return -ENOENT;
 961
 962         drm_modeset_acquire_init(&ctx, 0);
 963
 964         state = drm_atomic_state_alloc(plane->dev);
 965         if (!state) {
 966                 ret = -ENOMEM;
 967                 goto out;
 968         }
 969         state->acquire_ctx = &ctx;
 970
 971         while (1) {
 972                 plane_state = drm_atomic_get_plane_state(state, plane);
 973                 ret = PTR_ERR_OR_ZERO(plane_state);
 974                 if (!ret) {
 975                         to_intel_plane_state(plane_state)->ckey = *set;
 976                         ret = drm_atomic_commit(state);
 977                 }
 978
 979                 if (ret != -EDEADLK)
 980                         break;
 981
 982                 drm_atomic_state_clear(state);
 983                 drm_modeset_backoff(&ctx);
 984         }
 985
 986         drm_atomic_state_put(state);
 987 out:
 988         drm_modeset_drop_locks(&ctx);
 989         drm_modeset_acquire_fini(&ctx);
 990         return ret;
 991 }
 992
 993 static const uint32_t ilk_plane_formats[] = {
 994         DRM_FORMAT_XRGB8888,
 995         DRM_FORMAT_YUYV,
 996         DRM_FORMAT_YVYU,
 997         DRM_FORMAT_UYVY,
 998         DRM_FORMAT_VYUY,
 999 };
1000
1001 static const uint32_t snb_plane_formats[] = {
1002         DRM_FORMAT_XBGR8888,
1003         DRM_FORMAT_XRGB8888,
1004         DRM_FORMAT_YUYV,
1005         DRM_FORMAT_YVYU,
1006         DRM_FORMAT_UYVY,
1007         DRM_FORMAT_VYUY,
1008 };
1009
1010 static const uint32_t vlv_plane_formats[] = {
1011         DRM_FORMAT_RGB565,
1012         DRM_FORMAT_ABGR8888,
1013         DRM_FORMAT_ARGB8888,
1014         DRM_FORMAT_XBGR8888,
1015         DRM_FORMAT_XRGB8888,
1016         DRM_FORMAT_XBGR2101010,
1017         DRM_FORMAT_ABGR2101010,
1018         DRM_FORMAT_YUYV,
1019         DRM_FORMAT_YVYU,
1020         DRM_FORMAT_UYVY,
1021         DRM_FORMAT_VYUY,
1022 };
1023
1024 static uint32_t skl_plane_formats[] = {
1025         DRM_FORMAT_RGB565,
1026         DRM_FORMAT_ABGR8888,
1027         DRM_FORMAT_ARGB8888,
1028         DRM_FORMAT_XBGR8888,
1029         DRM_FORMAT_XRGB8888,
1030         DRM_FORMAT_YUYV,
1031         DRM_FORMAT_YVYU,
1032         DRM_FORMAT_UYVY,
1033         DRM_FORMAT_VYUY,
1034 };
1035
1036 struct intel_plane *
1037 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1038                           enum pipe pipe, int plane)
1039 {
1040         struct intel_plane *intel_plane = NULL;
1041         struct intel_plane_state *state = NULL;
1042         unsigned long possible_crtcs;
1043         const uint32_t *plane_formats;
1044         unsigned int supported_rotations;
1045         int num_plane_formats;
1046         int ret;
1047
1048         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1049         if (!intel_plane) {
1050                 ret = -ENOMEM;
1051                 goto fail;
1052         }
1053
1054         state = intel_create_plane_state(&intel_plane->base);
1055         if (!state) {
1056                 ret = -ENOMEM;
1057                 goto fail;
1058         }
1059         intel_plane->base.state = &state->base;
1060
1061         if (INTEL_GEN(dev_priv) >= 9) {
1062                 intel_plane->can_scale = true;
1063                 state->scaler_id = -1;
1064
1065                 intel_plane->update_plane = skl_update_plane;
1066                 intel_plane->disable_plane = skl_disable_plane;
1067
1068                 plane_formats = skl_plane_formats;
1069                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1070         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1071                 intel_plane->can_scale = false;
1072                 intel_plane->max_downscale = 1;
1073
1074                 intel_plane->update_plane = vlv_update_plane;
1075                 intel_plane->disable_plane = vlv_disable_plane;
1076
1077                 plane_formats = vlv_plane_formats;
1078                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1079         } else if (INTEL_GEN(dev_priv) >= 7) {
1080                 if (IS_IVYBRIDGE(dev_priv)) {
1081                         intel_plane->can_scale = true;
1082                         intel_plane->max_downscale = 2;
1083                 } else {
1084                         intel_plane->can_scale = false;
1085                         intel_plane->max_downscale = 1;
1086                 }
1087
1088                 intel_plane->update_plane = ivb_update_plane;
1089                 intel_plane->disable_plane = ivb_disable_plane;
1090
1091                 plane_formats = snb_plane_formats;
1092                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1093         } else {
1094                 intel_plane->can_scale = true;
1095                 intel_plane->max_downscale = 16;
1096
1097                 intel_plane->update_plane = ilk_update_plane;
1098                 intel_plane->disable_plane = ilk_disable_plane;
1099
1100                 if (IS_GEN6(dev_priv)) {
1101                         plane_formats = snb_plane_formats;
1102                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1103                 } else {
1104                         plane_formats = ilk_plane_formats;
1105                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1106                 }
1107         }
1108
1109         if (INTEL_GEN(dev_priv) >= 9) {
1110                 supported_rotations =
1111                         DRM_ROTATE_0 | DRM_ROTATE_90 |
1112                         DRM_ROTATE_180 | DRM_ROTATE_270;
1113         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1114                 supported_rotations =
1115                         DRM_ROTATE_0 | DRM_ROTATE_180 |
1116                         DRM_REFLECT_X;
1117         } else {
1118                 supported_rotations =
1119                         DRM_ROTATE_0 | DRM_ROTATE_180;
1120         }
1121
1122         intel_plane->pipe = pipe;
1123         intel_plane->plane = plane;
1124         intel_plane->id = PLANE_SPRITE0 + plane;
1125         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1126         intel_plane->check_plane = intel_check_sprite_plane;
1127
1128         possible_crtcs = (1 << pipe);
1129
1130         if (INTEL_GEN(dev_priv) >= 9)
1131                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1132                                                possible_crtcs, &intel_plane_funcs,
1133                                                plane_formats, num_plane_formats,
1134                                                DRM_PLANE_TYPE_OVERLAY,
1135                                                "plane %d%c", plane + 2, pipe_name(pipe));
1136         else
1137                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1138                                                possible_crtcs, &intel_plane_funcs,
1139                                                plane_formats, num_plane_formats,
1140                                                DRM_PLANE_TYPE_OVERLAY,
1141                                                "sprite %c", sprite_name(pipe, plane));
1142         if (ret)
1143                 goto fail;
1144
1145         drm_plane_create_rotation_property(&intel_plane->base,
1146                                            DRM_ROTATE_0,
1147                                            supported_rotations);
1148
1149         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1150
1151         return intel_plane;
1152
1153 fail:
1154         kfree(state);
1155         kfree(intel_plane);
1156
1157         return ERR_PTR(ret);
1158 }