2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
94 return container_of(panel, struct panel_simple, base);
97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
119 drm_display_mode_from_videomode(&vm, mode);
121 mode->type |= DRM_MODE_TYPE_DRIVER;
123 if (panel->desc->num_timings == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
126 drm_mode_probed_add(connector, mode);
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
133 mode = drm_mode_duplicate(drm, m);
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_set_name(mode);
147 drm_mode_probed_add(connector, mode);
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
162 static int panel_simple_disable(struct drm_panel *panel)
164 struct panel_simple *p = to_panel_simple(panel);
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
183 static int panel_simple_unprepare(struct drm_panel *panel)
185 struct panel_simple *p = to_panel_simple(panel);
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
193 regulator_disable(p->supply);
195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
203 static int panel_simple_prepare(struct drm_panel *panel)
205 struct panel_simple *p = to_panel_simple(panel);
211 err = regulator_enable(p->supply);
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
218 gpiod_set_value_cansleep(p->enable_gpio, 1);
220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
228 static int panel_simple_enable(struct drm_panel *panel)
230 struct panel_simple *p = to_panel_simple(panel);
235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
249 static int panel_simple_get_modes(struct drm_panel *panel)
251 struct panel_simple *p = to_panel_simple(panel);
254 /* probe EDID if a DDC bus is available */
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
257 drm_mode_connector_update_edid_property(panel->connector, edid);
259 num += drm_add_edid_modes(panel->connector, edid);
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
270 static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
274 struct panel_simple *p = to_panel_simple(panel);
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
284 return p->desc->num_timings;
287 static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
293 .get_timings = panel_simple_get_timings,
296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
306 panel->enabled = false;
307 panel->prepared = false;
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
318 dev_err(dev, "failed to request GPIO: %d\n", err);
322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
327 if (!panel->backlight)
328 return -EPROBE_DEFER;
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
346 err = drm_panel_add(&panel->base);
350 dev_set_drvdata(dev, panel);
356 put_device(&panel->ddc->dev);
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
364 static int panel_simple_remove(struct device *dev)
366 struct panel_simple *panel = dev_get_drvdata(dev);
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
371 panel_simple_disable(&panel->base);
374 put_device(&panel->ddc->dev);
376 if (panel->backlight)
377 put_device(&panel->backlight->dev);
382 static void panel_simple_shutdown(struct device *dev)
384 struct panel_simple *panel = dev_get_drvdata(dev);
386 panel_simple_disable(&panel->base);
389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
392 .hsync_start = 480 + 2,
393 .hsync_end = 480 + 2 + 41,
394 .htotal = 480 + 2 + 41 + 2,
396 .vsync_start = 272 + 2,
397 .vsync_end = 272 + 2 + 10,
398 .vtotal = 272 + 2 + 10 + 2,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
404 .modes = &ire_am_480272h3tmqw_t01h_mode,
411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
414 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
417 .hsync_start = (ha) + (hfp), \
418 .hsync_end = (ha) + (hfp) + (hs), \
419 .htotal = (ha) + (hfp) + (hs) + (hbp), \
421 .vsync_start = (va) + (vfp), \
422 .vsync_end = (va) + (vfp) + (vs), \
423 .vtotal = (va) + (vfp) + (vs) + (vbp), \
428 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
431 .hsync_start = 800 + 0,
432 .hsync_end = 800 + 0 + 255,
433 .htotal = 800 + 0 + 255 + 0,
435 .vsync_start = 480 + 2,
436 .vsync_end = 480 + 2 + 45,
437 .vtotal = 480 + 2 + 45 + 0,
439 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
442 static const struct panel_desc ampire_am800480r3tmqwa1h = {
443 .modes = &ire_am800480r3tmqwa1h_mode,
450 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
453 static const struct drm_display_mode auo_b101aw03_mode = {
456 .hsync_start = 1024 + 156,
457 .hsync_end = 1024 + 156 + 8,
458 .htotal = 1024 + 156 + 8 + 156,
460 .vsync_start = 600 + 16,
461 .vsync_end = 600 + 16 + 6,
462 .vtotal = 600 + 16 + 6 + 16,
466 static const struct panel_desc auo_b101aw03 = {
467 .modes = &auo_b101aw03_mode,
476 static const struct drm_display_mode auo_b101ean01_mode = {
479 .hsync_start = 1280 + 119,
480 .hsync_end = 1280 + 119 + 32,
481 .htotal = 1280 + 119 + 32 + 21,
483 .vsync_start = 800 + 4,
484 .vsync_end = 800 + 4 + 20,
485 .vtotal = 800 + 4 + 20 + 8,
489 static const struct panel_desc auo_b101ean01 = {
490 .modes = &auo_b101ean01_mode,
499 static const struct drm_display_mode auo_b101xtn01_mode = {
502 .hsync_start = 1366 + 20,
503 .hsync_end = 1366 + 20 + 70,
504 .htotal = 1366 + 20 + 70,
506 .vsync_start = 768 + 14,
507 .vsync_end = 768 + 14 + 42,
508 .vtotal = 768 + 14 + 42,
510 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
513 static const struct panel_desc auo_b101xtn01 = {
514 .modes = &auo_b101xtn01_mode,
523 static const struct drm_display_mode auo_b116xw03_mode = {
526 .hsync_start = 1366 + 40,
527 .hsync_end = 1366 + 40 + 40,
528 .htotal = 1366 + 40 + 40 + 32,
530 .vsync_start = 768 + 10,
531 .vsync_end = 768 + 10 + 12,
532 .vtotal = 768 + 10 + 12 + 6,
536 static const struct panel_desc auo_b116xw03 = {
537 .modes = &auo_b116xw03_mode,
546 static const struct drm_display_mode auo_b133xtn01_mode = {
549 .hsync_start = 1366 + 48,
550 .hsync_end = 1366 + 48 + 32,
551 .htotal = 1366 + 48 + 32 + 20,
553 .vsync_start = 768 + 3,
554 .vsync_end = 768 + 3 + 6,
555 .vtotal = 768 + 3 + 6 + 13,
559 static const struct panel_desc auo_b133xtn01 = {
560 .modes = &auo_b133xtn01_mode,
569 static const struct drm_display_mode auo_b133htn01_mode = {
572 .hsync_start = 1920 + 172,
573 .hsync_end = 1920 + 172 + 80,
574 .htotal = 1920 + 172 + 80 + 60,
576 .vsync_start = 1080 + 25,
577 .vsync_end = 1080 + 25 + 10,
578 .vtotal = 1080 + 25 + 10 + 10,
582 static const struct panel_desc auo_b133htn01 = {
583 .modes = &auo_b133htn01_mode,
597 static const struct display_timing auo_g133han01_timings = {
598 .pixelclock = { 134000000, 141200000, 149000000 },
599 .hactive = { 1920, 1920, 1920 },
600 .hfront_porch = { 39, 58, 77 },
601 .hback_porch = { 59, 88, 117 },
602 .hsync_len = { 28, 42, 56 },
603 .vactive = { 1080, 1080, 1080 },
604 .vfront_porch = { 3, 8, 11 },
605 .vback_porch = { 5, 14, 19 },
606 .vsync_len = { 4, 14, 19 },
609 static const struct panel_desc auo_g133han01 = {
610 .timings = &auo_g133han01_timings,
623 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
626 static const struct display_timing auo_g185han01_timings = {
627 .pixelclock = { 120000000, 144000000, 175000000 },
628 .hactive = { 1920, 1920, 1920 },
629 .hfront_porch = { 18, 60, 74 },
630 .hback_porch = { 12, 44, 54 },
631 .hsync_len = { 10, 24, 32 },
632 .vactive = { 1080, 1080, 1080 },
633 .vfront_porch = { 6, 10, 40 },
634 .vback_porch = { 2, 5, 20 },
635 .vsync_len = { 2, 5, 20 },
638 static const struct panel_desc auo_g185han01 = {
639 .timings = &auo_g185han01_timings,
652 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
655 static const struct display_timing auo_p320hvn03_timings = {
656 .pixelclock = { 106000000, 148500000, 164000000 },
657 .hactive = { 1920, 1920, 1920 },
658 .hfront_porch = { 25, 50, 130 },
659 .hback_porch = { 25, 50, 130 },
660 .hsync_len = { 20, 40, 105 },
661 .vactive = { 1080, 1080, 1080 },
662 .vfront_porch = { 8, 17, 150 },
663 .vback_porch = { 8, 17, 150 },
664 .vsync_len = { 4, 11, 100 },
667 static const struct panel_desc auo_p320hvn03 = {
668 .timings = &auo_p320hvn03_timings,
680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
683 static const struct drm_display_mode auo_t215hvn01_mode = {
686 .hsync_start = 1920 + 88,
687 .hsync_end = 1920 + 88 + 44,
688 .htotal = 1920 + 88 + 44 + 148,
690 .vsync_start = 1080 + 4,
691 .vsync_end = 1080 + 4 + 5,
692 .vtotal = 1080 + 4 + 5 + 36,
696 static const struct panel_desc auo_t215hvn01 = {
697 .modes = &auo_t215hvn01_mode,
710 static const struct drm_display_mode avic_tm070ddh03_mode = {
713 .hsync_start = 1024 + 160,
714 .hsync_end = 1024 + 160 + 4,
715 .htotal = 1024 + 160 + 4 + 156,
717 .vsync_start = 600 + 17,
718 .vsync_end = 600 + 17 + 1,
719 .vtotal = 600 + 17 + 1 + 17,
723 static const struct panel_desc avic_tm070ddh03 = {
724 .modes = &avic_tm070ddh03_mode,
738 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
742 .hsync_start = 1280 + 48,
743 .hsync_end = 1280 + 48 + 32,
744 .htotal = 1280 + 48 + 32 + 80,
746 .vsync_start = 800 + 3,
747 .vsync_end = 800 + 3 + 5,
748 .vtotal = 800 + 3 + 5 + 24,
754 .hsync_start = 1280 + 48,
755 .hsync_end = 1280 + 48 + 32,
756 .htotal = 1280 + 48 + 32 + 80,
758 .vsync_start = 800 + 3,
759 .vsync_end = 800 + 3 + 5,
760 .vtotal = 800 + 3 + 5 + 24,
765 static const struct panel_desc boe_nv101wxmn51 = {
766 .modes = boe_nv101wxmn51_modes,
767 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
780 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
783 .hsync_start = 800 + 49,
784 .hsync_end = 800 + 49 + 33,
785 .htotal = 800 + 49 + 33 + 17,
787 .vsync_start = 1280 + 1,
788 .vsync_end = 1280 + 1 + 7,
789 .vtotal = 1280 + 1 + 7 + 15,
791 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
794 static const struct panel_desc chunghwa_claa070wp03xg = {
795 .modes = &chunghwa_claa070wp03xg_mode,
804 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
807 .hsync_start = 1366 + 58,
808 .hsync_end = 1366 + 58 + 58,
809 .htotal = 1366 + 58 + 58 + 58,
811 .vsync_start = 768 + 4,
812 .vsync_end = 768 + 4 + 4,
813 .vtotal = 768 + 4 + 4 + 4,
817 static const struct panel_desc chunghwa_claa101wa01a = {
818 .modes = &chunghwa_claa101wa01a_mode,
827 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
830 .hsync_start = 1366 + 48,
831 .hsync_end = 1366 + 48 + 32,
832 .htotal = 1366 + 48 + 32 + 20,
834 .vsync_start = 768 + 16,
835 .vsync_end = 768 + 16 + 8,
836 .vtotal = 768 + 16 + 8 + 16,
840 static const struct panel_desc chunghwa_claa101wb01 = {
841 .modes = &chunghwa_claa101wb01_mode,
850 static const struct drm_display_mode edt_et057090dhu_mode = {
853 .hsync_start = 640 + 16,
854 .hsync_end = 640 + 16 + 30,
855 .htotal = 640 + 16 + 30 + 114,
857 .vsync_start = 480 + 10,
858 .vsync_end = 480 + 10 + 3,
859 .vtotal = 480 + 10 + 3 + 32,
861 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
864 static const struct panel_desc edt_et057090dhu = {
865 .modes = &edt_et057090dhu_mode,
872 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
873 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
876 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
879 .hsync_start = 800 + 40,
880 .hsync_end = 800 + 40 + 128,
881 .htotal = 800 + 40 + 128 + 88,
883 .vsync_start = 480 + 10,
884 .vsync_end = 480 + 10 + 2,
885 .vtotal = 480 + 10 + 2 + 33,
887 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
890 static const struct panel_desc edt_etm0700g0dh6 = {
891 .modes = &edt_etm0700g0dh6_mode,
898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
899 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
902 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
905 .hsync_start = 800 + 168,
906 .hsync_end = 800 + 168 + 64,
907 .htotal = 800 + 168 + 64 + 88,
909 .vsync_start = 480 + 37,
910 .vsync_end = 480 + 37 + 2,
911 .vtotal = 480 + 37 + 2 + 8,
915 static const struct panel_desc foxlink_fl500wvr00_a0t = {
916 .modes = &foxlink_fl500wvr00_a0t_mode,
923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
926 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
929 .hsync_start = 480 + 5,
930 .hsync_end = 480 + 5 + 1,
931 .htotal = 480 + 5 + 1 + 40,
933 .vsync_start = 272 + 8,
934 .vsync_end = 272 + 8 + 1,
935 .vtotal = 272 + 8 + 1 + 8,
939 static const struct panel_desc giantplus_gpg482739qs5 = {
940 .modes = &giantplus_gpg482739qs5_mode,
947 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
950 static const struct display_timing hannstar_hsd070pww1_timing = {
951 .pixelclock = { 64300000, 71100000, 82000000 },
952 .hactive = { 1280, 1280, 1280 },
953 .hfront_porch = { 1, 1, 10 },
954 .hback_porch = { 1, 1, 10 },
956 * According to the data sheet, the minimum horizontal blanking interval
957 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
958 * minimum working horizontal blanking interval to be 60 clocks.
960 .hsync_len = { 58, 158, 661 },
961 .vactive = { 800, 800, 800 },
962 .vfront_porch = { 1, 1, 10 },
963 .vback_porch = { 1, 1, 10 },
964 .vsync_len = { 1, 21, 203 },
965 .flags = DISPLAY_FLAGS_DE_HIGH,
968 static const struct panel_desc hannstar_hsd070pww1 = {
969 .timings = &hannstar_hsd070pww1_timing,
976 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
979 static const struct display_timing hannstar_hsd100pxn1_timing = {
980 .pixelclock = { 55000000, 65000000, 75000000 },
981 .hactive = { 1024, 1024, 1024 },
982 .hfront_porch = { 40, 40, 40 },
983 .hback_porch = { 220, 220, 220 },
984 .hsync_len = { 20, 60, 100 },
985 .vactive = { 768, 768, 768 },
986 .vfront_porch = { 7, 7, 7 },
987 .vback_porch = { 21, 21, 21 },
988 .vsync_len = { 10, 10, 10 },
989 .flags = DISPLAY_FLAGS_DE_HIGH,
992 static const struct panel_desc hannstar_hsd100pxn1 = {
993 .timings = &hannstar_hsd100pxn1_timing,
1000 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1003 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1006 .hsync_start = 800 + 85,
1007 .hsync_end = 800 + 85 + 86,
1008 .htotal = 800 + 85 + 86 + 85,
1010 .vsync_start = 480 + 16,
1011 .vsync_end = 480 + 16 + 13,
1012 .vtotal = 480 + 16 + 13 + 16,
1016 static const struct panel_desc hitachi_tx23d38vm0caa = {
1017 .modes = &hitachi_tx23d38vm0caa_mode,
1026 static const struct drm_display_mode innolux_at043tn24_mode = {
1029 .hsync_start = 480 + 2,
1030 .hsync_end = 480 + 2 + 41,
1031 .htotal = 480 + 2 + 41 + 2,
1033 .vsync_start = 272 + 2,
1034 .vsync_end = 272 + 2 + 11,
1035 .vtotal = 272 + 2 + 11 + 2,
1037 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1040 static const struct panel_desc innolux_at043tn24 = {
1041 .modes = &innolux_at043tn24_mode,
1048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1051 static const struct drm_display_mode innolux_at070tn92_mode = {
1054 .hsync_start = 800 + 210,
1055 .hsync_end = 800 + 210 + 20,
1056 .htotal = 800 + 210 + 20 + 46,
1058 .vsync_start = 480 + 22,
1059 .vsync_end = 480 + 22 + 10,
1060 .vtotal = 480 + 22 + 23 + 10,
1064 static const struct panel_desc innolux_at070tn92 = {
1065 .modes = &innolux_at070tn92_mode,
1071 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1074 static const struct display_timing innolux_g101ice_l01_timing = {
1075 .pixelclock = { 60400000, 71100000, 74700000 },
1076 .hactive = { 1280, 1280, 1280 },
1077 .hfront_porch = { 41, 80, 100 },
1078 .hback_porch = { 40, 79, 99 },
1079 .hsync_len = { 1, 1, 1 },
1080 .vactive = { 800, 800, 800 },
1081 .vfront_porch = { 5, 11, 14 },
1082 .vback_porch = { 4, 11, 14 },
1083 .vsync_len = { 1, 1, 1 },
1084 .flags = DISPLAY_FLAGS_DE_HIGH,
1087 static const struct panel_desc innolux_g101ice_l01 = {
1088 .timings = &innolux_g101ice_l01_timing,
1099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1102 static const struct display_timing innolux_g121i1_l01_timing = {
1103 .pixelclock = { 67450000, 71000000, 74550000 },
1104 .hactive = { 1280, 1280, 1280 },
1105 .hfront_porch = { 40, 80, 160 },
1106 .hback_porch = { 39, 79, 159 },
1107 .hsync_len = { 1, 1, 1 },
1108 .vactive = { 800, 800, 800 },
1109 .vfront_porch = { 5, 11, 100 },
1110 .vback_porch = { 4, 11, 99 },
1111 .vsync_len = { 1, 1, 1 },
1114 static const struct panel_desc innolux_g121i1_l01 = {
1115 .timings = &innolux_g121i1_l01_timing,
1126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1129 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1132 .hsync_start = 1024 + 0,
1133 .hsync_end = 1024 + 1,
1134 .htotal = 1024 + 0 + 1 + 320,
1136 .vsync_start = 768 + 38,
1137 .vsync_end = 768 + 38 + 1,
1138 .vtotal = 768 + 38 + 1 + 0,
1140 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1143 static const struct panel_desc innolux_g121x1_l03 = {
1144 .modes = &innolux_g121x1_l03_mode,
1158 static const struct drm_display_mode innolux_n116bge_mode = {
1161 .hsync_start = 1366 + 136,
1162 .hsync_end = 1366 + 136 + 30,
1163 .htotal = 1366 + 136 + 30 + 60,
1165 .vsync_start = 768 + 8,
1166 .vsync_end = 768 + 8 + 12,
1167 .vtotal = 768 + 8 + 12 + 12,
1169 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1172 static const struct panel_desc innolux_n116bge = {
1173 .modes = &innolux_n116bge_mode,
1182 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1185 .hsync_start = 1366 + 16,
1186 .hsync_end = 1366 + 16 + 34,
1187 .htotal = 1366 + 16 + 34 + 50,
1189 .vsync_start = 768 + 2,
1190 .vsync_end = 768 + 2 + 6,
1191 .vtotal = 768 + 2 + 6 + 12,
1195 static const struct panel_desc innolux_n156bge_l21 = {
1196 .modes = &innolux_n156bge_l21_mode,
1205 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1208 .hsync_start = 1024 + 128,
1209 .hsync_end = 1024 + 128 + 64,
1210 .htotal = 1024 + 128 + 64 + 128,
1212 .vsync_start = 600 + 16,
1213 .vsync_end = 600 + 16 + 4,
1214 .vtotal = 600 + 16 + 4 + 16,
1218 static const struct panel_desc innolux_zj070na_01p = {
1219 .modes = &innolux_zj070na_01p_mode,
1228 static const struct display_timing kyo_tcg121xglp_timing = {
1229 .pixelclock = { 52000000, 65000000, 71000000 },
1230 .hactive = { 1024, 1024, 1024 },
1231 .hfront_porch = { 2, 2, 2 },
1232 .hback_porch = { 2, 2, 2 },
1233 .hsync_len = { 86, 124, 244 },
1234 .vactive = { 768, 768, 768 },
1235 .vfront_porch = { 2, 2, 2 },
1236 .vback_porch = { 2, 2, 2 },
1237 .vsync_len = { 6, 34, 73 },
1238 .flags = DISPLAY_FLAGS_DE_HIGH,
1241 static const struct panel_desc kyo_tcg121xglp = {
1242 .timings = &kyo_tcg121xglp_timing,
1249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1252 static const struct drm_display_mode lg_lb070wv8_mode = {
1255 .hsync_start = 800 + 88,
1256 .hsync_end = 800 + 88 + 80,
1257 .htotal = 800 + 88 + 80 + 88,
1259 .vsync_start = 480 + 10,
1260 .vsync_end = 480 + 10 + 25,
1261 .vtotal = 480 + 10 + 25 + 10,
1265 static const struct panel_desc lg_lb070wv8 = {
1266 .modes = &lg_lb070wv8_mode,
1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1276 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1279 .hsync_start = 1536 + 12,
1280 .hsync_end = 1536 + 12 + 16,
1281 .htotal = 1536 + 12 + 16 + 48,
1283 .vsync_start = 2048 + 8,
1284 .vsync_end = 2048 + 8 + 4,
1285 .vtotal = 2048 + 8 + 4 + 8,
1287 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1290 static const struct panel_desc lg_lp079qx1_sp0v = {
1291 .modes = &lg_lp079qx1_sp0v_mode,
1299 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1302 .hsync_start = 2048 + 150,
1303 .hsync_end = 2048 + 150 + 5,
1304 .htotal = 2048 + 150 + 5 + 5,
1306 .vsync_start = 1536 + 3,
1307 .vsync_end = 1536 + 3 + 1,
1308 .vtotal = 1536 + 3 + 1 + 9,
1312 static const struct panel_desc lg_lp097qx1_spa1 = {
1313 .modes = &lg_lp097qx1_spa1_mode,
1321 static const struct drm_display_mode lg_lp120up1_mode = {
1324 .hsync_start = 1920 + 40,
1325 .hsync_end = 1920 + 40 + 40,
1326 .htotal = 1920 + 40 + 40+ 80,
1328 .vsync_start = 1280 + 4,
1329 .vsync_end = 1280 + 4 + 4,
1330 .vtotal = 1280 + 4 + 4 + 12,
1334 static const struct panel_desc lg_lp120up1 = {
1335 .modes = &lg_lp120up1_mode,
1344 static const struct drm_display_mode lg_lp129qe_mode = {
1347 .hsync_start = 2560 + 48,
1348 .hsync_end = 2560 + 48 + 32,
1349 .htotal = 2560 + 48 + 32 + 80,
1351 .vsync_start = 1700 + 3,
1352 .vsync_end = 1700 + 3 + 10,
1353 .vtotal = 1700 + 3 + 10 + 36,
1357 static const struct panel_desc lg_lp129qe = {
1358 .modes = &lg_lp129qe_mode,
1367 static const struct display_timing nec_nl12880bc20_05_timing = {
1368 .pixelclock = { 67000000, 71000000, 75000000 },
1369 .hactive = { 1280, 1280, 1280 },
1370 .hfront_porch = { 2, 30, 30 },
1371 .hback_porch = { 6, 100, 100 },
1372 .hsync_len = { 2, 30, 30 },
1373 .vactive = { 800, 800, 800 },
1374 .vfront_porch = { 5, 5, 5 },
1375 .vback_porch = { 11, 11, 11 },
1376 .vsync_len = { 7, 7, 7 },
1379 static const struct panel_desc nec_nl12880bc20_05 = {
1380 .timings = &nec_nl12880bc20_05_timing,
1391 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1394 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1397 .hsync_start = 480 + 2,
1398 .hsync_end = 480 + 2 + 41,
1399 .htotal = 480 + 2 + 41 + 2,
1401 .vsync_start = 272 + 2,
1402 .vsync_end = 272 + 2 + 4,
1403 .vtotal = 272 + 2 + 4 + 2,
1405 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1408 static const struct panel_desc nec_nl4827hc19_05b = {
1409 .modes = &nec_nl4827hc19_05b_mode,
1416 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1417 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1420 static const struct drm_display_mode netron_dy_e231732_mode = {
1423 .hsync_start = 1024 + 160,
1424 .hsync_end = 1024 + 160 + 70,
1425 .htotal = 1024 + 160 + 70 + 90,
1427 .vsync_start = 600 + 127,
1428 .vsync_end = 600 + 127 + 20,
1429 .vtotal = 600 + 127 + 20 + 3,
1433 static const struct panel_desc netron_dy_e231732 = {
1434 .modes = &netron_dy_e231732_mode,
1440 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1443 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1444 .pixelclock = { 130000000, 148350000, 163000000 },
1445 .hactive = { 1920, 1920, 1920 },
1446 .hfront_porch = { 80, 100, 100 },
1447 .hback_porch = { 100, 120, 120 },
1448 .hsync_len = { 50, 60, 60 },
1449 .vactive = { 1080, 1080, 1080 },
1450 .vfront_porch = { 12, 30, 30 },
1451 .vback_porch = { 4, 10, 10 },
1452 .vsync_len = { 4, 5, 5 },
1455 static const struct panel_desc nlt_nl192108ac18_02d = {
1456 .timings = &nlt_nl192108ac18_02d_timing,
1466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1469 static const struct drm_display_mode nvd_9128_mode = {
1472 .hsync_start = 800 + 130,
1473 .hsync_end = 800 + 130 + 98,
1474 .htotal = 800 + 0 + 130 + 98,
1476 .vsync_start = 480 + 10,
1477 .vsync_end = 480 + 10 + 50,
1478 .vtotal = 480 + 0 + 10 + 50,
1481 static const struct panel_desc nvd_9128 = {
1482 .modes = &nvd_9128_mode,
1489 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1492 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1493 .pixelclock = { 30000000, 30000000, 40000000 },
1494 .hactive = { 800, 800, 800 },
1495 .hfront_porch = { 40, 40, 40 },
1496 .hback_porch = { 40, 40, 40 },
1497 .hsync_len = { 1, 48, 48 },
1498 .vactive = { 480, 480, 480 },
1499 .vfront_porch = { 13, 13, 13 },
1500 .vback_porch = { 29, 29, 29 },
1501 .vsync_len = { 3, 3, 3 },
1502 .flags = DISPLAY_FLAGS_DE_HIGH,
1505 static const struct panel_desc okaya_rs800480t_7x0gp = {
1506 .timings = &okaya_rs800480t_7x0gp_timing,
1519 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1522 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1525 .hsync_start = 480 + 5,
1526 .hsync_end = 480 + 5 + 30,
1527 .htotal = 480 + 5 + 30 + 10,
1529 .vsync_start = 272 + 8,
1530 .vsync_end = 272 + 8 + 5,
1531 .vtotal = 272 + 8 + 5 + 3,
1535 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1536 .modes = &olimex_lcd_olinuxino_43ts_mode,
1542 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1546 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1547 * pixel clocks, but this is the timing that was being used in the Adafruit
1548 * installation instructions.
1550 static const struct drm_display_mode ontat_yx700wv03_mode = {
1561 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1566 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1568 static const struct panel_desc ontat_yx700wv03 = {
1569 .modes = &ontat_yx700wv03_mode,
1576 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1579 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1582 .hsync_start = 480 + 10,
1583 .hsync_end = 480 + 10 + 10,
1584 .htotal = 480 + 10 + 10 + 15,
1586 .vsync_start = 800 + 3,
1587 .vsync_end = 800 + 3 + 3,
1588 .vtotal = 800 + 3 + 3 + 3,
1592 static const struct panel_desc ortustech_com43h4m85ulc = {
1593 .modes = &ortustech_com43h4m85ulc_mode,
1600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1601 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1604 static const struct drm_display_mode qd43003c0_40_mode = {
1607 .hsync_start = 480 + 8,
1608 .hsync_end = 480 + 8 + 4,
1609 .htotal = 480 + 8 + 4 + 39,
1611 .vsync_start = 272 + 4,
1612 .vsync_end = 272 + 4 + 10,
1613 .vtotal = 272 + 4 + 10 + 2,
1617 static const struct panel_desc qd43003c0_40 = {
1618 .modes = &qd43003c0_40_mode,
1625 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1628 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1631 .hsync_start = 2560 + 48,
1632 .hsync_end = 2560 + 48 + 32,
1633 .htotal = 2560 + 48 + 32 + 80,
1635 .vsync_start = 1600 + 2,
1636 .vsync_end = 1600 + 2 + 5,
1637 .vtotal = 1600 + 2 + 5 + 57,
1641 static const struct panel_desc samsung_lsn122dl01_c01 = {
1642 .modes = &samsung_lsn122dl01_c01_mode,
1650 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1653 .hsync_start = 1024 + 24,
1654 .hsync_end = 1024 + 24 + 136,
1655 .htotal = 1024 + 24 + 136 + 160,
1657 .vsync_start = 600 + 3,
1658 .vsync_end = 600 + 3 + 6,
1659 .vtotal = 600 + 3 + 6 + 61,
1663 static const struct panel_desc samsung_ltn101nt05 = {
1664 .modes = &samsung_ltn101nt05_mode,
1673 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1676 .hsync_start = 1366 + 64,
1677 .hsync_end = 1366 + 64 + 48,
1678 .htotal = 1366 + 64 + 48 + 128,
1680 .vsync_start = 768 + 2,
1681 .vsync_end = 768 + 2 + 5,
1682 .vtotal = 768 + 2 + 5 + 17,
1686 static const struct panel_desc samsung_ltn140at29_301 = {
1687 .modes = &samsung_ltn140at29_301_mode,
1696 static const struct display_timing sharp_lq101k1ly04_timing = {
1697 .pixelclock = { 60000000, 65000000, 80000000 },
1698 .hactive = { 1280, 1280, 1280 },
1699 .hfront_porch = { 20, 20, 20 },
1700 .hback_porch = { 20, 20, 20 },
1701 .hsync_len = { 10, 10, 10 },
1702 .vactive = { 800, 800, 800 },
1703 .vfront_porch = { 4, 4, 4 },
1704 .vback_porch = { 4, 4, 4 },
1705 .vsync_len = { 4, 4, 4 },
1706 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1709 static const struct panel_desc sharp_lq101k1ly04 = {
1710 .timings = &sharp_lq101k1ly04_timing,
1717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1720 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1723 .hsync_start = 2400 + 48,
1724 .hsync_end = 2400 + 48 + 32,
1725 .htotal = 2400 + 48 + 32 + 80,
1727 .vsync_start = 1600 + 3,
1728 .vsync_end = 1600 + 3 + 10,
1729 .vtotal = 1600 + 3 + 10 + 33,
1731 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1734 static const struct panel_desc sharp_lq123p1jx31 = {
1735 .modes = &sharp_lq123p1jx31_mode,
1749 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1752 .hsync_start = 1024 + 168,
1753 .hsync_end = 1024 + 168 + 64,
1754 .htotal = 1024 + 168 + 64 + 88,
1756 .vsync_start = 768 + 37,
1757 .vsync_end = 768 + 37 + 2,
1758 .vtotal = 768 + 37 + 2 + 8,
1762 static const struct panel_desc sharp_lq150x1lg11 = {
1763 .modes = &sharp_lq150x1lg11_mode,
1770 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1773 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1776 .hsync_start = 800 + 1,
1777 .hsync_end = 800 + 1 + 64,
1778 .htotal = 800 + 1 + 64 + 64,
1780 .vsync_start = 480 + 1,
1781 .vsync_end = 480 + 1 + 23,
1782 .vtotal = 480 + 1 + 23 + 22,
1786 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1787 .modes = &shelly_sca07010_bfn_lnn_mode,
1793 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1796 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1799 .hsync_start = 1920 + 16,
1800 .hsync_end = 1920 + 16 + 16,
1801 .htotal = 1920 + 16 + 16 + 32,
1803 .vsync_start = 1200 + 15,
1804 .vsync_end = 1200 + 15 + 2,
1805 .vtotal = 1200 + 15 + 2 + 18,
1807 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1810 static const struct panel_desc starry_kr122ea0sra = {
1811 .modes = &starry_kr122ea0sra_mode,
1818 .prepare = 10 + 200,
1820 .unprepare = 10 + 500,
1824 static const struct display_timing tianma_tm070jdhg30_timing = {
1825 .pixelclock = { 62600000, 68200000, 78100000 },
1826 .hactive = { 1280, 1280, 1280 },
1827 .hfront_porch = { 15, 64, 159 },
1828 .hback_porch = { 5, 5, 5 },
1829 .hsync_len = { 1, 1, 256 },
1830 .vactive = { 800, 800, 800 },
1831 .vfront_porch = { 3, 40, 99 },
1832 .vback_porch = { 2, 2, 2 },
1833 .vsync_len = { 1, 1, 128 },
1834 .flags = DISPLAY_FLAGS_DE_HIGH,
1837 static const struct panel_desc tianma_tm070jdhg30 = {
1838 .timings = &tianma_tm070jdhg30_timing,
1845 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1848 static const struct drm_display_mode tpk_f07a_0102_mode = {
1851 .hsync_start = 800 + 40,
1852 .hsync_end = 800 + 40 + 128,
1853 .htotal = 800 + 40 + 128 + 88,
1855 .vsync_start = 480 + 10,
1856 .vsync_end = 480 + 10 + 2,
1857 .vtotal = 480 + 10 + 2 + 33,
1861 static const struct panel_desc tpk_f07a_0102 = {
1862 .modes = &tpk_f07a_0102_mode,
1868 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1871 static const struct drm_display_mode tpk_f10a_0102_mode = {
1874 .hsync_start = 1024 + 176,
1875 .hsync_end = 1024 + 176 + 5,
1876 .htotal = 1024 + 176 + 5 + 88,
1878 .vsync_start = 600 + 20,
1879 .vsync_end = 600 + 20 + 5,
1880 .vtotal = 600 + 20 + 5 + 25,
1884 static const struct panel_desc tpk_f10a_0102 = {
1885 .modes = &tpk_f10a_0102_mode,
1893 static const struct display_timing urt_umsh_8596md_timing = {
1894 .pixelclock = { 33260000, 33260000, 33260000 },
1895 .hactive = { 800, 800, 800 },
1896 .hfront_porch = { 41, 41, 41 },
1897 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1898 .hsync_len = { 71, 128, 128 },
1899 .vactive = { 480, 480, 480 },
1900 .vfront_porch = { 10, 10, 10 },
1901 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1902 .vsync_len = { 2, 2, 2 },
1903 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1904 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1907 static const struct panel_desc urt_umsh_8596md_lvds = {
1908 .timings = &urt_umsh_8596md_timing,
1915 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1918 static const struct panel_desc urt_umsh_8596md_parallel = {
1919 .timings = &urt_umsh_8596md_timing,
1926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1929 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
1932 .hsync_start = 320 + 20,
1933 .hsync_end = 320 + 20 + 30,
1934 .htotal = 320 + 20 + 30 + 38,
1936 .vsync_start = 240 + 4,
1937 .vsync_end = 240 + 4 + 3,
1938 .vtotal = 240 + 4 + 3 + 15,
1940 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1943 static const struct panel_desc winstar_wf35ltiacd = {
1944 .modes = &winstar_wf35ltiacd_mode,
1951 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1954 static const struct of_device_id platform_of_match[] = {
1956 .compatible = "ampire,am-480272h3tmqw-t01h",
1957 .data = &ire_am_480272h3tmqw_t01h,
1959 .compatible = "ampire,am800480r3tmqwa1h",
1960 .data = &ire_am800480r3tmqwa1h,
1962 .compatible = "auo,b101aw03",
1963 .data = &auo_b101aw03,
1965 .compatible = "auo,b101ean01",
1966 .data = &auo_b101ean01,
1968 .compatible = "auo,b101xtn01",
1969 .data = &auo_b101xtn01,
1971 .compatible = "auo,b116xw03",
1972 .data = &auo_b116xw03,
1974 .compatible = "auo,b133htn01",
1975 .data = &auo_b133htn01,
1977 .compatible = "auo,b133xtn01",
1978 .data = &auo_b133xtn01,
1980 .compatible = "auo,g133han01",
1981 .data = &auo_g133han01,
1983 .compatible = "auo,g185han01",
1984 .data = &auo_g185han01,
1986 .compatible = "auo,p320hvn03",
1987 .data = &auo_p320hvn03,
1989 .compatible = "auo,t215hvn01",
1990 .data = &auo_t215hvn01,
1992 .compatible = "avic,tm070ddh03",
1993 .data = &avic_tm070ddh03,
1995 .compatible = "boe,nv101wxmn51",
1996 .data = &boe_nv101wxmn51,
1998 .compatible = "chunghwa,claa070wp03xg",
1999 .data = &chunghwa_claa070wp03xg,
2001 .compatible = "chunghwa,claa101wa01a",
2002 .data = &chunghwa_claa101wa01a
2004 .compatible = "chunghwa,claa101wb01",
2005 .data = &chunghwa_claa101wb01
2007 .compatible = "edt,et057090dhu",
2008 .data = &edt_et057090dhu,
2010 .compatible = "edt,et070080dh6",
2011 .data = &edt_etm0700g0dh6,
2013 .compatible = "edt,etm0700g0dh6",
2014 .data = &edt_etm0700g0dh6,
2016 .compatible = "foxlink,fl500wvr00-a0t",
2017 .data = &foxlink_fl500wvr00_a0t,
2019 .compatible = "giantplus,gpg482739qs5",
2020 .data = &giantplus_gpg482739qs5
2022 .compatible = "hannstar,hsd070pww1",
2023 .data = &hannstar_hsd070pww1,
2025 .compatible = "hannstar,hsd100pxn1",
2026 .data = &hannstar_hsd100pxn1,
2028 .compatible = "hit,tx23d38vm0caa",
2029 .data = &hitachi_tx23d38vm0caa
2031 .compatible = "innolux,at043tn24",
2032 .data = &innolux_at043tn24,
2034 .compatible = "innolux,at070tn92",
2035 .data = &innolux_at070tn92,
2037 .compatible ="innolux,g101ice-l01",
2038 .data = &innolux_g101ice_l01
2040 .compatible ="innolux,g121i1-l01",
2041 .data = &innolux_g121i1_l01
2043 .compatible = "innolux,g121x1-l03",
2044 .data = &innolux_g121x1_l03,
2046 .compatible = "innolux,n116bge",
2047 .data = &innolux_n116bge,
2049 .compatible = "innolux,n156bge-l21",
2050 .data = &innolux_n156bge_l21,
2052 .compatible = "innolux,zj070na-01p",
2053 .data = &innolux_zj070na_01p,
2055 .compatible = "kyo,tcg121xglp",
2056 .data = &kyo_tcg121xglp,
2058 .compatible = "lg,lb070wv8",
2059 .data = &lg_lb070wv8,
2061 .compatible = "lg,lp079qx1-sp0v",
2062 .data = &lg_lp079qx1_sp0v,
2064 .compatible = "lg,lp097qx1-spa1",
2065 .data = &lg_lp097qx1_spa1,
2067 .compatible = "lg,lp120up1",
2068 .data = &lg_lp120up1,
2070 .compatible = "lg,lp129qe",
2071 .data = &lg_lp129qe,
2073 .compatible = "nec,nl12880bc20-05",
2074 .data = &nec_nl12880bc20_05,
2076 .compatible = "nec,nl4827hc19-05b",
2077 .data = &nec_nl4827hc19_05b,
2079 .compatible = "netron-dy,e231732",
2080 .data = &netron_dy_e231732,
2082 .compatible = "nlt,nl192108ac18-02d",
2083 .data = &nlt_nl192108ac18_02d,
2085 .compatible = "nvd,9128",
2088 .compatible = "okaya,rs800480t-7x0gp",
2089 .data = &okaya_rs800480t_7x0gp,
2091 .compatible = "olimex,lcd-olinuxino-43-ts",
2092 .data = &olimex_lcd_olinuxino_43ts,
2094 .compatible = "ontat,yx700wv03",
2095 .data = &ontat_yx700wv03,
2097 .compatible = "ortustech,com43h4m85ulc",
2098 .data = &ortustech_com43h4m85ulc,
2100 .compatible = "qiaodian,qd43003c0-40",
2101 .data = &qd43003c0_40,
2103 .compatible = "samsung,lsn122dl01-c01",
2104 .data = &samsung_lsn122dl01_c01,
2106 .compatible = "samsung,ltn101nt05",
2107 .data = &samsung_ltn101nt05,
2109 .compatible = "samsung,ltn140at29-301",
2110 .data = &samsung_ltn140at29_301,
2112 .compatible = "sharp,lq101k1ly04",
2113 .data = &sharp_lq101k1ly04,
2115 .compatible = "sharp,lq123p1jx31",
2116 .data = &sharp_lq123p1jx31,
2118 .compatible = "sharp,lq150x1lg11",
2119 .data = &sharp_lq150x1lg11,
2121 .compatible = "shelly,sca07010-bfn-lnn",
2122 .data = &shelly_sca07010_bfn_lnn,
2124 .compatible = "starry,kr122ea0sra",
2125 .data = &starry_kr122ea0sra,
2127 .compatible = "tianma,tm070jdhg30",
2128 .data = &tianma_tm070jdhg30,
2130 .compatible = "tpk,f07a-0102",
2131 .data = &tpk_f07a_0102,
2133 .compatible = "tpk,f10a-0102",
2134 .data = &tpk_f10a_0102,
2136 .compatible = "urt,umsh-8596md-t",
2137 .data = &urt_umsh_8596md_parallel,
2139 .compatible = "urt,umsh-8596md-1t",
2140 .data = &urt_umsh_8596md_parallel,
2142 .compatible = "urt,umsh-8596md-7t",
2143 .data = &urt_umsh_8596md_parallel,
2145 .compatible = "urt,umsh-8596md-11t",
2146 .data = &urt_umsh_8596md_lvds,
2148 .compatible = "urt,umsh-8596md-19t",
2149 .data = &urt_umsh_8596md_lvds,
2151 .compatible = "urt,umsh-8596md-20t",
2152 .data = &urt_umsh_8596md_parallel,
2154 .compatible = "winstar,wf35ltiacd",
2155 .data = &winstar_wf35ltiacd,
2160 MODULE_DEVICE_TABLE(of, platform_of_match);
2162 static int panel_simple_platform_probe(struct platform_device *pdev)
2164 const struct of_device_id *id;
2166 id = of_match_node(platform_of_match, pdev->dev.of_node);
2170 return panel_simple_probe(&pdev->dev, id->data);
2173 static int panel_simple_platform_remove(struct platform_device *pdev)
2175 return panel_simple_remove(&pdev->dev);
2178 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2180 panel_simple_shutdown(&pdev->dev);
2183 static struct platform_driver panel_simple_platform_driver = {
2185 .name = "panel-simple",
2186 .of_match_table = platform_of_match,
2188 .probe = panel_simple_platform_probe,
2189 .remove = panel_simple_platform_remove,
2190 .shutdown = panel_simple_platform_shutdown,
2193 struct panel_desc_dsi {
2194 struct panel_desc desc;
2196 unsigned long flags;
2197 enum mipi_dsi_pixel_format format;
2201 static const struct drm_display_mode auo_b080uan01_mode = {
2204 .hsync_start = 1200 + 62,
2205 .hsync_end = 1200 + 62 + 4,
2206 .htotal = 1200 + 62 + 4 + 62,
2208 .vsync_start = 1920 + 9,
2209 .vsync_end = 1920 + 9 + 2,
2210 .vtotal = 1920 + 9 + 2 + 8,
2214 static const struct panel_desc_dsi auo_b080uan01 = {
2216 .modes = &auo_b080uan01_mode,
2224 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2225 .format = MIPI_DSI_FMT_RGB888,
2229 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2232 .hsync_start = 1200 + 120,
2233 .hsync_end = 1200 + 120 + 20,
2234 .htotal = 1200 + 120 + 20 + 21,
2236 .vsync_start = 1920 + 21,
2237 .vsync_end = 1920 + 21 + 3,
2238 .vtotal = 1920 + 21 + 3 + 18,
2240 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2243 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2245 .modes = &boe_tv080wum_nl0_mode,
2252 .flags = MIPI_DSI_MODE_VIDEO |
2253 MIPI_DSI_MODE_VIDEO_BURST |
2254 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2255 .format = MIPI_DSI_FMT_RGB888,
2259 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2262 .hsync_start = 800 + 32,
2263 .hsync_end = 800 + 32 + 1,
2264 .htotal = 800 + 32 + 1 + 57,
2266 .vsync_start = 1280 + 28,
2267 .vsync_end = 1280 + 28 + 1,
2268 .vtotal = 1280 + 28 + 1 + 14,
2272 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2274 .modes = &lg_ld070wx3_sl01_mode,
2282 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2283 .format = MIPI_DSI_FMT_RGB888,
2287 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2290 .hsync_start = 720 + 12,
2291 .hsync_end = 720 + 12 + 4,
2292 .htotal = 720 + 12 + 4 + 112,
2294 .vsync_start = 1280 + 8,
2295 .vsync_end = 1280 + 8 + 4,
2296 .vtotal = 1280 + 8 + 4 + 12,
2300 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2302 .modes = &lg_lh500wx1_sd03_mode,
2310 .flags = MIPI_DSI_MODE_VIDEO,
2311 .format = MIPI_DSI_FMT_RGB888,
2315 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2318 .hsync_start = 1920 + 154,
2319 .hsync_end = 1920 + 154 + 16,
2320 .htotal = 1920 + 154 + 16 + 32,
2322 .vsync_start = 1200 + 17,
2323 .vsync_end = 1200 + 17 + 2,
2324 .vtotal = 1200 + 17 + 2 + 16,
2328 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2330 .modes = &panasonic_vvx10f004b00_mode,
2338 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2339 MIPI_DSI_CLOCK_NON_CONTINUOUS,
2340 .format = MIPI_DSI_FMT_RGB888,
2344 static const struct of_device_id dsi_of_match[] = {
2346 .compatible = "auo,b080uan01",
2347 .data = &auo_b080uan01
2349 .compatible = "boe,tv080wum-nl0",
2350 .data = &boe_tv080wum_nl0
2352 .compatible = "lg,ld070wx3-sl01",
2353 .data = &lg_ld070wx3_sl01
2355 .compatible = "lg,lh500wx1-sd03",
2356 .data = &lg_lh500wx1_sd03
2358 .compatible = "panasonic,vvx10f004b00",
2359 .data = &panasonic_vvx10f004b00
2364 MODULE_DEVICE_TABLE(of, dsi_of_match);
2366 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2368 const struct panel_desc_dsi *desc;
2369 const struct of_device_id *id;
2372 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2378 err = panel_simple_probe(&dsi->dev, &desc->desc);
2382 dsi->mode_flags = desc->flags;
2383 dsi->format = desc->format;
2384 dsi->lanes = desc->lanes;
2386 return mipi_dsi_attach(dsi);
2389 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2393 err = mipi_dsi_detach(dsi);
2395 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2397 return panel_simple_remove(&dsi->dev);
2400 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2402 panel_simple_shutdown(&dsi->dev);
2405 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2407 .name = "panel-simple-dsi",
2408 .of_match_table = dsi_of_match,
2410 .probe = panel_simple_dsi_probe,
2411 .remove = panel_simple_dsi_remove,
2412 .shutdown = panel_simple_dsi_shutdown,
2415 static int __init panel_simple_init(void)
2419 err = platform_driver_register(&panel_simple_platform_driver);
2423 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2424 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2431 module_init(panel_simple_init);
2433 static void __exit panel_simple_exit(void)
2435 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2436 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2438 platform_driver_unregister(&panel_simple_platform_driver);
2440 module_exit(panel_simple_exit);
2442 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2443 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2444 MODULE_LICENSE("GPL and additional rights");