2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
94 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
97 .hsync_start = (ha) + (hfp), \
98 .hsync_end = (ha) + (hfp) + (hs), \
99 .htotal = (ha) + (hfp) + (hs) + (hbp), \
101 .vsync_start = (va) + (vfp), \
102 .vsync_end = (va) + (vfp) + (vs), \
103 .vtotal = (va) + (vfp) + (vs) + (vbp), \
108 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
110 return container_of(panel, struct panel_simple, base);
113 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
115 struct drm_connector *connector = panel->base.connector;
116 struct drm_device *drm = panel->base.drm;
117 struct drm_display_mode *mode;
118 unsigned int i, num = 0;
123 for (i = 0; i < panel->desc->num_timings; i++) {
124 const struct display_timing *dt = &panel->desc->timings[i];
127 videomode_from_timing(dt, &vm);
128 mode = drm_mode_create(drm);
130 dev_err(drm->dev, "failed to add mode %ux%u\n",
131 dt->hactive.typ, dt->vactive.typ);
135 drm_display_mode_from_videomode(&vm, mode);
137 mode->type |= DRM_MODE_TYPE_DRIVER;
139 if (panel->desc->num_timings == 1)
140 mode->type |= DRM_MODE_TYPE_PREFERRED;
142 drm_mode_probed_add(connector, mode);
146 for (i = 0; i < panel->desc->num_modes; i++) {
147 const struct drm_display_mode *m = &panel->desc->modes[i];
149 mode = drm_mode_duplicate(drm, m);
151 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
152 m->hdisplay, m->vdisplay, m->vrefresh);
156 mode->type |= DRM_MODE_TYPE_DRIVER;
158 if (panel->desc->num_modes == 1)
159 mode->type |= DRM_MODE_TYPE_PREFERRED;
161 drm_mode_set_name(mode);
163 drm_mode_probed_add(connector, mode);
167 connector->display_info.bpc = panel->desc->bpc;
168 connector->display_info.width_mm = panel->desc->size.width;
169 connector->display_info.height_mm = panel->desc->size.height;
171 if (panel->bus_fmt_override)
172 drm_display_info_set_bus_formats(&connector->display_info,
173 &panel->bus_fmt_override, 1);
174 else if (panel->desc->bus_format)
175 drm_display_info_set_bus_formats(&connector->display_info,
176 &panel->desc->bus_format, 1);
177 connector->display_info.bus_flags = panel->desc->bus_flags;
182 static int panel_simple_disable(struct drm_panel *panel)
184 struct panel_simple *p = to_panel_simple(panel);
190 p->backlight->props.power = FB_BLANK_POWERDOWN;
191 p->backlight->props.state |= BL_CORE_FBBLANK;
192 backlight_update_status(p->backlight);
195 if (p->desc->delay.disable)
196 msleep(p->desc->delay.disable);
203 static int panel_simple_unprepare(struct drm_panel *panel)
205 struct panel_simple *p = to_panel_simple(panel);
211 gpiod_set_value_cansleep(p->enable_gpio, 0);
213 regulator_disable(p->supply);
215 if (p->desc->delay.unprepare)
216 msleep(p->desc->delay.unprepare);
223 static int panel_simple_prepare(struct drm_panel *panel)
225 struct panel_simple *p = to_panel_simple(panel);
231 err = regulator_enable(p->supply);
233 dev_err(panel->dev, "failed to enable supply: %d\n", err);
238 gpiod_set_value_cansleep(p->enable_gpio, 1);
240 if (p->desc->delay.prepare)
241 msleep(p->desc->delay.prepare);
248 static int panel_simple_enable(struct drm_panel *panel)
250 struct panel_simple *p = to_panel_simple(panel);
255 if (p->desc->delay.enable)
256 msleep(p->desc->delay.enable);
259 p->backlight->props.state &= ~BL_CORE_FBBLANK;
260 p->backlight->props.power = FB_BLANK_UNBLANK;
261 backlight_update_status(p->backlight);
269 static int panel_simple_get_modes(struct drm_panel *panel)
271 struct panel_simple *p = to_panel_simple(panel);
274 /* probe EDID if a DDC bus is available */
276 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
277 drm_mode_connector_update_edid_property(panel->connector, edid);
279 num += drm_add_edid_modes(panel->connector, edid);
284 /* add hard-coded panel modes */
285 num += panel_simple_get_fixed_modes(p);
290 static int panel_simple_get_timings(struct drm_panel *panel,
291 unsigned int num_timings,
292 struct display_timing *timings)
294 struct panel_simple *p = to_panel_simple(panel);
297 if (p->desc->num_timings < num_timings)
298 num_timings = p->desc->num_timings;
301 for (i = 0; i < num_timings; i++)
302 timings[i] = p->desc->timings[i];
304 return p->desc->num_timings;
307 static inline int panel_simple_check_quirks(struct device *dev,
308 struct panel_simple *p)
312 if (of_property_read_string(dev->of_node, "bus-format-override",
314 if (strcmp(bus_fmt, "rgb24") == 0)
315 p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X24;
316 else if (strcmp(bus_fmt, "rgb666") == 0)
317 p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X18;
318 else if (strcmp(bus_fmt, "rgb565") == 0)
319 p->bus_fmt_override = MEDIA_BUS_FMT_RGB565_1X16;
320 else if (strcmp(bus_fmt, "spwg-18") == 0)
321 p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG;
322 else if (strcmp(bus_fmt, "spwg-24") == 0)
323 p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
324 else if (strcmp(bus_fmt, "jeida-24") == 0)
325 p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
328 "Unsupported bus-format-override value: '%s'\n",
330 return p->bus_fmt_override ? 0 : -EINVAL;
335 static const struct drm_panel_funcs panel_simple_funcs = {
336 .disable = panel_simple_disable,
337 .unprepare = panel_simple_unprepare,
338 .prepare = panel_simple_prepare,
339 .enable = panel_simple_enable,
340 .get_modes = panel_simple_get_modes,
341 .get_timings = panel_simple_get_timings,
344 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
346 struct device_node *backlight, *ddc;
347 struct panel_simple *panel;
350 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
354 panel->enabled = false;
355 panel->prepared = false;
358 panel->supply = devm_regulator_get(dev, "power");
359 if (IS_ERR(panel->supply))
360 return PTR_ERR(panel->supply);
362 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
364 if (IS_ERR(panel->enable_gpio)) {
365 err = PTR_ERR(panel->enable_gpio);
366 dev_err(dev, "failed to request GPIO: %d\n", err);
370 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
372 panel->backlight = of_find_backlight_by_node(backlight);
373 of_node_put(backlight);
375 if (!panel->backlight)
376 return -EPROBE_DEFER;
379 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
381 panel->ddc = of_find_i2c_adapter_by_node(ddc);
390 err = panel_simple_check_quirks(dev, panel);
394 drm_panel_init(&panel->base);
395 panel->base.dev = dev;
396 panel->base.funcs = &panel_simple_funcs;
398 err = drm_panel_add(&panel->base);
402 dev_set_drvdata(dev, panel);
408 put_device(&panel->ddc->dev);
410 if (panel->backlight)
411 put_device(&panel->backlight->dev);
416 static int panel_simple_remove(struct device *dev)
418 struct panel_simple *panel = dev_get_drvdata(dev);
420 drm_panel_detach(&panel->base);
421 drm_panel_remove(&panel->base);
423 panel_simple_disable(&panel->base);
426 put_device(&panel->ddc->dev);
428 if (panel->backlight)
429 put_device(&panel->backlight->dev);
434 static void panel_simple_shutdown(struct device *dev)
436 struct panel_simple *panel = dev_get_drvdata(dev);
438 panel_simple_disable(&panel->base);
441 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode =
442 SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
445 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
446 .modes = &ire_am_480272h3tmqw_t01h_mode,
453 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
456 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode =
457 SP_DISPLAY_MODE(33333, 800, 0, 255, 0, 480, 2, 45, 0, 60,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
460 static const struct panel_desc ampire_am800480r3tmqwa1h = {
461 .modes = &ire_am800480r3tmqwa1h_mode,
468 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
471 static const struct drm_display_mode auo_b101aw03_mode =
472 SP_DISPLAY_MODE(51450, 1024, 156, 8, 156, 600, 16, 6, 16, 60, 0);
474 static const struct panel_desc auo_b101aw03 = {
475 .modes = &auo_b101aw03_mode,
484 static const struct drm_display_mode auo_b101ean01_mode =
485 SP_DISPLAY_MODE(72500, 1280, 119, 32, 21, 800, 4, 20, 8, 60, 0);
487 static const struct panel_desc auo_b101ean01 = {
488 .modes = &auo_b101ean01_mode,
497 static const struct drm_display_mode auo_b101xtn01_mode =
498 SP_DISPLAY_MODE(72000, 1366, 20, 70, 0, 768, 14, 42, 0, 60,
499 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
501 static const struct panel_desc auo_b101xtn01 = {
502 .modes = &auo_b101xtn01_mode,
511 static const struct drm_display_mode auo_b116xw03_mode =
512 SP_DISPLAY_MODE(70589, 1366, 40, 40, 32, 768, 10, 12, 6, 60, 0);
514 static const struct panel_desc auo_b116xw03 = {
515 .modes = &auo_b116xw03_mode,
524 static const struct drm_display_mode auo_b133xtn01_mode =
525 SP_DISPLAY_MODE(69500, 1366, 48, 32, 20, 768, 3, 6, 13, 60, 0);
527 static const struct panel_desc auo_b133xtn01 = {
528 .modes = &auo_b133xtn01_mode,
537 static const struct drm_display_mode auo_b133htn01_mode =
538 SP_DISPLAY_MODE(150660, 1920, 172, 80, 60, 1080, 25, 10, 10, 60, 0);
540 static const struct panel_desc auo_b133htn01 = {
541 .modes = &auo_b133htn01_mode,
555 static const struct display_timing auo_g133han01_timings = {
556 .pixelclock = { 134000000, 141200000, 149000000 },
557 .hactive = { 1920, 1920, 1920 },
558 .hfront_porch = { 39, 58, 77 },
559 .hback_porch = { 59, 88, 117 },
560 .hsync_len = { 28, 42, 56 },
561 .vactive = { 1080, 1080, 1080 },
562 .vfront_porch = { 3, 8, 11 },
563 .vback_porch = { 5, 14, 19 },
564 .vsync_len = { 4, 14, 19 },
567 static const struct panel_desc auo_g133han01 = {
568 .timings = &auo_g133han01_timings,
581 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
584 static const struct display_timing auo_g185han01_timings = {
585 .pixelclock = { 120000000, 144000000, 175000000 },
586 .hactive = { 1920, 1920, 1920 },
587 .hfront_porch = { 18, 60, 74 },
588 .hback_porch = { 12, 44, 54 },
589 .hsync_len = { 10, 24, 32 },
590 .vactive = { 1080, 1080, 1080 },
591 .vfront_porch = { 6, 10, 40 },
592 .vback_porch = { 2, 5, 20 },
593 .vsync_len = { 2, 5, 20 },
596 static const struct panel_desc auo_g185han01 = {
597 .timings = &auo_g185han01_timings,
610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
613 static const struct display_timing auo_p320hvn03_timings = {
614 .pixelclock = { 106000000, 148500000, 164000000 },
615 .hactive = { 1920, 1920, 1920 },
616 .hfront_porch = { 25, 50, 130 },
617 .hback_porch = { 25, 50, 130 },
618 .hsync_len = { 20, 40, 105 },
619 .vactive = { 1080, 1080, 1080 },
620 .vfront_porch = { 8, 17, 150 },
621 .vback_porch = { 8, 17, 150 },
622 .vsync_len = { 4, 11, 100 },
625 static const struct panel_desc auo_p320hvn03 = {
626 .timings = &auo_p320hvn03_timings,
638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
641 static const struct drm_display_mode auo_t215hvn01_mode =
642 SP_DISPLAY_MODE(148800, 1920, 88, 44, 148, 1080, 4, 5, 36, 60, 0);
644 static const struct panel_desc auo_t215hvn01 = {
645 .modes = &auo_t215hvn01_mode,
658 static const struct drm_display_mode avic_tm070ddh03_mode =
659 SP_DISPLAY_MODE(51200, 1024, 160, 4, 156, 600, 17, 1, 17, 60, 0);
661 static const struct panel_desc avic_tm070ddh03 = {
662 .modes = &avic_tm070ddh03_mode,
676 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
677 SP_DISPLAY_MODE(71900, 1280, 48, 32, 80, 800, 3, 5, 24, 60, 0),
678 SP_DISPLAY_MODE(57500, 1280, 48, 32, 80, 800, 3, 5, 24, 48, 0),
681 static const struct panel_desc boe_nv101wxmn51 = {
682 .modes = boe_nv101wxmn51_modes,
683 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
696 static const struct drm_display_mode chunghwa_claa070wp03xg_mode =
697 SP_DISPLAY_MODE(66770, 800, 49, 33, 17, 1280, 1, 7, 15, 60,
698 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
700 static const struct panel_desc chunghwa_claa070wp03xg = {
701 .modes = &chunghwa_claa070wp03xg_mode,
710 static const struct drm_display_mode chunghwa_claa101wa01a_mode =
711 SP_DISPLAY_MODE(72070, 1366, 58, 58, 58, 768, 4, 4, 4, 60, 0);
713 static const struct panel_desc chunghwa_claa101wa01a = {
714 .modes = &chunghwa_claa101wa01a_mode,
723 static const struct drm_display_mode chunghwa_claa101wb01_mode =
724 SP_DISPLAY_MODE(69300, 1366, 48, 32, 20, 768, 16, 8, 16, 60, 0);
726 static const struct panel_desc chunghwa_claa101wb01 = {
727 .modes = &chunghwa_claa101wb01_mode,
736 static const struct drm_display_mode edt_et057090dhu_mode =
737 SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
738 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
740 static const struct panel_desc edt_et057090dhu = {
741 .modes = &edt_et057090dhu_mode,
748 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
749 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
752 static const struct drm_display_mode edt_etm0700g0dh6_mode =
753 SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
756 static const struct panel_desc edt_etm0700g0dh6 = {
757 .modes = &edt_etm0700g0dh6_mode,
764 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
768 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
769 SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
771 static const struct panel_desc foxlink_fl500wvr00_a0t = {
772 .modes = &foxlink_fl500wvr00_a0t_mode,
779 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
782 static const struct drm_display_mode giantplus_gpg482739qs5_mode =
783 SP_DISPLAY_MODE(9000, 480, 5, 1, 40, 272, 8, 1, 8, 60, 0);
785 static const struct panel_desc giantplus_gpg482739qs5 = {
786 .modes = &giantplus_gpg482739qs5_mode,
793 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
796 static const struct display_timing hannstar_hsd070pww1_timing = {
797 .pixelclock = { 64300000, 71100000, 82000000 },
798 .hactive = { 1280, 1280, 1280 },
799 .hfront_porch = { 1, 1, 10 },
800 .hback_porch = { 1, 1, 10 },
802 * According to the data sheet, the minimum horizontal blanking interval
803 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
804 * minimum working horizontal blanking interval to be 60 clocks.
806 .hsync_len = { 58, 158, 661 },
807 .vactive = { 800, 800, 800 },
808 .vfront_porch = { 1, 1, 10 },
809 .vback_porch = { 1, 1, 10 },
810 .vsync_len = { 1, 21, 203 },
811 .flags = DISPLAY_FLAGS_DE_HIGH,
814 static const struct panel_desc hannstar_hsd070pww1 = {
815 .timings = &hannstar_hsd070pww1_timing,
822 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
825 static const struct display_timing hannstar_hsd100pxn1_timing = {
826 .pixelclock = { 55000000, 65000000, 75000000 },
827 .hactive = { 1024, 1024, 1024 },
828 .hfront_porch = { 40, 40, 40 },
829 .hback_porch = { 220, 220, 220 },
830 .hsync_len = { 20, 60, 100 },
831 .vactive = { 768, 768, 768 },
832 .vfront_porch = { 7, 7, 7 },
833 .vback_porch = { 21, 21, 21 },
834 .vsync_len = { 10, 10, 10 },
835 .flags = DISPLAY_FLAGS_DE_HIGH,
838 static const struct panel_desc hannstar_hsd100pxn1 = {
839 .timings = &hannstar_hsd100pxn1_timing,
846 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
849 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode =
850 SP_DISPLAY_MODE(33333, 800, 85, 86, 85, 480, 16, 13, 16, 60, 0);
852 static const struct panel_desc hitachi_tx23d38vm0caa = {
853 .modes = &hitachi_tx23d38vm0caa_mode,
862 static const struct drm_display_mode innolux_at043tn24_mode =
863 SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 11, 2, 60,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
866 static const struct panel_desc innolux_at043tn24 = {
867 .modes = &innolux_at043tn24_mode,
874 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
877 static const struct drm_display_mode innolux_at070tn92_mode =
878 SP_DISPLAY_MODE(33333, 800, 210, 20, 46, 480, 22, 10, 23, 60, 0);
880 static const struct panel_desc innolux_at070tn92 = {
881 .modes = &innolux_at070tn92_mode,
887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
890 static const struct display_timing innolux_g101ice_l01_timing = {
891 .pixelclock = { 60400000, 71100000, 74700000 },
892 .hactive = { 1280, 1280, 1280 },
893 .hfront_porch = { 41, 80, 100 },
894 .hback_porch = { 40, 79, 99 },
895 .hsync_len = { 1, 1, 1 },
896 .vactive = { 800, 800, 800 },
897 .vfront_porch = { 5, 11, 14 },
898 .vback_porch = { 4, 11, 14 },
899 .vsync_len = { 1, 1, 1 },
900 .flags = DISPLAY_FLAGS_DE_HIGH,
903 static const struct panel_desc innolux_g101ice_l01 = {
904 .timings = &innolux_g101ice_l01_timing,
915 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
918 static const struct display_timing innolux_g121i1_l01_timing = {
919 .pixelclock = { 67450000, 71000000, 74550000 },
920 .hactive = { 1280, 1280, 1280 },
921 .hfront_porch = { 40, 80, 160 },
922 .hback_porch = { 39, 79, 159 },
923 .hsync_len = { 1, 1, 1 },
924 .vactive = { 800, 800, 800 },
925 .vfront_porch = { 5, 11, 100 },
926 .vback_porch = { 4, 11, 99 },
927 .vsync_len = { 1, 1, 1 },
930 static const struct panel_desc innolux_g121i1_l01 = {
931 .timings = &innolux_g121i1_l01_timing,
942 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
945 static const struct drm_display_mode innolux_g121x1_l03_mode =
946 SP_DISPLAY_MODE(65000, 1024, 0, 1, 320, 768, 38, 1, 0, 60,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
949 static const struct panel_desc innolux_g121x1_l03 = {
950 .modes = &innolux_g121x1_l03_mode,
964 static const struct drm_display_mode innolux_n116bge_mode =
965 SP_DISPLAY_MODE(76420, 1366, 136, 30, 60, 768, 8, 12, 12, 60,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
968 static const struct panel_desc innolux_n116bge = {
969 .modes = &innolux_n116bge_mode,
978 static const struct drm_display_mode innolux_n156bge_l21_mode =
979 SP_DISPLAY_MODE(69300, 1366, 16, 34, 50, 768, 2, 6, 12, 60, 0);
981 static const struct panel_desc innolux_n156bge_l21 = {
982 .modes = &innolux_n156bge_l21_mode,
991 static const struct drm_display_mode innolux_zj070na_01p_mode =
992 SP_DISPLAY_MODE(51501, 1024, 128, 64, 128, 600, 16, 4, 16, 60, 0);
994 static const struct panel_desc innolux_zj070na_01p = {
995 .modes = &innolux_zj070na_01p_mode,
1004 static const struct display_timing kyo_tcg121xglp_timing = {
1005 .pixelclock = { 52000000, 65000000, 71000000 },
1006 .hactive = { 1024, 1024, 1024 },
1007 .hfront_porch = { 2, 2, 2 },
1008 .hback_porch = { 2, 2, 2 },
1009 .hsync_len = { 86, 124, 244 },
1010 .vactive = { 768, 768, 768 },
1011 .vfront_porch = { 2, 2, 2 },
1012 .vback_porch = { 2, 2, 2 },
1013 .vsync_len = { 6, 34, 73 },
1014 .flags = DISPLAY_FLAGS_DE_HIGH,
1017 static const struct panel_desc kyo_tcg121xglp = {
1018 .timings = &kyo_tcg121xglp_timing,
1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1028 static const struct drm_display_mode lg_lb070wv8_mode =
1029 SP_DISPLAY_MODE(33246, 800, 88, 80, 88, 480, 10, 25, 10, 60, 0);
1031 static const struct panel_desc lg_lb070wv8 = {
1032 .modes = &lg_lb070wv8_mode,
1039 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1042 static const struct drm_display_mode lg_lp079qx1_sp0v_mode =
1043 SP_DISPLAY_MODE(200000, 1536, 12, 16, 48, 2048, 8, 4, 8, 60,
1044 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1046 static const struct panel_desc lg_lp079qx1_sp0v = {
1047 .modes = &lg_lp079qx1_sp0v_mode,
1055 static const struct drm_display_mode lg_lp097qx1_spa1_mode =
1056 SP_DISPLAY_MODE(205210, 2048, 150, 5, 5, 1536, 3, 1, 9, 60, 0);
1058 static const struct panel_desc lg_lp097qx1_spa1 = {
1059 .modes = &lg_lp097qx1_spa1_mode,
1067 static const struct drm_display_mode lg_lp120up1_mode =
1068 SP_DISPLAY_MODE(162300, 1920, 40, 40, 80, 1280, 4, 4, 12, 60, 0);
1070 static const struct panel_desc lg_lp120up1 = {
1071 .modes = &lg_lp120up1_mode,
1080 static const struct drm_display_mode lg_lp129qe_mode =
1081 SP_DISPLAY_MODE(285250, 2560, 48, 32, 80, 1700, 3, 10, 36, 60, 0);
1083 static const struct panel_desc lg_lp129qe = {
1084 .modes = &lg_lp129qe_mode,
1093 static const struct display_timing nec_nl12880bc20_05_timing = {
1094 .pixelclock = { 67000000, 71000000, 75000000 },
1095 .hactive = { 1280, 1280, 1280 },
1096 .hfront_porch = { 2, 30, 30 },
1097 .hback_porch = { 6, 100, 100 },
1098 .hsync_len = { 2, 30, 30 },
1099 .vactive = { 800, 800, 800 },
1100 .vfront_porch = { 5, 5, 5 },
1101 .vback_porch = { 11, 11, 11 },
1102 .vsync_len = { 7, 7, 7 },
1105 static const struct panel_desc nec_nl12880bc20_05 = {
1106 .timings = &nec_nl12880bc20_05_timing,
1117 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1120 static const struct drm_display_mode nec_nl4827hc19_05b_mode =
1121 SP_DISPLAY_MODE(10870, 480, 2, 41, 2, 272, 2, 4, 2, 74,
1122 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1124 static const struct panel_desc nec_nl4827hc19_05b = {
1125 .modes = &nec_nl4827hc19_05b_mode,
1132 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1133 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1136 static const struct drm_display_mode netron_dy_e231732_mode =
1137 SP_DISPLAY_MODE(66000, 1024, 160, 70, 90, 600, 127, 20, 3, 60, 0);
1139 static const struct panel_desc netron_dy_e231732 = {
1140 .modes = &netron_dy_e231732_mode,
1146 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1149 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1150 .pixelclock = { 130000000, 148350000, 163000000 },
1151 .hactive = { 1920, 1920, 1920 },
1152 .hfront_porch = { 80, 100, 100 },
1153 .hback_porch = { 100, 120, 120 },
1154 .hsync_len = { 50, 60, 60 },
1155 .vactive = { 1080, 1080, 1080 },
1156 .vfront_porch = { 12, 30, 30 },
1157 .vback_porch = { 4, 10, 10 },
1158 .vsync_len = { 4, 5, 5 },
1161 static const struct panel_desc nlt_nl192108ac18_02d = {
1162 .timings = &nlt_nl192108ac18_02d_timing,
1172 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1175 static const struct drm_display_mode nvd_9128_mode =
1176 SP_DISPLAY_MODE(29500, 800, 130, 98, 0, 480, 10, 50, 0, 0, 0);
1178 static const struct panel_desc nvd_9128 = {
1179 .modes = &nvd_9128_mode,
1186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1189 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1190 .pixelclock = { 30000000, 30000000, 40000000 },
1191 .hactive = { 800, 800, 800 },
1192 .hfront_porch = { 40, 40, 40 },
1193 .hback_porch = { 40, 40, 40 },
1194 .hsync_len = { 1, 48, 48 },
1195 .vactive = { 480, 480, 480 },
1196 .vfront_porch = { 13, 13, 13 },
1197 .vback_porch = { 29, 29, 29 },
1198 .vsync_len = { 3, 3, 3 },
1199 .flags = DISPLAY_FLAGS_DE_HIGH,
1202 static const struct panel_desc okaya_rs800480t_7x0gp = {
1203 .timings = &okaya_rs800480t_7x0gp_timing,
1216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1219 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode =
1220 SP_DISPLAY_MODE(9000, 480, 5, 30, 10, 272, 8, 5, 3, 60, 0);
1222 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1223 .modes = &olimex_lcd_olinuxino_43ts_mode,
1229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1233 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1234 * pixel clocks, but this is the timing that was being used in the Adafruit
1235 * installation instructions.
1237 static const struct drm_display_mode ontat_yx700wv03_mode =
1238 SP_DISPLAY_MODE(29500, 800, 24, 72, 96, 480, 3, 10, 7, 60,
1239 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1243 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1245 static const struct panel_desc ontat_yx700wv03 = {
1246 .modes = &ontat_yx700wv03_mode,
1253 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1256 static const struct drm_display_mode ortustech_com43h4m85ulc_mode =
1257 SP_DISPLAY_MODE(25000, 480, 10, 10, 15, 800, 3, 3, 3, 60, 0);
1259 static const struct panel_desc ortustech_com43h4m85ulc = {
1260 .modes = &ortustech_com43h4m85ulc_mode,
1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1268 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1271 static const struct drm_display_mode qd43003c0_40_mode =
1272 SP_DISPLAY_MODE(9000, 480, 8, 4, 39, 272, 4, 10, 2, 60, 0);
1274 static const struct panel_desc qd43003c0_40 = {
1275 .modes = &qd43003c0_40_mode,
1282 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1285 static const struct drm_display_mode samsung_lsn122dl01_c01_mode =
1286 SP_DISPLAY_MODE(271560, 2560, 48, 32, 80, 1600, 2, 5, 57, 60, 0);
1288 static const struct panel_desc samsung_lsn122dl01_c01 = {
1289 .modes = &samsung_lsn122dl01_c01_mode,
1297 static const struct drm_display_mode samsung_ltn101nt05_mode =
1298 SP_DISPLAY_MODE(54030, 1024, 24, 136, 160, 600, 3, 6, 61, 60, 0);
1300 static const struct panel_desc samsung_ltn101nt05 = {
1301 .modes = &samsung_ltn101nt05_mode,
1310 static const struct drm_display_mode samsung_ltn140at29_301_mode =
1311 SP_DISPLAY_MODE(76300, 1366, 64, 48, 128, 768, 2, 5, 17, 60, 0);
1313 static const struct panel_desc samsung_ltn140at29_301 = {
1314 .modes = &samsung_ltn140at29_301_mode,
1323 static const struct display_timing sharp_lq101k1ly04_timing = {
1324 .pixelclock = { 60000000, 65000000, 80000000 },
1325 .hactive = { 1280, 1280, 1280 },
1326 .hfront_porch = { 20, 20, 20 },
1327 .hback_porch = { 20, 20, 20 },
1328 .hsync_len = { 10, 10, 10 },
1329 .vactive = { 800, 800, 800 },
1330 .vfront_porch = { 4, 4, 4 },
1331 .vback_porch = { 4, 4, 4 },
1332 .vsync_len = { 4, 4, 4 },
1333 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1336 static const struct panel_desc sharp_lq101k1ly04 = {
1337 .timings = &sharp_lq101k1ly04_timing,
1344 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1347 static const struct drm_display_mode sharp_lq123p1jx31_mode =
1348 SP_DISPLAY_MODE(252750, 2400, 48, 32, 80, 1600, 3, 10, 33, 60,
1349 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1351 static const struct panel_desc sharp_lq123p1jx31 = {
1352 .modes = &sharp_lq123p1jx31_mode,
1366 static const struct drm_display_mode sharp_lq150x1lg11_mode =
1367 SP_DISPLAY_MODE(71100, 1024, 168, 64, 88, 768, 37, 2, 8, 60, 0);
1369 static const struct panel_desc sharp_lq150x1lg11 = {
1370 .modes = &sharp_lq150x1lg11_mode,
1377 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1380 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode =
1381 SP_DISPLAY_MODE(33300, 800, 1, 64, 64, 480, 1, 23, 22, 60, 0);
1383 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1384 .modes = &shelly_sca07010_bfn_lnn_mode,
1390 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1393 static const struct drm_display_mode starry_kr122ea0sra_mode =
1394 SP_DISPLAY_MODE(147000, 1920, 16, 16, 32, 1200, 15, 2, 18, 60,
1395 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1397 static const struct panel_desc starry_kr122ea0sra = {
1398 .modes = &starry_kr122ea0sra_mode,
1405 .prepare = 10 + 200,
1407 .unprepare = 10 + 500,
1411 static const struct display_timing tianma_tm070jdhg30_timing = {
1412 .pixelclock = { 62600000, 68200000, 78100000 },
1413 .hactive = { 1280, 1280, 1280 },
1414 .hfront_porch = { 15, 64, 159 },
1415 .hback_porch = { 5, 5, 5 },
1416 .hsync_len = { 1, 1, 256 },
1417 .vactive = { 800, 800, 800 },
1418 .vfront_porch = { 3, 40, 99 },
1419 .vback_porch = { 2, 2, 2 },
1420 .vsync_len = { 1, 1, 128 },
1421 .flags = DISPLAY_FLAGS_DE_HIGH,
1424 static const struct panel_desc tianma_tm070jdhg30 = {
1425 .timings = &tianma_tm070jdhg30_timing,
1432 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1435 static const struct drm_display_mode tpk_f07a_0102_mode =
1436 SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60, 0);
1438 static const struct panel_desc tpk_f07a_0102 = {
1439 .modes = &tpk_f07a_0102_mode,
1445 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1448 static const struct drm_display_mode tpk_f10a_0102_mode =
1449 SP_DISPLAY_MODE(45000, 1024, 176, 5, 88, 600, 20, 5, 25, 60, 0);
1451 static const struct panel_desc tpk_f10a_0102 = {
1452 .modes = &tpk_f10a_0102_mode,
1460 static const struct display_timing urt_umsh_8596md_timing = {
1461 .pixelclock = { 33260000, 33260000, 33260000 },
1462 .hactive = { 800, 800, 800 },
1463 .hfront_porch = { 41, 41, 41 },
1464 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1465 .hsync_len = { 71, 128, 128 },
1466 .vactive = { 480, 480, 480 },
1467 .vfront_porch = { 10, 10, 10 },
1468 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1469 .vsync_len = { 2, 2, 2 },
1470 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1471 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1474 static const struct panel_desc urt_umsh_8596md_lvds = {
1475 .timings = &urt_umsh_8596md_timing,
1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1485 static const struct panel_desc urt_umsh_8596md_parallel = {
1486 .timings = &urt_umsh_8596md_timing,
1493 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1496 static const struct drm_display_mode winstar_wf35ltiacd_mode =
1497 SP_DISPLAY_MODE(6410, 320, 20, 30, 38, 240, 4, 3, 15, 60,
1498 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1500 static const struct panel_desc winstar_wf35ltiacd = {
1501 .modes = &winstar_wf35ltiacd_mode,
1508 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1511 static const struct of_device_id platform_of_match[] = {
1513 .compatible = "ampire,am-480272h3tmqw-t01h",
1514 .data = &ire_am_480272h3tmqw_t01h,
1516 .compatible = "ampire,am800480r3tmqwa1h",
1517 .data = &ire_am800480r3tmqwa1h,
1519 .compatible = "auo,b101aw03",
1520 .data = &auo_b101aw03,
1522 .compatible = "auo,b101ean01",
1523 .data = &auo_b101ean01,
1525 .compatible = "auo,b101xtn01",
1526 .data = &auo_b101xtn01,
1528 .compatible = "auo,b116xw03",
1529 .data = &auo_b116xw03,
1531 .compatible = "auo,b133htn01",
1532 .data = &auo_b133htn01,
1534 .compatible = "auo,b133xtn01",
1535 .data = &auo_b133xtn01,
1537 .compatible = "auo,g133han01",
1538 .data = &auo_g133han01,
1540 .compatible = "auo,g185han01",
1541 .data = &auo_g185han01,
1543 .compatible = "auo,p320hvn03",
1544 .data = &auo_p320hvn03,
1546 .compatible = "auo,t215hvn01",
1547 .data = &auo_t215hvn01,
1549 .compatible = "avic,tm070ddh03",
1550 .data = &avic_tm070ddh03,
1552 .compatible = "boe,nv101wxmn51",
1553 .data = &boe_nv101wxmn51,
1555 .compatible = "chunghwa,claa070wp03xg",
1556 .data = &chunghwa_claa070wp03xg,
1558 .compatible = "chunghwa,claa101wa01a",
1559 .data = &chunghwa_claa101wa01a
1561 .compatible = "chunghwa,claa101wb01",
1562 .data = &chunghwa_claa101wb01
1564 .compatible = "edt,et057090dhu",
1565 .data = &edt_et057090dhu,
1567 .compatible = "edt,et070080dh6",
1568 .data = &edt_etm0700g0dh6,
1570 .compatible = "edt,etm0700g0dh6",
1571 .data = &edt_etm0700g0dh6,
1573 .compatible = "foxlink,fl500wvr00-a0t",
1574 .data = &foxlink_fl500wvr00_a0t,
1576 .compatible = "giantplus,gpg482739qs5",
1577 .data = &giantplus_gpg482739qs5
1579 .compatible = "hannstar,hsd070pww1",
1580 .data = &hannstar_hsd070pww1,
1582 .compatible = "hannstar,hsd100pxn1",
1583 .data = &hannstar_hsd100pxn1,
1585 .compatible = "hit,tx23d38vm0caa",
1586 .data = &hitachi_tx23d38vm0caa
1588 .compatible = "innolux,at043tn24",
1589 .data = &innolux_at043tn24,
1591 .compatible = "innolux,at070tn92",
1592 .data = &innolux_at070tn92,
1594 .compatible ="innolux,g101ice-l01",
1595 .data = &innolux_g101ice_l01
1597 .compatible ="innolux,g121i1-l01",
1598 .data = &innolux_g121i1_l01
1600 .compatible = "innolux,g121x1-l03",
1601 .data = &innolux_g121x1_l03,
1603 .compatible = "innolux,n116bge",
1604 .data = &innolux_n116bge,
1606 .compatible = "innolux,n156bge-l21",
1607 .data = &innolux_n156bge_l21,
1609 .compatible = "innolux,zj070na-01p",
1610 .data = &innolux_zj070na_01p,
1612 .compatible = "kyo,tcg121xglp",
1613 .data = &kyo_tcg121xglp,
1615 .compatible = "lg,lb070wv8",
1616 .data = &lg_lb070wv8,
1618 .compatible = "lg,lp079qx1-sp0v",
1619 .data = &lg_lp079qx1_sp0v,
1621 .compatible = "lg,lp097qx1-spa1",
1622 .data = &lg_lp097qx1_spa1,
1624 .compatible = "lg,lp120up1",
1625 .data = &lg_lp120up1,
1627 .compatible = "lg,lp129qe",
1628 .data = &lg_lp129qe,
1630 .compatible = "nec,nl12880bc20-05",
1631 .data = &nec_nl12880bc20_05,
1633 .compatible = "nec,nl4827hc19-05b",
1634 .data = &nec_nl4827hc19_05b,
1636 .compatible = "netron-dy,e231732",
1637 .data = &netron_dy_e231732,
1639 .compatible = "nlt,nl192108ac18-02d",
1640 .data = &nlt_nl192108ac18_02d,
1642 .compatible = "nvd,9128",
1645 .compatible = "okaya,rs800480t-7x0gp",
1646 .data = &okaya_rs800480t_7x0gp,
1648 .compatible = "olimex,lcd-olinuxino-43-ts",
1649 .data = &olimex_lcd_olinuxino_43ts,
1651 .compatible = "ontat,yx700wv03",
1652 .data = &ontat_yx700wv03,
1654 .compatible = "ortustech,com43h4m85ulc",
1655 .data = &ortustech_com43h4m85ulc,
1657 .compatible = "qiaodian,qd43003c0-40",
1658 .data = &qd43003c0_40,
1660 .compatible = "samsung,lsn122dl01-c01",
1661 .data = &samsung_lsn122dl01_c01,
1663 .compatible = "samsung,ltn101nt05",
1664 .data = &samsung_ltn101nt05,
1666 .compatible = "samsung,ltn140at29-301",
1667 .data = &samsung_ltn140at29_301,
1669 .compatible = "sharp,lq101k1ly04",
1670 .data = &sharp_lq101k1ly04,
1672 .compatible = "sharp,lq123p1jx31",
1673 .data = &sharp_lq123p1jx31,
1675 .compatible = "sharp,lq150x1lg11",
1676 .data = &sharp_lq150x1lg11,
1678 .compatible = "shelly,sca07010-bfn-lnn",
1679 .data = &shelly_sca07010_bfn_lnn,
1681 .compatible = "starry,kr122ea0sra",
1682 .data = &starry_kr122ea0sra,
1684 .compatible = "tianma,tm070jdhg30",
1685 .data = &tianma_tm070jdhg30,
1687 .compatible = "tpk,f07a-0102",
1688 .data = &tpk_f07a_0102,
1690 .compatible = "tpk,f10a-0102",
1691 .data = &tpk_f10a_0102,
1693 .compatible = "urt,umsh-8596md-t",
1694 .data = &urt_umsh_8596md_parallel,
1696 .compatible = "urt,umsh-8596md-1t",
1697 .data = &urt_umsh_8596md_parallel,
1699 .compatible = "urt,umsh-8596md-7t",
1700 .data = &urt_umsh_8596md_parallel,
1702 .compatible = "urt,umsh-8596md-11t",
1703 .data = &urt_umsh_8596md_lvds,
1705 .compatible = "urt,umsh-8596md-19t",
1706 .data = &urt_umsh_8596md_lvds,
1708 .compatible = "urt,umsh-8596md-20t",
1709 .data = &urt_umsh_8596md_parallel,
1711 .compatible = "winstar,wf35ltiacd",
1712 .data = &winstar_wf35ltiacd,
1717 MODULE_DEVICE_TABLE(of, platform_of_match);
1719 static int panel_simple_platform_probe(struct platform_device *pdev)
1721 const struct of_device_id *id;
1723 id = of_match_node(platform_of_match, pdev->dev.of_node);
1727 return panel_simple_probe(&pdev->dev, id->data);
1730 static int panel_simple_platform_remove(struct platform_device *pdev)
1732 return panel_simple_remove(&pdev->dev);
1735 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1737 panel_simple_shutdown(&pdev->dev);
1740 static struct platform_driver panel_simple_platform_driver = {
1742 .name = "panel-simple",
1743 .of_match_table = platform_of_match,
1745 .probe = panel_simple_platform_probe,
1746 .remove = panel_simple_platform_remove,
1747 .shutdown = panel_simple_platform_shutdown,
1750 struct panel_desc_dsi {
1751 struct panel_desc desc;
1753 unsigned long flags;
1754 enum mipi_dsi_pixel_format format;
1758 static const struct drm_display_mode auo_b080uan01_mode =
1759 SP_DISPLAY_MODE(154500, 1200, 62, 4, 62, 1920, 9, 2, 8, 60, 0);
1761 static const struct panel_desc_dsi auo_b080uan01 = {
1763 .modes = &auo_b080uan01_mode,
1771 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1772 .format = MIPI_DSI_FMT_RGB888,
1776 static const struct drm_display_mode boe_tv080wum_nl0_mode =
1777 SP_DISPLAY_MODE(160000, 1200, 120, 20, 21, 1920, 21, 3, 18, 60,
1778 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1780 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1782 .modes = &boe_tv080wum_nl0_mode,
1789 .flags = MIPI_DSI_MODE_VIDEO |
1790 MIPI_DSI_MODE_VIDEO_BURST |
1791 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1792 .format = MIPI_DSI_FMT_RGB888,
1796 static const struct drm_display_mode lg_ld070wx3_sl01_mode =
1797 SP_DISPLAY_MODE(71000, 800, 32, 1, 57, 1280, 28, 1, 14, 60, 0);
1799 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1801 .modes = &lg_ld070wx3_sl01_mode,
1809 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1810 .format = MIPI_DSI_FMT_RGB888,
1814 static const struct drm_display_mode lg_lh500wx1_sd03_mode =
1815 SP_DISPLAY_MODE(67000, 720, 12, 4, 112, 1280, 8, 4, 12, 60, 0);
1817 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1819 .modes = &lg_lh500wx1_sd03_mode,
1827 .flags = MIPI_DSI_MODE_VIDEO,
1828 .format = MIPI_DSI_FMT_RGB888,
1832 static const struct drm_display_mode panasonic_vvx10f004b00_mode =
1833 SP_DISPLAY_MODE(157200, 1920, 154, 16, 32, 1200, 17, 2, 16, 60, 0);
1835 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1837 .modes = &panasonic_vvx10f004b00_mode,
1845 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1846 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1847 .format = MIPI_DSI_FMT_RGB888,
1851 static const struct of_device_id dsi_of_match[] = {
1853 .compatible = "auo,b080uan01",
1854 .data = &auo_b080uan01
1856 .compatible = "boe,tv080wum-nl0",
1857 .data = &boe_tv080wum_nl0
1859 .compatible = "lg,ld070wx3-sl01",
1860 .data = &lg_ld070wx3_sl01
1862 .compatible = "lg,lh500wx1-sd03",
1863 .data = &lg_lh500wx1_sd03
1865 .compatible = "panasonic,vvx10f004b00",
1866 .data = &panasonic_vvx10f004b00
1871 MODULE_DEVICE_TABLE(of, dsi_of_match);
1873 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1875 const struct panel_desc_dsi *desc;
1876 const struct of_device_id *id;
1879 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1885 err = panel_simple_probe(&dsi->dev, &desc->desc);
1889 dsi->mode_flags = desc->flags;
1890 dsi->format = desc->format;
1891 dsi->lanes = desc->lanes;
1893 return mipi_dsi_attach(dsi);
1896 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1900 err = mipi_dsi_detach(dsi);
1902 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1904 return panel_simple_remove(&dsi->dev);
1907 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1909 panel_simple_shutdown(&dsi->dev);
1912 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1914 .name = "panel-simple-dsi",
1915 .of_match_table = dsi_of_match,
1917 .probe = panel_simple_dsi_probe,
1918 .remove = panel_simple_dsi_remove,
1919 .shutdown = panel_simple_dsi_shutdown,
1922 static int __init panel_simple_init(void)
1926 err = platform_driver_register(&panel_simple_platform_driver);
1930 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1931 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1938 module_init(panel_simple_init);
1940 static void __exit panel_simple_exit(void)
1942 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1943 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1945 platform_driver_unregister(&panel_simple_platform_driver);
1947 module_exit(panel_simple_exit);
1949 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1950 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1951 MODULE_LICENSE("GPL and additional rights");