2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
92 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
95 .hsync_start = (ha) + (hfp), \
96 .hsync_end = (ha) + (hfp) + (hs), \
97 .htotal = (ha) + (hfp) + (hs) + (hbp), \
99 .vsync_start = (va) + (vfp), \
100 .vsync_end = (va) + (vfp) + (vs), \
101 .vtotal = (va) + (vfp) + (vs) + (vbp), \
106 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
108 return container_of(panel, struct panel_simple, base);
111 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
113 struct drm_connector *connector = panel->base.connector;
114 struct drm_device *drm = panel->base.drm;
115 struct drm_display_mode *mode;
116 unsigned int i, num = 0;
121 for (i = 0; i < panel->desc->num_timings; i++) {
122 const struct display_timing *dt = &panel->desc->timings[i];
125 videomode_from_timing(dt, &vm);
126 mode = drm_mode_create(drm);
128 dev_err(drm->dev, "failed to add mode %ux%u\n",
129 dt->hactive.typ, dt->vactive.typ);
133 drm_display_mode_from_videomode(&vm, mode);
135 mode->type |= DRM_MODE_TYPE_DRIVER;
137 if (panel->desc->num_timings == 1)
138 mode->type |= DRM_MODE_TYPE_PREFERRED;
140 drm_mode_probed_add(connector, mode);
144 for (i = 0; i < panel->desc->num_modes; i++) {
145 const struct drm_display_mode *m = &panel->desc->modes[i];
147 mode = drm_mode_duplicate(drm, m);
149 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
150 m->hdisplay, m->vdisplay, m->vrefresh);
154 mode->type |= DRM_MODE_TYPE_DRIVER;
156 if (panel->desc->num_modes == 1)
157 mode->type |= DRM_MODE_TYPE_PREFERRED;
159 drm_mode_set_name(mode);
161 drm_mode_probed_add(connector, mode);
165 connector->display_info.bpc = panel->desc->bpc;
166 connector->display_info.width_mm = panel->desc->size.width;
167 connector->display_info.height_mm = panel->desc->size.height;
168 if (panel->desc->bus_format)
169 drm_display_info_set_bus_formats(&connector->display_info,
170 &panel->desc->bus_format, 1);
171 connector->display_info.bus_flags = panel->desc->bus_flags;
176 static int panel_simple_disable(struct drm_panel *panel)
178 struct panel_simple *p = to_panel_simple(panel);
184 p->backlight->props.power = FB_BLANK_POWERDOWN;
185 p->backlight->props.state |= BL_CORE_FBBLANK;
186 backlight_update_status(p->backlight);
189 if (p->desc->delay.disable)
190 msleep(p->desc->delay.disable);
197 static int panel_simple_unprepare(struct drm_panel *panel)
199 struct panel_simple *p = to_panel_simple(panel);
205 gpiod_set_value_cansleep(p->enable_gpio, 0);
207 regulator_disable(p->supply);
209 if (p->desc->delay.unprepare)
210 msleep(p->desc->delay.unprepare);
217 static int panel_simple_prepare(struct drm_panel *panel)
219 struct panel_simple *p = to_panel_simple(panel);
225 err = regulator_enable(p->supply);
227 dev_err(panel->dev, "failed to enable supply: %d\n", err);
232 gpiod_set_value_cansleep(p->enable_gpio, 1);
234 if (p->desc->delay.prepare)
235 msleep(p->desc->delay.prepare);
242 static int panel_simple_enable(struct drm_panel *panel)
244 struct panel_simple *p = to_panel_simple(panel);
249 if (p->desc->delay.enable)
250 msleep(p->desc->delay.enable);
253 p->backlight->props.state &= ~BL_CORE_FBBLANK;
254 p->backlight->props.power = FB_BLANK_UNBLANK;
255 backlight_update_status(p->backlight);
263 static int panel_simple_get_modes(struct drm_panel *panel)
265 struct panel_simple *p = to_panel_simple(panel);
268 /* probe EDID if a DDC bus is available */
270 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
271 drm_mode_connector_update_edid_property(panel->connector, edid);
273 num += drm_add_edid_modes(panel->connector, edid);
278 /* add hard-coded panel modes */
279 num += panel_simple_get_fixed_modes(p);
284 static int panel_simple_get_timings(struct drm_panel *panel,
285 unsigned int num_timings,
286 struct display_timing *timings)
288 struct panel_simple *p = to_panel_simple(panel);
291 if (p->desc->num_timings < num_timings)
292 num_timings = p->desc->num_timings;
295 for (i = 0; i < num_timings; i++)
296 timings[i] = p->desc->timings[i];
298 return p->desc->num_timings;
301 static const struct drm_panel_funcs panel_simple_funcs = {
302 .disable = panel_simple_disable,
303 .unprepare = panel_simple_unprepare,
304 .prepare = panel_simple_prepare,
305 .enable = panel_simple_enable,
306 .get_modes = panel_simple_get_modes,
307 .get_timings = panel_simple_get_timings,
310 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
312 struct device_node *backlight, *ddc;
313 struct panel_simple *panel;
316 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
320 panel->enabled = false;
321 panel->prepared = false;
324 panel->supply = devm_regulator_get(dev, "power");
325 if (IS_ERR(panel->supply))
326 return PTR_ERR(panel->supply);
328 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
330 if (IS_ERR(panel->enable_gpio)) {
331 err = PTR_ERR(panel->enable_gpio);
332 dev_err(dev, "failed to request GPIO: %d\n", err);
336 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
338 panel->backlight = of_find_backlight_by_node(backlight);
339 of_node_put(backlight);
341 if (!panel->backlight)
342 return -EPROBE_DEFER;
345 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
347 panel->ddc = of_find_i2c_adapter_by_node(ddc);
356 drm_panel_init(&panel->base);
357 panel->base.dev = dev;
358 panel->base.funcs = &panel_simple_funcs;
360 err = drm_panel_add(&panel->base);
364 dev_set_drvdata(dev, panel);
370 put_device(&panel->ddc->dev);
372 if (panel->backlight)
373 put_device(&panel->backlight->dev);
378 static int panel_simple_remove(struct device *dev)
380 struct panel_simple *panel = dev_get_drvdata(dev);
382 drm_panel_detach(&panel->base);
383 drm_panel_remove(&panel->base);
385 panel_simple_disable(&panel->base);
388 put_device(&panel->ddc->dev);
390 if (panel->backlight)
391 put_device(&panel->backlight->dev);
396 static void panel_simple_shutdown(struct device *dev)
398 struct panel_simple *panel = dev_get_drvdata(dev);
400 panel_simple_disable(&panel->base);
403 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode =
404 SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
407 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
408 .modes = &ire_am_480272h3tmqw_t01h_mode,
415 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
418 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode =
419 SP_DISPLAY_MODE(33333, 800, 0, 255, 0, 480, 2, 45, 0, 60,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
422 static const struct panel_desc ampire_am800480r3tmqwa1h = {
423 .modes = &ire_am800480r3tmqwa1h_mode,
430 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
433 static const struct drm_display_mode auo_b101aw03_mode =
434 SP_DISPLAY_MODE(51450, 1024, 156, 8, 156, 600, 16, 6, 16, 60, 0);
436 static const struct panel_desc auo_b101aw03 = {
437 .modes = &auo_b101aw03_mode,
446 static const struct drm_display_mode auo_b101ean01_mode =
447 SP_DISPLAY_MODE(72500, 1280, 119, 32, 21, 800, 4, 20, 8, 60, 0);
449 static const struct panel_desc auo_b101ean01 = {
450 .modes = &auo_b101ean01_mode,
459 static const struct drm_display_mode auo_b101xtn01_mode =
460 SP_DISPLAY_MODE(72000, 1366, 20, 70, 0, 768, 14, 42, 0, 60,
461 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
463 static const struct panel_desc auo_b101xtn01 = {
464 .modes = &auo_b101xtn01_mode,
473 static const struct drm_display_mode auo_b116xw03_mode =
474 SP_DISPLAY_MODE(70589, 1366, 40, 40, 32, 768, 10, 12, 6, 60, 0);
476 static const struct panel_desc auo_b116xw03 = {
477 .modes = &auo_b116xw03_mode,
486 static const struct drm_display_mode auo_b133xtn01_mode =
487 SP_DISPLAY_MODE(69500, 1366, 48, 32, 20, 768, 3, 6, 13, 60, 0);
489 static const struct panel_desc auo_b133xtn01 = {
490 .modes = &auo_b133xtn01_mode,
499 static const struct drm_display_mode auo_b133htn01_mode =
500 SP_DISPLAY_MODE(150660, 1920, 172, 80, 60, 1080, 25, 10, 10, 60, 0);
502 static const struct panel_desc auo_b133htn01 = {
503 .modes = &auo_b133htn01_mode,
517 static const struct display_timing auo_g133han01_timings = {
518 .pixelclock = { 134000000, 141200000, 149000000 },
519 .hactive = { 1920, 1920, 1920 },
520 .hfront_porch = { 39, 58, 77 },
521 .hback_porch = { 59, 88, 117 },
522 .hsync_len = { 28, 42, 56 },
523 .vactive = { 1080, 1080, 1080 },
524 .vfront_porch = { 3, 8, 11 },
525 .vback_porch = { 5, 14, 19 },
526 .vsync_len = { 4, 14, 19 },
529 static const struct panel_desc auo_g133han01 = {
530 .timings = &auo_g133han01_timings,
543 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
546 static const struct display_timing auo_g185han01_timings = {
547 .pixelclock = { 120000000, 144000000, 175000000 },
548 .hactive = { 1920, 1920, 1920 },
549 .hfront_porch = { 18, 60, 74 },
550 .hback_porch = { 12, 44, 54 },
551 .hsync_len = { 10, 24, 32 },
552 .vactive = { 1080, 1080, 1080 },
553 .vfront_porch = { 6, 10, 40 },
554 .vback_porch = { 2, 5, 20 },
555 .vsync_len = { 2, 5, 20 },
558 static const struct panel_desc auo_g185han01 = {
559 .timings = &auo_g185han01_timings,
572 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
575 static const struct display_timing auo_p320hvn03_timings = {
576 .pixelclock = { 106000000, 148500000, 164000000 },
577 .hactive = { 1920, 1920, 1920 },
578 .hfront_porch = { 25, 50, 130 },
579 .hback_porch = { 25, 50, 130 },
580 .hsync_len = { 20, 40, 105 },
581 .vactive = { 1080, 1080, 1080 },
582 .vfront_porch = { 8, 17, 150 },
583 .vback_porch = { 8, 17, 150 },
584 .vsync_len = { 4, 11, 100 },
587 static const struct panel_desc auo_p320hvn03 = {
588 .timings = &auo_p320hvn03_timings,
600 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
603 static const struct drm_display_mode auo_t215hvn01_mode =
604 SP_DISPLAY_MODE(148800, 1920, 88, 44, 148, 1080, 4, 5, 36, 60, 0);
606 static const struct panel_desc auo_t215hvn01 = {
607 .modes = &auo_t215hvn01_mode,
620 static const struct drm_display_mode avic_tm070ddh03_mode =
621 SP_DISPLAY_MODE(51200, 1024, 160, 4, 156, 600, 17, 1, 17, 60, 0);
623 static const struct panel_desc avic_tm070ddh03 = {
624 .modes = &avic_tm070ddh03_mode,
638 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
639 SP_DISPLAY_MODE(71900, 1280, 48, 32, 80, 800, 3, 5, 24, 60, 0),
640 SP_DISPLAY_MODE(57500, 1280, 48, 32, 80, 800, 3, 5, 24, 48, 0),
643 static const struct panel_desc boe_nv101wxmn51 = {
644 .modes = boe_nv101wxmn51_modes,
645 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
658 static const struct drm_display_mode chunghwa_claa070wp03xg_mode =
659 SP_DISPLAY_MODE(66770, 800, 49, 33, 17, 1280, 1, 7, 15, 60,
660 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
662 static const struct panel_desc chunghwa_claa070wp03xg = {
663 .modes = &chunghwa_claa070wp03xg_mode,
672 static const struct drm_display_mode chunghwa_claa101wa01a_mode =
673 SP_DISPLAY_MODE(72070, 1366, 58, 58, 58, 768, 4, 4, 4, 60, 0);
675 static const struct panel_desc chunghwa_claa101wa01a = {
676 .modes = &chunghwa_claa101wa01a_mode,
685 static const struct drm_display_mode chunghwa_claa101wb01_mode =
686 SP_DISPLAY_MODE(69300, 1366, 48, 32, 20, 768, 16, 8, 16, 60, 0);
688 static const struct panel_desc chunghwa_claa101wb01 = {
689 .modes = &chunghwa_claa101wb01_mode,
698 static const struct drm_display_mode edt_et057090dhu_mode =
699 SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
700 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
702 static const struct panel_desc edt_et057090dhu = {
703 .modes = &edt_et057090dhu_mode,
710 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
711 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
714 static const struct drm_display_mode edt_etm0700g0dh6_mode =
715 SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60,
716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
718 static const struct panel_desc edt_etm0700g0dh6 = {
719 .modes = &edt_etm0700g0dh6_mode,
726 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
727 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
730 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
731 SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
733 static const struct panel_desc foxlink_fl500wvr00_a0t = {
734 .modes = &foxlink_fl500wvr00_a0t_mode,
741 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
744 static const struct drm_display_mode giantplus_gpg482739qs5_mode =
745 SP_DISPLAY_MODE(9000, 480, 5, 1, 40, 272, 8, 1, 8, 60, 0);
747 static const struct panel_desc giantplus_gpg482739qs5 = {
748 .modes = &giantplus_gpg482739qs5_mode,
755 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
758 static const struct display_timing hannstar_hsd070pww1_timing = {
759 .pixelclock = { 64300000, 71100000, 82000000 },
760 .hactive = { 1280, 1280, 1280 },
761 .hfront_porch = { 1, 1, 10 },
762 .hback_porch = { 1, 1, 10 },
764 * According to the data sheet, the minimum horizontal blanking interval
765 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
766 * minimum working horizontal blanking interval to be 60 clocks.
768 .hsync_len = { 58, 158, 661 },
769 .vactive = { 800, 800, 800 },
770 .vfront_porch = { 1, 1, 10 },
771 .vback_porch = { 1, 1, 10 },
772 .vsync_len = { 1, 21, 203 },
773 .flags = DISPLAY_FLAGS_DE_HIGH,
776 static const struct panel_desc hannstar_hsd070pww1 = {
777 .timings = &hannstar_hsd070pww1_timing,
784 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
787 static const struct display_timing hannstar_hsd100pxn1_timing = {
788 .pixelclock = { 55000000, 65000000, 75000000 },
789 .hactive = { 1024, 1024, 1024 },
790 .hfront_porch = { 40, 40, 40 },
791 .hback_porch = { 220, 220, 220 },
792 .hsync_len = { 20, 60, 100 },
793 .vactive = { 768, 768, 768 },
794 .vfront_porch = { 7, 7, 7 },
795 .vback_porch = { 21, 21, 21 },
796 .vsync_len = { 10, 10, 10 },
797 .flags = DISPLAY_FLAGS_DE_HIGH,
800 static const struct panel_desc hannstar_hsd100pxn1 = {
801 .timings = &hannstar_hsd100pxn1_timing,
808 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
811 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode =
812 SP_DISPLAY_MODE(33333, 800, 85, 86, 85, 480, 16, 13, 16, 60, 0);
814 static const struct panel_desc hitachi_tx23d38vm0caa = {
815 .modes = &hitachi_tx23d38vm0caa_mode,
824 static const struct drm_display_mode innolux_at043tn24_mode =
825 SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 11, 2, 60,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
828 static const struct panel_desc innolux_at043tn24 = {
829 .modes = &innolux_at043tn24_mode,
836 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
839 static const struct drm_display_mode innolux_at070tn92_mode =
840 SP_DISPLAY_MODE(33333, 800, 210, 20, 46, 480, 22, 10, 23, 60, 0);
842 static const struct panel_desc innolux_at070tn92 = {
843 .modes = &innolux_at070tn92_mode,
849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
852 static const struct display_timing innolux_g101ice_l01_timing = {
853 .pixelclock = { 60400000, 71100000, 74700000 },
854 .hactive = { 1280, 1280, 1280 },
855 .hfront_porch = { 41, 80, 100 },
856 .hback_porch = { 40, 79, 99 },
857 .hsync_len = { 1, 1, 1 },
858 .vactive = { 800, 800, 800 },
859 .vfront_porch = { 5, 11, 14 },
860 .vback_porch = { 4, 11, 14 },
861 .vsync_len = { 1, 1, 1 },
862 .flags = DISPLAY_FLAGS_DE_HIGH,
865 static const struct panel_desc innolux_g101ice_l01 = {
866 .timings = &innolux_g101ice_l01_timing,
877 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
880 static const struct display_timing innolux_g121i1_l01_timing = {
881 .pixelclock = { 67450000, 71000000, 74550000 },
882 .hactive = { 1280, 1280, 1280 },
883 .hfront_porch = { 40, 80, 160 },
884 .hback_porch = { 39, 79, 159 },
885 .hsync_len = { 1, 1, 1 },
886 .vactive = { 800, 800, 800 },
887 .vfront_porch = { 5, 11, 100 },
888 .vback_porch = { 4, 11, 99 },
889 .vsync_len = { 1, 1, 1 },
892 static const struct panel_desc innolux_g121i1_l01 = {
893 .timings = &innolux_g121i1_l01_timing,
904 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
907 static const struct drm_display_mode innolux_g121x1_l03_mode =
908 SP_DISPLAY_MODE(65000, 1024, 0, 1, 320, 768, 38, 1, 0, 60,
909 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
911 static const struct panel_desc innolux_g121x1_l03 = {
912 .modes = &innolux_g121x1_l03_mode,
926 static const struct drm_display_mode innolux_n116bge_mode =
927 SP_DISPLAY_MODE(76420, 1366, 136, 30, 60, 768, 8, 12, 12, 60,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
930 static const struct panel_desc innolux_n116bge = {
931 .modes = &innolux_n116bge_mode,
940 static const struct drm_display_mode innolux_n156bge_l21_mode =
941 SP_DISPLAY_MODE(69300, 1366, 16, 34, 50, 768, 2, 6, 12, 60, 0);
943 static const struct panel_desc innolux_n156bge_l21 = {
944 .modes = &innolux_n156bge_l21_mode,
953 static const struct drm_display_mode innolux_zj070na_01p_mode =
954 SP_DISPLAY_MODE(51501, 1024, 128, 64, 128, 600, 16, 4, 16, 60, 0);
956 static const struct panel_desc innolux_zj070na_01p = {
957 .modes = &innolux_zj070na_01p_mode,
966 static const struct display_timing kyo_tcg121xglp_timing = {
967 .pixelclock = { 52000000, 65000000, 71000000 },
968 .hactive = { 1024, 1024, 1024 },
969 .hfront_porch = { 2, 2, 2 },
970 .hback_porch = { 2, 2, 2 },
971 .hsync_len = { 86, 124, 244 },
972 .vactive = { 768, 768, 768 },
973 .vfront_porch = { 2, 2, 2 },
974 .vback_porch = { 2, 2, 2 },
975 .vsync_len = { 6, 34, 73 },
976 .flags = DISPLAY_FLAGS_DE_HIGH,
979 static const struct panel_desc kyo_tcg121xglp = {
980 .timings = &kyo_tcg121xglp_timing,
987 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
990 static const struct drm_display_mode lg_lb070wv8_mode =
991 SP_DISPLAY_MODE(33246, 800, 88, 80, 88, 480, 10, 25, 10, 60, 0);
993 static const struct panel_desc lg_lb070wv8 = {
994 .modes = &lg_lb070wv8_mode,
1001 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1004 static const struct drm_display_mode lg_lp079qx1_sp0v_mode =
1005 SP_DISPLAY_MODE(200000, 1536, 12, 16, 48, 2048, 8, 4, 8, 60,
1006 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1008 static const struct panel_desc lg_lp079qx1_sp0v = {
1009 .modes = &lg_lp079qx1_sp0v_mode,
1017 static const struct drm_display_mode lg_lp097qx1_spa1_mode =
1018 SP_DISPLAY_MODE(205210, 2048, 150, 5, 5, 1536, 3, 1, 9, 60, 0);
1020 static const struct panel_desc lg_lp097qx1_spa1 = {
1021 .modes = &lg_lp097qx1_spa1_mode,
1029 static const struct drm_display_mode lg_lp120up1_mode =
1030 SP_DISPLAY_MODE(162300, 1920, 40, 40, 80, 1280, 4, 4, 12, 60, 0);
1032 static const struct panel_desc lg_lp120up1 = {
1033 .modes = &lg_lp120up1_mode,
1042 static const struct drm_display_mode lg_lp129qe_mode =
1043 SP_DISPLAY_MODE(285250, 2560, 48, 32, 80, 1700, 3, 10, 36, 60, 0);
1045 static const struct panel_desc lg_lp129qe = {
1046 .modes = &lg_lp129qe_mode,
1055 static const struct display_timing nec_nl12880bc20_05_timing = {
1056 .pixelclock = { 67000000, 71000000, 75000000 },
1057 .hactive = { 1280, 1280, 1280 },
1058 .hfront_porch = { 2, 30, 30 },
1059 .hback_porch = { 6, 100, 100 },
1060 .hsync_len = { 2, 30, 30 },
1061 .vactive = { 800, 800, 800 },
1062 .vfront_porch = { 5, 5, 5 },
1063 .vback_porch = { 11, 11, 11 },
1064 .vsync_len = { 7, 7, 7 },
1067 static const struct panel_desc nec_nl12880bc20_05 = {
1068 .timings = &nec_nl12880bc20_05_timing,
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1082 static const struct drm_display_mode nec_nl4827hc19_05b_mode =
1083 SP_DISPLAY_MODE(10870, 480, 2, 41, 2, 272, 2, 4, 2, 74,
1084 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1086 static const struct panel_desc nec_nl4827hc19_05b = {
1087 .modes = &nec_nl4827hc19_05b_mode,
1094 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1095 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1098 static const struct drm_display_mode netron_dy_e231732_mode =
1099 SP_DISPLAY_MODE(66000, 1024, 160, 70, 90, 600, 127, 20, 3, 60, 0);
1101 static const struct panel_desc netron_dy_e231732 = {
1102 .modes = &netron_dy_e231732_mode,
1108 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1111 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1112 .pixelclock = { 130000000, 148350000, 163000000 },
1113 .hactive = { 1920, 1920, 1920 },
1114 .hfront_porch = { 80, 100, 100 },
1115 .hback_porch = { 100, 120, 120 },
1116 .hsync_len = { 50, 60, 60 },
1117 .vactive = { 1080, 1080, 1080 },
1118 .vfront_porch = { 12, 30, 30 },
1119 .vback_porch = { 4, 10, 10 },
1120 .vsync_len = { 4, 5, 5 },
1123 static const struct panel_desc nlt_nl192108ac18_02d = {
1124 .timings = &nlt_nl192108ac18_02d_timing,
1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1137 static const struct drm_display_mode nvd_9128_mode =
1138 SP_DISPLAY_MODE(29500, 800, 130, 98, 0, 480, 10, 50, 0, 0, 0);
1140 static const struct panel_desc nvd_9128 = {
1141 .modes = &nvd_9128_mode,
1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1151 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1152 .pixelclock = { 30000000, 30000000, 40000000 },
1153 .hactive = { 800, 800, 800 },
1154 .hfront_porch = { 40, 40, 40 },
1155 .hback_porch = { 40, 40, 40 },
1156 .hsync_len = { 1, 48, 48 },
1157 .vactive = { 480, 480, 480 },
1158 .vfront_porch = { 13, 13, 13 },
1159 .vback_porch = { 29, 29, 29 },
1160 .vsync_len = { 3, 3, 3 },
1161 .flags = DISPLAY_FLAGS_DE_HIGH,
1164 static const struct panel_desc okaya_rs800480t_7x0gp = {
1165 .timings = &okaya_rs800480t_7x0gp_timing,
1178 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1181 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode =
1182 SP_DISPLAY_MODE(9000, 480, 5, 30, 10, 272, 8, 5, 3, 60, 0);
1184 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1185 .modes = &olimex_lcd_olinuxino_43ts_mode,
1191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1195 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1196 * pixel clocks, but this is the timing that was being used in the Adafruit
1197 * installation instructions.
1199 static const struct drm_display_mode ontat_yx700wv03_mode =
1200 SP_DISPLAY_MODE(29500, 800, 24, 72, 96, 480, 3, 10, 7, 60,
1201 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1205 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1207 static const struct panel_desc ontat_yx700wv03 = {
1208 .modes = &ontat_yx700wv03_mode,
1215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1218 static const struct drm_display_mode ortustech_com43h4m85ulc_mode =
1219 SP_DISPLAY_MODE(25000, 480, 10, 10, 15, 800, 3, 3, 3, 60, 0);
1221 static const struct panel_desc ortustech_com43h4m85ulc = {
1222 .modes = &ortustech_com43h4m85ulc_mode,
1229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1233 static const struct drm_display_mode qd43003c0_40_mode =
1234 SP_DISPLAY_MODE(9000, 480, 8, 4, 39, 272, 4, 10, 2, 60, 0);
1236 static const struct panel_desc qd43003c0_40 = {
1237 .modes = &qd43003c0_40_mode,
1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1247 static const struct drm_display_mode samsung_lsn122dl01_c01_mode =
1248 SP_DISPLAY_MODE(271560, 2560, 48, 32, 80, 1600, 2, 5, 57, 60, 0);
1250 static const struct panel_desc samsung_lsn122dl01_c01 = {
1251 .modes = &samsung_lsn122dl01_c01_mode,
1259 static const struct drm_display_mode samsung_ltn101nt05_mode =
1260 SP_DISPLAY_MODE(54030, 1024, 24, 136, 160, 600, 3, 6, 61, 60, 0);
1262 static const struct panel_desc samsung_ltn101nt05 = {
1263 .modes = &samsung_ltn101nt05_mode,
1272 static const struct drm_display_mode samsung_ltn140at29_301_mode =
1273 SP_DISPLAY_MODE(76300, 1366, 64, 48, 128, 768, 2, 5, 17, 60, 0);
1275 static const struct panel_desc samsung_ltn140at29_301 = {
1276 .modes = &samsung_ltn140at29_301_mode,
1285 static const struct display_timing sharp_lq101k1ly04_timing = {
1286 .pixelclock = { 60000000, 65000000, 80000000 },
1287 .hactive = { 1280, 1280, 1280 },
1288 .hfront_porch = { 20, 20, 20 },
1289 .hback_porch = { 20, 20, 20 },
1290 .hsync_len = { 10, 10, 10 },
1291 .vactive = { 800, 800, 800 },
1292 .vfront_porch = { 4, 4, 4 },
1293 .vback_porch = { 4, 4, 4 },
1294 .vsync_len = { 4, 4, 4 },
1295 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1298 static const struct panel_desc sharp_lq101k1ly04 = {
1299 .timings = &sharp_lq101k1ly04_timing,
1306 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1309 static const struct drm_display_mode sharp_lq123p1jx31_mode =
1310 SP_DISPLAY_MODE(252750, 2400, 48, 32, 80, 1600, 3, 10, 33, 60,
1311 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1313 static const struct panel_desc sharp_lq123p1jx31 = {
1314 .modes = &sharp_lq123p1jx31_mode,
1328 static const struct drm_display_mode sharp_lq150x1lg11_mode =
1329 SP_DISPLAY_MODE(71100, 1024, 168, 64, 88, 768, 37, 2, 8, 60, 0);
1331 static const struct panel_desc sharp_lq150x1lg11 = {
1332 .modes = &sharp_lq150x1lg11_mode,
1339 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1342 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode =
1343 SP_DISPLAY_MODE(33300, 800, 1, 64, 64, 480, 1, 23, 22, 60, 0);
1345 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1346 .modes = &shelly_sca07010_bfn_lnn_mode,
1352 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1355 static const struct drm_display_mode starry_kr122ea0sra_mode =
1356 SP_DISPLAY_MODE(147000, 1920, 16, 16, 32, 1200, 15, 2, 18, 60,
1357 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1359 static const struct panel_desc starry_kr122ea0sra = {
1360 .modes = &starry_kr122ea0sra_mode,
1367 .prepare = 10 + 200,
1369 .unprepare = 10 + 500,
1373 static const struct display_timing tianma_tm070jdhg30_timing = {
1374 .pixelclock = { 62600000, 68200000, 78100000 },
1375 .hactive = { 1280, 1280, 1280 },
1376 .hfront_porch = { 15, 64, 159 },
1377 .hback_porch = { 5, 5, 5 },
1378 .hsync_len = { 1, 1, 256 },
1379 .vactive = { 800, 800, 800 },
1380 .vfront_porch = { 3, 40, 99 },
1381 .vback_porch = { 2, 2, 2 },
1382 .vsync_len = { 1, 1, 128 },
1383 .flags = DISPLAY_FLAGS_DE_HIGH,
1386 static const struct panel_desc tianma_tm070jdhg30 = {
1387 .timings = &tianma_tm070jdhg30_timing,
1394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1397 static const struct drm_display_mode tpk_f07a_0102_mode =
1398 SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60, 0);
1400 static const struct panel_desc tpk_f07a_0102 = {
1401 .modes = &tpk_f07a_0102_mode,
1407 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1410 static const struct drm_display_mode tpk_f10a_0102_mode =
1411 SP_DISPLAY_MODE(45000, 1024, 176, 5, 88, 600, 20, 5, 25, 60, 0);
1413 static const struct panel_desc tpk_f10a_0102 = {
1414 .modes = &tpk_f10a_0102_mode,
1422 static const struct display_timing urt_umsh_8596md_timing = {
1423 .pixelclock = { 33260000, 33260000, 33260000 },
1424 .hactive = { 800, 800, 800 },
1425 .hfront_porch = { 41, 41, 41 },
1426 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1427 .hsync_len = { 71, 128, 128 },
1428 .vactive = { 480, 480, 480 },
1429 .vfront_porch = { 10, 10, 10 },
1430 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1431 .vsync_len = { 2, 2, 2 },
1432 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1433 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1436 static const struct panel_desc urt_umsh_8596md_lvds = {
1437 .timings = &urt_umsh_8596md_timing,
1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1447 static const struct panel_desc urt_umsh_8596md_parallel = {
1448 .timings = &urt_umsh_8596md_timing,
1455 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1458 static const struct drm_display_mode winstar_wf35ltiacd_mode =
1459 SP_DISPLAY_MODE(6410, 320, 20, 30, 38, 240, 4, 3, 15, 60,
1460 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1462 static const struct panel_desc winstar_wf35ltiacd = {
1463 .modes = &winstar_wf35ltiacd_mode,
1470 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1473 static const struct of_device_id platform_of_match[] = {
1475 .compatible = "ampire,am-480272h3tmqw-t01h",
1476 .data = &ire_am_480272h3tmqw_t01h,
1478 .compatible = "ampire,am800480r3tmqwa1h",
1479 .data = &ire_am800480r3tmqwa1h,
1481 .compatible = "auo,b101aw03",
1482 .data = &auo_b101aw03,
1484 .compatible = "auo,b101ean01",
1485 .data = &auo_b101ean01,
1487 .compatible = "auo,b101xtn01",
1488 .data = &auo_b101xtn01,
1490 .compatible = "auo,b116xw03",
1491 .data = &auo_b116xw03,
1493 .compatible = "auo,b133htn01",
1494 .data = &auo_b133htn01,
1496 .compatible = "auo,b133xtn01",
1497 .data = &auo_b133xtn01,
1499 .compatible = "auo,g133han01",
1500 .data = &auo_g133han01,
1502 .compatible = "auo,g185han01",
1503 .data = &auo_g185han01,
1505 .compatible = "auo,p320hvn03",
1506 .data = &auo_p320hvn03,
1508 .compatible = "auo,t215hvn01",
1509 .data = &auo_t215hvn01,
1511 .compatible = "avic,tm070ddh03",
1512 .data = &avic_tm070ddh03,
1514 .compatible = "boe,nv101wxmn51",
1515 .data = &boe_nv101wxmn51,
1517 .compatible = "chunghwa,claa070wp03xg",
1518 .data = &chunghwa_claa070wp03xg,
1520 .compatible = "chunghwa,claa101wa01a",
1521 .data = &chunghwa_claa101wa01a
1523 .compatible = "chunghwa,claa101wb01",
1524 .data = &chunghwa_claa101wb01
1526 .compatible = "edt,et057090dhu",
1527 .data = &edt_et057090dhu,
1529 .compatible = "edt,et070080dh6",
1530 .data = &edt_etm0700g0dh6,
1532 .compatible = "edt,etm0700g0dh6",
1533 .data = &edt_etm0700g0dh6,
1535 .compatible = "foxlink,fl500wvr00-a0t",
1536 .data = &foxlink_fl500wvr00_a0t,
1538 .compatible = "giantplus,gpg482739qs5",
1539 .data = &giantplus_gpg482739qs5
1541 .compatible = "hannstar,hsd070pww1",
1542 .data = &hannstar_hsd070pww1,
1544 .compatible = "hannstar,hsd100pxn1",
1545 .data = &hannstar_hsd100pxn1,
1547 .compatible = "hit,tx23d38vm0caa",
1548 .data = &hitachi_tx23d38vm0caa
1550 .compatible = "innolux,at043tn24",
1551 .data = &innolux_at043tn24,
1553 .compatible = "innolux,at070tn92",
1554 .data = &innolux_at070tn92,
1556 .compatible ="innolux,g101ice-l01",
1557 .data = &innolux_g101ice_l01
1559 .compatible ="innolux,g121i1-l01",
1560 .data = &innolux_g121i1_l01
1562 .compatible = "innolux,g121x1-l03",
1563 .data = &innolux_g121x1_l03,
1565 .compatible = "innolux,n116bge",
1566 .data = &innolux_n116bge,
1568 .compatible = "innolux,n156bge-l21",
1569 .data = &innolux_n156bge_l21,
1571 .compatible = "innolux,zj070na-01p",
1572 .data = &innolux_zj070na_01p,
1574 .compatible = "kyo,tcg121xglp",
1575 .data = &kyo_tcg121xglp,
1577 .compatible = "lg,lb070wv8",
1578 .data = &lg_lb070wv8,
1580 .compatible = "lg,lp079qx1-sp0v",
1581 .data = &lg_lp079qx1_sp0v,
1583 .compatible = "lg,lp097qx1-spa1",
1584 .data = &lg_lp097qx1_spa1,
1586 .compatible = "lg,lp120up1",
1587 .data = &lg_lp120up1,
1589 .compatible = "lg,lp129qe",
1590 .data = &lg_lp129qe,
1592 .compatible = "nec,nl12880bc20-05",
1593 .data = &nec_nl12880bc20_05,
1595 .compatible = "nec,nl4827hc19-05b",
1596 .data = &nec_nl4827hc19_05b,
1598 .compatible = "netron-dy,e231732",
1599 .data = &netron_dy_e231732,
1601 .compatible = "nlt,nl192108ac18-02d",
1602 .data = &nlt_nl192108ac18_02d,
1604 .compatible = "nvd,9128",
1607 .compatible = "okaya,rs800480t-7x0gp",
1608 .data = &okaya_rs800480t_7x0gp,
1610 .compatible = "olimex,lcd-olinuxino-43-ts",
1611 .data = &olimex_lcd_olinuxino_43ts,
1613 .compatible = "ontat,yx700wv03",
1614 .data = &ontat_yx700wv03,
1616 .compatible = "ortustech,com43h4m85ulc",
1617 .data = &ortustech_com43h4m85ulc,
1619 .compatible = "qiaodian,qd43003c0-40",
1620 .data = &qd43003c0_40,
1622 .compatible = "samsung,lsn122dl01-c01",
1623 .data = &samsung_lsn122dl01_c01,
1625 .compatible = "samsung,ltn101nt05",
1626 .data = &samsung_ltn101nt05,
1628 .compatible = "samsung,ltn140at29-301",
1629 .data = &samsung_ltn140at29_301,
1631 .compatible = "sharp,lq101k1ly04",
1632 .data = &sharp_lq101k1ly04,
1634 .compatible = "sharp,lq123p1jx31",
1635 .data = &sharp_lq123p1jx31,
1637 .compatible = "sharp,lq150x1lg11",
1638 .data = &sharp_lq150x1lg11,
1640 .compatible = "shelly,sca07010-bfn-lnn",
1641 .data = &shelly_sca07010_bfn_lnn,
1643 .compatible = "starry,kr122ea0sra",
1644 .data = &starry_kr122ea0sra,
1646 .compatible = "tianma,tm070jdhg30",
1647 .data = &tianma_tm070jdhg30,
1649 .compatible = "tpk,f07a-0102",
1650 .data = &tpk_f07a_0102,
1652 .compatible = "tpk,f10a-0102",
1653 .data = &tpk_f10a_0102,
1655 .compatible = "urt,umsh-8596md-t",
1656 .data = &urt_umsh_8596md_parallel,
1658 .compatible = "urt,umsh-8596md-1t",
1659 .data = &urt_umsh_8596md_parallel,
1661 .compatible = "urt,umsh-8596md-7t",
1662 .data = &urt_umsh_8596md_parallel,
1664 .compatible = "urt,umsh-8596md-11t",
1665 .data = &urt_umsh_8596md_lvds,
1667 .compatible = "urt,umsh-8596md-19t",
1668 .data = &urt_umsh_8596md_lvds,
1670 .compatible = "urt,umsh-8596md-20t",
1671 .data = &urt_umsh_8596md_parallel,
1673 .compatible = "winstar,wf35ltiacd",
1674 .data = &winstar_wf35ltiacd,
1679 MODULE_DEVICE_TABLE(of, platform_of_match);
1681 static int panel_simple_platform_probe(struct platform_device *pdev)
1683 const struct of_device_id *id;
1685 id = of_match_node(platform_of_match, pdev->dev.of_node);
1689 return panel_simple_probe(&pdev->dev, id->data);
1692 static int panel_simple_platform_remove(struct platform_device *pdev)
1694 return panel_simple_remove(&pdev->dev);
1697 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1699 panel_simple_shutdown(&pdev->dev);
1702 static struct platform_driver panel_simple_platform_driver = {
1704 .name = "panel-simple",
1705 .of_match_table = platform_of_match,
1707 .probe = panel_simple_platform_probe,
1708 .remove = panel_simple_platform_remove,
1709 .shutdown = panel_simple_platform_shutdown,
1712 struct panel_desc_dsi {
1713 struct panel_desc desc;
1715 unsigned long flags;
1716 enum mipi_dsi_pixel_format format;
1720 static const struct drm_display_mode auo_b080uan01_mode =
1721 SP_DISPLAY_MODE(154500, 1200, 62, 4, 62, 1920, 9, 2, 8, 60, 0);
1723 static const struct panel_desc_dsi auo_b080uan01 = {
1725 .modes = &auo_b080uan01_mode,
1733 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1734 .format = MIPI_DSI_FMT_RGB888,
1738 static const struct drm_display_mode boe_tv080wum_nl0_mode =
1739 SP_DISPLAY_MODE(160000, 1200, 120, 20, 21, 1920, 21, 3, 18, 60,
1740 DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1742 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1744 .modes = &boe_tv080wum_nl0_mode,
1751 .flags = MIPI_DSI_MODE_VIDEO |
1752 MIPI_DSI_MODE_VIDEO_BURST |
1753 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1754 .format = MIPI_DSI_FMT_RGB888,
1758 static const struct drm_display_mode lg_ld070wx3_sl01_mode =
1759 SP_DISPLAY_MODE(71000, 800, 32, 1, 57, 1280, 28, 1, 14, 60, 0);
1761 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1763 .modes = &lg_ld070wx3_sl01_mode,
1771 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1772 .format = MIPI_DSI_FMT_RGB888,
1776 static const struct drm_display_mode lg_lh500wx1_sd03_mode =
1777 SP_DISPLAY_MODE(67000, 720, 12, 4, 112, 1280, 8, 4, 12, 60, 0);
1779 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1781 .modes = &lg_lh500wx1_sd03_mode,
1789 .flags = MIPI_DSI_MODE_VIDEO,
1790 .format = MIPI_DSI_FMT_RGB888,
1794 static const struct drm_display_mode panasonic_vvx10f004b00_mode =
1795 SP_DISPLAY_MODE(157200, 1920, 154, 16, 32, 1200, 17, 2, 16, 60, 0);
1797 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1799 .modes = &panasonic_vvx10f004b00_mode,
1807 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1808 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1809 .format = MIPI_DSI_FMT_RGB888,
1813 static const struct of_device_id dsi_of_match[] = {
1815 .compatible = "auo,b080uan01",
1816 .data = &auo_b080uan01
1818 .compatible = "boe,tv080wum-nl0",
1819 .data = &boe_tv080wum_nl0
1821 .compatible = "lg,ld070wx3-sl01",
1822 .data = &lg_ld070wx3_sl01
1824 .compatible = "lg,lh500wx1-sd03",
1825 .data = &lg_lh500wx1_sd03
1827 .compatible = "panasonic,vvx10f004b00",
1828 .data = &panasonic_vvx10f004b00
1833 MODULE_DEVICE_TABLE(of, dsi_of_match);
1835 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1837 const struct panel_desc_dsi *desc;
1838 const struct of_device_id *id;
1841 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1847 err = panel_simple_probe(&dsi->dev, &desc->desc);
1851 dsi->mode_flags = desc->flags;
1852 dsi->format = desc->format;
1853 dsi->lanes = desc->lanes;
1855 return mipi_dsi_attach(dsi);
1858 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1862 err = mipi_dsi_detach(dsi);
1864 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1866 return panel_simple_remove(&dsi->dev);
1869 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1871 panel_simple_shutdown(&dsi->dev);
1874 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1876 .name = "panel-simple-dsi",
1877 .of_match_table = dsi_of_match,
1879 .probe = panel_simple_dsi_probe,
1880 .remove = panel_simple_dsi_remove,
1881 .shutdown = panel_simple_dsi_shutdown,
1884 static int __init panel_simple_init(void)
1888 err = platform_driver_register(&panel_simple_platform_driver);
1892 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1893 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1900 module_init(panel_simple_init);
1902 static void __exit panel_simple_exit(void)
1904 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1905 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1907 platform_driver_unregister(&panel_simple_platform_driver);
1909 module_exit(panel_simple_exit);
1911 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1912 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1913 MODULE_LICENSE("GPL and additional rights");