drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_audio.h"
  31 #include "atom.h"
  32 #include <linux/backlight.h>
  33
  34 extern int atom_debug;
  35
  36 static u8
  37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  38 {
  39         u8 backlight_level;
  40         u32 bios_2_scratch;
  41
  42         if (rdev->family >= CHIP_R600)
  43                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  44         else
  45                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  46
  47         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  48                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  49
  50         return backlight_level;
  51 }
  52
  53 static void
  54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  55                                        u8 backlight_level)
  56 {
  57         u32 bios_2_scratch;
  58
  59         if (rdev->family >= CHIP_R600)
  60                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  61         else
  62                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  63
  64         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  65         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  66                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  67
  68         if (rdev->family >= CHIP_R600)
  69                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  70         else
  71                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  72 }
  73
  74 u8
  75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  76 {
  77         struct drm_device *dev = radeon_encoder->base.dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79
  80         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  81                 return 0;
  82
  83         return radeon_atom_get_backlight_level_from_reg(rdev);
  84 }
  85
  86 void
  87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  88 {
  89         struct drm_encoder *encoder = &radeon_encoder->base;
  90         struct drm_device *dev = radeon_encoder->base.dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         struct radeon_encoder_atom_dig *dig;
  93         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  94         int index;
  95
  96         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  97                 return;
  98
  99         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 100             radeon_encoder->enc_priv) {
 101                 dig = radeon_encoder->enc_priv;
 102                 dig->backlight_level = level;
 103                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 104
 105                 switch (radeon_encoder->encoder_id) {
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 107                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 108                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 109                         if (dig->backlight_level == 0) {
 110                                 args.ucAction = ATOM_LCD_BLOFF;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                         } else {
 113                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 114                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 115                                 args.ucAction = ATOM_LCD_BLON;
 116                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 117                         }
 118                         break;
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 120                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 123                         if (dig->backlight_level == 0)
 124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 125                         else {
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 127                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 128                         }
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 137
 138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 139 {
 140         u8 level;
 141
 142         /* Convert brightness to hardware level */
 143         if (bd->props.brightness < 0)
 144                 level = 0;
 145         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 146                 level = RADEON_MAX_BL_LEVEL;
 147         else
 148                 level = bd->props.brightness;
 149
 150         return level;
 151 }
 152
 153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 154 {
 155         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 156         struct radeon_encoder *radeon_encoder = pdata->encoder;
 157
 158         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 159
 160         return 0;
 161 }
 162
 163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 164 {
 165         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 166         struct radeon_encoder *radeon_encoder = pdata->encoder;
 167         struct drm_device *dev = radeon_encoder->base.dev;
 168         struct radeon_device *rdev = dev->dev_private;
 169
 170         return radeon_atom_get_backlight_level_from_reg(rdev);
 171 }
 172
 173 static const struct backlight_ops radeon_atom_backlight_ops = {
 174         .get_brightness = radeon_atom_backlight_get_brightness,
 175         .update_status  = radeon_atom_backlight_update_status,
 176 };
 177
 178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 179                                 struct drm_connector *drm_connector)
 180 {
 181         struct drm_device *dev = radeon_encoder->base.dev;
 182         struct radeon_device *rdev = dev->dev_private;
 183         struct backlight_device *bd;
 184         struct backlight_properties props;
 185         struct radeon_backlight_privdata *pdata;
 186         struct radeon_encoder_atom_dig *dig;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         dig = radeon_encoder->enc_priv;
 226         dig->bl_dev = bd;
 227
 228         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 229         /* Set a reasonable default here if the level is 0 otherwise
 230          * fbdev will attempt to turn the backlight on after console
 231          * unblanking and it will try and restore 0 which turns the backlight
 232          * off again.
 233          */
 234         if (bd->props.brightness == 0)
 235                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 236         bd->props.power = FB_BLANK_UNBLANK;
 237         backlight_update_status(bd);
 238
 239         DRM_INFO("radeon atom DIG backlight initialized\n");
 240         rdev->mode_info.bl_encoder = radeon_encoder;
 241
 242         return;
 243
 244 error:
 245         kfree(pdata);
 246         return;
 247 }
 248
 249 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 250 {
 251         struct drm_device *dev = radeon_encoder->base.dev;
 252         struct radeon_device *rdev = dev->dev_private;
 253         struct backlight_device *bd = NULL;
 254         struct radeon_encoder_atom_dig *dig;
 255
 256         if (!radeon_encoder->enc_priv)
 257                 return;
 258
 259         if (!rdev->is_atom_bios)
 260                 return;
 261
 262         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 263                 return;
 264
 265         dig = radeon_encoder->enc_priv;
 266         bd = dig->bl_dev;
 267         dig->bl_dev = NULL;
 268
 269         if (bd) {
 270                 struct radeon_legacy_backlight_privdata *pdata;
 271
 272                 pdata = bl_get_data(bd);
 273                 backlight_device_unregister(bd);
 274                 kfree(pdata);
 275
 276                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 277         }
 278 }
 279
 280 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 281
 282 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 283 {
 284 }
 285
 286 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 287 {
 288 }
 289
 290 #endif
 291
 292 /* evil but including atombios.h is much worse */
 293 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 294                                 struct drm_display_mode *mode);
 295
 296 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 297                                    const struct drm_display_mode *mode,
 298                                    struct drm_display_mode *adjusted_mode)
 299 {
 300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 301         struct drm_device *dev = encoder->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303
 304         /* set the active encoder to connector routing */
 305         radeon_encoder_set_active_device(encoder);
 306         drm_mode_set_crtcinfo(adjusted_mode, 0);
 307
 308         /* hw bug */
 309         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 310             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 311                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 312
 313         /* get the native mode for scaling */
 314         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 315                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 316         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 317                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 318                 if (tv_dac) {
 319                         if (tv_dac->tv_std == TV_STD_NTSC ||
 320                             tv_dac->tv_std == TV_STD_NTSC_J ||
 321                             tv_dac->tv_std == TV_STD_PAL_M)
 322                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 323                         else
 324                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 325                 }
 326         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 327                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 328         }
 329
 330         if (ASIC_IS_DCE3(rdev) &&
 331             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 332              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 333                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 334                 radeon_dp_set_link_config(connector, adjusted_mode);
 335         }
 336
 337         return true;
 338 }
 339
 340 static void
 341 atombios_dac_setup(struct drm_encoder *encoder, int action)
 342 {
 343         struct drm_device *dev = encoder->dev;
 344         struct radeon_device *rdev = dev->dev_private;
 345         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 346         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 347         int index = 0;
 348         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 349
 350         memset(&args, 0, sizeof(args));
 351
 352         switch (radeon_encoder->encoder_id) {
 353         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 354         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 355                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 356                 break;
 357         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 358         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 359                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 360                 break;
 361         }
 362
 363         args.ucAction = action;
 364
 365         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 366                 args.ucDacStandard = ATOM_DAC1_PS2;
 367         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 368                 args.ucDacStandard = ATOM_DAC1_CV;
 369         else {
 370                 switch (dac_info->tv_std) {
 371                 case TV_STD_PAL:
 372                 case TV_STD_PAL_M:
 373                 case TV_STD_SCART_PAL:
 374                 case TV_STD_SECAM:
 375                 case TV_STD_PAL_CN:
 376                         args.ucDacStandard = ATOM_DAC1_PAL;
 377                         break;
 378                 case TV_STD_NTSC:
 379                 case TV_STD_NTSC_J:
 380                 case TV_STD_PAL_60:
 381                 default:
 382                         args.ucDacStandard = ATOM_DAC1_NTSC;
 383                         break;
 384                 }
 385         }
 386         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 387
 388         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 389
 390 }
 391
 392 static void
 393 atombios_tv_setup(struct drm_encoder *encoder, int action)
 394 {
 395         struct drm_device *dev = encoder->dev;
 396         struct radeon_device *rdev = dev->dev_private;
 397         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 398         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 399         int index = 0;
 400         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 401
 402         memset(&args, 0, sizeof(args));
 403
 404         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 405
 406         args.sTVEncoder.ucAction = action;
 407
 408         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 409                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 410         else {
 411                 switch (dac_info->tv_std) {
 412                 case TV_STD_NTSC:
 413                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 414                         break;
 415                 case TV_STD_PAL:
 416                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 417                         break;
 418                 case TV_STD_PAL_M:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 420                         break;
 421                 case TV_STD_PAL_60:
 422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 423                         break;
 424                 case TV_STD_NTSC_J:
 425                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 426                         break;
 427                 case TV_STD_SCART_PAL:
 428                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 429                         break;
 430                 case TV_STD_SECAM:
 431                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 432                         break;
 433                 case TV_STD_PAL_CN:
 434                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 435                         break;
 436                 default:
 437                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 438                         break;
 439                 }
 440         }
 441
 442         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 443
 444         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 445
 446 }
 447
 448 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 449 {
 450         int bpc = 8;
 451
 452         if (encoder->crtc) {
 453                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 454                 bpc = radeon_crtc->bpc;
 455         }
 456
 457         switch (bpc) {
 458         case 0:
 459                 return PANEL_BPC_UNDEFINE;
 460         case 6:
 461                 return PANEL_6BIT_PER_COLOR;
 462         case 8:
 463         default:
 464                 return PANEL_8BIT_PER_COLOR;
 465         case 10:
 466                 return PANEL_10BIT_PER_COLOR;
 467         case 12:
 468                 return PANEL_12BIT_PER_COLOR;
 469         case 16:
 470                 return PANEL_16BIT_PER_COLOR;
 471         }
 472 }
 473
 474 union dvo_encoder_control {
 475         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 476         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 477         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 478         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 479 };
 480
 481 void
 482 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 483 {
 484         struct drm_device *dev = encoder->dev;
 485         struct radeon_device *rdev = dev->dev_private;
 486         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 487         union dvo_encoder_control args;
 488         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 489         uint8_t frev, crev;
 490
 491         memset(&args, 0, sizeof(args));
 492
 493         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 494                 return;
 495
 496         /* some R4xx chips have the wrong frev */
 497         if (rdev->family <= CHIP_RV410)
 498                 frev = 1;
 499
 500         switch (frev) {
 501         case 1:
 502                 switch (crev) {
 503                 case 1:
 504                         /* R4xx, R5xx */
 505                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 506
 507                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 508                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 509
 510                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 511                         break;
 512                 case 2:
 513                         /* RS600/690/740 */
 514                         args.dvo.sDVOEncoder.ucAction = action;
 515                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 516                         /* DFP1, CRT1, TV1 depending on the type of port */
 517                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 518
 519                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 520                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 521                         break;
 522                 case 3:
 523                         /* R6xx */
 524                         args.dvo_v3.ucAction = action;
 525                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 526                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 527                         break;
 528                 case 4:
 529                         /* DCE8 */
 530                         args.dvo_v4.ucAction = action;
 531                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 532                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 533                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 534                         break;
 535                 default:
 536                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 537                         break;
 538                 }
 539                 break;
 540         default:
 541                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 542                 break;
 543         }
 544
 545         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 546 }
 547
 548 union lvds_encoder_control {
 549         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 550         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 551 };
 552
 553 void
 554 atombios_digital_setup(struct drm_encoder *encoder, int action)
 555 {
 556         struct drm_device *dev = encoder->dev;
 557         struct radeon_device *rdev = dev->dev_private;
 558         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 559         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 560         union lvds_encoder_control args;
 561         int index = 0;
 562         int hdmi_detected = 0;
 563         uint8_t frev, crev;
 564
 565         if (!dig)
 566                 return;
 567
 568         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 569                 hdmi_detected = 1;
 570
 571         memset(&args, 0, sizeof(args));
 572
 573         switch (radeon_encoder->encoder_id) {
 574         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 575                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 576                 break;
 577         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 578         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 579                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 580                 break;
 581         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 582                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 583                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 584                 else
 585                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 586                 break;
 587         }
 588
 589         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 590                 return;
 591
 592         switch (frev) {
 593         case 1:
 594         case 2:
 595                 switch (crev) {
 596                 case 1:
 597                         args.v1.ucMisc = 0;
 598                         args.v1.ucAction = action;
 599                         if (hdmi_detected)
 600                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 601                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 602                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 603                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 604                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 605                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 606                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 607                         } else {
 608                                 if (dig->linkb)
 609                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 610                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 611                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 612                                 /*if (pScrn->rgbBits == 8) */
 613                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 614                         }
 615                         break;
 616                 case 2:
 617                 case 3:
 618                         args.v2.ucMisc = 0;
 619                         args.v2.ucAction = action;
 620                         if (crev == 3) {
 621                                 if (dig->coherent_mode)
 622                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 623                         }
 624                         if (hdmi_detected)
 625                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 626                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 627                         args.v2.ucTruncate = 0;
 628                         args.v2.ucSpatial = 0;
 629                         args.v2.ucTemporal = 0;
 630                         args.v2.ucFRC = 0;
 631                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 632                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 633                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 634                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 635                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 636                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 637                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 638                                 }
 639                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 640                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 641                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 642                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 643                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 644                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 645                                 }
 646                         } else {
 647                                 if (dig->linkb)
 648                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 649                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 650                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 651                         }
 652                         break;
 653                 default:
 654                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 655                         break;
 656                 }
 657                 break;
 658         default:
 659                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 660                 break;
 661         }
 662
 663         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 664 }
 665
 666 int
 667 atombios_get_encoder_mode(struct drm_encoder *encoder)
 668 {
 669         struct drm_device *dev = encoder->dev;
 670         struct radeon_device *rdev = dev->dev_private;
 671         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 672         struct drm_connector *connector;
 673         struct radeon_connector *radeon_connector;
 674         struct radeon_connector_atom_dig *dig_connector;
 675         struct radeon_encoder_atom_dig *dig_enc;
 676
 677         if (radeon_encoder_is_digital(encoder)) {
 678                 dig_enc = radeon_encoder->enc_priv;
 679                 if (dig_enc->active_mst_links)
 680                         return ATOM_ENCODER_MODE_DP_MST;
 681         }
 682         if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 683                 return ATOM_ENCODER_MODE_DP_MST;
 684         /* dp bridges are always DP */
 685         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 686                 return ATOM_ENCODER_MODE_DP;
 687
 688         /* DVO is always DVO */
 689         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 690             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 691                 return ATOM_ENCODER_MODE_DVO;
 692
 693         connector = radeon_get_connector_for_encoder(encoder);
 694         /* if we don't have an active device yet, just use one of
 695          * the connectors tied to the encoder.
 696          */
 697         if (!connector)
 698                 connector = radeon_get_connector_for_encoder_init(encoder);
 699         radeon_connector = to_radeon_connector(connector);
 700
 701         switch (connector->connector_type) {
 702         case DRM_MODE_CONNECTOR_DVII:
 703         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 704                 if (radeon_audio != 0) {
 705                         if (radeon_connector->use_digital &&
 706                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 707                                 return ATOM_ENCODER_MODE_HDMI;
 708                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 709                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 710                                 return ATOM_ENCODER_MODE_HDMI;
 711                         else if (radeon_connector->use_digital)
 712                                 return ATOM_ENCODER_MODE_DVI;
 713                         else
 714                                 return ATOM_ENCODER_MODE_CRT;
 715                 } else if (radeon_connector->use_digital) {
 716                         return ATOM_ENCODER_MODE_DVI;
 717                 } else {
 718                         return ATOM_ENCODER_MODE_CRT;
 719                 }
 720                 break;
 721         case DRM_MODE_CONNECTOR_DVID:
 722         case DRM_MODE_CONNECTOR_HDMIA:
 723         default:
 724                 if (radeon_audio != 0) {
 725                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 726                                 return ATOM_ENCODER_MODE_HDMI;
 727                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 728                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 729                                 return ATOM_ENCODER_MODE_HDMI;
 730                         else
 731                                 return ATOM_ENCODER_MODE_DVI;
 732                 } else {
 733                         return ATOM_ENCODER_MODE_DVI;
 734                 }
 735                 break;
 736         case DRM_MODE_CONNECTOR_LVDS:
 737                 return ATOM_ENCODER_MODE_LVDS;
 738                 break;
 739         case DRM_MODE_CONNECTOR_DisplayPort:
 740                 dig_connector = radeon_connector->con_priv;
 741                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 742                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 743                         if (radeon_audio != 0 &&
 744                             drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 745                             ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 746                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 747                         return ATOM_ENCODER_MODE_DP;
 748                 } else if (radeon_audio != 0) {
 749                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 750                                 return ATOM_ENCODER_MODE_HDMI;
 751                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 752                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 753                                 return ATOM_ENCODER_MODE_HDMI;
 754                         else
 755                                 return ATOM_ENCODER_MODE_DVI;
 756                 } else {
 757                         return ATOM_ENCODER_MODE_DVI;
 758                 }
 759                 break;
 760         case DRM_MODE_CONNECTOR_eDP:
 761                 if (radeon_audio != 0 &&
 762                     drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 763                     ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 764                         return ATOM_ENCODER_MODE_DP_AUDIO;
 765                 return ATOM_ENCODER_MODE_DP;
 766         case DRM_MODE_CONNECTOR_DVIA:
 767         case DRM_MODE_CONNECTOR_VGA:
 768                 return ATOM_ENCODER_MODE_CRT;
 769                 break;
 770         case DRM_MODE_CONNECTOR_Composite:
 771         case DRM_MODE_CONNECTOR_SVIDEO:
 772         case DRM_MODE_CONNECTOR_9PinDIN:
 773                 /* fix me */
 774                 return ATOM_ENCODER_MODE_TV;
 775                 /*return ATOM_ENCODER_MODE_CV;*/
 776                 break;
 777         }
 778 }
 779
 780 /*
 781  * DIG Encoder/Transmitter Setup
 782  *
 783  * DCE 3.0/3.1
 784  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 785  * Supports up to 3 digital outputs
 786  * - 2 DIG encoder blocks.
 787  * DIG1 can drive UNIPHY link A or link B
 788  * DIG2 can drive UNIPHY link B or LVTMA
 789  *
 790  * DCE 3.2
 791  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 792  * Supports up to 5 digital outputs
 793  * - 2 DIG encoder blocks.
 794  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 795  *
 796  * DCE 4.0/5.0/6.0
 797  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 798  * Supports up to 6 digital outputs
 799  * - 6 DIG encoder blocks.
 800  * - DIG to PHY mapping is hardcoded
 801  * DIG1 drives UNIPHY0 link A, A+B
 802  * DIG2 drives UNIPHY0 link B
 803  * DIG3 drives UNIPHY1 link A, A+B
 804  * DIG4 drives UNIPHY1 link B
 805  * DIG5 drives UNIPHY2 link A, A+B
 806  * DIG6 drives UNIPHY2 link B
 807  *
 808  * DCE 4.1
 809  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 810  * Supports up to 6 digital outputs
 811  * - 2 DIG encoder blocks.
 812  * llano
 813  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 814  * ontario
 815  * DIG1 drives UNIPHY0/1/2 link A
 816  * DIG2 drives UNIPHY0/1/2 link B
 817  *
 818  * Routing
 819  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 820  * Examples:
 821  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 822  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 823  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 824  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 825  */
 826
 827 union dig_encoder_control {
 828         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 829         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 830         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 831         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 832 };
 833
 834 void
 835 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 836 {
 837         struct drm_device *dev = encoder->dev;
 838         struct radeon_device *rdev = dev->dev_private;
 839         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 840         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 841         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 842         union dig_encoder_control args;
 843         int index = 0;
 844         uint8_t frev, crev;
 845         int dp_clock = 0;
 846         int dp_lane_count = 0;
 847         int hpd_id = RADEON_HPD_NONE;
 848
 849         if (connector) {
 850                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 851                 struct radeon_connector_atom_dig *dig_connector =
 852                         radeon_connector->con_priv;
 853
 854                 dp_clock = dig_connector->dp_clock;
 855                 dp_lane_count = dig_connector->dp_lane_count;
 856                 hpd_id = radeon_connector->hpd.hpd;
 857         }
 858
 859         /* no dig encoder assigned */
 860         if (dig->dig_encoder == -1)
 861                 return;
 862
 863         memset(&args, 0, sizeof(args));
 864
 865         if (ASIC_IS_DCE4(rdev))
 866                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 867         else {
 868                 if (dig->dig_encoder)
 869                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 870                 else
 871                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 872         }
 873
 874         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 875                 return;
 876
 877         switch (frev) {
 878         case 1:
 879                 switch (crev) {
 880                 case 1:
 881                         args.v1.ucAction = action;
 882                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 883                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 884                                 args.v3.ucPanelMode = panel_mode;
 885                         else
 886                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 887
 888                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 889                                 args.v1.ucLaneNum = dp_lane_count;
 890                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 891                                 args.v1.ucLaneNum = 8;
 892                         else
 893                                 args.v1.ucLaneNum = 4;
 894
 895                         switch (radeon_encoder->encoder_id) {
 896                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 897                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 898                                 break;
 899                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 900                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 901                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 902                                 break;
 903                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 904                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 905                                 break;
 906                         }
 907                         if (dig->linkb)
 908                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 909                         else
 910                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 911
 912                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 913                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 914
 915                         break;
 916                 case 2:
 917                 case 3:
 918                         args.v3.ucAction = action;
 919                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 920                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 921                                 args.v3.ucPanelMode = panel_mode;
 922                         else
 923                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 924
 925                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 926                                 args.v3.ucLaneNum = dp_lane_count;
 927                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 928                                 args.v3.ucLaneNum = 8;
 929                         else
 930                                 args.v3.ucLaneNum = 4;
 931
 932                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 933                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 934                         if (enc_override != -1)
 935                                 args.v3.acConfig.ucDigSel = enc_override;
 936                         else
 937                                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 938                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 939                         break;
 940                 case 4:
 941                         args.v4.ucAction = action;
 942                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 943                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 944                                 args.v4.ucPanelMode = panel_mode;
 945                         else
 946                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 947
 948                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 949                                 args.v4.ucLaneNum = dp_lane_count;
 950                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 951                                 args.v4.ucLaneNum = 8;
 952                         else
 953                                 args.v4.ucLaneNum = 4;
 954
 955                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 956                                 if (dp_clock == 540000)
 957                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 958                                 else if (dp_clock == 324000)
 959                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 960                                 else if (dp_clock == 270000)
 961                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 962                                 else
 963                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 964                         }
 965
 966                         if (enc_override != -1)
 967                                 args.v4.acConfig.ucDigSel = enc_override;
 968                         else
 969                                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 970                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 971                         if (hpd_id == RADEON_HPD_NONE)
 972                                 args.v4.ucHPD_ID = 0;
 973                         else
 974                                 args.v4.ucHPD_ID = hpd_id + 1;
 975                         break;
 976                 default:
 977                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 978                         break;
 979                 }
 980                 break;
 981         default:
 982                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 983                 break;
 984         }
 985
 986         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 987
 988 }
 989
 990 void
 991 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 992 {
 993         atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
 994 }
 995
 996 union dig_transmitter_control {
 997         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 998         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 999         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1000         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1001         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1002 };
1003
1004 void
1005 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1006 {
1007         struct drm_device *dev = encoder->dev;
1008         struct radeon_device *rdev = dev->dev_private;
1009         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1010         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1011         struct drm_connector *connector;
1012         union dig_transmitter_control args;
1013         int index = 0;
1014         uint8_t frev, crev;
1015         bool is_dp = false;
1016         int pll_id = 0;
1017         int dp_clock = 0;
1018         int dp_lane_count = 0;
1019         int connector_object_id = 0;
1020         int igp_lane_info = 0;
1021         int dig_encoder = dig->dig_encoder;
1022         int hpd_id = RADEON_HPD_NONE;
1023
1024         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1025                 connector = radeon_get_connector_for_encoder_init(encoder);
1026                 /* just needed to avoid bailing in the encoder check.  the encoder
1027                  * isn't used for init
1028                  */
1029                 dig_encoder = 0;
1030         } else
1031                 connector = radeon_get_connector_for_encoder(encoder);
1032
1033         if (connector) {
1034                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1035                 struct radeon_connector_atom_dig *dig_connector =
1036                         radeon_connector->con_priv;
1037
1038                 hpd_id = radeon_connector->hpd.hpd;
1039                 dp_clock = dig_connector->dp_clock;
1040                 dp_lane_count = dig_connector->dp_lane_count;
1041                 connector_object_id =
1042                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1043                 igp_lane_info = dig_connector->igp_lane_info;
1044         }
1045
1046         if (encoder->crtc) {
1047                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1048                 pll_id = radeon_crtc->pll_id;
1049         }
1050
1051         /* no dig encoder assigned */
1052         if (dig_encoder == -1)
1053                 return;
1054
1055         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1056                 is_dp = true;
1057
1058         memset(&args, 0, sizeof(args));
1059
1060         switch (radeon_encoder->encoder_id) {
1061         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1062                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1063                 break;
1064         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1065         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1066         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1067         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1068                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1069                 break;
1070         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1071                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1072                 break;
1073         }
1074
1075         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1076                 return;
1077
1078         switch (frev) {
1079         case 1:
1080                 switch (crev) {
1081                 case 1:
1082                         args.v1.ucAction = action;
1083                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1084                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1085                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1086                                 args.v1.asMode.ucLaneSel = lane_num;
1087                                 args.v1.asMode.ucLaneSet = lane_set;
1088                         } else {
1089                                 if (is_dp)
1090                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1091                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1092                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1093                                 else
1094                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1095                         }
1096
1097                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1098
1099                         if (dig_encoder)
1100                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1101                         else
1102                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1103
1104                         if ((rdev->flags & RADEON_IS_IGP) &&
1105                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1106                                 if (is_dp ||
1107                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1108                                         if (igp_lane_info & 0x1)
1109                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1110                                         else if (igp_lane_info & 0x2)
1111                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1112                                         else if (igp_lane_info & 0x4)
1113                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1114                                         else if (igp_lane_info & 0x8)
1115                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1116                                 } else {
1117                                         if (igp_lane_info & 0x3)
1118                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1119                                         else if (igp_lane_info & 0xc)
1120                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1121                                 }
1122                         }
1123
1124                         if (dig->linkb)
1125                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1126                         else
1127                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1128
1129                         if (is_dp)
1130                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1131                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1132                                 if (dig->coherent_mode)
1133                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1134                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1135                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1136                         }
1137                         break;
1138                 case 2:
1139                         args.v2.ucAction = action;
1140                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1141                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1142                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1143                                 args.v2.asMode.ucLaneSel = lane_num;
1144                                 args.v2.asMode.ucLaneSet = lane_set;
1145                         } else {
1146                                 if (is_dp)
1147                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1148                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1149                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1150                                 else
1151                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1152                         }
1153
1154                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1155                         if (dig->linkb)
1156                                 args.v2.acConfig.ucLinkSel = 1;
1157
1158                         switch (radeon_encoder->encoder_id) {
1159                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1160                                 args.v2.acConfig.ucTransmitterSel = 0;
1161                                 break;
1162                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1163                                 args.v2.acConfig.ucTransmitterSel = 1;
1164                                 break;
1165                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1166                                 args.v2.acConfig.ucTransmitterSel = 2;
1167                                 break;
1168                         }
1169
1170                         if (is_dp) {
1171                                 args.v2.acConfig.fCoherentMode = 1;
1172                                 args.v2.acConfig.fDPConnector = 1;
1173                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1174                                 if (dig->coherent_mode)
1175                                         args.v2.acConfig.fCoherentMode = 1;
1176                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1177                                         args.v2.acConfig.fDualLinkConnector = 1;
1178                         }
1179                         break;
1180                 case 3:
1181                         args.v3.ucAction = action;
1182                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1183                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1184                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1185                                 args.v3.asMode.ucLaneSel = lane_num;
1186                                 args.v3.asMode.ucLaneSet = lane_set;
1187                         } else {
1188                                 if (is_dp)
1189                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1190                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1191                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1192                                 else
1193                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1194                         }
1195
1196                         if (is_dp)
1197                                 args.v3.ucLaneNum = dp_lane_count;
1198                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1199                                 args.v3.ucLaneNum = 8;
1200                         else
1201                                 args.v3.ucLaneNum = 4;
1202
1203                         if (dig->linkb)
1204                                 args.v3.acConfig.ucLinkSel = 1;
1205                         if (dig_encoder & 1)
1206                                 args.v3.acConfig.ucEncoderSel = 1;
1207
1208                         /* Select the PLL for the PHY
1209                          * DP PHY should be clocked from external src if there is
1210                          * one.
1211                          */
1212                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1213                         if (is_dp && rdev->clock.dp_extclk)
1214                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1215                         else
1216                                 args.v3.acConfig.ucRefClkSource = pll_id;
1217
1218                         switch (radeon_encoder->encoder_id) {
1219                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1220                                 args.v3.acConfig.ucTransmitterSel = 0;
1221                                 break;
1222                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1223                                 args.v3.acConfig.ucTransmitterSel = 1;
1224                                 break;
1225                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1226                                 args.v3.acConfig.ucTransmitterSel = 2;
1227                                 break;
1228                         }
1229
1230                         if (is_dp)
1231                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1232                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1233                                 if (dig->coherent_mode)
1234                                         args.v3.acConfig.fCoherentMode = 1;
1235                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1236                                         args.v3.acConfig.fDualLinkConnector = 1;
1237                         }
1238                         break;
1239                 case 4:
1240                         args.v4.ucAction = action;
1241                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1242                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1243                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1244                                 args.v4.asMode.ucLaneSel = lane_num;
1245                                 args.v4.asMode.ucLaneSet = lane_set;
1246                         } else {
1247                                 if (is_dp)
1248                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1249                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1250                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1251                                 else
1252                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1253                         }
1254
1255                         if (is_dp)
1256                                 args.v4.ucLaneNum = dp_lane_count;
1257                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1258                                 args.v4.ucLaneNum = 8;
1259                         else
1260                                 args.v4.ucLaneNum = 4;
1261
1262                         if (dig->linkb)
1263                                 args.v4.acConfig.ucLinkSel = 1;
1264                         if (dig_encoder & 1)
1265                                 args.v4.acConfig.ucEncoderSel = 1;
1266
1267                         /* Select the PLL for the PHY
1268                          * DP PHY should be clocked from external src if there is
1269                          * one.
1270                          */
1271                         /* On DCE5 DCPLL usually generates the DP ref clock */
1272                         if (is_dp) {
1273                                 if (rdev->clock.dp_extclk)
1274                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1275                                 else
1276                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1277                         } else
1278                                 args.v4.acConfig.ucRefClkSource = pll_id;
1279
1280                         switch (radeon_encoder->encoder_id) {
1281                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1282                                 args.v4.acConfig.ucTransmitterSel = 0;
1283                                 break;
1284                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1285                                 args.v4.acConfig.ucTransmitterSel = 1;
1286                                 break;
1287                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1288                                 args.v4.acConfig.ucTransmitterSel = 2;
1289                                 break;
1290                         }
1291
1292                         if (is_dp)
1293                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1294                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1295                                 if (dig->coherent_mode)
1296                                         args.v4.acConfig.fCoherentMode = 1;
1297                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1298                                         args.v4.acConfig.fDualLinkConnector = 1;
1299                         }
1300                         break;
1301                 case 5:
1302                         args.v5.ucAction = action;
1303                         if (is_dp)
1304                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1305                         else
1306                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1307
1308                         switch (radeon_encoder->encoder_id) {
1309                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1310                                 if (dig->linkb)
1311                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1312                                 else
1313                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1314                                 break;
1315                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1316                                 if (dig->linkb)
1317                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1318                                 else
1319                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1320                                 break;
1321                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1322                                 if (dig->linkb)
1323                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1324                                 else
1325                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1326                                 break;
1327                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1328                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1329                                 break;
1330                         }
1331                         if (is_dp)
1332                                 args.v5.ucLaneNum = dp_lane_count;
1333                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1334                                 args.v5.ucLaneNum = 8;
1335                         else
1336                                 args.v5.ucLaneNum = 4;
1337                         args.v5.ucConnObjId = connector_object_id;
1338                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1339
1340                         if (is_dp && rdev->clock.dp_extclk)
1341                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1342                         else
1343                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1344
1345                         if (is_dp)
1346                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1347                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1348                                 if (dig->coherent_mode)
1349                                         args.v5.asConfig.ucCoherentMode = 1;
1350                         }
1351                         if (hpd_id == RADEON_HPD_NONE)
1352                                 args.v5.asConfig.ucHPDSel = 0;
1353                         else
1354                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1355                         args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1356                         args.v5.ucDPLaneSet = lane_set;
1357                         break;
1358                 default:
1359                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1360                         break;
1361                 }
1362                 break;
1363         default:
1364                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1365                 break;
1366         }
1367
1368         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1369 }
1370
1371 void
1372 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1373 {
1374         atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1375 }
1376
1377 bool
1378 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1379 {
1380         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1381         struct drm_device *dev = radeon_connector->base.dev;
1382         struct radeon_device *rdev = dev->dev_private;
1383         union dig_transmitter_control args;
1384         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1385         uint8_t frev, crev;
1386
1387         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1388                 goto done;
1389
1390         if (!ASIC_IS_DCE4(rdev))
1391                 goto done;
1392
1393         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1394             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1395                 goto done;
1396
1397         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1398                 goto done;
1399
1400         memset(&args, 0, sizeof(args));
1401
1402         args.v1.ucAction = action;
1403
1404         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1405
1406         /* wait for the panel to power up */
1407         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1408                 int i;
1409
1410                 for (i = 0; i < 300; i++) {
1411                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1412                                 return true;
1413                         mdelay(1);
1414                 }
1415                 return false;
1416         }
1417 done:
1418         return true;
1419 }
1420
1421 union external_encoder_control {
1422         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1423         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1424 };
1425
1426 static void
1427 atombios_external_encoder_setup(struct drm_encoder *encoder,
1428                                 struct drm_encoder *ext_encoder,
1429                                 int action)
1430 {
1431         struct drm_device *dev = encoder->dev;
1432         struct radeon_device *rdev = dev->dev_private;
1433         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1434         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1435         union external_encoder_control args;
1436         struct drm_connector *connector;
1437         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1438         u8 frev, crev;
1439         int dp_clock = 0;
1440         int dp_lane_count = 0;
1441         int connector_object_id = 0;
1442         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1443
1444         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1445                 connector = radeon_get_connector_for_encoder_init(encoder);
1446         else
1447                 connector = radeon_get_connector_for_encoder(encoder);
1448
1449         if (connector) {
1450                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1451                 struct radeon_connector_atom_dig *dig_connector =
1452                         radeon_connector->con_priv;
1453
1454                 dp_clock = dig_connector->dp_clock;
1455                 dp_lane_count = dig_connector->dp_lane_count;
1456                 connector_object_id =
1457                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1458         }
1459
1460         memset(&args, 0, sizeof(args));
1461
1462         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1463                 return;
1464
1465         switch (frev) {
1466         case 1:
1467                 /* no params on frev 1 */
1468                 break;
1469         case 2:
1470                 switch (crev) {
1471                 case 1:
1472                 case 2:
1473                         args.v1.sDigEncoder.ucAction = action;
1474                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1475                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1476
1477                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1478                                 if (dp_clock == 270000)
1479                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1480                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1481                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1482                                 args.v1.sDigEncoder.ucLaneNum = 8;
1483                         else
1484                                 args.v1.sDigEncoder.ucLaneNum = 4;
1485                         break;
1486                 case 3:
1487                         args.v3.sExtEncoder.ucAction = action;
1488                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1489                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1490                         else
1491                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1492                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1493
1494                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1495                                 if (dp_clock == 270000)
1496                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1497                                 else if (dp_clock == 540000)
1498                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1499                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1500                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1501                                 args.v3.sExtEncoder.ucLaneNum = 8;
1502                         else
1503                                 args.v3.sExtEncoder.ucLaneNum = 4;
1504                         switch (ext_enum) {
1505                         case GRAPH_OBJECT_ENUM_ID1:
1506                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1507                                 break;
1508                         case GRAPH_OBJECT_ENUM_ID2:
1509                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1510                                 break;
1511                         case GRAPH_OBJECT_ENUM_ID3:
1512                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1513                                 break;
1514                         }
1515                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1516                         break;
1517                 default:
1518                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1519                         return;
1520                 }
1521                 break;
1522         default:
1523                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1524                 return;
1525         }
1526         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1527 }
1528
1529 static void
1530 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1531 {
1532         struct drm_device *dev = encoder->dev;
1533         struct radeon_device *rdev = dev->dev_private;
1534         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1535         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1536         ENABLE_YUV_PS_ALLOCATION args;
1537         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1538         uint32_t temp, reg;
1539
1540         memset(&args, 0, sizeof(args));
1541
1542         if (rdev->family >= CHIP_R600)
1543                 reg = R600_BIOS_3_SCRATCH;
1544         else
1545                 reg = RADEON_BIOS_3_SCRATCH;
1546
1547         /* XXX: fix up scratch reg handling */
1548         temp = RREG32(reg);
1549         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1550                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1551                              (radeon_crtc->crtc_id << 18)));
1552         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1553                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1554         else
1555                 WREG32(reg, 0);
1556
1557         if (enable)
1558                 args.ucEnable = ATOM_ENABLE;
1559         args.ucCRTC = radeon_crtc->crtc_id;
1560
1561         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1562
1563         WREG32(reg, temp);
1564 }
1565
1566 static void
1567 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1568 {
1569         struct drm_device *dev = encoder->dev;
1570         struct radeon_device *rdev = dev->dev_private;
1571         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1572         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1573         int index = 0;
1574
1575         memset(&args, 0, sizeof(args));
1576
1577         switch (radeon_encoder->encoder_id) {
1578         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1579         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1580                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1581                 break;
1582         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1583         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1584         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1585                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1586                 break;
1587         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1588                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1589                 break;
1590         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1591                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1592                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1593                 else
1594                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1595                 break;
1596         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1597         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1598                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1599                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1600                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1601                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1602                 else
1603                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1604                 break;
1605         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1606         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1607                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1608                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1609                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1610                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1611                 else
1612                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1613                 break;
1614         default:
1615                 return;
1616         }
1617
1618         switch (mode) {
1619         case DRM_MODE_DPMS_ON:
1620                 args.ucAction = ATOM_ENABLE;
1621                 /* workaround for DVOOutputControl on some RS690 systems */
1622                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1623                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1624                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1625                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1626                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1627                 } else
1628                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1629                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1630                         if (rdev->mode_info.bl_encoder) {
1631                                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1632
1633                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1634                         } else {
1635                                 args.ucAction = ATOM_LCD_BLON;
1636                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1637                         }
1638                 }
1639                 break;
1640         case DRM_MODE_DPMS_STANDBY:
1641         case DRM_MODE_DPMS_SUSPEND:
1642         case DRM_MODE_DPMS_OFF:
1643                 args.ucAction = ATOM_DISABLE;
1644                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1645                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1646                         args.ucAction = ATOM_LCD_BLOFF;
1647                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1648                 }
1649                 break;
1650         }
1651 }
1652
1653 static void
1654 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1655 {
1656         struct drm_device *dev = encoder->dev;
1657         struct radeon_device *rdev = dev->dev_private;
1658         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1659         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1660         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1661         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1662         struct radeon_connector *radeon_connector = NULL;
1663         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1664         bool travis_quirk = false;
1665
1666         if (connector) {
1667                 radeon_connector = to_radeon_connector(connector);
1668                 radeon_dig_connector = radeon_connector->con_priv;
1669                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1670                      ENCODER_OBJECT_ID_TRAVIS) &&
1671                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1672                     !ASIC_IS_DCE5(rdev))
1673                         travis_quirk = true;
1674         }
1675
1676         switch (mode) {
1677         case DRM_MODE_DPMS_ON:
1678                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1679                         if (!connector)
1680                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1681                         else
1682                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1683
1684                         /* setup and enable the encoder */
1685                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1686                         atombios_dig_encoder_setup(encoder,
1687                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1688                                                    dig->panel_mode);
1689                         if (ext_encoder) {
1690                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1691                                         atombios_external_encoder_setup(encoder, ext_encoder,
1692                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1693                         }
1694                 } else if (ASIC_IS_DCE4(rdev)) {
1695                         /* setup and enable the encoder */
1696                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1697                 } else {
1698                         /* setup and enable the encoder and transmitter */
1699                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1700                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1701                 }
1702                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1703                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1704                                 atombios_set_edp_panel_power(connector,
1705                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1706                                 radeon_dig_connector->edp_on = true;
1707                         }
1708                 }
1709                 /* enable the transmitter */
1710                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1711                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1712                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1713                         radeon_dp_link_train(encoder, connector);
1714                         if (ASIC_IS_DCE4(rdev))
1715                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1716                 }
1717                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1718                         if (rdev->mode_info.bl_encoder)
1719                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1720                         else
1721                                 atombios_dig_transmitter_setup(encoder,
1722                                                                ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1723                 }
1724                 if (ext_encoder)
1725                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1726                 break;
1727         case DRM_MODE_DPMS_STANDBY:
1728         case DRM_MODE_DPMS_SUSPEND:
1729         case DRM_MODE_DPMS_OFF:
1730
1731                 /* don't power off encoders with active MST links */
1732                 if (dig->active_mst_links)
1733                         return;
1734
1735                 if (ASIC_IS_DCE4(rdev)) {
1736                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1737                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1738                 }
1739                 if (ext_encoder)
1740                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1741                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1742                         atombios_dig_transmitter_setup(encoder,
1743                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1744
1745                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1746                     connector && !travis_quirk)
1747                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1748                 if (ASIC_IS_DCE4(rdev)) {
1749                         /* disable the transmitter */
1750                         atombios_dig_transmitter_setup(encoder,
1751                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1752                 } else {
1753                         /* disable the encoder and transmitter */
1754                         atombios_dig_transmitter_setup(encoder,
1755                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1756                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1757                 }
1758                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1759                         if (travis_quirk)
1760                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1761                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1762                                 atombios_set_edp_panel_power(connector,
1763                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1764                                 radeon_dig_connector->edp_on = false;
1765                         }
1766                 }
1767                 break;
1768         }
1769 }
1770
1771 static void
1772 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1773 {
1774         struct drm_device *dev = encoder->dev;
1775         struct radeon_device *rdev = dev->dev_private;
1776         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1777         int encoder_mode = atombios_get_encoder_mode(encoder);
1778
1779         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1780                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1781                   radeon_encoder->active_device);
1782
1783         if ((radeon_audio != 0) &&
1784             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1785              ENCODER_MODE_IS_DP(encoder_mode)))
1786                 radeon_audio_dpms(encoder, mode);
1787
1788         switch (radeon_encoder->encoder_id) {
1789         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1790         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1791         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1792         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1793         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1794         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1795         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1796         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1797                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1798                 break;
1799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1800         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1801         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1802         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1803         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1804                 radeon_atom_encoder_dpms_dig(encoder, mode);
1805                 break;
1806         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1807                 if (ASIC_IS_DCE5(rdev)) {
1808                         switch (mode) {
1809                         case DRM_MODE_DPMS_ON:
1810                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1811                                 break;
1812                         case DRM_MODE_DPMS_STANDBY:
1813                         case DRM_MODE_DPMS_SUSPEND:
1814                         case DRM_MODE_DPMS_OFF:
1815                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1816                                 break;
1817                         }
1818                 } else if (ASIC_IS_DCE3(rdev))
1819                         radeon_atom_encoder_dpms_dig(encoder, mode);
1820                 else
1821                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1822                 break;
1823         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1824         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1825                 if (ASIC_IS_DCE5(rdev)) {
1826                         switch (mode) {
1827                         case DRM_MODE_DPMS_ON:
1828                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1829                                 break;
1830                         case DRM_MODE_DPMS_STANDBY:
1831                         case DRM_MODE_DPMS_SUSPEND:
1832                         case DRM_MODE_DPMS_OFF:
1833                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1834                                 break;
1835                         }
1836                 } else
1837                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1838                 break;
1839         default:
1840                 return;
1841         }
1842
1843         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1844
1845 }
1846
1847 union crtc_source_param {
1848         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1849         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1850 };
1851
1852 static void
1853 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1854 {
1855         struct drm_device *dev = encoder->dev;
1856         struct radeon_device *rdev = dev->dev_private;
1857         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1858         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1859         union crtc_source_param args;
1860         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1861         uint8_t frev, crev;
1862         struct radeon_encoder_atom_dig *dig;
1863
1864         memset(&args, 0, sizeof(args));
1865
1866         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1867                 return;
1868
1869         switch (frev) {
1870         case 1:
1871                 switch (crev) {
1872                 case 1:
1873                 default:
1874                         if (ASIC_IS_AVIVO(rdev))
1875                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1876                         else {
1877                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1878                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1879                                 } else {
1880                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1881                                 }
1882                         }
1883                         switch (radeon_encoder->encoder_id) {
1884                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1885                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1886                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1887                                 break;
1888                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1889                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1890                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1891                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1892                                 else
1893                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1894                                 break;
1895                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1896                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1897                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1898                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1899                                 break;
1900                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1901                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1902                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1903                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1904                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1905                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1906                                 else
1907                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1908                                 break;
1909                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1910                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1911                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1912                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1913                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1914                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1915                                 else
1916                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1917                                 break;
1918                         }
1919                         break;
1920                 case 2:
1921                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1922                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1923                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1924
1925                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1926                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1927                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1928                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1929                                 else
1930                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1931                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1932                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1933                         } else {
1934                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1935                         }
1936                         switch (radeon_encoder->encoder_id) {
1937                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1938                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1939                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1940                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1941                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1942                                 dig = radeon_encoder->enc_priv;
1943                                 switch (dig->dig_encoder) {
1944                                 case 0:
1945                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1946                                         break;
1947                                 case 1:
1948                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1949                                         break;
1950                                 case 2:
1951                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1952                                         break;
1953                                 case 3:
1954                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1955                                         break;
1956                                 case 4:
1957                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1958                                         break;
1959                                 case 5:
1960                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1961                                         break;
1962                                 case 6:
1963                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1964                                         break;
1965                                 }
1966                                 break;
1967                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1968                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1969                                 break;
1970                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1971                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1972                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1973                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1974                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1975                                 else
1976                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1977                                 break;
1978                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1979                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1980                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1981                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1982                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1983                                 else
1984                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1985                                 break;
1986                         }
1987                         break;
1988                 }
1989                 break;
1990         default:
1991                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1992                 return;
1993         }
1994
1995         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1996
1997         /* update scratch regs with new routing */
1998         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1999 }
2000
2001 void
2002 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2003 {
2004         struct drm_device *dev = encoder->dev;
2005         struct radeon_device *rdev = dev->dev_private;
2006         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2007         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2008         uint8_t frev, crev;
2009         union crtc_source_param args;
2010
2011         memset(&args, 0, sizeof(args));
2012
2013         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2014                 return;
2015
2016         if (frev != 1 && crev != 2)
2017                 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2018
2019         args.v2.ucCRTC = radeon_crtc->crtc_id;
2020         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2021
2022         switch (fe) {
2023         case 0:
2024                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2025                 break;
2026         case 1:
2027                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2028                 break;
2029         case 2:
2030                 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2031                 break;
2032         case 3:
2033                 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2034                 break;
2035         case 4:
2036                 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2037                 break;
2038         case 5:
2039                 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2040                 break;
2041         case 6:
2042                 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2043                 break;
2044         }
2045         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2046 }
2047
2048 static void
2049 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2050                               struct drm_display_mode *mode)
2051 {
2052         struct drm_device *dev = encoder->dev;
2053         struct radeon_device *rdev = dev->dev_private;
2054         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2055         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2056
2057         /* Funky macbooks */
2058         if ((dev->pdev->device == 0x71C5) &&
2059             (dev->pdev->subsystem_vendor == 0x106b) &&
2060             (dev->pdev->subsystem_device == 0x0080)) {
2061                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2062                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2063
2064                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2065                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2066
2067                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2068                 }
2069         }
2070
2071         /* set scaler clears this on some chips */
2072         if (ASIC_IS_AVIVO(rdev) &&
2073             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2074                 if (ASIC_IS_DCE8(rdev)) {
2075                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2076                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2077                                        CIK_INTERLEAVE_EN);
2078                         else
2079                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2080                 } else if (ASIC_IS_DCE4(rdev)) {
2081                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2082                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2083                                        EVERGREEN_INTERLEAVE_EN);
2084                         else
2085                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2086                 } else {
2087                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2088                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2089                                        AVIVO_D1MODE_INTERLEAVE_EN);
2090                         else
2091                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2092                 }
2093         }
2094 }
2095
2096 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2097 {
2098         if (enc_idx < 0)
2099                 return;
2100         rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2101 }
2102
2103 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2104 {
2105         struct drm_device *dev = encoder->dev;
2106         struct radeon_device *rdev = dev->dev_private;
2107         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2108         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2109         struct drm_encoder *test_encoder;
2110         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2111         uint32_t dig_enc_in_use = 0;
2112         int enc_idx = -1;
2113
2114         if (fe_idx >= 0) {
2115                 enc_idx = fe_idx;
2116                 goto assigned;
2117         }
2118         if (ASIC_IS_DCE6(rdev)) {
2119                 /* DCE6 */
2120                 switch (radeon_encoder->encoder_id) {
2121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2122                         if (dig->linkb)
2123                                 enc_idx = 1;
2124                         else
2125                                 enc_idx = 0;
2126                         break;
2127                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2128                         if (dig->linkb)
2129                                 enc_idx = 3;
2130                         else
2131                                 enc_idx = 2;
2132                         break;
2133                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2134                         if (dig->linkb)
2135                                 enc_idx = 5;
2136                         else
2137                                 enc_idx = 4;
2138                         break;
2139                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2140                         enc_idx = 6;
2141                         break;
2142                 }
2143                 goto assigned;
2144         } else if (ASIC_IS_DCE4(rdev)) {
2145                 /* DCE4/5 */
2146                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2147                         /* ontario follows DCE4 */
2148                         if (rdev->family == CHIP_PALM) {
2149                                 if (dig->linkb)
2150                                         enc_idx = 1;
2151                                 else
2152                                         enc_idx = 0;
2153                         } else
2154                                 /* llano follows DCE3.2 */
2155                                 enc_idx = radeon_crtc->crtc_id;
2156                 } else {
2157                         switch (radeon_encoder->encoder_id) {
2158                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2159                                 if (dig->linkb)
2160                                         enc_idx = 1;
2161                                 else
2162                                         enc_idx = 0;
2163                                 break;
2164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2165                                 if (dig->linkb)
2166                                         enc_idx = 3;
2167                                 else
2168                                         enc_idx = 2;
2169                                 break;
2170                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2171                                 if (dig->linkb)
2172                                         enc_idx = 5;
2173                                 else
2174                                         enc_idx = 4;
2175                                 break;
2176                         }
2177                 }
2178                 goto assigned;
2179         }
2180
2181         /* on DCE32 and encoder can driver any block so just crtc id */
2182         if (ASIC_IS_DCE32(rdev)) {
2183                 enc_idx = radeon_crtc->crtc_id;
2184                 goto assigned;
2185         }
2186
2187         /* on DCE3 - LVTMA can only be driven by DIGB */
2188         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2189                 struct radeon_encoder *radeon_test_encoder;
2190
2191                 if (encoder == test_encoder)
2192                         continue;
2193
2194                 if (!radeon_encoder_is_digital(test_encoder))
2195                         continue;
2196
2197                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2198                 dig = radeon_test_encoder->enc_priv;
2199
2200                 if (dig->dig_encoder >= 0)
2201                         dig_enc_in_use |= (1 << dig->dig_encoder);
2202         }
2203
2204         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2205                 if (dig_enc_in_use & 0x2)
2206                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2207                 return 1;
2208         }
2209         if (!(dig_enc_in_use & 1))
2210                 return 0;
2211         return 1;
2212
2213 assigned:
2214         if (enc_idx == -1) {
2215                 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2216                 return 0;
2217         }
2218         if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2219                 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2220         }
2221         rdev->mode_info.active_encoders |= (1 << enc_idx);
2222         return enc_idx;
2223 }
2224
2225 /* This only needs to be called once at startup */
2226 void
2227 radeon_atom_encoder_init(struct radeon_device *rdev)
2228 {
2229         struct drm_device *dev = rdev->ddev;
2230         struct drm_encoder *encoder;
2231
2232         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2233                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2234                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2235
2236                 switch (radeon_encoder->encoder_id) {
2237                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2238                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2239                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2240                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2241                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2242                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2243                         break;
2244                 default:
2245                         break;
2246                 }
2247
2248                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2249                         atombios_external_encoder_setup(encoder, ext_encoder,
2250                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2251         }
2252 }
2253
2254 static void
2255 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2256                              struct drm_display_mode *mode,
2257                              struct drm_display_mode *adjusted_mode)
2258 {
2259         struct drm_device *dev = encoder->dev;
2260         struct radeon_device *rdev = dev->dev_private;
2261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2262         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2263         int encoder_mode;
2264
2265         radeon_encoder->pixel_clock = adjusted_mode->clock;
2266
2267         /* need to call this here rather than in prepare() since we need some crtc info */
2268         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2269
2270         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2271                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2272                         atombios_yuv_setup(encoder, true);
2273                 else
2274                         atombios_yuv_setup(encoder, false);
2275         }
2276
2277         switch (radeon_encoder->encoder_id) {
2278         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2279         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2280         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2281         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2282                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2283                 break;
2284         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2285         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2286         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2287         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2288         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2289                 /* handled in dpms */
2290                 break;
2291         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2292         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2293         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2294                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2295                 break;
2296         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2298         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2299         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2300                 atombios_dac_setup(encoder, ATOM_ENABLE);
2301                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2302                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2303                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2304                         else
2305                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2306                 }
2307                 break;
2308         }
2309
2310         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2311
2312         encoder_mode = atombios_get_encoder_mode(encoder);
2313         if (connector && (radeon_audio != 0) &&
2314             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2315              ENCODER_MODE_IS_DP(encoder_mode)))
2316                 radeon_audio_mode_set(encoder, adjusted_mode);
2317 }
2318
2319 static bool
2320 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2321 {
2322         struct drm_device *dev = encoder->dev;
2323         struct radeon_device *rdev = dev->dev_private;
2324         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2325         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2326
2327         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2328                                        ATOM_DEVICE_CV_SUPPORT |
2329                                        ATOM_DEVICE_CRT_SUPPORT)) {
2330                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2331                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2332                 uint8_t frev, crev;
2333
2334                 memset(&args, 0, sizeof(args));
2335
2336                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2337                         return false;
2338
2339                 args.sDacload.ucMisc = 0;
2340
2341                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2342                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2343                         args.sDacload.ucDacType = ATOM_DAC_A;
2344                 else
2345                         args.sDacload.ucDacType = ATOM_DAC_B;
2346
2347                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2348                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2349                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2350                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2351                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2352                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2353                         if (crev >= 3)
2354                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2355                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2356                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2357                         if (crev >= 3)
2358                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2359                 }
2360
2361                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2362
2363                 return true;
2364         } else
2365                 return false;
2366 }
2367
2368 static enum drm_connector_status
2369 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2370 {
2371         struct drm_device *dev = encoder->dev;
2372         struct radeon_device *rdev = dev->dev_private;
2373         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2374         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2375         uint32_t bios_0_scratch;
2376
2377         if (!atombios_dac_load_detect(encoder, connector)) {
2378                 DRM_DEBUG_KMS("detect returned false \n");
2379                 return connector_status_unknown;
2380         }
2381
2382         if (rdev->family >= CHIP_R600)
2383                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2384         else
2385                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2386
2387         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2388         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2389                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2390                         return connector_status_connected;
2391         }
2392         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2393                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2394                         return connector_status_connected;
2395         }
2396         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2397                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2398                         return connector_status_connected;
2399         }
2400         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2401                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2402                         return connector_status_connected; /* CTV */
2403                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2404                         return connector_status_connected; /* STV */
2405         }
2406         return connector_status_disconnected;
2407 }
2408
2409 static enum drm_connector_status
2410 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2411 {
2412         struct drm_device *dev = encoder->dev;
2413         struct radeon_device *rdev = dev->dev_private;
2414         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2415         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2416         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2417         u32 bios_0_scratch;
2418
2419         if (!ASIC_IS_DCE4(rdev))
2420                 return connector_status_unknown;
2421
2422         if (!ext_encoder)
2423                 return connector_status_unknown;
2424
2425         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2426                 return connector_status_unknown;
2427
2428         /* load detect on the dp bridge */
2429         atombios_external_encoder_setup(encoder, ext_encoder,
2430                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2431
2432         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2433
2434         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2435         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2436                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2437                         return connector_status_connected;
2438         }
2439         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2440                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2441                         return connector_status_connected;
2442         }
2443         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2444                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2445                         return connector_status_connected;
2446         }
2447         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2448                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2449                         return connector_status_connected; /* CTV */
2450                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2451                         return connector_status_connected; /* STV */
2452         }
2453         return connector_status_disconnected;
2454 }
2455
2456 void
2457 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2458 {
2459         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2460
2461         if (ext_encoder)
2462                 /* ddc_setup on the dp bridge */
2463                 atombios_external_encoder_setup(encoder, ext_encoder,
2464                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2465
2466 }
2467
2468 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2469 {
2470         struct radeon_device *rdev = encoder->dev->dev_private;
2471         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2472         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2473
2474         if ((radeon_encoder->active_device &
2475              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2476             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2477              ENCODER_OBJECT_ID_NONE)) {
2478                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2479                 if (dig) {
2480                         if (dig->dig_encoder >= 0)
2481                                 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2482                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2483                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2484                                 if (rdev->family >= CHIP_R600)
2485                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2486                                 else
2487                                         /* RS600/690/740 have only 1 afmt block */
2488                                         dig->afmt = rdev->mode_info.afmt[0];
2489                         }
2490                 }
2491         }
2492
2493         radeon_atom_output_lock(encoder, true);
2494
2495         if (connector) {
2496                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2497
2498                 /* select the clock/data port if it uses a router */
2499                 if (radeon_connector->router.cd_valid)
2500                         radeon_router_select_cd_port(radeon_connector);
2501
2502                 /* turn eDP panel on for mode set */
2503                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2504                         atombios_set_edp_panel_power(connector,
2505                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2506         }
2507
2508         /* this is needed for the pll/ss setup to work correctly in some cases */
2509         atombios_set_encoder_crtc_source(encoder);
2510         /* set up the FMT blocks */
2511         if (ASIC_IS_DCE8(rdev))
2512                 dce8_program_fmt(encoder);
2513         else if (ASIC_IS_DCE4(rdev))
2514                 dce4_program_fmt(encoder);
2515         else if (ASIC_IS_DCE3(rdev))
2516                 dce3_program_fmt(encoder);
2517         else if (ASIC_IS_AVIVO(rdev))
2518                 avivo_program_fmt(encoder);
2519 }
2520
2521 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2522 {
2523         /* need to call this here as we need the crtc set up */
2524         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2525         radeon_atom_output_lock(encoder, false);
2526 }
2527
2528 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2529 {
2530         struct drm_device *dev = encoder->dev;
2531         struct radeon_device *rdev = dev->dev_private;
2532         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2533         struct radeon_encoder_atom_dig *dig;
2534
2535         /* check for pre-DCE3 cards with shared encoders;
2536          * can't really use the links individually, so don't disable
2537          * the encoder if it's in use by another connector
2538          */
2539         if (!ASIC_IS_DCE3(rdev)) {
2540                 struct drm_encoder *other_encoder;
2541                 struct radeon_encoder *other_radeon_encoder;
2542
2543                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2544                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2545                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2546                             drm_helper_encoder_in_use(other_encoder))
2547                                 goto disable_done;
2548                 }
2549         }
2550
2551         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2552
2553         switch (radeon_encoder->encoder_id) {
2554         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2555         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2556         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2557         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2558                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2559                 break;
2560         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2561         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2562         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2563         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2564         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2565                 /* handled in dpms */
2566                 break;
2567         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2568         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2569         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2570                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2571                 break;
2572         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2573         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2574         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2575         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2576                 atombios_dac_setup(encoder, ATOM_DISABLE);
2577                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2578                         atombios_tv_setup(encoder, ATOM_DISABLE);
2579                 break;
2580         }
2581
2582 disable_done:
2583         if (radeon_encoder_is_digital(encoder)) {
2584                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2585                         if (rdev->asic->display.hdmi_enable)
2586                                 radeon_hdmi_enable(rdev, encoder, false);
2587                 }
2588                 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2589                         dig = radeon_encoder->enc_priv;
2590                         radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2591                         dig->dig_encoder = -1;
2592                         radeon_encoder->active_device = 0;
2593                 }
2594         } else
2595                 radeon_encoder->active_device = 0;
2596 }
2597
2598 /* these are handled by the primary encoders */
2599 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2600 {
2601
2602 }
2603
2604 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2605 {
2606
2607 }
2608
2609 static void
2610 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2611                          struct drm_display_mode *mode,
2612                          struct drm_display_mode *adjusted_mode)
2613 {
2614
2615 }
2616
2617 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2618 {
2619
2620 }
2621
2622 static void
2623 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2624 {
2625
2626 }
2627
2628 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2629                                        const struct drm_display_mode *mode,
2630                                        struct drm_display_mode *adjusted_mode)
2631 {
2632         return true;
2633 }
2634
2635 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2636         .dpms = radeon_atom_ext_dpms,
2637         .mode_fixup = radeon_atom_ext_mode_fixup,
2638         .prepare = radeon_atom_ext_prepare,
2639         .mode_set = radeon_atom_ext_mode_set,
2640         .commit = radeon_atom_ext_commit,
2641         .disable = radeon_atom_ext_disable,
2642         /* no detect for TMDS/LVDS yet */
2643 };
2644
2645 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2646         .dpms = radeon_atom_encoder_dpms,
2647         .mode_fixup = radeon_atom_mode_fixup,
2648         .prepare = radeon_atom_encoder_prepare,
2649         .mode_set = radeon_atom_encoder_mode_set,
2650         .commit = radeon_atom_encoder_commit,
2651         .disable = radeon_atom_encoder_disable,
2652         .detect = radeon_atom_dig_detect,
2653 };
2654
2655 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2656         .dpms = radeon_atom_encoder_dpms,
2657         .mode_fixup = radeon_atom_mode_fixup,
2658         .prepare = radeon_atom_encoder_prepare,
2659         .mode_set = radeon_atom_encoder_mode_set,
2660         .commit = radeon_atom_encoder_commit,
2661         .detect = radeon_atom_dac_detect,
2662 };
2663
2664 void radeon_enc_destroy(struct drm_encoder *encoder)
2665 {
2666         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2667         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2668                 radeon_atom_backlight_exit(radeon_encoder);
2669         kfree(radeon_encoder->enc_priv);
2670         drm_encoder_cleanup(encoder);
2671         kfree(radeon_encoder);
2672 }
2673
2674 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2675         .destroy = radeon_enc_destroy,
2676 };
2677
2678 static struct radeon_encoder_atom_dac *
2679 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2680 {
2681         struct drm_device *dev = radeon_encoder->base.dev;
2682         struct radeon_device *rdev = dev->dev_private;
2683         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2684
2685         if (!dac)
2686                 return NULL;
2687
2688         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2689         return dac;
2690 }
2691
2692 static struct radeon_encoder_atom_dig *
2693 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2694 {
2695         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2696         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2697
2698         if (!dig)
2699                 return NULL;
2700
2701         /* coherent mode by default */
2702         dig->coherent_mode = true;
2703         dig->dig_encoder = -1;
2704
2705         if (encoder_enum == 2)
2706                 dig->linkb = true;
2707         else
2708                 dig->linkb = false;
2709
2710         return dig;
2711 }
2712
2713 void
2714 radeon_add_atom_encoder(struct drm_device *dev,
2715                         uint32_t encoder_enum,
2716                         uint32_t supported_device,
2717                         u16 caps)
2718 {
2719         struct radeon_device *rdev = dev->dev_private;
2720         struct drm_encoder *encoder;
2721         struct radeon_encoder *radeon_encoder;
2722
2723         /* see if we already added it */
2724         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2725                 radeon_encoder = to_radeon_encoder(encoder);
2726                 if (radeon_encoder->encoder_enum == encoder_enum) {
2727                         radeon_encoder->devices |= supported_device;
2728                         return;
2729                 }
2730
2731         }
2732
2733         /* add a new one */
2734         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2735         if (!radeon_encoder)
2736                 return;
2737
2738         encoder = &radeon_encoder->base;
2739         switch (rdev->num_crtc) {
2740         case 1:
2741                 encoder->possible_crtcs = 0x1;
2742                 break;
2743         case 2:
2744         default:
2745                 encoder->possible_crtcs = 0x3;
2746                 break;
2747         case 4:
2748                 encoder->possible_crtcs = 0xf;
2749                 break;
2750         case 6:
2751                 encoder->possible_crtcs = 0x3f;
2752                 break;
2753         }
2754
2755         radeon_encoder->enc_priv = NULL;
2756
2757         radeon_encoder->encoder_enum = encoder_enum;
2758         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2759         radeon_encoder->devices = supported_device;
2760         radeon_encoder->rmx_type = RMX_OFF;
2761         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2762         radeon_encoder->is_ext_encoder = false;
2763         radeon_encoder->caps = caps;
2764
2765         switch (radeon_encoder->encoder_id) {
2766         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2767         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2768         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2769         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2770                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2771                         radeon_encoder->rmx_type = RMX_FULL;
2772                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2773                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2774                 } else {
2775                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2776                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2777                 }
2778                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2779                 break;
2780         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2781                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2782                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2783                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2784                 break;
2785         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2786         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2787         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2788                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2789                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2790                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2791                 break;
2792         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2793         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2794         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2795         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2796         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2798         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2800                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2801                         radeon_encoder->rmx_type = RMX_FULL;
2802                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2803                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2804                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2805                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2806                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2807                 } else {
2808                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2809                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2810                 }
2811                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2812                 break;
2813         case ENCODER_OBJECT_ID_SI170B:
2814         case ENCODER_OBJECT_ID_CH7303:
2815         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2816         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2817         case ENCODER_OBJECT_ID_TITFP513:
2818         case ENCODER_OBJECT_ID_VT1623:
2819         case ENCODER_OBJECT_ID_HDMI_SI1930:
2820         case ENCODER_OBJECT_ID_TRAVIS:
2821         case ENCODER_OBJECT_ID_NUTMEG:
2822                 /* these are handled by the primary encoders */
2823                 radeon_encoder->is_ext_encoder = true;
2824                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2825                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2826                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2827                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2828                 else
2829                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2830                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2831                 break;
2832         }
2833 }