drivers/gpu/drm/radeon/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "cikd.h"
  27 #include "r600_dpm.h"
  28 #include "kv_dpm.h"
  29 #include <linux/seq_file.h>
  30
  31 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  32 #define KV_MINIMUM_ENGINE_CLOCK         800
  33 #define SMC_RAM_END                     0x40000
  34
  35 static void kv_init_graphics_levels(struct radeon_device *rdev);
  36 static int kv_calculate_ds_divider(struct radeon_device *rdev);
  37 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
  38 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
  39 static void kv_enable_new_levels(struct radeon_device *rdev);
  40 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
  41                                            struct radeon_ps *new_rps);
  42 static int kv_set_enabled_levels(struct radeon_device *rdev);
  43 static int kv_force_dpm_highest(struct radeon_device *rdev);
  44 static int kv_force_dpm_lowest(struct radeon_device *rdev);
  45 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
  46                                         struct radeon_ps *new_rps,
  47                                         struct radeon_ps *old_rps);
  48 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
  49                                             int min_temp, int max_temp);
  50 static int kv_init_fps_limits(struct radeon_device *rdev);
  51
  52 static void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  53 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
  54 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
  55 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
  56
  57 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
  58 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
  59 extern void cik_update_cg(struct radeon_device *rdev,
  60                           u32 block, bool enable);
  61
  62 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
  63 {
  64         {  0,       4,        1    },
  65         {  1,       4,        1    },
  66         {  2,       5,        1    },
  67         {  3,       4,        2    },
  68         {  4,       1,        1    },
  69         {  5,       5,        2    },
  70         {  6,       6,        1    },
  71         {  7,       9,        2    },
  72         { 0xffffffff }
  73 };
  74
  75 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
  76 {
  77         {  0,       4,        1    },
  78         { 0xffffffff }
  79 };
  80
  81 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
  82 {
  83         {  0,       4,        1    },
  84         { 0xffffffff }
  85 };
  86
  87 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
  88 {
  89         {  0,       4,        1    },
  90         { 0xffffffff }
  91 };
  92
  93 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
  94 {
  95         {  0,       4,        1    },
  96         { 0xffffffff }
  97 };
  98
  99 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 100 {
 101         {  0,       4,        1    },
 102         {  1,       4,        1    },
 103         {  2,       5,        1    },
 104         {  3,       4,        1    },
 105         {  4,       1,        1    },
 106         {  5,       5,        1    },
 107         {  6,       6,        1    },
 108         {  7,       9,        1    },
 109         {  8,       4,        1    },
 110         {  9,       2,        1    },
 111         {  10,      3,        1    },
 112         {  11,      6,        1    },
 113         {  12,      8,        2    },
 114         {  13,      1,        1    },
 115         {  14,      2,        1    },
 116         {  15,      3,        1    },
 117         {  16,      1,        1    },
 118         {  17,      4,        1    },
 119         {  18,      3,        1    },
 120         {  19,      1,        1    },
 121         {  20,      8,        1    },
 122         {  21,      5,        1    },
 123         {  22,      1,        1    },
 124         {  23,      1,        1    },
 125         {  24,      4,        1    },
 126         {  27,      6,        1    },
 127         {  28,      1,        1    },
 128         { 0xffffffff }
 129 };
 130
 131 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 132 {
 133         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 134 };
 135
 136 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 137 {
 138         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 139 };
 140
 141 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 142 {
 143         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 144 };
 145
 146 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 147 {
 148         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 149 };
 150
 151 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 152 {
 153         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 154 };
 155
 156 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 157 {
 158         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 159 };
 160
 161 static const struct kv_pt_config_reg didt_config_kv[] =
 162 {
 163         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 164         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 165         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 166         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 167         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 168         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 169         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 170         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 171         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 172         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 173         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 174         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 175         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 176         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 177         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 178         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 179         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 180         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 181         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 182         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 183         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 184         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 185         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 186         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 187         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 188         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 189         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 190         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 191         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 192         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 193         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 194         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 195         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 196         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 197         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 198         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 199         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 200         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 201         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 202         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 203         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 204         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 205         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 206         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 207         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 208         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 209         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 210         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 211         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 212         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 213         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 214         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 215         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 216         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 217         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 218         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 219         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 220         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 221         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 222         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 223         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 224         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 225         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 226         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 227         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 228         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 229         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 230         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 231         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 232         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 233         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 234         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 235         { 0xFFFFFFFF }
 236 };
 237
 238 static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
 239 {
 240         struct kv_ps *ps = rps->ps_priv;
 241
 242         return ps;
 243 }
 244
 245 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
 246 {
 247         struct kv_power_info *pi = rdev->pm.dpm.priv;
 248
 249         return pi;
 250 }
 251
 252 #if 0
 253 static void kv_program_local_cac_table(struct radeon_device *rdev,
 254                                        const struct kv_lcac_config_values *local_cac_table,
 255                                        const struct kv_lcac_config_reg *local_cac_reg)
 256 {
 257         u32 i, count, data;
 258         const struct kv_lcac_config_values *values = local_cac_table;
 259
 260         while (values->block_id != 0xffffffff) {
 261                 count = values->signal_id;
 262                 for (i = 0; i < count; i++) {
 263                         data = ((values->block_id << local_cac_reg->block_shift) &
 264                                 local_cac_reg->block_mask);
 265                         data |= ((i << local_cac_reg->signal_shift) &
 266                                  local_cac_reg->signal_mask);
 267                         data |= ((values->t << local_cac_reg->t_shift) &
 268                                  local_cac_reg->t_mask);
 269                         data |= ((1 << local_cac_reg->enable_shift) &
 270                                  local_cac_reg->enable_mask);
 271                         WREG32_SMC(local_cac_reg->cntl, data);
 272                 }
 273                 values++;
 274         }
 275 }
 276 #endif
 277
 278 static int kv_program_pt_config_registers(struct radeon_device *rdev,
 279                                           const struct kv_pt_config_reg *cac_config_regs)
 280 {
 281         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 282         u32 data;
 283         u32 cache = 0;
 284
 285         if (config_regs == NULL)
 286                 return -EINVAL;
 287
 288         while (config_regs->offset != 0xFFFFFFFF) {
 289                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 290                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 291                 } else {
 292                         switch (config_regs->type) {
 293                         case KV_CONFIGREG_SMC_IND:
 294                                 data = RREG32_SMC(config_regs->offset);
 295                                 break;
 296                         case KV_CONFIGREG_DIDT_IND:
 297                                 data = RREG32_DIDT(config_regs->offset);
 298                                 break;
 299                         default:
 300                                 data = RREG32(config_regs->offset << 2);
 301                                 break;
 302                         }
 303
 304                         data &= ~config_regs->mask;
 305                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 306                         data |= cache;
 307                         cache = 0;
 308
 309                         switch (config_regs->type) {
 310                         case KV_CONFIGREG_SMC_IND:
 311                                 WREG32_SMC(config_regs->offset, data);
 312                                 break;
 313                         case KV_CONFIGREG_DIDT_IND:
 314                                 WREG32_DIDT(config_regs->offset, data);
 315                                 break;
 316                         default:
 317                                 WREG32(config_regs->offset << 2, data);
 318                                 break;
 319                         }
 320                 }
 321                 config_regs++;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
 328 {
 329         struct kv_power_info *pi = kv_get_pi(rdev);
 330         u32 data;
 331
 332         if (pi->caps_sq_ramping) {
 333                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 334                 if (enable)
 335                         data |= DIDT_CTRL_EN;
 336                 else
 337                         data &= ~DIDT_CTRL_EN;
 338                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 339         }
 340
 341         if (pi->caps_db_ramping) {
 342                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 343                 if (enable)
 344                         data |= DIDT_CTRL_EN;
 345                 else
 346                         data &= ~DIDT_CTRL_EN;
 347                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 348         }
 349
 350         if (pi->caps_td_ramping) {
 351                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 352                 if (enable)
 353                         data |= DIDT_CTRL_EN;
 354                 else
 355                         data &= ~DIDT_CTRL_EN;
 356                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 357         }
 358
 359         if (pi->caps_tcp_ramping) {
 360                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 361                 if (enable)
 362                         data |= DIDT_CTRL_EN;
 363                 else
 364                         data &= ~DIDT_CTRL_EN;
 365                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 366         }
 367 }
 368
 369 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
 370 {
 371         struct kv_power_info *pi = kv_get_pi(rdev);
 372         int ret;
 373
 374         if (pi->caps_sq_ramping ||
 375             pi->caps_db_ramping ||
 376             pi->caps_td_ramping ||
 377             pi->caps_tcp_ramping) {
 378                 cik_enter_rlc_safe_mode(rdev);
 379
 380                 if (enable) {
 381                         ret = kv_program_pt_config_registers(rdev, didt_config_kv);
 382                         if (ret) {
 383                                 cik_exit_rlc_safe_mode(rdev);
 384                                 return ret;
 385                         }
 386                 }
 387
 388                 kv_do_enable_didt(rdev, enable);
 389
 390                 cik_exit_rlc_safe_mode(rdev);
 391         }
 392
 393         return 0;
 394 }
 395
 396 #if 0
 397 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
 398 {
 399         struct kv_power_info *pi = kv_get_pi(rdev);
 400
 401         if (pi->caps_cac) {
 402                 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
 403                 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
 404                 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 405
 406                 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
 407                 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
 408                 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 409
 410                 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
 411                 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
 412                 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 413
 414                 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
 415                 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
 416                 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 417
 418                 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
 419                 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
 420                 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 421
 422                 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
 423                 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
 424                 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 425         }
 426 }
 427 #endif
 428
 429 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
 430 {
 431         struct kv_power_info *pi = kv_get_pi(rdev);
 432         int ret = 0;
 433
 434         if (pi->caps_cac) {
 435                 if (enable) {
 436                         ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
 437                         if (ret)
 438                                 pi->cac_enabled = false;
 439                         else
 440                                 pi->cac_enabled = true;
 441                 } else if (pi->cac_enabled) {
 442                         kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
 443                         pi->cac_enabled = false;
 444                 }
 445         }
 446
 447         return ret;
 448 }
 449
 450 static int kv_process_firmware_header(struct radeon_device *rdev)
 451 {
 452         struct kv_power_info *pi = kv_get_pi(rdev);
 453         u32 tmp;
 454         int ret;
 455
 456         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 457                                      offsetof(SMU7_Firmware_Header, DpmTable),
 458                                      &tmp, pi->sram_end);
 459
 460         if (ret == 0)
 461                 pi->dpm_table_start = tmp;
 462
 463         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 464                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 465                                      &tmp, pi->sram_end);
 466
 467         if (ret == 0)
 468                 pi->soft_regs_start = tmp;
 469
 470         return ret;
 471 }
 472
 473 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
 474 {
 475         struct kv_power_info *pi = kv_get_pi(rdev);
 476         int ret;
 477
 478         pi->graphics_voltage_change_enable = 1;
 479
 480         ret = kv_copy_bytes_to_smc(rdev,
 481                                    pi->dpm_table_start +
 482                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 483                                    &pi->graphics_voltage_change_enable,
 484                                    sizeof(u8), pi->sram_end);
 485
 486         return ret;
 487 }
 488
 489 static int kv_set_dpm_interval(struct radeon_device *rdev)
 490 {
 491         struct kv_power_info *pi = kv_get_pi(rdev);
 492         int ret;
 493
 494         pi->graphics_interval = 1;
 495
 496         ret = kv_copy_bytes_to_smc(rdev,
 497                                    pi->dpm_table_start +
 498                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 499                                    &pi->graphics_interval,
 500                                    sizeof(u8), pi->sram_end);
 501
 502         return ret;
 503 }
 504
 505 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
 506 {
 507         struct kv_power_info *pi = kv_get_pi(rdev);
 508         int ret;
 509
 510         ret = kv_copy_bytes_to_smc(rdev,
 511                                    pi->dpm_table_start +
 512                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 513                                    &pi->graphics_boot_level,
 514                                    sizeof(u8), pi->sram_end);
 515
 516         return ret;
 517 }
 518
 519 static void kv_program_vc(struct radeon_device *rdev)
 520 {
 521         WREG32_SMC(CG_FTV_0, 0x3FFFC000);
 522 }
 523
 524 static void kv_clear_vc(struct radeon_device *rdev)
 525 {
 526         WREG32_SMC(CG_FTV_0, 0);
 527 }
 528
 529 static int kv_set_divider_value(struct radeon_device *rdev,
 530                                 u32 index, u32 sclk)
 531 {
 532         struct kv_power_info *pi = kv_get_pi(rdev);
 533         struct atom_clock_dividers dividers;
 534         int ret;
 535
 536         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 537                                              sclk, false, &dividers);
 538         if (ret)
 539                 return ret;
 540
 541         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 542         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 543
 544         return 0;
 545 }
 546
 547 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
 548                                             u16 voltage)
 549 {
 550         return 6200 - (voltage * 25);
 551 }
 552
 553 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
 554                                             u32 vid_2bit)
 555 {
 556         struct kv_power_info *pi = kv_get_pi(rdev);
 557         u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
 558                                                  &pi->sys_info.vid_mapping_table,
 559                                                  vid_2bit);
 560
 561         return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
 562 }
 563
 564
 565 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 566 {
 567         struct kv_power_info *pi = kv_get_pi(rdev);
 568
 569         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 570         pi->graphics_level[index].MinVddNb =
 571                 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
 572
 573         return 0;
 574 }
 575
 576 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
 577 {
 578         struct kv_power_info *pi = kv_get_pi(rdev);
 579
 580         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 581
 582         return 0;
 583 }
 584
 585 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
 586                                       u32 index, bool enable)
 587 {
 588         struct kv_power_info *pi = kv_get_pi(rdev);
 589
 590         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 591 }
 592
 593 static void kv_start_dpm(struct radeon_device *rdev)
 594 {
 595         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
 596
 597         tmp |= GLOBAL_PWRMGT_EN;
 598         WREG32_SMC(GENERAL_PWRMGT, tmp);
 599
 600         kv_smc_dpm_enable(rdev, true);
 601 }
 602
 603 static void kv_stop_dpm(struct radeon_device *rdev)
 604 {
 605         kv_smc_dpm_enable(rdev, false);
 606 }
 607
 608 static void kv_start_am(struct radeon_device *rdev)
 609 {
 610         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 611
 612         sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
 613         sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
 614
 615         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 616 }
 617
 618 static void kv_reset_am(struct radeon_device *rdev)
 619 {
 620         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 621
 622         sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
 623
 624         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 625 }
 626
 627 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
 628 {
 629         return kv_notify_message_to_smu(rdev, freeze ?
 630                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 631 }
 632
 633 static int kv_force_lowest_valid(struct radeon_device *rdev)
 634 {
 635         return kv_force_dpm_lowest(rdev);
 636 }
 637
 638 static int kv_unforce_levels(struct radeon_device *rdev)
 639 {
 640         return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
 641 }
 642
 643 static int kv_update_sclk_t(struct radeon_device *rdev)
 644 {
 645         struct kv_power_info *pi = kv_get_pi(rdev);
 646         u32 low_sclk_interrupt_t = 0;
 647         int ret = 0;
 648
 649         if (pi->caps_sclk_throttle_low_notification) {
 650                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 651
 652                 ret = kv_copy_bytes_to_smc(rdev,
 653                                            pi->dpm_table_start +
 654                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 655                                            (u8 *)&low_sclk_interrupt_t,
 656                                            sizeof(u32), pi->sram_end);
 657         }
 658         return ret;
 659 }
 660
 661 static int kv_program_bootup_state(struct radeon_device *rdev)
 662 {
 663         struct kv_power_info *pi = kv_get_pi(rdev);
 664         u32 i;
 665         struct radeon_clock_voltage_dependency_table *table =
 666                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 667
 668         if (table && table->count) {
 669                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
 670                         if ((table->entries[i].clk == pi->boot_pl.sclk) ||
 671                             (i == 0))
 672                                 break;
 673                 }
 674
 675                 pi->graphics_boot_level = (u8)i;
 676                 kv_dpm_power_level_enable(rdev, i, true);
 677         } else {
 678                 struct sumo_sclk_voltage_mapping_table *table =
 679                         &pi->sys_info.sclk_voltage_mapping_table;
 680
 681                 if (table->num_max_dpm_entries == 0)
 682                         return -EINVAL;
 683
 684                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
 685                         if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) ||
 686                             (i == 0))
 687                                 break;
 688                 }
 689
 690                 pi->graphics_boot_level = (u8)i;
 691                 kv_dpm_power_level_enable(rdev, i, true);
 692         }
 693         return 0;
 694 }
 695
 696 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
 697 {
 698         struct kv_power_info *pi = kv_get_pi(rdev);
 699         int ret;
 700
 701         pi->graphics_therm_throttle_enable = 1;
 702
 703         ret = kv_copy_bytes_to_smc(rdev,
 704                                    pi->dpm_table_start +
 705                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 706                                    &pi->graphics_therm_throttle_enable,
 707                                    sizeof(u8), pi->sram_end);
 708
 709         return ret;
 710 }
 711
 712 static int kv_upload_dpm_settings(struct radeon_device *rdev)
 713 {
 714         struct kv_power_info *pi = kv_get_pi(rdev);
 715         int ret;
 716
 717         ret = kv_copy_bytes_to_smc(rdev,
 718                                    pi->dpm_table_start +
 719                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 720                                    (u8 *)&pi->graphics_level,
 721                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 722                                    pi->sram_end);
 723
 724         if (ret)
 725                 return ret;
 726
 727         ret = kv_copy_bytes_to_smc(rdev,
 728                                    pi->dpm_table_start +
 729                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 730                                    &pi->graphics_dpm_level_count,
 731                                    sizeof(u8), pi->sram_end);
 732
 733         return ret;
 734 }
 735
 736 static u32 kv_get_clock_difference(u32 a, u32 b)
 737 {
 738         return (a >= b) ? a - b : b - a;
 739 }
 740
 741 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
 742 {
 743         struct kv_power_info *pi = kv_get_pi(rdev);
 744         u32 value;
 745
 746         if (pi->caps_enable_dfs_bypass) {
 747                 if (kv_get_clock_difference(clk, 40000) < 200)
 748                         value = 3;
 749                 else if (kv_get_clock_difference(clk, 30000) < 200)
 750                         value = 2;
 751                 else if (kv_get_clock_difference(clk, 20000) < 200)
 752                         value = 7;
 753                 else if (kv_get_clock_difference(clk, 15000) < 200)
 754                         value = 6;
 755                 else if (kv_get_clock_difference(clk, 10000) < 200)
 756                         value = 8;
 757                 else
 758                         value = 0;
 759         } else {
 760                 value = 0;
 761         }
 762
 763         return value;
 764 }
 765
 766 static int kv_populate_uvd_table(struct radeon_device *rdev)
 767 {
 768         struct kv_power_info *pi = kv_get_pi(rdev);
 769         struct radeon_uvd_clock_voltage_dependency_table *table =
 770                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 771         struct atom_clock_dividers dividers;
 772         int ret;
 773         u32 i;
 774
 775         if (table == NULL || table->count == 0)
 776                 return 0;
 777
 778         pi->uvd_level_count = 0;
 779         for (i = 0; i < table->count; i++) {
 780                 if (pi->high_voltage_t &&
 781                     (pi->high_voltage_t < table->entries[i].v))
 782                         break;
 783
 784                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 785                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 786                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 787
 788                 pi->uvd_level[i].VClkBypassCntl =
 789                         (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
 790                 pi->uvd_level[i].DClkBypassCntl =
 791                         (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
 792
 793                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 794                                                      table->entries[i].vclk, false, &dividers);
 795                 if (ret)
 796                         return ret;
 797                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 798
 799                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 800                                                      table->entries[i].dclk, false, &dividers);
 801                 if (ret)
 802                         return ret;
 803                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 804
 805                 pi->uvd_level_count++;
 806         }
 807
 808         ret = kv_copy_bytes_to_smc(rdev,
 809                                    pi->dpm_table_start +
 810                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 811                                    (u8 *)&pi->uvd_level_count,
 812                                    sizeof(u8), pi->sram_end);
 813         if (ret)
 814                 return ret;
 815
 816         pi->uvd_interval = 1;
 817
 818         ret = kv_copy_bytes_to_smc(rdev,
 819                                    pi->dpm_table_start +
 820                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 821                                    &pi->uvd_interval,
 822                                    sizeof(u8), pi->sram_end);
 823         if (ret)
 824                 return ret;
 825
 826         ret = kv_copy_bytes_to_smc(rdev,
 827                                    pi->dpm_table_start +
 828                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 829                                    (u8 *)&pi->uvd_level,
 830                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 831                                    pi->sram_end);
 832
 833         return ret;
 834
 835 }
 836
 837 static int kv_populate_vce_table(struct radeon_device *rdev)
 838 {
 839         struct kv_power_info *pi = kv_get_pi(rdev);
 840         int ret;
 841         u32 i;
 842         struct radeon_vce_clock_voltage_dependency_table *table =
 843                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 844         struct atom_clock_dividers dividers;
 845
 846         if (table == NULL || table->count == 0)
 847                 return 0;
 848
 849         pi->vce_level_count = 0;
 850         for (i = 0; i < table->count; i++) {
 851                 if (pi->high_voltage_t &&
 852                     pi->high_voltage_t < table->entries[i].v)
 853                         break;
 854
 855                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 856                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 857
 858                 pi->vce_level[i].ClkBypassCntl =
 859                         (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
 860
 861                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 862                                                      table->entries[i].evclk, false, &dividers);
 863                 if (ret)
 864                         return ret;
 865                 pi->vce_level[i].Divider = (u8)dividers.post_div;
 866
 867                 pi->vce_level_count++;
 868         }
 869
 870         ret = kv_copy_bytes_to_smc(rdev,
 871                                    pi->dpm_table_start +
 872                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
 873                                    (u8 *)&pi->vce_level_count,
 874                                    sizeof(u8),
 875                                    pi->sram_end);
 876         if (ret)
 877                 return ret;
 878
 879         pi->vce_interval = 1;
 880
 881         ret = kv_copy_bytes_to_smc(rdev,
 882                                    pi->dpm_table_start +
 883                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
 884                                    (u8 *)&pi->vce_interval,
 885                                    sizeof(u8),
 886                                    pi->sram_end);
 887         if (ret)
 888                 return ret;
 889
 890         ret = kv_copy_bytes_to_smc(rdev,
 891                                    pi->dpm_table_start +
 892                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
 893                                    (u8 *)&pi->vce_level,
 894                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
 895                                    pi->sram_end);
 896
 897         return ret;
 898 }
 899
 900 static int kv_populate_samu_table(struct radeon_device *rdev)
 901 {
 902         struct kv_power_info *pi = kv_get_pi(rdev);
 903         struct radeon_clock_voltage_dependency_table *table =
 904                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
 905         struct atom_clock_dividers dividers;
 906         int ret;
 907         u32 i;
 908
 909         if (table == NULL || table->count == 0)
 910                 return 0;
 911
 912         pi->samu_level_count = 0;
 913         for (i = 0; i < table->count; i++) {
 914                 if (pi->high_voltage_t &&
 915                     pi->high_voltage_t < table->entries[i].v)
 916                         break;
 917
 918                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 919                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 920
 921                 pi->samu_level[i].ClkBypassCntl =
 922                         (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
 923
 924                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 925                                                      table->entries[i].clk, false, &dividers);
 926                 if (ret)
 927                         return ret;
 928                 pi->samu_level[i].Divider = (u8)dividers.post_div;
 929
 930                 pi->samu_level_count++;
 931         }
 932
 933         ret = kv_copy_bytes_to_smc(rdev,
 934                                    pi->dpm_table_start +
 935                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
 936                                    (u8 *)&pi->samu_level_count,
 937                                    sizeof(u8),
 938                                    pi->sram_end);
 939         if (ret)
 940                 return ret;
 941
 942         pi->samu_interval = 1;
 943
 944         ret = kv_copy_bytes_to_smc(rdev,
 945                                    pi->dpm_table_start +
 946                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
 947                                    (u8 *)&pi->samu_interval,
 948                                    sizeof(u8),
 949                                    pi->sram_end);
 950         if (ret)
 951                 return ret;
 952
 953         ret = kv_copy_bytes_to_smc(rdev,
 954                                    pi->dpm_table_start +
 955                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
 956                                    (u8 *)&pi->samu_level,
 957                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
 958                                    pi->sram_end);
 959         if (ret)
 960                 return ret;
 961
 962         return ret;
 963 }
 964
 965
 966 static int kv_populate_acp_table(struct radeon_device *rdev)
 967 {
 968         struct kv_power_info *pi = kv_get_pi(rdev);
 969         struct radeon_clock_voltage_dependency_table *table =
 970                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 971         struct atom_clock_dividers dividers;
 972         int ret;
 973         u32 i;
 974
 975         if (table == NULL || table->count == 0)
 976                 return 0;
 977
 978         pi->acp_level_count = 0;
 979         for (i = 0; i < table->count; i++) {
 980                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 981                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 982
 983                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 984                                                      table->entries[i].clk, false, &dividers);
 985                 if (ret)
 986                         return ret;
 987                 pi->acp_level[i].Divider = (u8)dividers.post_div;
 988
 989                 pi->acp_level_count++;
 990         }
 991
 992         ret = kv_copy_bytes_to_smc(rdev,
 993                                    pi->dpm_table_start +
 994                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
 995                                    (u8 *)&pi->acp_level_count,
 996                                    sizeof(u8),
 997                                    pi->sram_end);
 998         if (ret)
 999                 return ret;
1000
1001         pi->acp_interval = 1;
1002
1003         ret = kv_copy_bytes_to_smc(rdev,
1004                                    pi->dpm_table_start +
1005                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1006                                    (u8 *)&pi->acp_interval,
1007                                    sizeof(u8),
1008                                    pi->sram_end);
1009         if (ret)
1010                 return ret;
1011
1012         ret = kv_copy_bytes_to_smc(rdev,
1013                                    pi->dpm_table_start +
1014                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1015                                    (u8 *)&pi->acp_level,
1016                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1017                                    pi->sram_end);
1018         if (ret)
1019                 return ret;
1020
1021         return ret;
1022 }
1023
1024 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1025 {
1026         struct kv_power_info *pi = kv_get_pi(rdev);
1027         u32 i;
1028         struct radeon_clock_voltage_dependency_table *table =
1029                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1030
1031         if (table && table->count) {
1032                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1033                         if (pi->caps_enable_dfs_bypass) {
1034                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1035                                         pi->graphics_level[i].ClkBypassCntl = 3;
1036                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1037                                         pi->graphics_level[i].ClkBypassCntl = 2;
1038                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1039                                         pi->graphics_level[i].ClkBypassCntl = 7;
1040                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1041                                         pi->graphics_level[i].ClkBypassCntl = 6;
1042                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1043                                         pi->graphics_level[i].ClkBypassCntl = 8;
1044                                 else
1045                                         pi->graphics_level[i].ClkBypassCntl = 0;
1046                         } else {
1047                                 pi->graphics_level[i].ClkBypassCntl = 0;
1048                         }
1049                 }
1050         } else {
1051                 struct sumo_sclk_voltage_mapping_table *table =
1052                         &pi->sys_info.sclk_voltage_mapping_table;
1053                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1054                         if (pi->caps_enable_dfs_bypass) {
1055                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1056                                         pi->graphics_level[i].ClkBypassCntl = 3;
1057                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1058                                         pi->graphics_level[i].ClkBypassCntl = 2;
1059                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1060                                         pi->graphics_level[i].ClkBypassCntl = 7;
1061                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1062                                         pi->graphics_level[i].ClkBypassCntl = 6;
1063                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1064                                         pi->graphics_level[i].ClkBypassCntl = 8;
1065                                 else
1066                                         pi->graphics_level[i].ClkBypassCntl = 0;
1067                         } else {
1068                                 pi->graphics_level[i].ClkBypassCntl = 0;
1069                         }
1070                 }
1071         }
1072 }
1073
1074 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1075 {
1076         return kv_notify_message_to_smu(rdev, enable ?
1077                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1078 }
1079
1080 static void kv_update_current_ps(struct radeon_device *rdev,
1081                                  struct radeon_ps *rps)
1082 {
1083         struct kv_ps *new_ps = kv_get_ps(rps);
1084         struct kv_power_info *pi = kv_get_pi(rdev);
1085
1086         pi->current_rps = *rps;
1087         pi->current_ps = *new_ps;
1088         pi->current_rps.ps_priv = &pi->current_ps;
1089 }
1090
1091 static void kv_update_requested_ps(struct radeon_device *rdev,
1092                                    struct radeon_ps *rps)
1093 {
1094         struct kv_ps *new_ps = kv_get_ps(rps);
1095         struct kv_power_info *pi = kv_get_pi(rdev);
1096
1097         pi->requested_rps = *rps;
1098         pi->requested_ps = *new_ps;
1099         pi->requested_rps.ps_priv = &pi->requested_ps;
1100 }
1101
1102 int kv_dpm_enable(struct radeon_device *rdev)
1103 {
1104         struct kv_power_info *pi = kv_get_pi(rdev);
1105         int ret;
1106
1107         ret = kv_process_firmware_header(rdev);
1108         if (ret) {
1109                 DRM_ERROR("kv_process_firmware_header failed\n");
1110                 return ret;
1111         }
1112         kv_init_fps_limits(rdev);
1113         kv_init_graphics_levels(rdev);
1114         ret = kv_program_bootup_state(rdev);
1115         if (ret) {
1116                 DRM_ERROR("kv_program_bootup_state failed\n");
1117                 return ret;
1118         }
1119         kv_calculate_dfs_bypass_settings(rdev);
1120         ret = kv_upload_dpm_settings(rdev);
1121         if (ret) {
1122                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1123                 return ret;
1124         }
1125         ret = kv_populate_uvd_table(rdev);
1126         if (ret) {
1127                 DRM_ERROR("kv_populate_uvd_table failed\n");
1128                 return ret;
1129         }
1130         ret = kv_populate_vce_table(rdev);
1131         if (ret) {
1132                 DRM_ERROR("kv_populate_vce_table failed\n");
1133                 return ret;
1134         }
1135         ret = kv_populate_samu_table(rdev);
1136         if (ret) {
1137                 DRM_ERROR("kv_populate_samu_table failed\n");
1138                 return ret;
1139         }
1140         ret = kv_populate_acp_table(rdev);
1141         if (ret) {
1142                 DRM_ERROR("kv_populate_acp_table failed\n");
1143                 return ret;
1144         }
1145         kv_program_vc(rdev);
1146 #if 0
1147         kv_initialize_hardware_cac_manager(rdev);
1148 #endif
1149         kv_start_am(rdev);
1150         if (pi->enable_auto_thermal_throttling) {
1151                 ret = kv_enable_auto_thermal_throttling(rdev);
1152                 if (ret) {
1153                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1154                         return ret;
1155                 }
1156         }
1157         ret = kv_enable_dpm_voltage_scaling(rdev);
1158         if (ret) {
1159                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1160                 return ret;
1161         }
1162         ret = kv_set_dpm_interval(rdev);
1163         if (ret) {
1164                 DRM_ERROR("kv_set_dpm_interval failed\n");
1165                 return ret;
1166         }
1167         ret = kv_set_dpm_boot_state(rdev);
1168         if (ret) {
1169                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1170                 return ret;
1171         }
1172         ret = kv_enable_ulv(rdev, true);
1173         if (ret) {
1174                 DRM_ERROR("kv_enable_ulv failed\n");
1175                 return ret;
1176         }
1177         kv_start_dpm(rdev);
1178         ret = kv_enable_didt(rdev, true);
1179         if (ret) {
1180                 DRM_ERROR("kv_enable_didt failed\n");
1181                 return ret;
1182         }
1183         ret = kv_enable_smc_cac(rdev, true);
1184         if (ret) {
1185                 DRM_ERROR("kv_enable_smc_cac failed\n");
1186                 return ret;
1187         }
1188
1189         if (rdev->irq.installed &&
1190             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1191                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1192                 if (ret) {
1193                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1194                         return ret;
1195                 }
1196                 rdev->irq.dpm_thermal = true;
1197                 radeon_irq_set(rdev);
1198         }
1199
1200         /* powerdown unused blocks for now */
1201         kv_dpm_powergate_acp(rdev, true);
1202         kv_dpm_powergate_samu(rdev, true);
1203         kv_dpm_powergate_vce(rdev, true);
1204
1205         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1206
1207         return ret;
1208 }
1209
1210 void kv_dpm_disable(struct radeon_device *rdev)
1211 {
1212         kv_enable_smc_cac(rdev, false);
1213         kv_enable_didt(rdev, false);
1214         kv_clear_vc(rdev);
1215         kv_stop_dpm(rdev);
1216         kv_enable_ulv(rdev, false);
1217         kv_reset_am(rdev);
1218
1219         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1220 }
1221
1222 #if 0
1223 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1224                                       u16 reg_offset, u32 value)
1225 {
1226         struct kv_power_info *pi = kv_get_pi(rdev);
1227
1228         return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1229                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1230 }
1231
1232 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1233                                      u16 reg_offset, u32 *value)
1234 {
1235         struct kv_power_info *pi = kv_get_pi(rdev);
1236
1237         return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1238                                       value, pi->sram_end);
1239 }
1240 #endif
1241
1242 static void kv_init_sclk_t(struct radeon_device *rdev)
1243 {
1244         struct kv_power_info *pi = kv_get_pi(rdev);
1245
1246         pi->low_sclk_interrupt_t = 0;
1247 }
1248
1249 static int kv_init_fps_limits(struct radeon_device *rdev)
1250 {
1251         struct kv_power_info *pi = kv_get_pi(rdev);
1252         int ret = 0;
1253
1254         if (pi->caps_fps) {
1255                 u16 tmp;
1256
1257                 tmp = 45;
1258                 pi->fps_high_t = cpu_to_be16(tmp);
1259                 ret = kv_copy_bytes_to_smc(rdev,
1260                                            pi->dpm_table_start +
1261                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1262                                            (u8 *)&pi->fps_high_t,
1263                                            sizeof(u16), pi->sram_end);
1264
1265                 tmp = 30;
1266                 pi->fps_low_t = cpu_to_be16(tmp);
1267
1268                 ret = kv_copy_bytes_to_smc(rdev,
1269                                            pi->dpm_table_start +
1270                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1271                                            (u8 *)&pi->fps_low_t,
1272                                            sizeof(u16), pi->sram_end);
1273
1274         }
1275         return ret;
1276 }
1277
1278 static void kv_init_powergate_state(struct radeon_device *rdev)
1279 {
1280         struct kv_power_info *pi = kv_get_pi(rdev);
1281
1282         pi->uvd_power_gated = false;
1283         pi->vce_power_gated = false;
1284         pi->samu_power_gated = false;
1285         pi->acp_power_gated = false;
1286
1287 }
1288
1289 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1290 {
1291         return kv_notify_message_to_smu(rdev, enable ?
1292                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1293 }
1294
1295 #if 0
1296 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1297 {
1298         return kv_notify_message_to_smu(rdev, enable ?
1299                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1300 }
1301 #endif
1302
1303 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1304 {
1305         return kv_notify_message_to_smu(rdev, enable ?
1306                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1307 }
1308
1309 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1310 {
1311         return kv_notify_message_to_smu(rdev, enable ?
1312                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1313 }
1314
1315 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1316 {
1317         struct kv_power_info *pi = kv_get_pi(rdev);
1318         struct radeon_uvd_clock_voltage_dependency_table *table =
1319                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1320         int ret;
1321
1322         if (!gate) {
1323                 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1324                         pi->uvd_boot_level = table->count - 1;
1325                 else
1326                         pi->uvd_boot_level = 0;
1327
1328                 ret = kv_copy_bytes_to_smc(rdev,
1329                                            pi->dpm_table_start +
1330                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1331                                            (uint8_t *)&pi->uvd_boot_level,
1332                                            sizeof(u8), pi->sram_end);
1333                 if (ret)
1334                         return ret;
1335
1336                 if (!pi->caps_uvd_dpm ||
1337                     pi->caps_stable_p_state)
1338                         kv_send_msg_to_smc_with_parameter(rdev,
1339                                                           PPSMC_MSG_UVDDPM_SetEnabledMask,
1340                                                           (1 << pi->uvd_boot_level));
1341         }
1342
1343         return kv_enable_uvd_dpm(rdev, !gate);
1344 }
1345
1346 #if 0
1347 static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1348 {
1349         u8 i;
1350         struct radeon_vce_clock_voltage_dependency_table *table =
1351                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1352
1353         for (i = 0; i < table->count; i++) {
1354                 if (table->entries[i].evclk >= 0) /* XXX */
1355                         break;
1356         }
1357
1358         return i;
1359 }
1360
1361 static int kv_update_vce_dpm(struct radeon_device *rdev,
1362                              struct radeon_ps *radeon_new_state,
1363                              struct radeon_ps *radeon_current_state)
1364 {
1365         struct kv_power_info *pi = kv_get_pi(rdev);
1366         struct radeon_vce_clock_voltage_dependency_table *table =
1367                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1368         int ret;
1369
1370         if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1371                 if (pi->caps_stable_p_state)
1372                         pi->vce_boot_level = table->count - 1;
1373                 else
1374                         pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1375
1376                 ret = kv_copy_bytes_to_smc(rdev,
1377                                            pi->dpm_table_start +
1378                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1379                                            (u8 *)&pi->vce_boot_level,
1380                                            sizeof(u8),
1381                                            pi->sram_end);
1382                 if (ret)
1383                         return ret;
1384
1385                 if (pi->caps_stable_p_state)
1386                         kv_send_msg_to_smc_with_parameter(rdev,
1387                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1388                                                           (1 << pi->vce_boot_level));
1389
1390                 kv_enable_vce_dpm(rdev, true);
1391         } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1392                 kv_enable_vce_dpm(rdev, false);
1393         }
1394
1395         return 0;
1396 }
1397 #endif
1398
1399 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1400 {
1401         struct kv_power_info *pi = kv_get_pi(rdev);
1402         struct radeon_clock_voltage_dependency_table *table =
1403                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1404         int ret;
1405
1406         if (!gate) {
1407                 if (pi->caps_stable_p_state)
1408                         pi->samu_boot_level = table->count - 1;
1409                 else
1410                         pi->samu_boot_level = 0;
1411
1412                 ret = kv_copy_bytes_to_smc(rdev,
1413                                            pi->dpm_table_start +
1414                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1415                                            (u8 *)&pi->samu_boot_level,
1416                                            sizeof(u8),
1417                                            pi->sram_end);
1418                 if (ret)
1419                         return ret;
1420
1421                 if (pi->caps_stable_p_state)
1422                         kv_send_msg_to_smc_with_parameter(rdev,
1423                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1424                                                           (1 << pi->samu_boot_level));
1425         }
1426
1427         return kv_enable_samu_dpm(rdev, !gate);
1428 }
1429
1430 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1431 {
1432         struct kv_power_info *pi = kv_get_pi(rdev);
1433         struct radeon_clock_voltage_dependency_table *table =
1434                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1435         int ret;
1436
1437         if (!gate) {
1438                 if (pi->caps_stable_p_state)
1439                         pi->acp_boot_level = table->count - 1;
1440                 else
1441                         pi->acp_boot_level = 0;
1442
1443                 ret = kv_copy_bytes_to_smc(rdev,
1444                                            pi->dpm_table_start +
1445                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1446                                            (u8 *)&pi->acp_boot_level,
1447                                            sizeof(u8),
1448                                            pi->sram_end);
1449                 if (ret)
1450                         return ret;
1451
1452                 if (pi->caps_stable_p_state)
1453                         kv_send_msg_to_smc_with_parameter(rdev,
1454                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1455                                                           (1 << pi->acp_boot_level));
1456         }
1457
1458         return kv_enable_acp_dpm(rdev, !gate);
1459 }
1460
1461 static void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1462 {
1463         struct kv_power_info *pi = kv_get_pi(rdev);
1464
1465         if (pi->uvd_power_gated == gate)
1466                 return;
1467
1468         pi->uvd_power_gated = gate;
1469
1470         if (gate) {
1471                 kv_update_uvd_dpm(rdev, true);
1472                 if (pi->caps_uvd_pg)
1473                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1474         } else {
1475                 if (pi->caps_uvd_pg)
1476                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1477                 kv_update_uvd_dpm(rdev, false);
1478         }
1479 }
1480
1481 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1482 {
1483         struct kv_power_info *pi = kv_get_pi(rdev);
1484
1485         if (pi->vce_power_gated == gate)
1486                 return;
1487
1488         pi->vce_power_gated = gate;
1489
1490         if (gate) {
1491                 if (pi->caps_vce_pg)
1492                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1493         } else {
1494                 if (pi->caps_vce_pg)
1495                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1496         }
1497 }
1498
1499 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1500 {
1501         struct kv_power_info *pi = kv_get_pi(rdev);
1502
1503         if (pi->samu_power_gated == gate)
1504                 return;
1505
1506         pi->samu_power_gated = gate;
1507
1508         if (gate) {
1509                 kv_update_samu_dpm(rdev, true);
1510                 if (pi->caps_samu_pg)
1511                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1512         } else {
1513                 if (pi->caps_samu_pg)
1514                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1515                 kv_update_samu_dpm(rdev, false);
1516         }
1517 }
1518
1519 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1520 {
1521         struct kv_power_info *pi = kv_get_pi(rdev);
1522
1523         if (pi->acp_power_gated == gate)
1524                 return;
1525
1526         if (rdev->family == CHIP_KABINI)
1527                 return;
1528
1529         pi->acp_power_gated = gate;
1530
1531         if (gate) {
1532                 kv_update_acp_dpm(rdev, true);
1533                 if (pi->caps_acp_pg)
1534                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1535         } else {
1536                 if (pi->caps_acp_pg)
1537                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1538                 kv_update_acp_dpm(rdev, false);
1539         }
1540 }
1541
1542 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1543                                      struct radeon_ps *new_rps)
1544 {
1545         struct kv_ps *new_ps = kv_get_ps(new_rps);
1546         struct kv_power_info *pi = kv_get_pi(rdev);
1547         u32 i;
1548         struct radeon_clock_voltage_dependency_table *table =
1549                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1550
1551         if (table && table->count) {
1552                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1553                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1554                             (i == (pi->graphics_dpm_level_count - 1))) {
1555                                 pi->lowest_valid = i;
1556                                 break;
1557                         }
1558                 }
1559
1560                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1561                         if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) ||
1562                             (i == 0)) {
1563                                 pi->highest_valid = i;
1564                                 break;
1565                         }
1566                 }
1567
1568                 if (pi->lowest_valid > pi->highest_valid) {
1569                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1570                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1571                                 pi->highest_valid = pi->lowest_valid;
1572                         else
1573                                 pi->lowest_valid =  pi->highest_valid;
1574                 }
1575         } else {
1576                 struct sumo_sclk_voltage_mapping_table *table =
1577                         &pi->sys_info.sclk_voltage_mapping_table;
1578
1579                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1580                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1581                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1582                                 pi->lowest_valid = i;
1583                                 break;
1584                         }
1585                 }
1586
1587                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1588                         if (table->entries[i].sclk_frequency <=
1589                             new_ps->levels[new_ps->num_levels - 1].sclk ||
1590                             i == 0) {
1591                                 pi->highest_valid = i;
1592                                 break;
1593                         }
1594                 }
1595
1596                 if (pi->lowest_valid > pi->highest_valid) {
1597                         if ((new_ps->levels[0].sclk -
1598                              table->entries[pi->highest_valid].sclk_frequency) >
1599                             (table->entries[pi->lowest_valid].sclk_frequency -
1600                              new_ps->levels[new_ps->num_levels -1].sclk))
1601                                 pi->highest_valid = pi->lowest_valid;
1602                         else
1603                                 pi->lowest_valid =  pi->highest_valid;
1604                 }
1605         }
1606 }
1607
1608 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1609                                          struct radeon_ps *new_rps)
1610 {
1611         struct kv_ps *new_ps = kv_get_ps(new_rps);
1612         struct kv_power_info *pi = kv_get_pi(rdev);
1613         int ret = 0;
1614         u8 clk_bypass_cntl;
1615
1616         if (pi->caps_enable_dfs_bypass) {
1617                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1618                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1619                 ret = kv_copy_bytes_to_smc(rdev,
1620                                            (pi->dpm_table_start +
1621                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1622                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1623                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1624                                            &clk_bypass_cntl,
1625                                            sizeof(u8), pi->sram_end);
1626         }
1627
1628         return ret;
1629 }
1630
1631 static int kv_enable_nb_dpm(struct radeon_device *rdev)
1632 {
1633         struct kv_power_info *pi = kv_get_pi(rdev);
1634         int ret = 0;
1635
1636         if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1637                 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1638                 if (ret == 0)
1639                         pi->nb_dpm_enabled = true;
1640         }
1641
1642         return ret;
1643 }
1644
1645 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1646                                    enum radeon_dpm_forced_level level)
1647 {
1648         int ret;
1649
1650         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1651                 ret = kv_force_dpm_highest(rdev);
1652                 if (ret)
1653                         return ret;
1654         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1655                 ret = kv_force_dpm_lowest(rdev);
1656                 if (ret)
1657                         return ret;
1658         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1659                 ret = kv_unforce_levels(rdev);
1660                 if (ret)
1661                         return ret;
1662         }
1663
1664         rdev->pm.dpm.forced_level = level;
1665
1666         return 0;
1667 }
1668
1669 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1670 {
1671         struct kv_power_info *pi = kv_get_pi(rdev);
1672         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1673         struct radeon_ps *new_ps = &requested_ps;
1674
1675         kv_update_requested_ps(rdev, new_ps);
1676
1677         kv_apply_state_adjust_rules(rdev,
1678                                     &pi->requested_rps,
1679                                     &pi->current_rps);
1680
1681         return 0;
1682 }
1683
1684 int kv_dpm_set_power_state(struct radeon_device *rdev)
1685 {
1686         struct kv_power_info *pi = kv_get_pi(rdev);
1687         struct radeon_ps *new_ps = &pi->requested_rps;
1688         /*struct radeon_ps *old_ps = &pi->current_rps;*/
1689         int ret;
1690
1691         if (rdev->family == CHIP_KABINI) {
1692                 if (pi->enable_dpm) {
1693                         kv_set_valid_clock_range(rdev, new_ps);
1694                         kv_update_dfs_bypass_settings(rdev, new_ps);
1695                         ret = kv_calculate_ds_divider(rdev);
1696                         if (ret) {
1697                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1698                                 return ret;
1699                         }
1700                         kv_calculate_nbps_level_settings(rdev);
1701                         kv_calculate_dpm_settings(rdev);
1702                         kv_force_lowest_valid(rdev);
1703                         kv_enable_new_levels(rdev);
1704                         kv_upload_dpm_settings(rdev);
1705                         kv_program_nbps_index_settings(rdev, new_ps);
1706                         kv_unforce_levels(rdev);
1707                         kv_set_enabled_levels(rdev);
1708                         kv_force_lowest_valid(rdev);
1709                         kv_unforce_levels(rdev);
1710 #if 0
1711                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1712                         if (ret) {
1713                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1714                                 return ret;
1715                         }
1716 #endif
1717                         kv_update_uvd_dpm(rdev, false);
1718                         kv_update_sclk_t(rdev);
1719                 }
1720         } else {
1721                 if (pi->enable_dpm) {
1722                         kv_set_valid_clock_range(rdev, new_ps);
1723                         kv_update_dfs_bypass_settings(rdev, new_ps);
1724                         ret = kv_calculate_ds_divider(rdev);
1725                         if (ret) {
1726                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1727                                 return ret;
1728                         }
1729                         kv_calculate_nbps_level_settings(rdev);
1730                         kv_calculate_dpm_settings(rdev);
1731                         kv_freeze_sclk_dpm(rdev, true);
1732                         kv_upload_dpm_settings(rdev);
1733                         kv_program_nbps_index_settings(rdev, new_ps);
1734                         kv_freeze_sclk_dpm(rdev, false);
1735                         kv_set_enabled_levels(rdev);
1736 #if 0
1737                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1738                         if (ret) {
1739                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1740                                 return ret;
1741                         }
1742 #endif
1743                         kv_update_uvd_dpm(rdev, false);
1744                         kv_update_sclk_t(rdev);
1745                         kv_enable_nb_dpm(rdev);
1746                 }
1747         }
1748         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1749         return 0;
1750 }
1751
1752 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1753 {
1754         struct kv_power_info *pi = kv_get_pi(rdev);
1755         struct radeon_ps *new_ps = &pi->requested_rps;
1756
1757         kv_update_current_ps(rdev, new_ps);
1758 }
1759
1760 void kv_dpm_setup_asic(struct radeon_device *rdev)
1761 {
1762         sumo_take_smu_control(rdev, true);
1763         kv_init_powergate_state(rdev);
1764         kv_init_sclk_t(rdev);
1765 }
1766
1767 void kv_dpm_reset_asic(struct radeon_device *rdev)
1768 {
1769         kv_force_lowest_valid(rdev);
1770         kv_init_graphics_levels(rdev);
1771         kv_program_bootup_state(rdev);
1772         kv_upload_dpm_settings(rdev);
1773         kv_force_lowest_valid(rdev);
1774         kv_unforce_levels(rdev);
1775 }
1776
1777 //XXX use sumo_dpm_display_configuration_changed
1778
1779 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1780                                                 struct radeon_clock_and_voltage_limits *table)
1781 {
1782         struct kv_power_info *pi = kv_get_pi(rdev);
1783
1784         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1785                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1786                 table->sclk =
1787                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1788                 table->vddc =
1789                         kv_convert_2bit_index_to_voltage(rdev,
1790                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1791         }
1792
1793         table->mclk = pi->sys_info.nbp_memory_clock[0];
1794 }
1795
1796 static void kv_patch_voltage_values(struct radeon_device *rdev)
1797 {
1798         int i;
1799         struct radeon_uvd_clock_voltage_dependency_table *table =
1800                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1801
1802         if (table->count) {
1803                 for (i = 0; i < table->count; i++)
1804                         table->entries[i].v =
1805                                 kv_convert_8bit_index_to_voltage(rdev,
1806                                                                  table->entries[i].v);
1807         }
1808
1809 }
1810
1811 static void kv_construct_boot_state(struct radeon_device *rdev)
1812 {
1813         struct kv_power_info *pi = kv_get_pi(rdev);
1814
1815         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1816         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1817         pi->boot_pl.ds_divider_index = 0;
1818         pi->boot_pl.ss_divider_index = 0;
1819         pi->boot_pl.allow_gnb_slow = 1;
1820         pi->boot_pl.force_nbp_state = 0;
1821         pi->boot_pl.display_wm = 0;
1822         pi->boot_pl.vce_wm = 0;
1823 }
1824
1825 static int kv_force_dpm_highest(struct radeon_device *rdev)
1826 {
1827         int ret;
1828         u32 enable_mask, i;
1829
1830         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1831         if (ret)
1832                 return ret;
1833
1834         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {
1835                 if (enable_mask & (1 << i))
1836                         break;
1837         }
1838
1839         return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1840 }
1841
1842 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1843 {
1844         int ret;
1845         u32 enable_mask, i;
1846
1847         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1848         if (ret)
1849                 return ret;
1850
1851         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1852                 if (enable_mask & (1 << i))
1853                         break;
1854         }
1855
1856         return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1857 }
1858
1859 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1860                                              u32 sclk, u32 min_sclk_in_sr)
1861 {
1862         struct kv_power_info *pi = kv_get_pi(rdev);
1863         u32 i;
1864         u32 temp;
1865         u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1866                 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1867
1868         if (sclk < min)
1869                 return 0;
1870
1871         if (!pi->caps_sclk_ds)
1872                 return 0;
1873
1874         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {
1875                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1876                 if ((temp >= min) || (i == 0))
1877                         break;
1878         }
1879
1880         return (u8)i;
1881 }
1882
1883 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
1884 {
1885         struct kv_power_info *pi = kv_get_pi(rdev);
1886         struct radeon_clock_voltage_dependency_table *table =
1887                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1888         int i;
1889
1890         if (table && table->count) {
1891                 for (i = table->count - 1; i >= 0; i--) {
1892                         if (pi->high_voltage_t &&
1893                             (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
1894                              pi->high_voltage_t)) {
1895                                 *limit = i;
1896                                 return 0;
1897                         }
1898                 }
1899         } else {
1900                 struct sumo_sclk_voltage_mapping_table *table =
1901                         &pi->sys_info.sclk_voltage_mapping_table;
1902
1903                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
1904                         if (pi->high_voltage_t &&
1905                             (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
1906                              pi->high_voltage_t)) {
1907                                 *limit = i;
1908                                 return 0;
1909                         }
1910                 }
1911         }
1912
1913         *limit = 0;
1914         return 0;
1915 }
1916
1917 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
1918                                         struct radeon_ps *new_rps,
1919                                         struct radeon_ps *old_rps)
1920 {
1921         struct kv_ps *ps = kv_get_ps(new_rps);
1922         struct kv_power_info *pi = kv_get_pi(rdev);
1923         u32 min_sclk = 10000; /* ??? */
1924         u32 sclk, mclk = 0;
1925         int i, limit;
1926         bool force_high;
1927         struct radeon_clock_voltage_dependency_table *table =
1928                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1929         u32 stable_p_state_sclk = 0;
1930         struct radeon_clock_and_voltage_limits *max_limits =
1931                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1932
1933         mclk = max_limits->mclk;
1934         sclk = min_sclk;
1935
1936         if (pi->caps_stable_p_state) {
1937                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
1938
1939                 for (i = table->count - 1; i >= 0; i++) {
1940                         if (stable_p_state_sclk >= table->entries[i].clk) {
1941                                 stable_p_state_sclk = table->entries[i].clk;
1942                                 break;
1943                         }
1944                 }
1945
1946                 if (i > 0)
1947                         stable_p_state_sclk = table->entries[0].clk;
1948
1949                 sclk = stable_p_state_sclk;
1950         }
1951
1952         ps->need_dfs_bypass = true;
1953
1954         for (i = 0; i < ps->num_levels; i++) {
1955                 if (ps->levels[i].sclk < sclk)
1956                         ps->levels[i].sclk = sclk;
1957         }
1958
1959         if (table && table->count) {
1960                 for (i = 0; i < ps->num_levels; i++) {
1961                         if (pi->high_voltage_t &&
1962                             (pi->high_voltage_t <
1963                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
1964                                 kv_get_high_voltage_limit(rdev, &limit);
1965                                 ps->levels[i].sclk = table->entries[limit].clk;
1966                         }
1967                 }
1968         } else {
1969                 struct sumo_sclk_voltage_mapping_table *table =
1970                         &pi->sys_info.sclk_voltage_mapping_table;
1971
1972                 for (i = 0; i < ps->num_levels; i++) {
1973                         if (pi->high_voltage_t &&
1974                             (pi->high_voltage_t <
1975                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
1976                                 kv_get_high_voltage_limit(rdev, &limit);
1977                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
1978                         }
1979                 }
1980         }
1981
1982         if (pi->caps_stable_p_state) {
1983                 for (i = 0; i < ps->num_levels; i++) {
1984                         ps->levels[i].sclk = stable_p_state_sclk;
1985                 }
1986         }
1987
1988         pi->video_start = new_rps->dclk || new_rps->vclk;
1989
1990         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1991             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1992                 pi->battery_state = true;
1993         else
1994                 pi->battery_state = false;
1995
1996         if (rdev->family == CHIP_KABINI) {
1997                 ps->dpm0_pg_nb_ps_lo = 0x1;
1998                 ps->dpm0_pg_nb_ps_hi = 0x0;
1999                 ps->dpmx_nb_ps_lo = 0x1;
2000                 ps->dpmx_nb_ps_hi = 0x0;
2001         } else {
2002                 ps->dpm0_pg_nb_ps_lo = 0x1;
2003                 ps->dpm0_pg_nb_ps_hi = 0x0;
2004                 ps->dpmx_nb_ps_lo = 0x2;
2005                 ps->dpmx_nb_ps_hi = 0x1;
2006
2007                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2008                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2009                                 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2010                                 pi->disable_nb_ps3_in_battery;
2011                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2012                         ps->dpm0_pg_nb_ps_hi = 0x2;
2013                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2014                         ps->dpmx_nb_ps_hi = 0x2;
2015                 }
2016         }
2017 }
2018
2019 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2020                                                     u32 index, bool enable)
2021 {
2022         struct kv_power_info *pi = kv_get_pi(rdev);
2023
2024         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2025 }
2026
2027 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2028 {
2029         struct kv_power_info *pi = kv_get_pi(rdev);
2030         u32 sclk_in_sr = 10000; /* ??? */
2031         u32 i;
2032
2033         if (pi->lowest_valid > pi->highest_valid)
2034                 return -EINVAL;
2035
2036         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2037                 pi->graphics_level[i].DeepSleepDivId =
2038                         kv_get_sleep_divider_id_from_clock(rdev,
2039                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2040                                                            sclk_in_sr);
2041         }
2042         return 0;
2043 }
2044
2045 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2046 {
2047         struct kv_power_info *pi = kv_get_pi(rdev);
2048         u32 i;
2049         bool force_high;
2050         struct radeon_clock_and_voltage_limits *max_limits =
2051                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2052         u32 mclk = max_limits->mclk;
2053
2054         if (pi->lowest_valid > pi->highest_valid)
2055                 return -EINVAL;
2056
2057         if (rdev->family == CHIP_KABINI) {
2058                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2059                         pi->graphics_level[i].GnbSlow = 1;
2060                         pi->graphics_level[i].ForceNbPs1 = 0;
2061                         pi->graphics_level[i].UpH = 0;
2062                 }
2063
2064                 if (!pi->sys_info.nb_dpm_enable)
2065                         return 0;
2066
2067                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2068                               (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2069
2070                 if (force_high) {
2071                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2072                                 pi->graphics_level[i].GnbSlow = 0;
2073                 } else {
2074                         if (pi->battery_state)
2075                                 pi->graphics_level[0].ForceNbPs1 = 1;
2076
2077                         pi->graphics_level[1].GnbSlow = 0;
2078                         pi->graphics_level[2].GnbSlow = 0;
2079                         pi->graphics_level[3].GnbSlow = 0;
2080                         pi->graphics_level[4].GnbSlow = 0;
2081                 }
2082         } else {
2083                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2084                         pi->graphics_level[i].GnbSlow = 1;
2085                         pi->graphics_level[i].ForceNbPs1 = 0;
2086                         pi->graphics_level[i].UpH = 0;
2087                 }
2088
2089                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2090                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2091                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2092                         if (pi->lowest_valid != pi->highest_valid)
2093                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2094                 }
2095         }
2096         return 0;
2097 }
2098
2099 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2100 {
2101         struct kv_power_info *pi = kv_get_pi(rdev);
2102         u32 i;
2103
2104         if (pi->lowest_valid > pi->highest_valid)
2105                 return -EINVAL;
2106
2107         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2108                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2109
2110         return 0;
2111 }
2112
2113 static void kv_init_graphics_levels(struct radeon_device *rdev)
2114 {
2115         struct kv_power_info *pi = kv_get_pi(rdev);
2116         u32 i;
2117         struct radeon_clock_voltage_dependency_table *table =
2118                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2119
2120         if (table && table->count) {
2121                 u32 vid_2bit;
2122
2123                 pi->graphics_dpm_level_count = 0;
2124                 for (i = 0; i < table->count; i++) {
2125                         if (pi->high_voltage_t &&
2126                             (pi->high_voltage_t <
2127                              kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2128                                 break;
2129
2130                         kv_set_divider_value(rdev, i, table->entries[i].clk);
2131                         vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2132                                                              &pi->sys_info.vid_mapping_table,
2133                                                              table->entries[i].v);
2134                         kv_set_vid(rdev, i, vid_2bit);
2135                         kv_set_at(rdev, i, pi->at[i]);
2136                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2137                         pi->graphics_dpm_level_count++;
2138                 }
2139         } else {
2140                 struct sumo_sclk_voltage_mapping_table *table =
2141                         &pi->sys_info.sclk_voltage_mapping_table;
2142
2143                 pi->graphics_dpm_level_count = 0;
2144                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2145                         if (pi->high_voltage_t &&
2146                             pi->high_voltage_t <
2147                             kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2148                                 break;
2149
2150                         kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2151                         kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2152                         kv_set_at(rdev, i, pi->at[i]);
2153                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2154                         pi->graphics_dpm_level_count++;
2155                 }
2156         }
2157
2158         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2159                 kv_dpm_power_level_enable(rdev, i, false);
2160 }
2161
2162 static void kv_enable_new_levels(struct radeon_device *rdev)
2163 {
2164         struct kv_power_info *pi = kv_get_pi(rdev);
2165         u32 i;
2166
2167         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2168                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2169                         kv_dpm_power_level_enable(rdev, i, true);
2170         }
2171 }
2172
2173 static int kv_set_enabled_levels(struct radeon_device *rdev)
2174 {
2175         struct kv_power_info *pi = kv_get_pi(rdev);
2176         u32 i, new_mask = 0;
2177
2178         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2179                 new_mask |= (1 << i);
2180
2181         return kv_send_msg_to_smc_with_parameter(rdev,
2182                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2183                                                  new_mask);
2184 }
2185
2186 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2187                                            struct radeon_ps *new_rps)
2188 {
2189         struct kv_ps *new_ps = kv_get_ps(new_rps);
2190         struct kv_power_info *pi = kv_get_pi(rdev);
2191         u32 nbdpmconfig1;
2192
2193         if (rdev->family == CHIP_KABINI)
2194                 return;
2195
2196         if (pi->sys_info.nb_dpm_enable) {
2197                 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2198                 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2199                                   DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2200                 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2201                                  Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2202                                  DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2203                                  DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2204                 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2205         }
2206 }
2207
2208 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2209                                             int min_temp, int max_temp)
2210 {
2211         int low_temp = 0 * 1000;
2212         int high_temp = 255 * 1000;
2213         u32 tmp;
2214
2215         if (low_temp < min_temp)
2216                 low_temp = min_temp;
2217         if (high_temp > max_temp)
2218                 high_temp = max_temp;
2219         if (high_temp < low_temp) {
2220                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2221                 return -EINVAL;
2222         }
2223
2224         tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2225         tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2226         tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2227                 DIG_THERM_INTL(49 + (low_temp / 1000)));
2228         WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2229
2230         rdev->pm.dpm.thermal.min_temp = low_temp;
2231         rdev->pm.dpm.thermal.max_temp = high_temp;
2232
2233         return 0;
2234 }
2235
2236 union igp_info {
2237         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2238         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2239         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2240         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2241         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2242         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2243 };
2244
2245 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2246 {
2247         struct kv_power_info *pi = kv_get_pi(rdev);
2248         struct radeon_mode_info *mode_info = &rdev->mode_info;
2249         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2250         union igp_info *igp_info;
2251         u8 frev, crev;
2252         u16 data_offset;
2253         int i;
2254
2255         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2256                                    &frev, &crev, &data_offset)) {
2257                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2258                                               data_offset);
2259
2260                 if (crev != 8) {
2261                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2262                         return -EINVAL;
2263                 }
2264                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2265                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2266                 pi->sys_info.bootup_nb_voltage_index =
2267                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2268                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2269                         pi->sys_info.htc_tmp_lmt = 203;
2270                 else
2271                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2272                 if (igp_info->info_8.ucHtcHystLmt == 0)
2273                         pi->sys_info.htc_hyst_lmt = 5;
2274                 else
2275                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2276                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2277                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2278                 }
2279
2280                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2281                         pi->sys_info.nb_dpm_enable = true;
2282                 else
2283                         pi->sys_info.nb_dpm_enable = false;
2284
2285                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2286                         pi->sys_info.nbp_memory_clock[i] =
2287                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2288                         pi->sys_info.nbp_n_clock[i] =
2289                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2290                 }
2291                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2292                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2293                         pi->caps_enable_dfs_bypass = true;
2294
2295                 sumo_construct_sclk_voltage_mapping_table(rdev,
2296                                                           &pi->sys_info.sclk_voltage_mapping_table,
2297                                                           igp_info->info_8.sAvail_SCLK);
2298
2299                 sumo_construct_vid_mapping_table(rdev,
2300                                                  &pi->sys_info.vid_mapping_table,
2301                                                  igp_info->info_8.sAvail_SCLK);
2302
2303                 kv_construct_max_power_limits_table(rdev,
2304                                                     &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2305         }
2306         return 0;
2307 }
2308
2309 union power_info {
2310         struct _ATOM_POWERPLAY_INFO info;
2311         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2312         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2313         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2314         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2315         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2316 };
2317
2318 union pplib_clock_info {
2319         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2320         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2321         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2322         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2323 };
2324
2325 union pplib_power_state {
2326         struct _ATOM_PPLIB_STATE v1;
2327         struct _ATOM_PPLIB_STATE_V2 v2;
2328 };
2329
2330 static void kv_patch_boot_state(struct radeon_device *rdev,
2331                                 struct kv_ps *ps)
2332 {
2333         struct kv_power_info *pi = kv_get_pi(rdev);
2334
2335         ps->num_levels = 1;
2336         ps->levels[0] = pi->boot_pl;
2337 }
2338
2339 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2340                                           struct radeon_ps *rps,
2341                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2342                                           u8 table_rev)
2343 {
2344         struct kv_ps *ps = kv_get_ps(rps);
2345
2346         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2347         rps->class = le16_to_cpu(non_clock_info->usClassification);
2348         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2349
2350         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2351                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2352                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2353         } else {
2354                 rps->vclk = 0;
2355                 rps->dclk = 0;
2356         }
2357
2358         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2359                 rdev->pm.dpm.boot_ps = rps;
2360                 kv_patch_boot_state(rdev, ps);
2361         }
2362         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2363                 rdev->pm.dpm.uvd_ps = rps;
2364 }
2365
2366 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2367                                       struct radeon_ps *rps, int index,
2368                                         union pplib_clock_info *clock_info)
2369 {
2370         struct kv_power_info *pi = kv_get_pi(rdev);
2371         struct kv_ps *ps = kv_get_ps(rps);
2372         struct kv_pl *pl = &ps->levels[index];
2373         u32 sclk;
2374
2375         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2376         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2377         pl->sclk = sclk;
2378         pl->vddc_index = clock_info->sumo.vddcIndex;
2379
2380         ps->num_levels = index + 1;
2381
2382         if (pi->caps_sclk_ds) {
2383                 pl->ds_divider_index = 5;
2384                 pl->ss_divider_index = 5;
2385         }
2386 }
2387
2388 static int kv_parse_power_table(struct radeon_device *rdev)
2389 {
2390         struct radeon_mode_info *mode_info = &rdev->mode_info;
2391         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2392         union pplib_power_state *power_state;
2393         int i, j, k, non_clock_array_index, clock_array_index;
2394         union pplib_clock_info *clock_info;
2395         struct _StateArray *state_array;
2396         struct _ClockInfoArray *clock_info_array;
2397         struct _NonClockInfoArray *non_clock_info_array;
2398         union power_info *power_info;
2399         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2400         u16 data_offset;
2401         u8 frev, crev;
2402         u8 *power_state_offset;
2403         struct kv_ps *ps;
2404
2405         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2406                                    &frev, &crev, &data_offset))
2407                 return -EINVAL;
2408         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2409
2410         state_array = (struct _StateArray *)
2411                 (mode_info->atom_context->bios + data_offset +
2412                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2413         clock_info_array = (struct _ClockInfoArray *)
2414                 (mode_info->atom_context->bios + data_offset +
2415                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2416         non_clock_info_array = (struct _NonClockInfoArray *)
2417                 (mode_info->atom_context->bios + data_offset +
2418                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2419
2420         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2421                                   state_array->ucNumEntries, GFP_KERNEL);
2422         if (!rdev->pm.dpm.ps)
2423                 return -ENOMEM;
2424         power_state_offset = (u8 *)state_array->states;
2425         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2426         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2427         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2428         for (i = 0; i < state_array->ucNumEntries; i++) {
2429                 power_state = (union pplib_power_state *)power_state_offset;
2430                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2431                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2432                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2433                 if (!rdev->pm.power_state[i].clock_info)
2434                         return -EINVAL;
2435                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2436                 if (ps == NULL) {
2437                         kfree(rdev->pm.dpm.ps);
2438                         return -ENOMEM;
2439                 }
2440                 rdev->pm.dpm.ps[i].ps_priv = ps;
2441                 k = 0;
2442                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2443                         clock_array_index = power_state->v2.clockInfoIndex[j];
2444                         if (clock_array_index >= clock_info_array->ucNumEntries)
2445                                 continue;
2446                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2447                                 break;
2448                         clock_info = (union pplib_clock_info *)
2449                                 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2450                         kv_parse_pplib_clock_info(rdev,
2451                                                   &rdev->pm.dpm.ps[i], k,
2452                                                   clock_info);
2453                         k++;
2454                 }
2455                 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2456                                               non_clock_info,
2457                                               non_clock_info_array->ucEntrySize);
2458                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2459         }
2460         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2461         return 0;
2462 }
2463
2464 int kv_dpm_init(struct radeon_device *rdev)
2465 {
2466         struct kv_power_info *pi;
2467         int ret, i;
2468
2469         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2470         if (pi == NULL)
2471                 return -ENOMEM;
2472         rdev->pm.dpm.priv = pi;
2473
2474         ret = r600_parse_extended_power_table(rdev);
2475         if (ret)
2476                 return ret;
2477
2478         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2479                 pi->at[i] = TRINITY_AT_DFLT;
2480
2481         pi->sram_end = SMC_RAM_END;
2482
2483         if (rdev->family == CHIP_KABINI)
2484                 pi->high_voltage_t = 4001;
2485
2486         pi->enable_nb_dpm = true;
2487
2488         pi->caps_power_containment = true;
2489         pi->caps_cac = true;
2490         pi->enable_didt = false;
2491         if (pi->enable_didt) {
2492                 pi->caps_sq_ramping = true;
2493                 pi->caps_db_ramping = true;
2494                 pi->caps_td_ramping = true;
2495                 pi->caps_tcp_ramping = true;
2496         }
2497
2498         pi->caps_sclk_ds = true;
2499         pi->enable_auto_thermal_throttling = true;
2500         pi->disable_nb_ps3_in_battery = false;
2501         pi->bapm_enable = true;
2502         pi->voltage_drop_t = 0;
2503         pi->caps_sclk_throttle_low_notification = false;
2504         pi->caps_fps = false; /* true? */
2505         pi->caps_uvd_pg = false; /* XXX */
2506         pi->caps_uvd_dpm = true;
2507         pi->caps_vce_pg = false;
2508         pi->caps_samu_pg = false;
2509         pi->caps_acp_pg = false;
2510         pi->caps_stable_p_state = false;
2511
2512         ret = kv_parse_sys_info_table(rdev);
2513         if (ret)
2514                 return ret;
2515
2516         kv_patch_voltage_values(rdev);
2517         kv_construct_boot_state(rdev);
2518
2519         ret = kv_parse_power_table(rdev);
2520         if (ret)
2521                 return ret;
2522
2523         pi->enable_dpm = true;
2524
2525         return 0;
2526 }
2527
2528 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2529                                                     struct seq_file *m)
2530 {
2531         struct kv_power_info *pi = kv_get_pi(rdev);
2532         u32 current_index =
2533                 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2534                 CURR_SCLK_INDEX_SHIFT;
2535         u32 sclk, tmp;
2536         u16 vddc;
2537
2538         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2539                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2540         } else {
2541                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2542                 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2543                         SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2544                 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2545                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2546                            current_index, sclk, vddc);
2547         }
2548 }
2549
2550 void kv_dpm_print_power_state(struct radeon_device *rdev,
2551                               struct radeon_ps *rps)
2552 {
2553         int i;
2554         struct kv_ps *ps = kv_get_ps(rps);
2555
2556         r600_dpm_print_class_info(rps->class, rps->class2);
2557         r600_dpm_print_cap_info(rps->caps);
2558         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2559         for (i = 0; i < ps->num_levels; i++) {
2560                 struct kv_pl *pl = &ps->levels[i];
2561                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2562                        i, pl->sclk,
2563                        kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2564         }
2565         r600_dpm_print_ps_status(rdev, rps);
2566 }
2567
2568 void kv_dpm_fini(struct radeon_device *rdev)
2569 {
2570         int i;
2571
2572         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2573                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2574         }
2575         kfree(rdev->pm.dpm.ps);
2576         kfree(rdev->pm.dpm.priv);
2577         r600_free_extended_power_table(rdev);
2578 }
2579
2580 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2581 {
2582
2583 }
2584
2585 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2586 {
2587         struct kv_power_info *pi = kv_get_pi(rdev);
2588         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2589
2590         if (low)
2591                 return requested_state->levels[0].sclk;
2592         else
2593                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2594 }
2595
2596 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2597 {
2598         struct kv_power_info *pi = kv_get_pi(rdev);
2599
2600         return pi->sys_info.bootup_uma_clk;
2601 }
2602