drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <linux/clk.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <linux/component.h>
  41 #include <linux/of_device.h>
  42 #include "vc4_drv.h"
  43 #include "vc4_regs.h"
  44
  45 struct vc4_crtc {
  46         struct drm_crtc base;
  47         const struct vc4_crtc_data *data;
  48         void __iomem *regs;
  49
  50         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  51         ktime_t t_vblank;
  52
  53         /* Which HVS channel we're using for our CRTC. */
  54         int channel;
  55
  56         u8 lut_r[256];
  57         u8 lut_g[256];
  58         u8 lut_b[256];
  59         /* Size in pixels of the COB memory allocated to this CRTC. */
  60         u32 cob_size;
  61
  62         struct drm_pending_vblank_event *event;
  63 };
  64
  65 struct vc4_crtc_state {
  66         struct drm_crtc_state base;
  67         /* Dlist area for this CRTC configuration. */
  68         struct drm_mm_node mm;
  69 };
  70
  71 static inline struct vc4_crtc *
  72 to_vc4_crtc(struct drm_crtc *crtc)
  73 {
  74         return (struct vc4_crtc *)crtc;
  75 }
  76
  77 static inline struct vc4_crtc_state *
  78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  79 {
  80         return (struct vc4_crtc_state *)crtc_state;
  81 }
  82
  83 struct vc4_crtc_data {
  84         /* Which channel of the HVS this pixelvalve sources from. */
  85         int hvs_channel;
  86
  87         enum vc4_encoder_type encoder_types[4];
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                              bool in_vblank_irq, int *vpos, int *hpos,
 156                              ktime_t *stime, ktime_t *etime,
 157                              const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 161         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 162         u32 val;
 163         int fifo_lines;
 164         int vblank_lines;
 165         bool ret = false;
 166
 167         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 168
 169         /* Get optional system timestamp before query. */
 170         if (stime)
 171                 *stime = ktime_get();
 172
 173         /*
 174          * Read vertical scanline which is currently composed for our
 175          * pixelvalve by the HVS, and also the scaler status.
 176          */
 177         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 178
 179         /* Get optional system timestamp after query. */
 180         if (etime)
 181                 *etime = ktime_get();
 182
 183         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 184
 185         /* Vertical position of hvs composed scanline. */
 186         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 187         *hpos = 0;
 188
 189         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 190                 *vpos /= 2;
 191
 192                 /* Use hpos to correct for field offset in interlaced mode. */
 193                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 194                         *hpos += mode->crtc_htotal / 2;
 195         }
 196
 197         /* This is the offset we need for translating hvs -> pv scanout pos. */
 198         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 199
 200         if (fifo_lines > 0)
 201                 ret = true;
 202
 203         /* HVS more than fifo_lines into frame for compositing? */
 204         if (*vpos > fifo_lines) {
 205                 /*
 206                  * We are in active scanout and can get some meaningful results
 207                  * from HVS. The actual PV scanout can not trail behind more
 208                  * than fifo_lines as that is the fifo's capacity. Assume that
 209                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 210                  * refilling the fifo and PV consuming from the fifo, ie.
 211                  * whenever the PV consumes and frees up a scanline in the
 212                  * fifo, the HVS will immediately refill it, therefore
 213                  * incrementing vpos. Therefore we choose HVS read position -
 214                  * fifo size in scanlines as a estimate of the real scanout
 215                  * position of the PV.
 216                  */
 217                 *vpos -= fifo_lines + 1;
 218
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         vblank_lines = mode->vtotal - mode->vdisplay;
 232
 233         if (in_vblank_irq) {
 234                 /*
 235                  * Assume the irq handler got called close to first
 236                  * line of vblank, so PV has about a full vblank
 237                  * scanlines to go, and as a base timestamp use the
 238                  * one taken at entry into vblank irq handler, so it
 239                  * is not affected by random delays due to lock
 240                  * contention on event_lock or vblank_time lock in
 241                  * the core.
 242                  */
 243                 *vpos = -vblank_lines;
 244
 245                 if (stime)
 246                         *stime = vc4_crtc->t_vblank;
 247                 if (etime)
 248                         *etime = vc4_crtc->t_vblank;
 249
 250                 /*
 251                  * If the HVS fifo is not yet full then we know for certain
 252                  * we are at the very beginning of vblank, as the hvs just
 253                  * started refilling, and the stime and etime timestamps
 254                  * truly correspond to start of vblank.
 255                  *
 256                  * Unfortunately there's no way to report this to upper levels
 257                  * and make it more useful.
 258                  */
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 273 {
 274         drm_crtc_cleanup(crtc);
 275 }
 276
 277 static void
 278 vc4_crtc_lut_load(struct drm_crtc *crtc)
 279 {
 280         struct drm_device *dev = crtc->dev;
 281         struct vc4_dev *vc4 = to_vc4_dev(dev);
 282         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 283         u32 i;
 284
 285         /* The LUT memory is laid out with each HVS channel in order,
 286          * each of which takes 256 writes for R, 256 for G, then 256
 287          * for B.
 288          */
 289         HVS_WRITE(SCALER_GAMADDR,
 290                   SCALER_GAMADDR_AUTOINC |
 291                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 292
 293         for (i = 0; i < crtc->gamma_size; i++)
 294                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 295         for (i = 0; i < crtc->gamma_size; i++)
 296                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 297         for (i = 0; i < crtc->gamma_size; i++)
 298                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 299 }
 300
 301 static int
 302 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 303                    uint32_t size,
 304                    struct drm_modeset_acquire_ctx *ctx)
 305 {
 306         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 307         u32 i;
 308
 309         for (i = 0; i < size; i++) {
 310                 vc4_crtc->lut_r[i] = r[i] >> 8;
 311                 vc4_crtc->lut_g[i] = g[i] >> 8;
 312                 vc4_crtc->lut_b[i] = b[i] >> 8;
 313         }
 314
 315         vc4_crtc_lut_load(crtc);
 316
 317         return 0;
 318 }
 319
 320 static u32 vc4_get_fifo_full_level(u32 format)
 321 {
 322         static const u32 fifo_len_bytes = 64;
 323         static const u32 hvs_latency_pix = 6;
 324
 325         switch (format) {
 326         case PV_CONTROL_FORMAT_DSIV_16:
 327         case PV_CONTROL_FORMAT_DSIC_16:
 328                 return fifo_len_bytes - 2 * hvs_latency_pix;
 329         case PV_CONTROL_FORMAT_DSIV_18:
 330                 return fifo_len_bytes - 14;
 331         case PV_CONTROL_FORMAT_24:
 332         case PV_CONTROL_FORMAT_DSIV_24:
 333         default:
 334                 return fifo_len_bytes - 3 * hvs_latency_pix;
 335         }
 336 }
 337
 338 /*
 339  * Returns the encoder attached to the CRTC.
 340  *
 341  * VC4 can only scan out to one encoder at a time, while the DRM core
 342  * allows drivers to push pixels to more than one encoder from the
 343  * same CRTC.
 344  */
 345 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 346 {
 347         struct drm_connector *connector;
 348         struct drm_connector_list_iter conn_iter;
 349
 350         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 351         drm_for_each_connector_iter(connector, &conn_iter) {
 352                 if (connector->state->crtc == crtc) {
 353                         drm_connector_list_iter_end(&conn_iter);
 354                         return connector->encoder;
 355                 }
 356         }
 357         drm_connector_list_iter_end(&conn_iter);
 358
 359         return NULL;
 360 }
 361
 362 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 363 {
 364         struct drm_device *dev = crtc->dev;
 365         struct vc4_dev *vc4 = to_vc4_dev(dev);
 366         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 367         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 368         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 369         struct drm_crtc_state *state = crtc->state;
 370         struct drm_display_mode *mode = &state->adjusted_mode;
 371         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 372         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 373         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 374                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 375         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 376         bool debug_dump_regs = false;
 377
 378         if (debug_dump_regs) {
 379                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 380                 vc4_crtc_dump_regs(vc4_crtc);
 381         }
 382
 383         /* Reset the PV fifo. */
 384         CRTC_WRITE(PV_CONTROL, 0);
 385         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 386         CRTC_WRITE(PV_CONTROL, 0);
 387
 388         CRTC_WRITE(PV_HORZA,
 389                    VC4_SET_FIELD((mode->htotal -
 390                                   mode->hsync_end) * pixel_rep,
 391                                  PV_HORZA_HBP) |
 392                    VC4_SET_FIELD((mode->hsync_end -
 393                                   mode->hsync_start) * pixel_rep,
 394                                  PV_HORZA_HSYNC));
 395         CRTC_WRITE(PV_HORZB,
 396                    VC4_SET_FIELD((mode->hsync_start -
 397                                   mode->hdisplay) * pixel_rep,
 398                                  PV_HORZB_HFP) |
 399                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 400
 401         CRTC_WRITE(PV_VERTA,
 402                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 403                                  PV_VERTA_VBP) |
 404                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 405                                  PV_VERTA_VSYNC));
 406         CRTC_WRITE(PV_VERTB,
 407                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 408                                  PV_VERTB_VFP) |
 409                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 410
 411         if (interlace) {
 412                 CRTC_WRITE(PV_VERTA_EVEN,
 413                            VC4_SET_FIELD(mode->crtc_vtotal -
 414                                          mode->crtc_vsync_end - 1,
 415                                          PV_VERTA_VBP) |
 416                            VC4_SET_FIELD(mode->crtc_vsync_end -
 417                                          mode->crtc_vsync_start,
 418                                          PV_VERTA_VSYNC));
 419                 CRTC_WRITE(PV_VERTB_EVEN,
 420                            VC4_SET_FIELD(mode->crtc_vsync_start -
 421                                          mode->crtc_vdisplay,
 422                                          PV_VERTB_VFP) |
 423                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 424
 425                 /* We set up first field even mode for HDMI.  VEC's
 426                  * NTSC mode would want first field odd instead, once
 427                  * we support it (to do so, set ODD_FIRST and put the
 428                  * delay in VSYNCD_EVEN instead).
 429                  */
 430                 CRTC_WRITE(PV_V_CONTROL,
 431                            PV_VCONTROL_CONTINUOUS |
 432                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 433                            PV_VCONTROL_INTERLACE |
 434                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 435                                          PV_VCONTROL_ODD_DELAY));
 436                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 437         } else {
 438                 CRTC_WRITE(PV_V_CONTROL,
 439                            PV_VCONTROL_CONTINUOUS |
 440                            (is_dsi ? PV_VCONTROL_DSI : 0));
 441         }
 442
 443         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 444
 445         CRTC_WRITE(PV_CONTROL,
 446                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 447                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 448                                  PV_CONTROL_FIFO_LEVEL) |
 449                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 450                    PV_CONTROL_CLR_AT_START |
 451                    PV_CONTROL_TRIGGER_UNDERFLOW |
 452                    PV_CONTROL_WAIT_HSTART |
 453                    VC4_SET_FIELD(vc4_encoder->clock_select,
 454                                  PV_CONTROL_CLK_SELECT) |
 455                    PV_CONTROL_FIFO_CLR |
 456                    PV_CONTROL_EN);
 457
 458         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 459                   SCALER_DISPBKGND_AUTOHS |
 460                   SCALER_DISPBKGND_GAMMA |
 461                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 462
 463         /* Reload the LUT, since the SRAMs would have been disabled if
 464          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 465          */
 466         vc4_crtc_lut_load(crtc);
 467
 468         if (debug_dump_regs) {
 469                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 470                 vc4_crtc_dump_regs(vc4_crtc);
 471         }
 472 }
 473
 474 static void require_hvs_enabled(struct drm_device *dev)
 475 {
 476         struct vc4_dev *vc4 = to_vc4_dev(dev);
 477
 478         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 479                      SCALER_DISPCTRL_ENABLE);
 480 }
 481
 482 static void vc4_crtc_disable(struct drm_crtc *crtc)
 483 {
 484         struct drm_device *dev = crtc->dev;
 485         struct vc4_dev *vc4 = to_vc4_dev(dev);
 486         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 487         u32 chan = vc4_crtc->channel;
 488         int ret;
 489         require_hvs_enabled(dev);
 490
 491         /* Disable vblank irq handling before crtc is disabled. */
 492         drm_crtc_vblank_off(crtc);
 493
 494         CRTC_WRITE(PV_V_CONTROL,
 495                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 496         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 497         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 498
 499         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 500             SCALER_DISPCTRLX_ENABLE) {
 501                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 502                           SCALER_DISPCTRLX_RESET);
 503
 504                 /* While the docs say that reset is self-clearing, it
 505                  * seems it doesn't actually.
 506                  */
 507                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 508         }
 509
 510         /* Once we leave, the scaler should be disabled and its fifo empty. */
 511
 512         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 513
 514         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 515                                    SCALER_DISPSTATX_MODE) !=
 516                      SCALER_DISPSTATX_MODE_DISABLED);
 517
 518         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 519                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 520                      SCALER_DISPSTATX_EMPTY);
 521 }
 522
 523 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 524 {
 525         struct drm_device *dev = crtc->dev;
 526         struct vc4_dev *vc4 = to_vc4_dev(dev);
 527         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 528         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 529
 530         if (crtc->state->event) {
 531                 unsigned long flags;
 532
 533                 crtc->state->event->pipe = drm_crtc_index(crtc);
 534
 535                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 536
 537                 spin_lock_irqsave(&dev->event_lock, flags);
 538                 vc4_crtc->event = crtc->state->event;
 539                 crtc->state->event = NULL;
 540
 541                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 542                           vc4_state->mm.start);
 543
 544                 spin_unlock_irqrestore(&dev->event_lock, flags);
 545         } else {
 546                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 547                           vc4_state->mm.start);
 548         }
 549 }
 550
 551 static void vc4_crtc_enable(struct drm_crtc *crtc)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct vc4_dev *vc4 = to_vc4_dev(dev);
 555         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 556         struct drm_crtc_state *state = crtc->state;
 557         struct drm_display_mode *mode = &state->adjusted_mode;
 558
 559         require_hvs_enabled(dev);
 560
 561         /* Enable vblank irq handling before crtc is started otherwise
 562          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 563          */
 564         drm_crtc_vblank_on(crtc);
 565         vc4_crtc_update_dlist(crtc);
 566
 567         /* Turn on the scaler, which will wait for vstart to start
 568          * compositing.
 569          */
 570         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 571                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 572                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 573                   SCALER_DISPCTRLX_ENABLE);
 574
 575         /* Turn on the pixel valve, which will emit the vstart signal. */
 576         CRTC_WRITE(PV_V_CONTROL,
 577                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 578 }
 579
 580 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 581                                 const struct drm_display_mode *mode,
 582                                 struct drm_display_mode *adjusted_mode)
 583 {
 584         /* Do not allow doublescan modes from user space */
 585         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 586                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 587                               crtc->base.id);
 588                 return false;
 589         }
 590
 591         return true;
 592 }
 593
 594 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 595                                  struct drm_crtc_state *state)
 596 {
 597         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 598         struct drm_device *dev = crtc->dev;
 599         struct vc4_dev *vc4 = to_vc4_dev(dev);
 600         struct drm_plane *plane;
 601         unsigned long flags;
 602         const struct drm_plane_state *plane_state;
 603         u32 dlist_count = 0;
 604         int ret;
 605
 606         /* The pixelvalve can only feed one encoder (and encoders are
 607          * 1:1 with connectors.)
 608          */
 609         if (hweight32(state->connector_mask) > 1)
 610                 return -EINVAL;
 611
 612         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 613                 dlist_count += vc4_plane_dlist_size(plane_state);
 614
 615         dlist_count++; /* Account for SCALER_CTL0_END. */
 616
 617         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 618         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 619                                  dlist_count);
 620         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 621         if (ret)
 622                 return ret;
 623
 624         return 0;
 625 }
 626
 627 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 628                                   struct drm_crtc_state *old_state)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct vc4_dev *vc4 = to_vc4_dev(dev);
 632         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 633         struct drm_plane *plane;
 634         bool debug_dump_regs = false;
 635         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 636         u32 __iomem *dlist_next = dlist_start;
 637
 638         if (debug_dump_regs) {
 639                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 640                 vc4_hvs_dump_state(dev);
 641         }
 642
 643         /* Copy all the active planes' dlist contents to the hardware dlist. */
 644         drm_atomic_crtc_for_each_plane(plane, crtc) {
 645                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 646         }
 647
 648         writel(SCALER_CTL0_END, dlist_next);
 649         dlist_next++;
 650
 651         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 652
 653         /* Only update DISPLIST if the CRTC was already running and is not
 654          * being disabled.
 655          * vc4_crtc_enable() takes care of updating the dlist just after
 656          * re-enabling VBLANK interrupts and before enabling the engine.
 657          * If the CRTC is being disabled, there's no point in updating this
 658          * information.
 659          */
 660         if (crtc->state->active && old_state->active)
 661                 vc4_crtc_update_dlist(crtc);
 662
 663         if (debug_dump_regs) {
 664                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 665                 vc4_hvs_dump_state(dev);
 666         }
 667 }
 668
 669 static int vc4_enable_vblank(struct drm_crtc *crtc)
 670 {
 671         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 672
 673         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 674
 675         return 0;
 676 }
 677
 678 static void vc4_disable_vblank(struct drm_crtc *crtc)
 679 {
 680         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 681
 682         CRTC_WRITE(PV_INTEN, 0);
 683 }
 684
 685 /* Must be called with the event lock held */
 686 bool vc4_event_pending(struct drm_crtc *crtc)
 687 {
 688         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 689
 690         return !!vc4_crtc->event;
 691 }
 692
 693 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 694 {
 695         struct drm_crtc *crtc = &vc4_crtc->base;
 696         struct drm_device *dev = crtc->dev;
 697         struct vc4_dev *vc4 = to_vc4_dev(dev);
 698         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 699         u32 chan = vc4_crtc->channel;
 700         unsigned long flags;
 701
 702         spin_lock_irqsave(&dev->event_lock, flags);
 703         if (vc4_crtc->event &&
 704             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 705                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 706                 vc4_crtc->event = NULL;
 707                 drm_crtc_vblank_put(crtc);
 708         }
 709         spin_unlock_irqrestore(&dev->event_lock, flags);
 710 }
 711
 712 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 713 {
 714         struct vc4_crtc *vc4_crtc = data;
 715         u32 stat = CRTC_READ(PV_INTSTAT);
 716         irqreturn_t ret = IRQ_NONE;
 717
 718         if (stat & PV_INT_VFP_START) {
 719                 vc4_crtc->t_vblank = ktime_get();
 720                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 721                 drm_crtc_handle_vblank(&vc4_crtc->base);
 722                 vc4_crtc_handle_page_flip(vc4_crtc);
 723                 ret = IRQ_HANDLED;
 724         }
 725
 726         return ret;
 727 }
 728
 729 struct vc4_async_flip_state {
 730         struct drm_crtc *crtc;
 731         struct drm_framebuffer *fb;
 732         struct drm_pending_vblank_event *event;
 733
 734         struct vc4_seqno_cb cb;
 735 };
 736
 737 /* Called when the V3D execution for the BO being flipped to is done, so that
 738  * we can actually update the plane's address to point to it.
 739  */
 740 static void
 741 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 742 {
 743         struct vc4_async_flip_state *flip_state =
 744                 container_of(cb, struct vc4_async_flip_state, cb);
 745         struct drm_crtc *crtc = flip_state->crtc;
 746         struct drm_device *dev = crtc->dev;
 747         struct vc4_dev *vc4 = to_vc4_dev(dev);
 748         struct drm_plane *plane = crtc->primary;
 749
 750         vc4_plane_async_set_fb(plane, flip_state->fb);
 751         if (flip_state->event) {
 752                 unsigned long flags;
 753
 754                 spin_lock_irqsave(&dev->event_lock, flags);
 755                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 756                 spin_unlock_irqrestore(&dev->event_lock, flags);
 757         }
 758
 759         drm_crtc_vblank_put(crtc);
 760         drm_framebuffer_unreference(flip_state->fb);
 761         kfree(flip_state);
 762
 763         up(&vc4->async_modeset);
 764 }
 765
 766 /* Implements async (non-vblank-synced) page flips.
 767  *
 768  * The page flip ioctl needs to return immediately, so we grab the
 769  * modeset semaphore on the pipe, and queue the address update for
 770  * when V3D is done with the BO being flipped to.
 771  */
 772 static int vc4_async_page_flip(struct drm_crtc *crtc,
 773                                struct drm_framebuffer *fb,
 774                                struct drm_pending_vblank_event *event,
 775                                uint32_t flags)
 776 {
 777         struct drm_device *dev = crtc->dev;
 778         struct vc4_dev *vc4 = to_vc4_dev(dev);
 779         struct drm_plane *plane = crtc->primary;
 780         int ret = 0;
 781         struct vc4_async_flip_state *flip_state;
 782         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 783         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 784
 785         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 786         if (!flip_state)
 787                 return -ENOMEM;
 788
 789         drm_framebuffer_reference(fb);
 790         flip_state->fb = fb;
 791         flip_state->crtc = crtc;
 792         flip_state->event = event;
 793
 794         /* Make sure all other async modesetes have landed. */
 795         ret = down_interruptible(&vc4->async_modeset);
 796         if (ret) {
 797                 drm_framebuffer_unreference(fb);
 798                 kfree(flip_state);
 799                 return ret;
 800         }
 801
 802         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 803
 804         /* Immediately update the plane's legacy fb pointer, so that later
 805          * modeset prep sees the state that will be present when the semaphore
 806          * is released.
 807          */
 808         drm_atomic_set_fb_for_plane(plane->state, fb);
 809         plane->fb = fb;
 810
 811         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 812                            vc4_async_page_flip_complete);
 813
 814         /* Driver takes ownership of state on successful async commit. */
 815         return 0;
 816 }
 817
 818 static int vc4_page_flip(struct drm_crtc *crtc,
 819                          struct drm_framebuffer *fb,
 820                          struct drm_pending_vblank_event *event,
 821                          uint32_t flags,
 822                          struct drm_modeset_acquire_ctx *ctx)
 823 {
 824         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 825                 return vc4_async_page_flip(crtc, fb, event, flags);
 826         else
 827                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 828 }
 829
 830 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 831 {
 832         struct vc4_crtc_state *vc4_state;
 833
 834         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 835         if (!vc4_state)
 836                 return NULL;
 837
 838         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 839         return &vc4_state->base;
 840 }
 841
 842 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 843                                    struct drm_crtc_state *state)
 844 {
 845         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 846         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 847
 848         if (vc4_state->mm.allocated) {
 849                 unsigned long flags;
 850
 851                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 852                 drm_mm_remove_node(&vc4_state->mm);
 853                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 854
 855         }
 856
 857         drm_atomic_helper_crtc_destroy_state(crtc, state);
 858 }
 859
 860 static void
 861 vc4_crtc_reset(struct drm_crtc *crtc)
 862 {
 863         if (crtc->state)
 864                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 865
 866         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
 867         if (crtc->state)
 868                 crtc->state->crtc = crtc;
 869 }
 870
 871 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 872         .set_config = drm_atomic_helper_set_config,
 873         .destroy = vc4_crtc_destroy,
 874         .page_flip = vc4_page_flip,
 875         .set_property = NULL,
 876         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 877         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 878         .reset = vc4_crtc_reset,
 879         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 880         .atomic_destroy_state = vc4_crtc_destroy_state,
 881         .gamma_set = vc4_crtc_gamma_set,
 882         .enable_vblank = vc4_enable_vblank,
 883         .disable_vblank = vc4_disable_vblank,
 884 };
 885
 886 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 887         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 888         .disable = vc4_crtc_disable,
 889         .enable = vc4_crtc_enable,
 890         .mode_fixup = vc4_crtc_mode_fixup,
 891         .atomic_check = vc4_crtc_atomic_check,
 892         .atomic_flush = vc4_crtc_atomic_flush,
 893 };
 894
 895 static const struct vc4_crtc_data pv0_data = {
 896         .hvs_channel = 0,
 897         .encoder_types = {
 898                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 899                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 900         },
 901 };
 902
 903 static const struct vc4_crtc_data pv1_data = {
 904         .hvs_channel = 2,
 905         .encoder_types = {
 906                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 907                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 908         },
 909 };
 910
 911 static const struct vc4_crtc_data pv2_data = {
 912         .hvs_channel = 1,
 913         .encoder_types = {
 914                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 915                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 916         },
 917 };
 918
 919 static const struct of_device_id vc4_crtc_dt_match[] = {
 920         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 921         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 922         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 923         {}
 924 };
 925
 926 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 927                                         struct drm_crtc *crtc)
 928 {
 929         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 930         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 931         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 932         struct drm_encoder *encoder;
 933
 934         drm_for_each_encoder(encoder, drm) {
 935                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 936                 int i;
 937
 938                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 939                         if (vc4_encoder->type == encoder_types[i]) {
 940                                 vc4_encoder->clock_select = i;
 941                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 942                                 break;
 943                         }
 944                 }
 945         }
 946 }
 947
 948 static void
 949 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 950 {
 951         struct drm_device *drm = vc4_crtc->base.dev;
 952         struct vc4_dev *vc4 = to_vc4_dev(drm);
 953         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 954         /* Top/base are supposed to be 4-pixel aligned, but the
 955          * Raspberry Pi firmware fills the low bits (which are
 956          * presumably ignored).
 957          */
 958         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 959         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 960
 961         vc4_crtc->cob_size = top - base + 4;
 962 }
 963
 964 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 965 {
 966         struct platform_device *pdev = to_platform_device(dev);
 967         struct drm_device *drm = dev_get_drvdata(master);
 968         struct vc4_crtc *vc4_crtc;
 969         struct drm_crtc *crtc;
 970         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 971         const struct of_device_id *match;
 972         int ret, i;
 973
 974         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 975         if (!vc4_crtc)
 976                 return -ENOMEM;
 977         crtc = &vc4_crtc->base;
 978
 979         match = of_match_device(vc4_crtc_dt_match, dev);
 980         if (!match)
 981                 return -ENODEV;
 982         vc4_crtc->data = match->data;
 983
 984         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 985         if (IS_ERR(vc4_crtc->regs))
 986                 return PTR_ERR(vc4_crtc->regs);
 987
 988         /* For now, we create just the primary and the legacy cursor
 989          * planes.  We should be able to stack more planes on easily,
 990          * but to do that we would need to compute the bandwidth
 991          * requirement of the plane configuration, and reject ones
 992          * that will take too much.
 993          */
 994         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 995         if (IS_ERR(primary_plane)) {
 996                 dev_err(dev, "failed to construct primary plane\n");
 997                 ret = PTR_ERR(primary_plane);
 998                 goto err;
 999         }
1000
1001         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1002                                   &vc4_crtc_funcs, NULL);
1003         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1004         primary_plane->crtc = crtc;
1005         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1006         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1007
1008         /* Set up some arbitrary number of planes.  We're not limited
1009          * by a set number of physical registers, just the space in
1010          * the HVS (16k) and how small an plane can be (28 bytes).
1011          * However, each plane we set up takes up some memory, and
1012          * increases the cost of looping over planes, which atomic
1013          * modesetting does quite a bit.  As a result, we pick a
1014          * modest number of planes to expose, that should hopefully
1015          * still cover any sane usecase.
1016          */
1017         for (i = 0; i < 8; i++) {
1018                 struct drm_plane *plane =
1019                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1020
1021                 if (IS_ERR(plane))
1022                         continue;
1023
1024                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1025         }
1026
1027         /* Set up the legacy cursor after overlay initialization,
1028          * since we overlay planes on the CRTC in the order they were
1029          * initialized.
1030          */
1031         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1032         if (!IS_ERR(cursor_plane)) {
1033                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1034                 cursor_plane->crtc = crtc;
1035                 crtc->cursor = cursor_plane;
1036         }
1037
1038         vc4_crtc_get_cob_allocation(vc4_crtc);
1039
1040         CRTC_WRITE(PV_INTEN, 0);
1041         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1042         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1043                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1044         if (ret)
1045                 goto err_destroy_planes;
1046
1047         vc4_set_crtc_possible_masks(drm, crtc);
1048
1049         for (i = 0; i < crtc->gamma_size; i++) {
1050                 vc4_crtc->lut_r[i] = i;
1051                 vc4_crtc->lut_g[i] = i;
1052                 vc4_crtc->lut_b[i] = i;
1053         }
1054
1055         platform_set_drvdata(pdev, vc4_crtc);
1056
1057         return 0;
1058
1059 err_destroy_planes:
1060         list_for_each_entry_safe(destroy_plane, temp,
1061                                  &drm->mode_config.plane_list, head) {
1062                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1063                     destroy_plane->funcs->destroy(destroy_plane);
1064         }
1065 err:
1066         return ret;
1067 }
1068
1069 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1070                             void *data)
1071 {
1072         struct platform_device *pdev = to_platform_device(dev);
1073         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1074
1075         vc4_crtc_destroy(&vc4_crtc->base);
1076
1077         CRTC_WRITE(PV_INTEN, 0);
1078
1079         platform_set_drvdata(pdev, NULL);
1080 }
1081
1082 static const struct component_ops vc4_crtc_ops = {
1083         .bind   = vc4_crtc_bind,
1084         .unbind = vc4_crtc_unbind,
1085 };
1086
1087 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1088 {
1089         return component_add(&pdev->dev, &vc4_crtc_ops);
1090 }
1091
1092 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1093 {
1094         component_del(&pdev->dev, &vc4_crtc_ops);
1095         return 0;
1096 }
1097
1098 struct platform_driver vc4_crtc_driver = {
1099         .probe = vc4_crtc_dev_probe,
1100         .remove = vc4_crtc_dev_remove,
1101         .driver = {
1102                 .name = "vc4_crtc",
1103                 .of_match_table = vc4_crtc_dt_match,
1104         },
1105 };