drivers/i2c/busses/i2c-exynos5.c

   1 /**
   2  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <linux/i2c.h>
  15 #include <linux/time.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/slab.h>
  23 #include <linux/io.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29  * HSI2C controller from Samsung supports 2 modes of operation
  30  * 1. Auto mode: Where in master automatically controls the whole transaction
  31  * 2. Manual mode: Software controls the transaction by issuing commands
  32  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
  33  *
  34  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
  35  *
  36  * Special bits are available for both modes of operation to set commands
  37  * and for checking transfer status
  38  */
  39
  40 /* Register Map */
  41 #define HSI2C_CTL               0x00
  42 #define HSI2C_FIFO_CTL          0x04
  43 #define HSI2C_TRAILIG_CTL       0x08
  44 #define HSI2C_CLK_CTL           0x0C
  45 #define HSI2C_CLK_SLOT          0x10
  46 #define HSI2C_INT_ENABLE        0x20
  47 #define HSI2C_INT_STATUS        0x24
  48 #define HSI2C_ERR_STATUS        0x2C
  49 #define HSI2C_FIFO_STATUS       0x30
  50 #define HSI2C_TX_DATA           0x34
  51 #define HSI2C_RX_DATA           0x38
  52 #define HSI2C_CONF              0x40
  53 #define HSI2C_AUTO_CONF         0x44
  54 #define HSI2C_TIMEOUT           0x48
  55 #define HSI2C_MANUAL_CMD        0x4C
  56 #define HSI2C_TRANS_STATUS      0x50
  57 #define HSI2C_TIMING_HS1        0x54
  58 #define HSI2C_TIMING_HS2        0x58
  59 #define HSI2C_TIMING_HS3        0x5C
  60 #define HSI2C_TIMING_FS1        0x60
  61 #define HSI2C_TIMING_FS2        0x64
  62 #define HSI2C_TIMING_FS3        0x68
  63 #define HSI2C_TIMING_SLA        0x6C
  64 #define HSI2C_ADDR              0x70
  65
  66 /* I2C_CTL Register bits */
  67 #define HSI2C_FUNC_MODE_I2C                     (1u << 0)
  68 #define HSI2C_MASTER                            (1u << 3)
  69 #define HSI2C_RXCHON                            (1u << 6)
  70 #define HSI2C_TXCHON                            (1u << 7)
  71 #define HSI2C_SW_RST                            (1u << 31)
  72
  73 /* I2C_FIFO_CTL Register bits */
  74 #define HSI2C_RXFIFO_EN                         (1u << 0)
  75 #define HSI2C_TXFIFO_EN                         (1u << 1)
  76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)           ((x) << 4)
  77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)           ((x) << 16)
  78
  79 /* I2C_TRAILING_CTL Register bits */
  80 #define HSI2C_TRAILING_COUNT                    (0xf)
  81
  82 /* I2C_INT_EN Register bits */
  83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN             (1u << 0)
  84 #define HSI2C_INT_RX_ALMOSTFULL_EN              (1u << 1)
  85 #define HSI2C_INT_TRAILING_EN                   (1u << 6)
  86
  87 /* I2C_INT_STAT Register bits */
  88 #define HSI2C_INT_TX_ALMOSTEMPTY                (1u << 0)
  89 #define HSI2C_INT_RX_ALMOSTFULL                 (1u << 1)
  90 #define HSI2C_INT_TX_UNDERRUN                   (1u << 2)
  91 #define HSI2C_INT_TX_OVERRUN                    (1u << 3)
  92 #define HSI2C_INT_RX_UNDERRUN                   (1u << 4)
  93 #define HSI2C_INT_RX_OVERRUN                    (1u << 5)
  94 #define HSI2C_INT_TRAILING                      (1u << 6)
  95 #define HSI2C_INT_I2C                           (1u << 9)
  96
  97 #define HSI2C_INT_TRANS_DONE                    (1u << 7)
  98 #define HSI2C_INT_TRANS_ABORT                   (1u << 8)
  99 #define HSI2C_INT_NO_DEV_ACK                    (1u << 9)
 100 #define HSI2C_INT_NO_DEV                        (1u << 10)
 101 #define HSI2C_INT_TIMEOUT                       (1u << 11)
 102 #define HSI2C_INT_I2C_TRANS                     (HSI2C_INT_TRANS_DONE | \
 103                                                 HSI2C_INT_TRANS_ABORT | \
 104                                                 HSI2C_INT_NO_DEV_ACK |  \
 105                                                 HSI2C_INT_NO_DEV |      \
 106                                                 HSI2C_INT_TIMEOUT)
 107
 108 /* I2C_FIFO_STAT Register bits */
 109 #define HSI2C_RX_FIFO_EMPTY                     (1u << 24)
 110 #define HSI2C_RX_FIFO_FULL                      (1u << 23)
 111 #define HSI2C_RX_FIFO_LVL(x)                    ((x >> 16) & 0x7f)
 112 #define HSI2C_TX_FIFO_EMPTY                     (1u << 8)
 113 #define HSI2C_TX_FIFO_FULL                      (1u << 7)
 114 #define HSI2C_TX_FIFO_LVL(x)                    ((x >> 0) & 0x7f)
 115
 116 /* I2C_CONF Register bits */
 117 #define HSI2C_AUTO_MODE                         (1u << 31)
 118 #define HSI2C_10BIT_ADDR_MODE                   (1u << 30)
 119 #define HSI2C_HS_MODE                           (1u << 29)
 120
 121 /* I2C_AUTO_CONF Register bits */
 122 #define HSI2C_READ_WRITE                        (1u << 16)
 123 #define HSI2C_STOP_AFTER_TRANS                  (1u << 17)
 124 #define HSI2C_MASTER_RUN                        (1u << 31)
 125
 126 /* I2C_TIMEOUT Register bits */
 127 #define HSI2C_TIMEOUT_EN                        (1u << 31)
 128 #define HSI2C_TIMEOUT_MASK                      0xff
 129
 130 /* I2C_TRANS_STATUS register bits */
 131 #define HSI2C_MASTER_BUSY                       (1u << 17)
 132 #define HSI2C_SLAVE_BUSY                        (1u << 16)
 133
 134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
 135 #define HSI2C_TIMEOUT_AUTO                      (1u << 4)
 136 #define HSI2C_NO_DEV                            (1u << 3)
 137 #define HSI2C_NO_DEV_ACK                        (1u << 2)
 138 #define HSI2C_TRANS_ABORT                       (1u << 1)
 139 #define HSI2C_TRANS_DONE                        (1u << 0)
 140
 141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
 142 #define HSI2C_MASTER_ST_MASK                    0xf
 143 #define HSI2C_MASTER_ST_IDLE                    0x0
 144 #define HSI2C_MASTER_ST_START                   0x1
 145 #define HSI2C_MASTER_ST_RESTART                 0x2
 146 #define HSI2C_MASTER_ST_STOP                    0x3
 147 #define HSI2C_MASTER_ST_MASTER_ID               0x4
 148 #define HSI2C_MASTER_ST_ADDR0                   0x5
 149 #define HSI2C_MASTER_ST_ADDR1                   0x6
 150 #define HSI2C_MASTER_ST_ADDR2                   0x7
 151 #define HSI2C_MASTER_ST_ADDR_SR                 0x8
 152 #define HSI2C_MASTER_ST_READ                    0x9
 153 #define HSI2C_MASTER_ST_WRITE                   0xa
 154 #define HSI2C_MASTER_ST_NO_ACK                  0xb
 155 #define HSI2C_MASTER_ST_LOSE                    0xc
 156 #define HSI2C_MASTER_ST_WAIT                    0xd
 157 #define HSI2C_MASTER_ST_WAIT_CMD                0xe
 158
 159 /* I2C_ADDR register bits */
 160 #define HSI2C_SLV_ADDR_SLV(x)                   ((x & 0x3ff) << 0)
 161 #define HSI2C_SLV_ADDR_MAS(x)                   ((x & 0x3ff) << 10)
 162 #define HSI2C_MASTER_ID(x)                      ((x & 0xff) << 24)
 163 #define MASTER_ID(x)                            ((x & 0x7) + 0x08)
 164
 165 /*
 166  * Controller operating frequency, timing values for operation
 167  * are calculated against this frequency
 168  */
 169 #define HSI2C_HS_TX_CLOCK       1000000
 170 #define HSI2C_FS_TX_CLOCK       100000
 171
 172 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
 173
 174 #define HSI2C_EXYNOS7   BIT(0)
 175
 176 struct exynos5_i2c {
 177         struct i2c_adapter      adap;
 178         unsigned int            suspended:1;
 179
 180         struct i2c_msg          *msg;
 181         struct completion       msg_complete;
 182         unsigned int            msg_ptr;
 183
 184         unsigned int            irq;
 185
 186         void __iomem            *regs;
 187         struct clk              *clk;
 188         struct device           *dev;
 189         int                     state;
 190
 191         spinlock_t              lock;           /* IRQ synchronization */
 192
 193         /*
 194          * Since the TRANS_DONE bit is cleared on read, and we may read it
 195          * either during an IRQ or after a transaction, keep track of its
 196          * state here.
 197          */
 198         int                     trans_done;
 199
 200         /* Controller operating frequency */
 201         unsigned int            op_clock;
 202
 203         /* Version of HS-I2C Hardware */
 204         struct exynos_hsi2c_variant     *variant;
 205 };
 206
 207 /**
 208  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
 209  * @fifo_depth: the fifo depth supported by the HSI2C module
 210  *
 211  * Specifies platform specific configuration of HSI2C module.
 212  * Note: A structure for driver specific platform data is used for future
 213  * expansion of its usage.
 214  */
 215 struct exynos_hsi2c_variant {
 216         unsigned int    fifo_depth;
 217         unsigned int    hw;
 218 };
 219
 220 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 221         .fifo_depth     = 64,
 222 };
 223
 224 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 225         .fifo_depth     = 16,
 226 };
 227
 228 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
 229         .fifo_depth     = 16,
 230         .hw             = HSI2C_EXYNOS7,
 231 };
 232
 233 static const struct of_device_id exynos5_i2c_match[] = {
 234         {
 235                 .compatible = "samsung,exynos5-hsi2c",
 236                 .data = &exynos5250_hsi2c_data
 237         }, {
 238                 .compatible = "samsung,exynos5250-hsi2c",
 239                 .data = &exynos5250_hsi2c_data
 240         }, {
 241                 .compatible = "samsung,exynos5260-hsi2c",
 242                 .data = &exynos5260_hsi2c_data
 243         }, {
 244                 .compatible = "samsung,exynos7-hsi2c",
 245                 .data = &exynos7_hsi2c_data
 246         }, {},
 247 };
 248 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 249
 250 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
 251                                         (struct platform_device *pdev)
 252 {
 253         const struct of_device_id *match;
 254
 255         match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
 256         return (struct exynos_hsi2c_variant *)match->data;
 257 }
 258
 259 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
 260 {
 261         writel(readl(i2c->regs + HSI2C_INT_STATUS),
 262                                 i2c->regs + HSI2C_INT_STATUS);
 263 }
 264
 265 /*
 266  * exynos5_i2c_set_timing: updates the registers with appropriate
 267  * timing values calculated
 268  *
 269  * Returns 0 on success, -EINVAL if the cycle length cannot
 270  * be calculated.
 271  */
 272 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
 273 {
 274         u32 i2c_timing_s1;
 275         u32 i2c_timing_s2;
 276         u32 i2c_timing_s3;
 277         u32 i2c_timing_sla;
 278         unsigned int t_start_su, t_start_hd;
 279         unsigned int t_stop_su;
 280         unsigned int t_data_su, t_data_hd;
 281         unsigned int t_scl_l, t_scl_h;
 282         unsigned int t_sr_release;
 283         unsigned int t_ftl_cycle;
 284         unsigned int clkin = clk_get_rate(i2c->clk);
 285         unsigned int op_clk = hs_timings ? i2c->op_clock :
 286                 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
 287                 i2c->op_clock;
 288         int div, clk_cycle, temp;
 289
 290         /*
 291          * In case of HSI2C controller in Exynos5 series
 292          * FPCLK / FI2C =
 293          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 294          *
 295          * In case of HSI2C controllers in Exynos7 series
 296          * FPCLK / FI2C =
 297          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
 298          *
 299          * clk_cycle := TSCLK_L + TSCLK_H
 300          * temp := (CLK_DIV + 1) * (clk_cycle + 2)
 301          *
 302          * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
 303          *
 304          */
 305         t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
 306         temp = clkin / op_clk - 8 - t_ftl_cycle;
 307         if (i2c->variant->hw != HSI2C_EXYNOS7)
 308                 temp -= t_ftl_cycle;
 309         div = temp / 512;
 310         clk_cycle = temp / (div + 1) - 2;
 311         if (temp < 4 || div >= 256 || clk_cycle < 2) {
 312                 dev_err(i2c->dev, "%s clock set-up failed\n",
 313                         hs_timings ? "HS" : "FS");
 314                 return -EINVAL;
 315         }
 316
 317         t_scl_l = clk_cycle / 2;
 318         t_scl_h = clk_cycle / 2;
 319         t_start_su = t_scl_l;
 320         t_start_hd = t_scl_l;
 321         t_stop_su = t_scl_l;
 322         t_data_su = t_scl_l / 2;
 323         t_data_hd = t_scl_l / 2;
 324         t_sr_release = clk_cycle;
 325
 326         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 327         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 328         i2c_timing_s3 = div << 16 | t_sr_release << 0;
 329         i2c_timing_sla = t_data_hd << 0;
 330
 331         dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
 332                 t_start_su, t_start_hd, t_stop_su);
 333         dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
 334                 t_data_su, t_scl_l, t_scl_h);
 335         dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
 336                 div, t_sr_release);
 337         dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 338
 339         if (hs_timings) {
 340                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
 341                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
 342                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
 343         } else {
 344                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
 345                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
 346                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
 347         }
 348         writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
 349
 350         return 0;
 351 }
 352
 353 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 354 {
 355         /* always set Fast Speed timings */
 356         int ret = exynos5_i2c_set_timing(i2c, false);
 357
 358         if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK)
 359                 return ret;
 360
 361         return exynos5_i2c_set_timing(i2c, true);
 362 }
 363
 364 /*
 365  * exynos5_i2c_init: configures the controller for I2C functionality
 366  * Programs I2C controller for Master mode operation
 367  */
 368 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
 369 {
 370         u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
 371         u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
 372
 373         /* Clear to disable Timeout */
 374         i2c_timeout &= ~HSI2C_TIMEOUT_EN;
 375         writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
 376
 377         writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 378                                         i2c->regs + HSI2C_CTL);
 379         writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 380
 381         if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
 382                 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
 383                                         i2c->regs + HSI2C_ADDR);
 384                 i2c_conf |= HSI2C_HS_MODE;
 385         }
 386
 387         writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
 388 }
 389
 390 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 391 {
 392         u32 i2c_ctl;
 393
 394         /* Set and clear the bit for reset */
 395         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 396         i2c_ctl |= HSI2C_SW_RST;
 397         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 398
 399         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 400         i2c_ctl &= ~HSI2C_SW_RST;
 401         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 402
 403         /* We don't expect calculations to fail during the run */
 404         exynos5_hsi2c_clock_setup(i2c);
 405         /* Initialize the configure registers */
 406         exynos5_i2c_init(i2c);
 407 }
 408
 409 /*
 410  * exynos5_i2c_irq: top level IRQ servicing routine
 411  *
 412  * INT_STATUS registers gives the interrupt details. Further,
 413  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
 414  * state of the bus.
 415  */
 416 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 417 {
 418         struct exynos5_i2c *i2c = dev_id;
 419         u32 fifo_level, int_status, fifo_status, trans_status;
 420         unsigned char byte;
 421         int len = 0;
 422
 423         i2c->state = -EINVAL;
 424
 425         spin_lock(&i2c->lock);
 426
 427         int_status = readl(i2c->regs + HSI2C_INT_STATUS);
 428         writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 429
 430         /* handle interrupt related to the transfer status */
 431         if (i2c->variant->hw == HSI2C_EXYNOS7) {
 432                 if (int_status & HSI2C_INT_TRANS_DONE) {
 433                         i2c->trans_done = 1;
 434                         i2c->state = 0;
 435                 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
 436                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 437                         i2c->state = -EAGAIN;
 438                         goto stop;
 439                 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
 440                         dev_dbg(i2c->dev, "No ACK from device\n");
 441                         i2c->state = -ENXIO;
 442                         goto stop;
 443                 } else if (int_status & HSI2C_INT_NO_DEV) {
 444                         dev_dbg(i2c->dev, "No device\n");
 445                         i2c->state = -ENXIO;
 446                         goto stop;
 447                 } else if (int_status & HSI2C_INT_TIMEOUT) {
 448                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 449                         i2c->state = -ETIMEDOUT;
 450                         goto stop;
 451                 }
 452
 453                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 454                 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
 455                         i2c->state = -EAGAIN;
 456                         goto stop;
 457                 }
 458         } else if (int_status & HSI2C_INT_I2C) {
 459                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 460                 if (trans_status & HSI2C_NO_DEV_ACK) {
 461                         dev_dbg(i2c->dev, "No ACK from device\n");
 462                         i2c->state = -ENXIO;
 463                         goto stop;
 464                 } else if (trans_status & HSI2C_NO_DEV) {
 465                         dev_dbg(i2c->dev, "No device\n");
 466                         i2c->state = -ENXIO;
 467                         goto stop;
 468                 } else if (trans_status & HSI2C_TRANS_ABORT) {
 469                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 470                         i2c->state = -EAGAIN;
 471                         goto stop;
 472                 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
 473                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 474                         i2c->state = -ETIMEDOUT;
 475                         goto stop;
 476                 } else if (trans_status & HSI2C_TRANS_DONE) {
 477                         i2c->trans_done = 1;
 478                         i2c->state = 0;
 479                 }
 480         }
 481
 482         if ((i2c->msg->flags & I2C_M_RD) && (int_status &
 483                         (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
 484                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 485                 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
 486                 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
 487
 488                 while (len > 0) {
 489                         byte = (unsigned char)
 490                                 readl(i2c->regs + HSI2C_RX_DATA);
 491                         i2c->msg->buf[i2c->msg_ptr++] = byte;
 492                         len--;
 493                 }
 494                 i2c->state = 0;
 495         } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
 496                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 497                 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
 498
 499                 len = i2c->variant->fifo_depth - fifo_level;
 500                 if (len > (i2c->msg->len - i2c->msg_ptr)) {
 501                         u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
 502
 503                         int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
 504                         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 505                         len = i2c->msg->len - i2c->msg_ptr;
 506                 }
 507
 508                 while (len > 0) {
 509                         byte = i2c->msg->buf[i2c->msg_ptr++];
 510                         writel(byte, i2c->regs + HSI2C_TX_DATA);
 511                         len--;
 512                 }
 513                 i2c->state = 0;
 514         }
 515
 516  stop:
 517         if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
 518             (i2c->state < 0)) {
 519                 writel(0, i2c->regs + HSI2C_INT_ENABLE);
 520                 exynos5_i2c_clr_pend_irq(i2c);
 521                 complete(&i2c->msg_complete);
 522         }
 523
 524         spin_unlock(&i2c->lock);
 525
 526         return IRQ_HANDLED;
 527 }
 528
 529 /*
 530  * exynos5_i2c_wait_bus_idle
 531  *
 532  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
 533  * cleared.
 534  *
 535  * Returns -EBUSY if the bus cannot be bought to idle
 536  */
 537 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
 538 {
 539         unsigned long stop_time;
 540         u32 trans_status;
 541
 542         /* wait for 100 milli seconds for the bus to be idle */
 543         stop_time = jiffies + msecs_to_jiffies(100) + 1;
 544         do {
 545                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 546                 if (!(trans_status & HSI2C_MASTER_BUSY))
 547                         return 0;
 548
 549                 usleep_range(50, 200);
 550         } while (time_before(jiffies, stop_time));
 551
 552         return -EBUSY;
 553 }
 554
 555 /*
 556  * exynos5_i2c_message_start: Configures the bus and starts the xfer
 557  * i2c: struct exynos5_i2c pointer for the current bus
 558  * stop: Enables stop after transfer if set. Set for last transfer of
 559  *       in the list of messages.
 560  *
 561  * Configures the bus for read/write function
 562  * Sets chip address to talk to, message length to be sent.
 563  * Enables appropriate interrupts and sends start xfer command.
 564  */
 565 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 566 {
 567         u32 i2c_ctl;
 568         u32 int_en = 0;
 569         u32 i2c_auto_conf = 0;
 570         u32 fifo_ctl;
 571         unsigned long flags;
 572         unsigned short trig_lvl;
 573
 574         if (i2c->variant->hw == HSI2C_EXYNOS7)
 575                 int_en |= HSI2C_INT_I2C_TRANS;
 576         else
 577                 int_en |= HSI2C_INT_I2C;
 578
 579         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 580         i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
 581         fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
 582
 583         if (i2c->msg->flags & I2C_M_RD) {
 584                 i2c_ctl |= HSI2C_RXCHON;
 585
 586                 i2c_auto_conf |= HSI2C_READ_WRITE;
 587
 588                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 589                         (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
 590                 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
 591
 592                 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
 593                         HSI2C_INT_TRAILING_EN);
 594         } else {
 595                 i2c_ctl |= HSI2C_TXCHON;
 596
 597                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 598                         (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
 599                 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
 600
 601                 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
 602         }
 603
 604         writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
 605
 606         writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
 607         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 608
 609         /*
 610          * Enable interrupts before starting the transfer so that we don't
 611          * miss any INT_I2C interrupts.
 612          */
 613         spin_lock_irqsave(&i2c->lock, flags);
 614         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 615
 616         if (stop == 1)
 617                 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
 618         i2c_auto_conf |= i2c->msg->len;
 619         i2c_auto_conf |= HSI2C_MASTER_RUN;
 620         writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
 621         spin_unlock_irqrestore(&i2c->lock, flags);
 622 }
 623
 624 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
 625                               struct i2c_msg *msgs, int stop)
 626 {
 627         unsigned long timeout;
 628         int ret;
 629
 630         i2c->msg = msgs;
 631         i2c->msg_ptr = 0;
 632         i2c->trans_done = 0;
 633
 634         reinit_completion(&i2c->msg_complete);
 635
 636         exynos5_i2c_message_start(i2c, stop);
 637
 638         timeout = wait_for_completion_timeout(&i2c->msg_complete,
 639                                               EXYNOS5_I2C_TIMEOUT);
 640         if (timeout == 0)
 641                 ret = -ETIMEDOUT;
 642         else
 643                 ret = i2c->state;
 644
 645         /*
 646          * If this is the last message to be transfered (stop == 1)
 647          * Then check if the bus can be brought back to idle.
 648          */
 649         if (ret == 0 && stop)
 650                 ret = exynos5_i2c_wait_bus_idle(i2c);
 651
 652         if (ret < 0) {
 653                 exynos5_i2c_reset(i2c);
 654                 if (ret == -ETIMEDOUT)
 655                         dev_warn(i2c->dev, "%s timeout\n",
 656                                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
 657         }
 658
 659         /* Return the state as in interrupt routine */
 660         return ret;
 661 }
 662
 663 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
 664                         struct i2c_msg *msgs, int num)
 665 {
 666         struct exynos5_i2c *i2c = adap->algo_data;
 667         int i = 0, ret = 0, stop = 0;
 668
 669         if (i2c->suspended) {
 670                 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
 671                 return -EIO;
 672         }
 673
 674         ret = clk_enable(i2c->clk);
 675         if (ret)
 676                 return ret;
 677
 678         for (i = 0; i < num; i++, msgs++) {
 679                 stop = (i == num - 1);
 680
 681                 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
 682
 683                 if (ret < 0)
 684                         goto out;
 685         }
 686
 687         if (i == num) {
 688                 ret = num;
 689         } else {
 690                 /* Only one message, cannot access the device */
 691                 if (i == 1)
 692                         ret = -EREMOTEIO;
 693                 else
 694                         ret = i;
 695
 696                 dev_warn(i2c->dev, "xfer message failed\n");
 697         }
 698
 699  out:
 700         clk_disable(i2c->clk);
 701         return ret;
 702 }
 703
 704 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
 705 {
 706         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 707 }
 708
 709 static const struct i2c_algorithm exynos5_i2c_algorithm = {
 710         .master_xfer            = exynos5_i2c_xfer,
 711         .functionality          = exynos5_i2c_func,
 712 };
 713
 714 static int exynos5_i2c_probe(struct platform_device *pdev)
 715 {
 716         struct device_node *np = pdev->dev.of_node;
 717         struct exynos5_i2c *i2c;
 718         struct resource *mem;
 719         int ret;
 720
 721         i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
 722         if (!i2c)
 723                 return -ENOMEM;
 724
 725         if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
 726                 i2c->op_clock = HSI2C_FS_TX_CLOCK;
 727
 728         strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
 729         i2c->adap.owner   = THIS_MODULE;
 730         i2c->adap.algo    = &exynos5_i2c_algorithm;
 731         i2c->adap.retries = 3;
 732
 733         i2c->dev = &pdev->dev;
 734         i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
 735         if (IS_ERR(i2c->clk)) {
 736                 dev_err(&pdev->dev, "cannot get clock\n");
 737                 return -ENOENT;
 738         }
 739
 740         ret = clk_prepare_enable(i2c->clk);
 741         if (ret)
 742                 return ret;
 743
 744         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 745         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 746         if (IS_ERR(i2c->regs)) {
 747                 ret = PTR_ERR(i2c->regs);
 748                 goto err_clk;
 749         }
 750
 751         i2c->adap.dev.of_node = np;
 752         i2c->adap.algo_data = i2c;
 753         i2c->adap.dev.parent = &pdev->dev;
 754
 755         /* Clear pending interrupts from u-boot or misc causes */
 756         exynos5_i2c_clr_pend_irq(i2c);
 757
 758         spin_lock_init(&i2c->lock);
 759         init_completion(&i2c->msg_complete);
 760
 761         i2c->irq = ret = platform_get_irq(pdev, 0);
 762         if (ret <= 0) {
 763                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 764                 ret = -EINVAL;
 765                 goto err_clk;
 766         }
 767
 768         ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
 769                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 770                                 dev_name(&pdev->dev), i2c);
 771
 772         if (ret != 0) {
 773                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
 774                 goto err_clk;
 775         }
 776
 777         /* Need to check the variant before setting up. */
 778         i2c->variant = exynos5_i2c_get_variant(pdev);
 779
 780         ret = exynos5_hsi2c_clock_setup(i2c);
 781         if (ret)
 782                 goto err_clk;
 783
 784         exynos5_i2c_reset(i2c);
 785
 786         ret = i2c_add_adapter(&i2c->adap);
 787         if (ret < 0)
 788                 goto err_clk;
 789
 790         platform_set_drvdata(pdev, i2c);
 791
 792         clk_disable(i2c->clk);
 793
 794         return 0;
 795
 796  err_clk:
 797         clk_disable_unprepare(i2c->clk);
 798         return ret;
 799 }
 800
 801 static int exynos5_i2c_remove(struct platform_device *pdev)
 802 {
 803         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 804
 805         i2c_del_adapter(&i2c->adap);
 806
 807         clk_unprepare(i2c->clk);
 808
 809         return 0;
 810 }
 811
 812 #ifdef CONFIG_PM_SLEEP
 813 static int exynos5_i2c_suspend_noirq(struct device *dev)
 814 {
 815         struct platform_device *pdev = to_platform_device(dev);
 816         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 817
 818         i2c->suspended = 1;
 819
 820         clk_unprepare(i2c->clk);
 821
 822         return 0;
 823 }
 824
 825 static int exynos5_i2c_resume_noirq(struct device *dev)
 826 {
 827         struct platform_device *pdev = to_platform_device(dev);
 828         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 829         int ret = 0;
 830
 831         ret = clk_prepare_enable(i2c->clk);
 832         if (ret)
 833                 return ret;
 834
 835         ret = exynos5_hsi2c_clock_setup(i2c);
 836         if (ret) {
 837                 clk_disable_unprepare(i2c->clk);
 838                 return ret;
 839         }
 840
 841         exynos5_i2c_init(i2c);
 842         clk_disable(i2c->clk);
 843         i2c->suspended = 0;
 844
 845         return 0;
 846 }
 847 #endif
 848
 849 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
 850         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
 851                                       exynos5_i2c_resume_noirq)
 852 };
 853
 854 static struct platform_driver exynos5_i2c_driver = {
 855         .probe          = exynos5_i2c_probe,
 856         .remove         = exynos5_i2c_remove,
 857         .driver         = {
 858                 .name   = "exynos5-hsi2c",
 859                 .pm     = &exynos5_i2c_dev_pm_ops,
 860                 .of_match_table = exynos5_i2c_match,
 861         },
 862 };
 863
 864 module_platform_driver(exynos5_i2c_driver);
 865
 866 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
 867 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
 868 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
 869 MODULE_LICENSE("GPL v2");