drivers/iio/adc/vf610_adc.c

   1 /*
   2  * Freescale Vybrid vf610 ADC driver
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include <linux/io.h>
  28 #include <linux/clk.h>
  29 #include <linux/completion.h>
  30 #include <linux/of.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/regulator/consumer.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/err.h>
  35
  36 #include <linux/iio/iio.h>
  37 #include <linux/iio/buffer.h>
  38 #include <linux/iio/sysfs.h>
  39 #include <linux/iio/trigger.h>
  40 #include <linux/iio/trigger_consumer.h>
  41 #include <linux/iio/triggered_buffer.h>
  42
  43 /* This will be the driver name the kernel reports */
  44 #define DRIVER_NAME "vf610-adc"
  45
  46 /* Vybrid/IMX ADC registers */
  47 #define VF610_REG_ADC_HC0               0x00
  48 #define VF610_REG_ADC_HC1               0x04
  49 #define VF610_REG_ADC_HS                0x08
  50 #define VF610_REG_ADC_R0                0x0c
  51 #define VF610_REG_ADC_R1                0x10
  52 #define VF610_REG_ADC_CFG               0x14
  53 #define VF610_REG_ADC_GC                0x18
  54 #define VF610_REG_ADC_GS                0x1c
  55 #define VF610_REG_ADC_CV                0x20
  56 #define VF610_REG_ADC_OFS               0x24
  57 #define VF610_REG_ADC_CAL               0x28
  58 #define VF610_REG_ADC_PCTL              0x30
  59
  60 /* Configuration register field define */
  61 #define VF610_ADC_MODE_BIT8             0x00
  62 #define VF610_ADC_MODE_BIT10            0x04
  63 #define VF610_ADC_MODE_BIT12            0x08
  64 #define VF610_ADC_MODE_MASK             0x0c
  65 #define VF610_ADC_BUSCLK2_SEL           0x01
  66 #define VF610_ADC_ALTCLK_SEL            0x02
  67 #define VF610_ADC_ADACK_SEL             0x03
  68 #define VF610_ADC_ADCCLK_MASK           0x03
  69 #define VF610_ADC_CLK_DIV2              0x20
  70 #define VF610_ADC_CLK_DIV4              0x40
  71 #define VF610_ADC_CLK_DIV8              0x60
  72 #define VF610_ADC_CLK_MASK              0x60
  73 #define VF610_ADC_ADLSMP_LONG           0x10
  74 #define VF610_ADC_ADSTS_SHORT   0x100
  75 #define VF610_ADC_ADSTS_NORMAL  0x200
  76 #define VF610_ADC_ADSTS_LONG    0x300
  77 #define VF610_ADC_ADSTS_MASK            0x300
  78 #define VF610_ADC_ADLPC_EN              0x80
  79 #define VF610_ADC_ADHSC_EN              0x400
  80 #define VF610_ADC_REFSEL_VALT           0x800
  81 #define VF610_ADC_REFSEL_VBG            0x1000
  82 #define VF610_ADC_ADTRG_HARD            0x2000
  83 #define VF610_ADC_AVGS_8                0x4000
  84 #define VF610_ADC_AVGS_16               0x8000
  85 #define VF610_ADC_AVGS_32               0xC000
  86 #define VF610_ADC_AVGS_MASK             0xC000
  87 #define VF610_ADC_OVWREN                0x10000
  88
  89 /* General control register field define */
  90 #define VF610_ADC_ADACKEN               0x1
  91 #define VF610_ADC_DMAEN                 0x2
  92 #define VF610_ADC_ACREN                 0x4
  93 #define VF610_ADC_ACFGT                 0x8
  94 #define VF610_ADC_ACFE                  0x10
  95 #define VF610_ADC_AVGEN                 0x20
  96 #define VF610_ADC_ADCON                 0x40
  97 #define VF610_ADC_CAL                   0x80
  98
  99 /* Other field define */
 100 #define VF610_ADC_ADCHC(x)              ((x) & 0x1F)
 101 #define VF610_ADC_AIEN                  (0x1 << 7)
 102 #define VF610_ADC_CONV_DISABLE          0x1F
 103 #define VF610_ADC_HS_COCO0              0x1
 104 #define VF610_ADC_CALF                  0x2
 105 #define VF610_ADC_TIMEOUT               msecs_to_jiffies(100)
 106
 107 #define DEFAULT_SAMPLE_TIME             1000
 108
 109 /* V at 25°C of 696 mV */
 110 #define VF610_VTEMP25_3V0               950
 111 /* V at 25°C of 699 mV */
 112 #define VF610_VTEMP25_3V3               867
 113 /* Typical sensor slope coefficient at all temperatures */
 114 #define VF610_TEMP_SLOPE_COEFF          1840
 115
 116 enum clk_sel {
 117         VF610_ADCIOC_BUSCLK_SET,
 118         VF610_ADCIOC_ALTCLK_SET,
 119         VF610_ADCIOC_ADACK_SET,
 120 };
 121
 122 enum vol_ref {
 123         VF610_ADCIOC_VR_VREF_SET,
 124         VF610_ADCIOC_VR_VALT_SET,
 125         VF610_ADCIOC_VR_VBG_SET,
 126 };
 127
 128 enum average_sel {
 129         VF610_ADC_SAMPLE_1,
 130         VF610_ADC_SAMPLE_4,
 131         VF610_ADC_SAMPLE_8,
 132         VF610_ADC_SAMPLE_16,
 133         VF610_ADC_SAMPLE_32,
 134 };
 135
 136 enum conversion_mode_sel {
 137         VF610_ADC_CONV_NORMAL,
 138         VF610_ADC_CONV_HIGH_SPEED,
 139         VF610_ADC_CONV_LOW_POWER,
 140 };
 141
 142 enum lst_adder_sel {
 143         VF610_ADCK_CYCLES_3,
 144         VF610_ADCK_CYCLES_5,
 145         VF610_ADCK_CYCLES_7,
 146         VF610_ADCK_CYCLES_9,
 147         VF610_ADCK_CYCLES_13,
 148         VF610_ADCK_CYCLES_17,
 149         VF610_ADCK_CYCLES_21,
 150         VF610_ADCK_CYCLES_25,
 151 };
 152
 153 struct vf610_adc_feature {
 154         enum clk_sel    clk_sel;
 155         enum vol_ref    vol_ref;
 156         enum conversion_mode_sel conv_mode;
 157
 158         int     clk_div;
 159         int     sample_rate;
 160         int     res_mode;
 161         u32 lst_adder_index;
 162         u32 default_sample_time;
 163
 164         bool    calibration;
 165         bool    ovwren;
 166 };
 167
 168 struct vf610_adc {
 169         struct device *dev;
 170         void __iomem *regs;
 171         struct clk *clk;
 172
 173         u32 vref_uv;
 174         u32 value;
 175         struct regulator *vref;
 176
 177         u32 max_adck_rate[3];
 178         struct vf610_adc_feature adc_feature;
 179
 180         u32 sample_freq_avail[5];
 181
 182         struct completion completion;
 183         u16 buffer[8];
 184 };
 185
 186 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
 187 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
 188
 189 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
 190 {
 191         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 192         unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
 193         u32 adck_period, lst_addr_min;
 194         int divisor, i;
 195
 196         adck_rate = info->max_adck_rate[adc_feature->conv_mode];
 197
 198         if (adck_rate) {
 199                 /* calculate clk divider which is within specification */
 200                 divisor = ipg_rate / adck_rate;
 201                 adc_feature->clk_div = 1 << fls(divisor + 1);
 202         } else {
 203                 /* fall-back value using a safe divisor */
 204                 adc_feature->clk_div = 8;
 205         }
 206
 207         adck_rate = ipg_rate / adc_feature->clk_div;
 208
 209         /*
 210          * Determine the long sample time adder value to be used based
 211          * on the default minimum sample time provided.
 212          */
 213         adck_period = NSEC_PER_SEC / adck_rate;
 214         lst_addr_min = adc_feature->default_sample_time / adck_period;
 215         for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
 216                 if (vf610_lst_adder[i] > lst_addr_min) {
 217                         adc_feature->lst_adder_index = i;
 218                         break;
 219                 }
 220         }
 221
 222         /*
 223          * Calculate ADC sample frequencies
 224          * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
 225          * which is the same as bus clock.
 226          *
 227          * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
 228          * SFCAdder: fixed to 6 ADCK cycles
 229          * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
 230          * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
 231          * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
 232          */
 233         for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
 234                 info->sample_freq_avail[i] =
 235                         adck_rate / (6 + vf610_hw_avgs[i] *
 236                          (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
 237 }
 238
 239 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
 240 {
 241         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 242
 243         /* set default Configuration for ADC controller */
 244         adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
 245         adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
 246
 247         adc_feature->calibration = true;
 248         adc_feature->ovwren = true;
 249
 250         adc_feature->res_mode = 12;
 251         adc_feature->sample_rate = 1;
 252
 253         adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
 254
 255         vf610_adc_calculate_rates(info);
 256 }
 257
 258 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
 259 {
 260         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 261         int cfg_data = 0;
 262         int gc_data = 0;
 263
 264         switch (adc_feature->clk_sel) {
 265         case VF610_ADCIOC_ALTCLK_SET:
 266                 cfg_data |= VF610_ADC_ALTCLK_SEL;
 267                 break;
 268         case VF610_ADCIOC_ADACK_SET:
 269                 cfg_data |= VF610_ADC_ADACK_SEL;
 270                 break;
 271         default:
 272                 break;
 273         }
 274
 275         /* low power set for calibration */
 276         cfg_data |= VF610_ADC_ADLPC_EN;
 277
 278         /* enable high speed for calibration */
 279         cfg_data |= VF610_ADC_ADHSC_EN;
 280
 281         /* voltage reference */
 282         switch (adc_feature->vol_ref) {
 283         case VF610_ADCIOC_VR_VREF_SET:
 284                 break;
 285         case VF610_ADCIOC_VR_VALT_SET:
 286                 cfg_data |= VF610_ADC_REFSEL_VALT;
 287                 break;
 288         case VF610_ADCIOC_VR_VBG_SET:
 289                 cfg_data |= VF610_ADC_REFSEL_VBG;
 290                 break;
 291         default:
 292                 dev_err(info->dev, "error voltage reference\n");
 293         }
 294
 295         /* data overwrite enable */
 296         if (adc_feature->ovwren)
 297                 cfg_data |= VF610_ADC_OVWREN;
 298
 299         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 300         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 301 }
 302
 303 static void vf610_adc_calibration(struct vf610_adc *info)
 304 {
 305         int adc_gc, hc_cfg;
 306
 307         if (!info->adc_feature.calibration)
 308                 return;
 309
 310         /* enable calibration interrupt */
 311         hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
 312         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 313
 314         adc_gc = readl(info->regs + VF610_REG_ADC_GC);
 315         writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
 316
 317         if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
 318                 dev_err(info->dev, "Timeout for adc calibration\n");
 319
 320         adc_gc = readl(info->regs + VF610_REG_ADC_GS);
 321         if (adc_gc & VF610_ADC_CALF)
 322                 dev_err(info->dev, "ADC calibration failed\n");
 323
 324         info->adc_feature.calibration = false;
 325 }
 326
 327 static void vf610_adc_cfg_set(struct vf610_adc *info)
 328 {
 329         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 330         int cfg_data;
 331
 332         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 333
 334         cfg_data &= ~VF610_ADC_ADLPC_EN;
 335         if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
 336                 cfg_data |= VF610_ADC_ADLPC_EN;
 337
 338         cfg_data &= ~VF610_ADC_ADHSC_EN;
 339         if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
 340                 cfg_data |= VF610_ADC_ADHSC_EN;
 341
 342         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 343 }
 344
 345 static void vf610_adc_sample_set(struct vf610_adc *info)
 346 {
 347         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 348         int cfg_data, gc_data;
 349
 350         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 351         gc_data = readl(info->regs + VF610_REG_ADC_GC);
 352
 353         /* resolution mode */
 354         cfg_data &= ~VF610_ADC_MODE_MASK;
 355         switch (adc_feature->res_mode) {
 356         case 8:
 357                 cfg_data |= VF610_ADC_MODE_BIT8;
 358                 break;
 359         case 10:
 360                 cfg_data |= VF610_ADC_MODE_BIT10;
 361                 break;
 362         case 12:
 363                 cfg_data |= VF610_ADC_MODE_BIT12;
 364                 break;
 365         default:
 366                 dev_err(info->dev, "error resolution mode\n");
 367                 break;
 368         }
 369
 370         /* clock select and clock divider */
 371         cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
 372         switch (adc_feature->clk_div) {
 373         case 1:
 374                 break;
 375         case 2:
 376                 cfg_data |= VF610_ADC_CLK_DIV2;
 377                 break;
 378         case 4:
 379                 cfg_data |= VF610_ADC_CLK_DIV4;
 380                 break;
 381         case 8:
 382                 cfg_data |= VF610_ADC_CLK_DIV8;
 383                 break;
 384         case 16:
 385                 switch (adc_feature->clk_sel) {
 386                 case VF610_ADCIOC_BUSCLK_SET:
 387                         cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
 388                         break;
 389                 default:
 390                         dev_err(info->dev, "error clk divider\n");
 391                         break;
 392                 }
 393                 break;
 394         }
 395
 396         /*
 397          * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
 398          * determined.
 399          */
 400         switch (adc_feature->lst_adder_index) {
 401         case VF610_ADCK_CYCLES_3:
 402                 break;
 403         case VF610_ADCK_CYCLES_5:
 404                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 405                 break;
 406         case VF610_ADCK_CYCLES_7:
 407                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 408                 break;
 409         case VF610_ADCK_CYCLES_9:
 410                 cfg_data |= VF610_ADC_ADSTS_LONG;
 411                 break;
 412         case VF610_ADCK_CYCLES_13:
 413                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 414                 break;
 415         case VF610_ADCK_CYCLES_17:
 416                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 417                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 418                 break;
 419         case VF610_ADCK_CYCLES_21:
 420                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 421                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 422                 break;
 423         case VF610_ADCK_CYCLES_25:
 424                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 425                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 426                 break;
 427         default:
 428                 dev_err(info->dev, "error in sample time select\n");
 429         }
 430
 431         /* update hardware average selection */
 432         cfg_data &= ~VF610_ADC_AVGS_MASK;
 433         gc_data &= ~VF610_ADC_AVGEN;
 434         switch (adc_feature->sample_rate) {
 435         case VF610_ADC_SAMPLE_1:
 436                 break;
 437         case VF610_ADC_SAMPLE_4:
 438                 gc_data |= VF610_ADC_AVGEN;
 439                 break;
 440         case VF610_ADC_SAMPLE_8:
 441                 gc_data |= VF610_ADC_AVGEN;
 442                 cfg_data |= VF610_ADC_AVGS_8;
 443                 break;
 444         case VF610_ADC_SAMPLE_16:
 445                 gc_data |= VF610_ADC_AVGEN;
 446                 cfg_data |= VF610_ADC_AVGS_16;
 447                 break;
 448         case VF610_ADC_SAMPLE_32:
 449                 gc_data |= VF610_ADC_AVGEN;
 450                 cfg_data |= VF610_ADC_AVGS_32;
 451                 break;
 452         default:
 453                 dev_err(info->dev,
 454                         "error hardware sample average select\n");
 455         }
 456
 457         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 458         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 459 }
 460
 461 static void vf610_adc_hw_init(struct vf610_adc *info)
 462 {
 463         /* CFG: Feature set */
 464         vf610_adc_cfg_post_set(info);
 465         vf610_adc_sample_set(info);
 466
 467         /* adc calibration */
 468         vf610_adc_calibration(info);
 469
 470         /* CFG: power and speed set */
 471         vf610_adc_cfg_set(info);
 472 }
 473
 474 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
 475                                      const struct iio_chan_spec *chan,
 476                                      unsigned int mode)
 477 {
 478         struct vf610_adc *info = iio_priv(indio_dev);
 479
 480         mutex_lock(&indio_dev->mlock);
 481         info->adc_feature.conv_mode = mode;
 482         vf610_adc_calculate_rates(info);
 483         vf610_adc_hw_init(info);
 484         mutex_unlock(&indio_dev->mlock);
 485
 486         return 0;
 487 }
 488
 489 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
 490                                      const struct iio_chan_spec *chan)
 491 {
 492         struct vf610_adc *info = iio_priv(indio_dev);
 493
 494         return info->adc_feature.conv_mode;
 495 }
 496
 497 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
 498                                                  "low-power" };
 499
 500 static const struct iio_enum vf610_conversion_mode = {
 501         .items = vf610_conv_modes,
 502         .num_items = ARRAY_SIZE(vf610_conv_modes),
 503         .get = vf610_get_conversion_mode,
 504         .set = vf610_set_conversion_mode,
 505 };
 506
 507 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
 508         IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
 509         {},
 510 };
 511
 512 #define VF610_ADC_CHAN(_idx, _chan_type) {                      \
 513         .type = (_chan_type),                                   \
 514         .indexed = 1,                                           \
 515         .channel = (_idx),                                      \
 516         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 517         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
 518                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 519         .ext_info = vf610_ext_info,                             \
 520         .scan_index = (_idx),                   \
 521         .scan_type = {                                  \
 522                 .sign = 'u',                            \
 523                 .realbits = 12,                         \
 524                 .storagebits = 16,                      \
 525         },                                              \
 526 }
 527
 528 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {  \
 529         .type = (_chan_type),   \
 530         .channel = (_idx),              \
 531         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),     \
 532         .scan_index = (_idx),                                   \
 533         .scan_type = {                                          \
 534                 .sign = 'u',                                    \
 535                 .realbits = 12,                                 \
 536                 .storagebits = 16,                              \
 537         },                                                      \
 538 }
 539
 540 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
 541         VF610_ADC_CHAN(0, IIO_VOLTAGE),
 542         VF610_ADC_CHAN(1, IIO_VOLTAGE),
 543         VF610_ADC_CHAN(2, IIO_VOLTAGE),
 544         VF610_ADC_CHAN(3, IIO_VOLTAGE),
 545         VF610_ADC_CHAN(4, IIO_VOLTAGE),
 546         VF610_ADC_CHAN(5, IIO_VOLTAGE),
 547         VF610_ADC_CHAN(6, IIO_VOLTAGE),
 548         VF610_ADC_CHAN(7, IIO_VOLTAGE),
 549         VF610_ADC_CHAN(8, IIO_VOLTAGE),
 550         VF610_ADC_CHAN(9, IIO_VOLTAGE),
 551         VF610_ADC_CHAN(10, IIO_VOLTAGE),
 552         VF610_ADC_CHAN(11, IIO_VOLTAGE),
 553         VF610_ADC_CHAN(12, IIO_VOLTAGE),
 554         VF610_ADC_CHAN(13, IIO_VOLTAGE),
 555         VF610_ADC_CHAN(14, IIO_VOLTAGE),
 556         VF610_ADC_CHAN(15, IIO_VOLTAGE),
 557         VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
 558         IIO_CHAN_SOFT_TIMESTAMP(32),
 559         /* sentinel */
 560 };
 561
 562 static int vf610_adc_read_data(struct vf610_adc *info)
 563 {
 564         int result;
 565
 566         result = readl(info->regs + VF610_REG_ADC_R0);
 567
 568         switch (info->adc_feature.res_mode) {
 569         case 8:
 570                 result &= 0xFF;
 571                 break;
 572         case 10:
 573                 result &= 0x3FF;
 574                 break;
 575         case 12:
 576                 result &= 0xFFF;
 577                 break;
 578         default:
 579                 break;
 580         }
 581
 582         return result;
 583 }
 584
 585 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
 586 {
 587         struct iio_dev *indio_dev = dev_id;
 588         struct vf610_adc *info = iio_priv(indio_dev);
 589         int coco;
 590
 591         coco = readl(info->regs + VF610_REG_ADC_HS);
 592         if (coco & VF610_ADC_HS_COCO0) {
 593                 info->value = vf610_adc_read_data(info);
 594                 if (iio_buffer_enabled(indio_dev)) {
 595                         info->buffer[0] = info->value;
 596                         iio_push_to_buffers_with_timestamp(indio_dev,
 597                                         info->buffer,
 598                                         iio_get_time_ns(indio_dev));
 599                         iio_trigger_notify_done(indio_dev->trig);
 600                 } else
 601                         complete(&info->completion);
 602         }
 603
 604         return IRQ_HANDLED;
 605 }
 606
 607 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
 608                                 struct device_attribute *attr, char *buf)
 609 {
 610         struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
 611         size_t len = 0;
 612         int i;
 613
 614         for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
 615                 len += scnprintf(buf + len, PAGE_SIZE - len,
 616                         "%u ", info->sample_freq_avail[i]);
 617
 618         /* replace trailing space by newline */
 619         buf[len - 1] = '\n';
 620
 621         return len;
 622 }
 623
 624 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
 625
 626 static struct attribute *vf610_attributes[] = {
 627         &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 628         NULL
 629 };
 630
 631 static const struct attribute_group vf610_attribute_group = {
 632         .attrs = vf610_attributes,
 633 };
 634
 635 static int vf610_read_raw(struct iio_dev *indio_dev,
 636                         struct iio_chan_spec const *chan,
 637                         int *val,
 638                         int *val2,
 639                         long mask)
 640 {
 641         struct vf610_adc *info = iio_priv(indio_dev);
 642         unsigned int hc_cfg;
 643         long ret;
 644
 645         switch (mask) {
 646         case IIO_CHAN_INFO_RAW:
 647         case IIO_CHAN_INFO_PROCESSED:
 648                 mutex_lock(&indio_dev->mlock);
 649                 if (iio_buffer_enabled(indio_dev)) {
 650                         mutex_unlock(&indio_dev->mlock);
 651                         return -EBUSY;
 652                 }
 653
 654                 reinit_completion(&info->completion);
 655                 hc_cfg = VF610_ADC_ADCHC(chan->channel);
 656                 hc_cfg |= VF610_ADC_AIEN;
 657                 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 658                 ret = wait_for_completion_interruptible_timeout
 659                                 (&info->completion, VF610_ADC_TIMEOUT);
 660                 if (ret == 0) {
 661                         mutex_unlock(&indio_dev->mlock);
 662                         return -ETIMEDOUT;
 663                 }
 664                 if (ret < 0) {
 665                         mutex_unlock(&indio_dev->mlock);
 666                         return ret;
 667                 }
 668
 669                 switch (chan->type) {
 670                 case IIO_VOLTAGE:
 671                         *val = info->value;
 672                         break;
 673                 case IIO_TEMP:
 674                         /*
 675                          * Calculate in degree Celsius times 1000
 676                          * Using the typical sensor slope of 1.84 mV/°C
 677                          * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
 678                          */
 679                         *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
 680                                         1000000 / VF610_TEMP_SLOPE_COEFF;
 681
 682                         break;
 683                 default:
 684                         mutex_unlock(&indio_dev->mlock);
 685                         return -EINVAL;
 686                 }
 687
 688                 mutex_unlock(&indio_dev->mlock);
 689                 return IIO_VAL_INT;
 690
 691         case IIO_CHAN_INFO_SCALE:
 692                 *val = info->vref_uv / 1000;
 693                 *val2 = info->adc_feature.res_mode;
 694                 return IIO_VAL_FRACTIONAL_LOG2;
 695
 696         case IIO_CHAN_INFO_SAMP_FREQ:
 697                 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
 698                 *val2 = 0;
 699                 return IIO_VAL_INT;
 700
 701         default:
 702                 break;
 703         }
 704
 705         return -EINVAL;
 706 }
 707
 708 static int vf610_write_raw(struct iio_dev *indio_dev,
 709                         struct iio_chan_spec const *chan,
 710                         int val,
 711                         int val2,
 712                         long mask)
 713 {
 714         struct vf610_adc *info = iio_priv(indio_dev);
 715         int i;
 716
 717         switch (mask) {
 718         case IIO_CHAN_INFO_SAMP_FREQ:
 719                 for (i = 0;
 720                         i < ARRAY_SIZE(info->sample_freq_avail);
 721                         i++)
 722                         if (val == info->sample_freq_avail[i]) {
 723                                 info->adc_feature.sample_rate = i;
 724                                 vf610_adc_sample_set(info);
 725                                 return 0;
 726                         }
 727                 break;
 728
 729         default:
 730                 break;
 731         }
 732
 733         return -EINVAL;
 734 }
 735
 736 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
 737 {
 738         struct vf610_adc *info = iio_priv(indio_dev);
 739         unsigned int channel;
 740         int ret;
 741         int val;
 742
 743         ret = iio_triggered_buffer_postenable(indio_dev);
 744         if (ret)
 745                 return ret;
 746
 747         val = readl(info->regs + VF610_REG_ADC_GC);
 748         val |= VF610_ADC_ADCON;
 749         writel(val, info->regs + VF610_REG_ADC_GC);
 750
 751         channel = find_first_bit(indio_dev->active_scan_mask,
 752                                                 indio_dev->masklength);
 753
 754         val = VF610_ADC_ADCHC(channel);
 755         val |= VF610_ADC_AIEN;
 756
 757         writel(val, info->regs + VF610_REG_ADC_HC0);
 758
 759         return 0;
 760 }
 761
 762 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
 763 {
 764         struct vf610_adc *info = iio_priv(indio_dev);
 765         unsigned int hc_cfg = 0;
 766         int val;
 767
 768         val = readl(info->regs + VF610_REG_ADC_GC);
 769         val &= ~VF610_ADC_ADCON;
 770         writel(val, info->regs + VF610_REG_ADC_GC);
 771
 772         hc_cfg |= VF610_ADC_CONV_DISABLE;
 773         hc_cfg &= ~VF610_ADC_AIEN;
 774
 775         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 776
 777         return iio_triggered_buffer_predisable(indio_dev);
 778 }
 779
 780 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
 781         .postenable = &vf610_adc_buffer_postenable,
 782         .predisable = &vf610_adc_buffer_predisable,
 783         .validate_scan_mask = &iio_validate_scan_mask_onehot,
 784 };
 785
 786 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
 787                         unsigned reg, unsigned writeval,
 788                         unsigned *readval)
 789 {
 790         struct vf610_adc *info = iio_priv(indio_dev);
 791
 792         if ((readval == NULL) ||
 793                 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
 794                 return -EINVAL;
 795
 796         *readval = readl(info->regs + reg);
 797
 798         return 0;
 799 }
 800
 801 static const struct iio_info vf610_adc_iio_info = {
 802         .driver_module = THIS_MODULE,
 803         .read_raw = &vf610_read_raw,
 804         .write_raw = &vf610_write_raw,
 805         .debugfs_reg_access = &vf610_adc_reg_access,
 806         .attrs = &vf610_attribute_group,
 807 };
 808
 809 static const struct of_device_id vf610_adc_match[] = {
 810         { .compatible = "fsl,vf610-adc", },
 811         { /* sentinel */ }
 812 };
 813 MODULE_DEVICE_TABLE(of, vf610_adc_match);
 814
 815 static int vf610_adc_probe(struct platform_device *pdev)
 816 {
 817         struct vf610_adc *info;
 818         struct iio_dev *indio_dev;
 819         struct resource *mem;
 820         int irq;
 821         int ret;
 822
 823         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
 824         if (!indio_dev) {
 825                 dev_err(&pdev->dev, "Failed allocating iio device\n");
 826                 return -ENOMEM;
 827         }
 828
 829         info = iio_priv(indio_dev);
 830         info->dev = &pdev->dev;
 831
 832         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 833         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 834         if (IS_ERR(info->regs))
 835                 return PTR_ERR(info->regs);
 836
 837         irq = platform_get_irq(pdev, 0);
 838         if (irq < 0) {
 839                 dev_err(&pdev->dev, "no irq resource?\n");
 840                 return irq;
 841         }
 842
 843         ret = devm_request_irq(info->dev, irq,
 844                                 vf610_adc_isr, 0,
 845                                 dev_name(&pdev->dev), indio_dev);
 846         if (ret < 0) {
 847                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
 848                 return ret;
 849         }
 850
 851         info->clk = devm_clk_get(&pdev->dev, "adc");
 852         if (IS_ERR(info->clk)) {
 853                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 854                                                 PTR_ERR(info->clk));
 855                 return PTR_ERR(info->clk);
 856         }
 857
 858         info->vref = devm_regulator_get(&pdev->dev, "vref");
 859         if (IS_ERR(info->vref))
 860                 return PTR_ERR(info->vref);
 861
 862         ret = regulator_enable(info->vref);
 863         if (ret)
 864                 return ret;
 865
 866         info->vref_uv = regulator_get_voltage(info->vref);
 867
 868         of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
 869                         info->max_adck_rate, 3);
 870
 871         ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
 872                         &info->adc_feature.default_sample_time);
 873         if (ret)
 874                 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
 875
 876         platform_set_drvdata(pdev, indio_dev);
 877
 878         init_completion(&info->completion);
 879
 880         indio_dev->name = dev_name(&pdev->dev);
 881         indio_dev->dev.parent = &pdev->dev;
 882         indio_dev->dev.of_node = pdev->dev.of_node;
 883         indio_dev->info = &vf610_adc_iio_info;
 884         indio_dev->modes = INDIO_DIRECT_MODE;
 885         indio_dev->channels = vf610_adc_iio_channels;
 886         indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
 887
 888         ret = clk_prepare_enable(info->clk);
 889         if (ret) {
 890                 dev_err(&pdev->dev,
 891                         "Could not prepare or enable the clock.\n");
 892                 goto error_adc_clk_enable;
 893         }
 894
 895         vf610_adc_cfg_init(info);
 896         vf610_adc_hw_init(info);
 897
 898         ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
 899                                         NULL, &iio_triggered_buffer_setup_ops);
 900         if (ret < 0) {
 901                 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
 902                 goto error_iio_device_register;
 903         }
 904
 905         ret = iio_device_register(indio_dev);
 906         if (ret) {
 907                 dev_err(&pdev->dev, "Couldn't register the device.\n");
 908                 goto error_adc_buffer_init;
 909         }
 910
 911         return 0;
 912
 913 error_adc_buffer_init:
 914         iio_triggered_buffer_cleanup(indio_dev);
 915 error_iio_device_register:
 916         clk_disable_unprepare(info->clk);
 917 error_adc_clk_enable:
 918         regulator_disable(info->vref);
 919
 920         return ret;
 921 }
 922
 923 static int vf610_adc_remove(struct platform_device *pdev)
 924 {
 925         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 926         struct vf610_adc *info = iio_priv(indio_dev);
 927
 928         iio_device_unregister(indio_dev);
 929         iio_triggered_buffer_cleanup(indio_dev);
 930         regulator_disable(info->vref);
 931         clk_disable_unprepare(info->clk);
 932
 933         return 0;
 934 }
 935
 936 #ifdef CONFIG_PM_SLEEP
 937 static int vf610_adc_suspend(struct device *dev)
 938 {
 939         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 940         struct vf610_adc *info = iio_priv(indio_dev);
 941         int hc_cfg;
 942
 943         /* ADC controller enters to stop mode */
 944         hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
 945         hc_cfg |= VF610_ADC_CONV_DISABLE;
 946         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 947
 948         clk_disable_unprepare(info->clk);
 949         regulator_disable(info->vref);
 950
 951         return 0;
 952 }
 953
 954 static int vf610_adc_resume(struct device *dev)
 955 {
 956         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 957         struct vf610_adc *info = iio_priv(indio_dev);
 958         int ret;
 959
 960         ret = regulator_enable(info->vref);
 961         if (ret)
 962                 return ret;
 963
 964         ret = clk_prepare_enable(info->clk);
 965         if (ret)
 966                 goto disable_reg;
 967
 968         vf610_adc_hw_init(info);
 969
 970         return 0;
 971
 972 disable_reg:
 973         regulator_disable(info->vref);
 974         return ret;
 975 }
 976 #endif
 977
 978 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
 979
 980 static struct platform_driver vf610_adc_driver = {
 981         .probe          = vf610_adc_probe,
 982         .remove         = vf610_adc_remove,
 983         .driver         = {
 984                 .name   = DRIVER_NAME,
 985                 .of_match_table = vf610_adc_match,
 986                 .pm     = &vf610_adc_pm_ops,
 987         },
 988 };
 989
 990 module_platform_driver(vf610_adc_driver);
 991
 992 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
 993 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
 994 MODULE_LICENSE("GPL v2");