drivers/infiniband/hw/i40iw/i40iw_ctrl.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include "i40iw_osdep.h"
  36 #include "i40iw_register.h"
  37 #include "i40iw_status.h"
  38 #include "i40iw_hmc.h"
  39
  40 #include "i40iw_d.h"
  41 #include "i40iw_type.h"
  42 #include "i40iw_p.h"
  43 #include "i40iw_vf.h"
  44 #include "i40iw_virtchnl.h"
  45
  46 /**
  47  * i40iw_insert_wqe_hdr - write wqe header
  48  * @wqe: cqp wqe for header
  49  * @header: header for the cqp wqe
  50  */
  51 static inline void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)
  52 {
  53         wmb();            /* make sure WQE is populated before polarity is set */
  54         set_64bit_val(wqe, 24, header);
  55 }
  56
  57 /**
  58  * i40iw_get_cqp_reg_info - get head and tail for cqp using registers
  59  * @cqp: struct for cqp hw
  60  * @val: cqp tail register value
  61  * @tail:wqtail register value
  62  * @error: cqp processing err
  63  */
  64 static inline void i40iw_get_cqp_reg_info(struct i40iw_sc_cqp *cqp,
  65                                           u32 *val,
  66                                           u32 *tail,
  67                                           u32 *error)
  68 {
  69         if (cqp->dev->is_pf) {
  70                 *val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL);
  71                 *tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL);
  72                 *error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR);
  73         } else {
  74                 *val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1);
  75                 *tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL);
  76                 *error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR);
  77         }
  78 }
  79
  80 /**
  81  * i40iw_cqp_poll_registers - poll cqp registers
  82  * @cqp: struct for cqp hw
  83  * @tail:wqtail register value
  84  * @count: how many times to try for completion
  85  */
  86 static enum i40iw_status_code i40iw_cqp_poll_registers(
  87                                                 struct i40iw_sc_cqp *cqp,
  88                                                 u32 tail,
  89                                                 u32 count)
  90 {
  91         u32 i = 0;
  92         u32 newtail, error, val;
  93
  94         while (i < count) {
  95                 i++;
  96                 i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error);
  97                 if (error) {
  98                         error = (cqp->dev->is_pf) ?
  99                                  i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES) :
 100                                  i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
 101                         return I40IW_ERR_CQP_COMPL_ERROR;
 102                 }
 103                 if (newtail != tail) {
 104                         /* SUCCESS */
 105                         I40IW_RING_MOVE_TAIL(cqp->sq_ring);
 106                         cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
 107                         return 0;
 108                 }
 109                 udelay(I40IW_SLEEP_COUNT);
 110         }
 111         return I40IW_ERR_TIMEOUT;
 112 }
 113
 114 /**
 115  * i40iw_sc_parse_fpm_commit_buf - parse fpm commit buffer
 116  * @buf: ptr to fpm commit buffer
 117  * @info: ptr to i40iw_hmc_obj_info struct
 118  * @sd: number of SDs for HMC objects
 119  *
 120  * parses fpm commit info and copy base value
 121  * of hmc objects in hmc_info
 122  */
 123 static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
 124                                 u64 *buf,
 125                                 struct i40iw_hmc_obj_info *info,
 126                                 u32 *sd)
 127 {
 128         u64 temp;
 129         u64 size;
 130         u64 base = 0;
 131         u32 i, j;
 132         u32 k = 0;
 133         u32 low;
 134
 135         /* copy base values in obj_info */
 136         for (i = I40IW_HMC_IW_QP, j = 0;
 137                         i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
 138                 get_64bit_val(buf, j, &temp);
 139                 info[i].base = RS_64_1(temp, 32) * 512;
 140                 if (info[i].base > base) {
 141                         base = info[i].base;
 142                         k = i;
 143                 }
 144                 low = (u32)(temp);
 145                 if (low)
 146                         info[i].cnt = low;
 147         }
 148         size = info[k].cnt * info[k].size + info[k].base;
 149         if (size & 0x1FFFFF)
 150                 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
 151         else
 152                 *sd = (u32)(size >> 21);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer
 159  * @buf: ptr to fpm query buffer
 160  * @info: ptr to i40iw_hmc_obj_info struct
 161  * @hmc_fpm_misc: ptr to fpm data
 162  *
 163  * parses fpm query buffer and copy max_cnt and
 164  * size value of hmc objects in hmc_info
 165  */
 166 static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
 167                                 u64 *buf,
 168                                 struct i40iw_hmc_info *hmc_info,
 169                                 struct i40iw_hmc_fpm_misc *hmc_fpm_misc)
 170 {
 171         u64 temp;
 172         struct i40iw_hmc_obj_info *obj_info;
 173         u32 i, j, size;
 174         u16 max_pe_sds;
 175
 176         obj_info = hmc_info->hmc_obj;
 177
 178         get_64bit_val(buf, 0, &temp);
 179         hmc_info->first_sd_index = (u16)RS_64(temp, I40IW_QUERY_FPM_FIRST_PE_SD_INDEX);
 180         max_pe_sds = (u16)RS_64(temp, I40IW_QUERY_FPM_MAX_PE_SDS);
 181
 182         /* Reduce SD count for VFs by 1 to account for PBLE backing page rounding */
 183         if (hmc_info->hmc_fn_id >= I40IW_FIRST_VF_FPM_ID)
 184                 max_pe_sds--;
 185         hmc_fpm_misc->max_sds = max_pe_sds;
 186         hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
 187
 188         for (i = I40IW_HMC_IW_QP, j = 8;
 189              i <= I40IW_HMC_IW_ARP; i++, j += 8) {
 190                 get_64bit_val(buf, j, &temp);
 191                 if (i == I40IW_HMC_IW_QP)
 192                         obj_info[i].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
 193                 else if (i == I40IW_HMC_IW_CQ)
 194                         obj_info[i].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
 195                 else
 196                         obj_info[i].max_cnt = (u32)temp;
 197
 198                 size = (u32)RS_64_1(temp, 32);
 199                 obj_info[i].size = ((u64)1 << size);
 200         }
 201         for (i = I40IW_HMC_IW_MR, j = 48;
 202                         i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
 203                 get_64bit_val(buf, j, &temp);
 204                 obj_info[i].max_cnt = (u32)temp;
 205                 size = (u32)RS_64_1(temp, 32);
 206                 obj_info[i].size = LS_64_1(1, size);
 207         }
 208
 209         get_64bit_val(buf, 120, &temp);
 210         hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
 211         get_64bit_val(buf, 120, &temp);
 212         hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
 213         get_64bit_val(buf, 120, &temp);
 214         hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
 215         get_64bit_val(buf, 64, &temp);
 216         hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE);
 217         if (!hmc_fpm_misc->xf_block_size)
 218                 return I40IW_ERR_INVALID_SIZE;
 219         get_64bit_val(buf, 80, &temp);
 220         hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE);
 221         if (!hmc_fpm_misc->q1_block_size)
 222                 return I40IW_ERR_INVALID_SIZE;
 223         return 0;
 224 }
 225
 226 /**
 227  * i40iw_fill_qos_list - Change all unknown qs handles to available ones
 228  * @qs_list: list of qs_handles to be fixed with valid qs_handles
 229  */
 230 static void i40iw_fill_qos_list(u16 *qs_list)
 231 {
 232         u16 qshandle = qs_list[0];
 233         int i;
 234
 235         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
 236                 if (qs_list[i] == QS_HANDLE_UNKNOWN)
 237                         qs_list[i] = qshandle;
 238                 else
 239                         qshandle = qs_list[i];
 240         }
 241 }
 242
 243 /**
 244  * i40iw_qp_from_entry - Given entry, get to the qp structure
 245  * @entry: Points to list of qp structure
 246  */
 247 static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry)
 248 {
 249         if (!entry)
 250                 return NULL;
 251
 252         return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list));
 253 }
 254
 255 /**
 256  * i40iw_get_qp - get the next qp from the list given current qp
 257  * @head: Listhead of qp's
 258  * @qp: current qp
 259  */
 260 static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp)
 261 {
 262         struct list_head *entry = NULL;
 263         struct list_head *lastentry;
 264
 265         if (list_empty(head))
 266                 return NULL;
 267
 268         if (!qp) {
 269                 entry = head->next;
 270         } else {
 271                 lastentry = &qp->list;
 272                 entry = (lastentry != head) ? lastentry->next : NULL;
 273         }
 274
 275         return i40iw_qp_from_entry(entry);
 276 }
 277
 278 /**
 279  * i40iw_change_l2params - given the new l2 parameters, change all qp
 280  * @vsi: pointer to the vsi structure
 281  * @l2params: New paramaters from l2
 282  */
 283 void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params)
 284 {
 285         struct i40iw_sc_dev *dev = vsi->dev;
 286         struct i40iw_sc_qp *qp = NULL;
 287         bool qs_handle_change = false;
 288         unsigned long flags;
 289         u16 qs_handle;
 290         int i;
 291
 292         vsi->mss = l2params->mss;
 293
 294         i40iw_fill_qos_list(l2params->qs_handle_list);
 295         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
 296                 qs_handle = l2params->qs_handle_list[i];
 297                 if (vsi->qos[i].qs_handle != qs_handle)
 298                         qs_handle_change = true;
 299                 spin_lock_irqsave(&vsi->qos[i].lock, flags);
 300                 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
 301                 while (qp) {
 302                         if (qs_handle_change) {
 303                                 qp->qs_handle = qs_handle;
 304                                 /* issue cqp suspend command */
 305                                 i40iw_qp_suspend_resume(dev, qp, true);
 306                         }
 307                         qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
 308                 }
 309                 spin_unlock_irqrestore(&vsi->qos[i].lock, flags);
 310                 vsi->qos[i].qs_handle = qs_handle;
 311         }
 312 }
 313
 314 /**
 315  * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
 316  * @qp: qp to be removed from qos
 317  */
 318 static void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
 319 {
 320         struct i40iw_sc_vsi *vsi = qp->vsi;
 321         unsigned long flags;
 322
 323         if (!qp->on_qoslist)
 324                 return;
 325         spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
 326         list_del(&qp->list);
 327         spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
 328 }
 329
 330 /**
 331  * i40iw_qp_add_qos - called during setctx fot qp to be added to qos
 332  * @qp: qp to be added to qos
 333  */
 334 void i40iw_qp_add_qos(struct i40iw_sc_qp *qp)
 335 {
 336         struct i40iw_sc_vsi *vsi = qp->vsi;
 337         unsigned long flags;
 338
 339         if (qp->on_qoslist)
 340                 return;
 341         spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
 342         qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
 343         list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
 344         qp->on_qoslist = true;
 345         spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
 346 }
 347
 348 /**
 349  * i40iw_sc_pd_init - initialize sc pd struct
 350  * @dev: sc device struct
 351  * @pd: sc pd ptr
 352  * @pd_id: pd_id for allocated pd
 353  * @abi_ver: ABI version from user context, -1 if not valid
 354  */
 355 static void i40iw_sc_pd_init(struct i40iw_sc_dev *dev,
 356                              struct i40iw_sc_pd *pd,
 357                              u16 pd_id,
 358                              int abi_ver)
 359 {
 360         pd->size = sizeof(*pd);
 361         pd->pd_id = pd_id;
 362         pd->abi_ver = abi_ver;
 363         pd->dev = dev;
 364 }
 365
 366 /**
 367  * i40iw_get_encoded_wqe_size - given wq size, returns hardware encoded size
 368  * @wqsize: size of the wq (sq, rq, srq) to encoded_size
 369  * @cqpsq: encoded size for sq for cqp as its encoded size is 1+ other wq's
 370  */
 371 u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq)
 372 {
 373         u8 encoded_size = 0;
 374
 375         /* cqp sq's hw coded value starts from 1 for size of 4
 376          * while it starts from 0 for qp' wq's.
 377          */
 378         if (cqpsq)
 379                 encoded_size = 1;
 380         wqsize >>= 2;
 381         while (wqsize >>= 1)
 382                 encoded_size++;
 383         return encoded_size;
 384 }
 385
 386 /**
 387  * i40iw_sc_cqp_init - Initialize buffers for a control Queue Pair
 388  * @cqp: IWARP control queue pair pointer
 389  * @info: IWARP control queue pair init info pointer
 390  *
 391  * Initializes the object and context buffers for a control Queue Pair.
 392  */
 393 static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
 394                                                 struct i40iw_cqp_init_info *info)
 395 {
 396         u8 hw_sq_size;
 397
 398         if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) ||
 399             (info->sq_size < I40IW_CQP_SW_SQSIZE_4) ||
 400             ((info->sq_size & (info->sq_size - 1))))
 401                 return I40IW_ERR_INVALID_SIZE;
 402
 403         hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true);
 404         cqp->size = sizeof(*cqp);
 405         cqp->sq_size = info->sq_size;
 406         cqp->hw_sq_size = hw_sq_size;
 407         cqp->sq_base = info->sq;
 408         cqp->host_ctx = info->host_ctx;
 409         cqp->sq_pa = info->sq_pa;
 410         cqp->host_ctx_pa = info->host_ctx_pa;
 411         cqp->dev = info->dev;
 412         cqp->struct_ver = info->struct_ver;
 413         cqp->scratch_array = info->scratch_array;
 414         cqp->polarity = 0;
 415         cqp->en_datacenter_tcp = info->en_datacenter_tcp;
 416         cqp->enabled_vf_count = info->enabled_vf_count;
 417         cqp->hmc_profile = info->hmc_profile;
 418         info->dev->cqp = cqp;
 419
 420         I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
 421         cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
 422         cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
 423
 424         i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
 425                     "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
 426                     __func__, cqp->sq_size, cqp->hw_sq_size,
 427                     cqp->sq_base, cqp->sq_pa, cqp, cqp->polarity);
 428         return 0;
 429 }
 430
 431 /**
 432  * i40iw_sc_cqp_create - create cqp during bringup
 433  * @cqp: struct for cqp hw
 434  * @maj_err: If error, major err number
 435  * @min_err: If error, minor err number
 436  */
 437 static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
 438                                                   u16 *maj_err,
 439                                                   u16 *min_err)
 440 {
 441         u64 temp;
 442         u32 cnt = 0, p1, p2, val = 0, err_code;
 443         enum i40iw_status_code ret_code;
 444
 445         *maj_err = 0;
 446         *min_err = 0;
 447
 448         ret_code = i40iw_allocate_dma_mem(cqp->dev->hw,
 449                                           &cqp->sdbuf,
 450                                           128,
 451                                           I40IW_SD_BUF_ALIGNMENT);
 452
 453         if (ret_code)
 454                 goto exit;
 455
 456         temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) |
 457                LS_64(cqp->struct_ver, I40IW_CQPHC_SVER);
 458
 459         set_64bit_val(cqp->host_ctx, 0, temp);
 460         set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
 461         temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) |
 462                LS_64(cqp->hmc_profile, I40IW_CQPHC_HMC_PROFILE);
 463         set_64bit_val(cqp->host_ctx, 16, temp);
 464         set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp);
 465         set_64bit_val(cqp->host_ctx, 32, 0);
 466         set_64bit_val(cqp->host_ctx, 40, 0);
 467         set_64bit_val(cqp->host_ctx, 48, 0);
 468         set_64bit_val(cqp->host_ctx, 56, 0);
 469
 470         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQP_HOST_CTX",
 471                         cqp->host_ctx, I40IW_CQP_CTX_SIZE * 8);
 472
 473         p1 = RS_32_1(cqp->host_ctx_pa, 32);
 474         p2 = (u32)cqp->host_ctx_pa;
 475
 476         if (cqp->dev->is_pf) {
 477                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, p1);
 478                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, p2);
 479         } else {
 480                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, p1);
 481                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, p2);
 482         }
 483         do {
 484                 if (cnt++ > I40IW_DONE_COUNT) {
 485                         i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
 486                         ret_code = I40IW_ERR_TIMEOUT;
 487                         /*
 488                          * read PFPE_CQPERRORCODES register to get the minor
 489                          * and major error code
 490                          */
 491                         if (cqp->dev->is_pf)
 492                                 err_code = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES);
 493                         else
 494                                 err_code = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
 495                         *min_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE);
 496                         *maj_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE);
 497                         goto exit;
 498                 }
 499                 udelay(I40IW_SLEEP_COUNT);
 500                 if (cqp->dev->is_pf)
 501                         val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS);
 502                 else
 503                         val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1);
 504         } while (!val);
 505
 506 exit:
 507         if (!ret_code)
 508                 cqp->process_cqp_sds = i40iw_update_sds_noccq;
 509         return ret_code;
 510 }
 511
 512 /**
 513  * i40iw_sc_cqp_post_sq - post of cqp's sq
 514  * @cqp: struct for cqp hw
 515  */
 516 void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp)
 517 {
 518         if (cqp->dev->is_pf)
 519                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
 520         else
 521                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CQPDB1, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
 522
 523         i40iw_debug(cqp->dev,
 524                     I40IW_DEBUG_WQE,
 525                     "%s: HEAD_TAIL[%04d,%04d,%04d]\n",
 526                     __func__,
 527                     cqp->sq_ring.head,
 528                     cqp->sq_ring.tail,
 529                     cqp->sq_ring.size);
 530 }
 531
 532 /**
 533  * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
 534  * @cqp: struct for cqp hw
 535  * @wqe_idx: we index of cqp ring
 536  */
 537 u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch)
 538 {
 539         u64 *wqe = NULL;
 540         u32     wqe_idx;
 541         enum i40iw_status_code ret_code;
 542
 543         if (I40IW_RING_FULL_ERR(cqp->sq_ring)) {
 544                 i40iw_debug(cqp->dev,
 545                             I40IW_DEBUG_WQE,
 546                             "%s: ring is full head %x tail %x size %x\n",
 547                             __func__,
 548                             cqp->sq_ring.head,
 549                             cqp->sq_ring.tail,
 550                             cqp->sq_ring.size);
 551                 return NULL;
 552         }
 553         I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code);
 554         cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
 555         if (ret_code)
 556                 return NULL;
 557         if (!wqe_idx)
 558                 cqp->polarity = !cqp->polarity;
 559
 560         wqe = cqp->sq_base[wqe_idx].elem;
 561         cqp->scratch_array[wqe_idx] = scratch;
 562         I40IW_CQP_INIT_WQE(wqe);
 563
 564         return wqe;
 565 }
 566
 567 /**
 568  * i40iw_sc_cqp_destroy - destroy cqp during close
 569  * @cqp: struct for cqp hw
 570  */
 571 static enum i40iw_status_code i40iw_sc_cqp_destroy(struct i40iw_sc_cqp *cqp)
 572 {
 573         u32 cnt = 0, val = 1;
 574         enum i40iw_status_code ret_code = 0;
 575         u32 cqpstat_addr;
 576
 577         if (cqp->dev->is_pf) {
 578                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, 0);
 579                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, 0);
 580                 cqpstat_addr = I40E_PFPE_CCQPSTATUS;
 581         } else {
 582                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, 0);
 583                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, 0);
 584                 cqpstat_addr = I40E_VFPE_CCQPSTATUS1;
 585         }
 586         do {
 587                 if (cnt++ > I40IW_DONE_COUNT) {
 588                         ret_code = I40IW_ERR_TIMEOUT;
 589                         break;
 590                 }
 591                 udelay(I40IW_SLEEP_COUNT);
 592                 val = i40iw_rd32(cqp->dev->hw, cqpstat_addr);
 593         } while (val);
 594
 595         i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
 596         return ret_code;
 597 }
 598
 599 /**
 600  * i40iw_sc_ccq_arm - enable intr for control cq
 601  * @ccq: ccq sc struct
 602  */
 603 static void i40iw_sc_ccq_arm(struct i40iw_sc_cq *ccq)
 604 {
 605         u64 temp_val;
 606         u16 sw_cq_sel;
 607         u8 arm_next_se;
 608         u8 arm_seq_num;
 609
 610         /* write to cq doorbell shadow area */
 611         /* arm next se should always be zero */
 612         get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val);
 613
 614         sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
 615         arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
 616
 617         arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
 618         arm_seq_num++;
 619
 620         temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
 621                    LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
 622                    LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
 623                    LS_64(1, I40IW_CQ_DBSA_ARM_NEXT);
 624
 625         set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val);
 626
 627         wmb();       /* make sure shadow area is updated before arming */
 628
 629         if (ccq->dev->is_pf)
 630                 i40iw_wr32(ccq->dev->hw, I40E_PFPE_CQARM, ccq->cq_uk.cq_id);
 631         else
 632                 i40iw_wr32(ccq->dev->hw, I40E_VFPE_CQARM1, ccq->cq_uk.cq_id);
 633 }
 634
 635 /**
 636  * i40iw_sc_ccq_get_cqe_info - get ccq's cq entry
 637  * @ccq: ccq sc struct
 638  * @info: completion q entry to return
 639  */
 640 static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info(
 641                                         struct i40iw_sc_cq *ccq,
 642                                         struct i40iw_ccq_cqe_info *info)
 643 {
 644         u64 qp_ctx, temp, temp1;
 645         u64 *cqe;
 646         struct i40iw_sc_cqp *cqp;
 647         u32 wqe_idx;
 648         u8 polarity;
 649         enum i40iw_status_code ret_code = 0;
 650
 651         if (ccq->cq_uk.avoid_mem_cflct)
 652                 cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(&ccq->cq_uk);
 653         else
 654                 cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&ccq->cq_uk);
 655
 656         get_64bit_val(cqe, 24, &temp);
 657         polarity = (u8)RS_64(temp, I40IW_CQ_VALID);
 658         if (polarity != ccq->cq_uk.polarity)
 659                 return I40IW_ERR_QUEUE_EMPTY;
 660
 661         get_64bit_val(cqe, 8, &qp_ctx);
 662         cqp = (struct i40iw_sc_cqp *)(unsigned long)qp_ctx;
 663         info->error = (bool)RS_64(temp, I40IW_CQ_ERROR);
 664         info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
 665         if (info->error) {
 666                 info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR);
 667                 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
 668         }
 669         wqe_idx = (u32)RS_64(temp, I40IW_CQ_WQEIDX);
 670         info->scratch = cqp->scratch_array[wqe_idx];
 671
 672         get_64bit_val(cqe, 16, &temp1);
 673         info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL);
 674         get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1);
 675         info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE);
 676         info->cqp = cqp;
 677
 678         /*  move the head for cq */
 679         I40IW_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
 680         if (I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring) == 0)
 681                 ccq->cq_uk.polarity ^= 1;
 682
 683         /* update cq tail in cq shadow memory also */
 684         I40IW_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
 685         set_64bit_val(ccq->cq_uk.shadow_area,
 686                       0,
 687                       I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring));
 688         wmb(); /* write shadow area before tail */
 689         I40IW_RING_MOVE_TAIL(cqp->sq_ring);
 690         ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
 691
 692         return ret_code;
 693 }
 694
 695 /**
 696  * i40iw_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
 697  * @cqp: struct for cqp hw
 698  * @op_code: cqp opcode for completion
 699  * @info: completion q entry to return
 700  */
 701 static enum i40iw_status_code i40iw_sc_poll_for_cqp_op_done(
 702                                         struct i40iw_sc_cqp *cqp,
 703                                         u8 op_code,
 704                                         struct i40iw_ccq_cqe_info *compl_info)
 705 {
 706         struct i40iw_ccq_cqe_info info;
 707         struct i40iw_sc_cq *ccq;
 708         enum i40iw_status_code ret_code = 0;
 709         u32 cnt = 0;
 710
 711         memset(&info, 0, sizeof(info));
 712         ccq = cqp->dev->ccq;
 713         while (1) {
 714                 if (cnt++ > I40IW_DONE_COUNT)
 715                         return I40IW_ERR_TIMEOUT;
 716
 717                 if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) {
 718                         udelay(I40IW_SLEEP_COUNT);
 719                         continue;
 720                 }
 721
 722                 if (info.error) {
 723                         ret_code = I40IW_ERR_CQP_COMPL_ERROR;
 724                         break;
 725                 }
 726                 /* check if opcode is cq create */
 727                 if (op_code != info.op_code) {
 728                         i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
 729                                     "%s: opcode mismatch for my op code 0x%x, returned opcode %x\n",
 730                                     __func__, op_code, info.op_code);
 731                 }
 732                 /* success, exit out of the loop */
 733                 if (op_code == info.op_code)
 734                         break;
 735         }
 736
 737         if (compl_info)
 738                 memcpy(compl_info, &info, sizeof(*compl_info));
 739
 740         return ret_code;
 741 }
 742
 743 /**
 744  * i40iw_sc_manage_push_page - Handle push page
 745  * @cqp: struct for cqp hw
 746  * @info: push page info
 747  * @scratch: u64 saved to be used during cqp completion
 748  * @post_sq: flag for cqp db to ring
 749  */
 750 static enum i40iw_status_code i40iw_sc_manage_push_page(
 751                                 struct i40iw_sc_cqp *cqp,
 752                                 struct i40iw_cqp_manage_push_page_info *info,
 753                                 u64 scratch,
 754                                 bool post_sq)
 755 {
 756         u64 *wqe;
 757         u64 header;
 758
 759         if (info->push_idx >= I40IW_MAX_PUSH_PAGE_COUNT)
 760                 return I40IW_ERR_INVALID_PUSH_PAGE_INDEX;
 761
 762         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 763         if (!wqe)
 764                 return I40IW_ERR_RING_FULL;
 765
 766         set_64bit_val(wqe, 16, info->qs_handle);
 767
 768         header = LS_64(info->push_idx, I40IW_CQPSQ_MPP_PPIDX) |
 769                  LS_64(I40IW_CQP_OP_MANAGE_PUSH_PAGES, I40IW_CQPSQ_OPCODE) |
 770                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
 771                  LS_64(info->free_page, I40IW_CQPSQ_MPP_FREE_PAGE);
 772
 773         i40iw_insert_wqe_hdr(wqe, header);
 774
 775         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_PUSH_PAGES WQE",
 776                         wqe, I40IW_CQP_WQE_SIZE * 8);
 777
 778         if (post_sq)
 779                 i40iw_sc_cqp_post_sq(cqp);
 780         return 0;
 781 }
 782
 783 /**
 784  * i40iw_sc_manage_hmc_pm_func_table - manage of function table
 785  * @cqp: struct for cqp hw
 786  * @scratch: u64 saved to be used during cqp completion
 787  * @vf_index: vf index for cqp
 788  * @free_pm_fcn: function number
 789  * @post_sq: flag for cqp db to ring
 790  */
 791 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table(
 792                                 struct i40iw_sc_cqp *cqp,
 793                                 u64 scratch,
 794                                 u8 vf_index,
 795                                 bool free_pm_fcn,
 796                                 bool post_sq)
 797 {
 798         u64 *wqe;
 799         u64 header;
 800
 801         if (vf_index >= I40IW_MAX_VF_PER_PF)
 802                 return I40IW_ERR_INVALID_VF_ID;
 803         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 804         if (!wqe)
 805                 return I40IW_ERR_RING_FULL;
 806
 807         header = LS_64(vf_index, I40IW_CQPSQ_MHMC_VFIDX) |
 808                  LS_64(I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, I40IW_CQPSQ_OPCODE) |
 809                  LS_64(free_pm_fcn, I40IW_CQPSQ_MHMC_FREEPMFN) |
 810                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 811
 812         i40iw_insert_wqe_hdr(wqe, header);
 813         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
 814                         wqe, I40IW_CQP_WQE_SIZE * 8);
 815         if (post_sq)
 816                 i40iw_sc_cqp_post_sq(cqp);
 817         return 0;
 818 }
 819
 820 /**
 821  * i40iw_sc_set_hmc_resource_profile - cqp wqe for hmc profile
 822  * @cqp: struct for cqp hw
 823  * @scratch: u64 saved to be used during cqp completion
 824  * @hmc_profile_type: type of profile to set
 825  * @vf_num: vf number for profile
 826  * @post_sq: flag for cqp db to ring
 827  * @poll_registers: flag to poll register for cqp completion
 828  */
 829 static enum i40iw_status_code i40iw_sc_set_hmc_resource_profile(
 830                                 struct i40iw_sc_cqp *cqp,
 831                                 u64 scratch,
 832                                 u8 hmc_profile_type,
 833                                 u8 vf_num, bool post_sq,
 834                                 bool poll_registers)
 835 {
 836         u64 *wqe;
 837         u64 header;
 838         u32 val, tail, error;
 839         enum i40iw_status_code ret_code = 0;
 840
 841         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 842         if (!wqe)
 843                 return I40IW_ERR_RING_FULL;
 844
 845         set_64bit_val(wqe, 16,
 846                       (LS_64(hmc_profile_type, I40IW_CQPSQ_SHMCRP_HMC_PROFILE) |
 847                                 LS_64(vf_num, I40IW_CQPSQ_SHMCRP_VFNUM)));
 848
 849         header = LS_64(I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE, I40IW_CQPSQ_OPCODE) |
 850                        LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 851
 852         i40iw_insert_wqe_hdr(wqe, header);
 853
 854         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
 855                         wqe, I40IW_CQP_WQE_SIZE * 8);
 856
 857         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
 858         if (error)
 859                 return I40IW_ERR_CQP_COMPL_ERROR;
 860
 861         if (post_sq) {
 862                 i40iw_sc_cqp_post_sq(cqp);
 863                 if (poll_registers)
 864                         ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000000);
 865                 else
 866                         ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
 867                                                                  I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
 868                                                                  NULL);
 869         }
 870
 871         return ret_code;
 872 }
 873
 874 /**
 875  * i40iw_sc_manage_hmc_pm_func_table_done - wait for cqp wqe completion for function table
 876  * @cqp: struct for cqp hw
 877  */
 878 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp *cqp)
 879 {
 880         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, NULL);
 881 }
 882
 883 /**
 884  * i40iw_sc_commit_fpm_values_done - wait for cqp eqe completion for fpm commit
 885  * @cqp: struct for cqp hw
 886  */
 887 static enum i40iw_status_code i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp *cqp)
 888 {
 889         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_COMMIT_FPM_VALUES, NULL);
 890 }
 891
 892 /**
 893  * i40iw_sc_commit_fpm_values - cqp wqe for commit fpm values
 894  * @cqp: struct for cqp hw
 895  * @scratch: u64 saved to be used during cqp completion
 896  * @hmc_fn_id: hmc function id
 897  * @commit_fpm_mem; Memory for fpm values
 898  * @post_sq: flag for cqp db to ring
 899  * @wait_type: poll ccq or cqp registers for cqp completion
 900  */
 901 static enum i40iw_status_code i40iw_sc_commit_fpm_values(
 902                                         struct i40iw_sc_cqp *cqp,
 903                                         u64 scratch,
 904                                         u8 hmc_fn_id,
 905                                         struct i40iw_dma_mem *commit_fpm_mem,
 906                                         bool post_sq,
 907                                         u8 wait_type)
 908 {
 909         u64 *wqe;
 910         u64 header;
 911         u32 tail, val, error;
 912         enum i40iw_status_code ret_code = 0;
 913
 914         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 915         if (!wqe)
 916                 return I40IW_ERR_RING_FULL;
 917
 918         set_64bit_val(wqe, 16, hmc_fn_id);
 919         set_64bit_val(wqe, 32, commit_fpm_mem->pa);
 920
 921         header = LS_64(I40IW_CQP_OP_COMMIT_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
 922                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 923
 924         i40iw_insert_wqe_hdr(wqe, header);
 925
 926         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "COMMIT_FPM_VALUES WQE",
 927                         wqe, I40IW_CQP_WQE_SIZE * 8);
 928
 929         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
 930         if (error)
 931                 return I40IW_ERR_CQP_COMPL_ERROR;
 932
 933         if (post_sq) {
 934                 i40iw_sc_cqp_post_sq(cqp);
 935
 936                 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
 937                         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
 938                 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
 939                         ret_code = i40iw_sc_commit_fpm_values_done(cqp);
 940         }
 941
 942         return ret_code;
 943 }
 944
 945 /**
 946  * i40iw_sc_query_fpm_values_done - poll for cqp wqe completion for query fpm
 947  * @cqp: struct for cqp hw
 948  */
 949 static enum i40iw_status_code i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp *cqp)
 950 {
 951         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_QUERY_FPM_VALUES, NULL);
 952 }
 953
 954 /**
 955  * i40iw_sc_query_fpm_values - cqp wqe query fpm values
 956  * @cqp: struct for cqp hw
 957  * @scratch: u64 saved to be used during cqp completion
 958  * @hmc_fn_id: hmc function id
 959  * @query_fpm_mem: memory for return fpm values
 960  * @post_sq: flag for cqp db to ring
 961  * @wait_type: poll ccq or cqp registers for cqp completion
 962  */
 963 static enum i40iw_status_code i40iw_sc_query_fpm_values(
 964                                         struct i40iw_sc_cqp *cqp,
 965                                         u64 scratch,
 966                                         u8 hmc_fn_id,
 967                                         struct i40iw_dma_mem *query_fpm_mem,
 968                                         bool post_sq,
 969                                         u8 wait_type)
 970 {
 971         u64 *wqe;
 972         u64 header;
 973         u32 tail, val, error;
 974         enum i40iw_status_code ret_code = 0;
 975
 976         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 977         if (!wqe)
 978                 return I40IW_ERR_RING_FULL;
 979
 980         set_64bit_val(wqe, 16, hmc_fn_id);
 981         set_64bit_val(wqe, 32, query_fpm_mem->pa);
 982
 983         header = LS_64(I40IW_CQP_OP_QUERY_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
 984                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 985
 986         i40iw_insert_wqe_hdr(wqe, header);
 987
 988         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_FPM WQE",
 989                         wqe, I40IW_CQP_WQE_SIZE * 8);
 990
 991         /* read the tail from CQP_TAIL register */
 992         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
 993
 994         if (error)
 995                 return I40IW_ERR_CQP_COMPL_ERROR;
 996
 997         if (post_sq) {
 998                 i40iw_sc_cqp_post_sq(cqp);
 999                 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
1000                         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
1001                 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
1002                         ret_code = i40iw_sc_query_fpm_values_done(cqp);
1003         }
1004
1005         return ret_code;
1006 }
1007
1008 /**
1009  * i40iw_sc_add_arp_cache_entry - cqp wqe add arp cache entry
1010  * @cqp: struct for cqp hw
1011  * @info: arp entry information
1012  * @scratch: u64 saved to be used during cqp completion
1013  * @post_sq: flag for cqp db to ring
1014  */
1015 static enum i40iw_status_code i40iw_sc_add_arp_cache_entry(
1016                                 struct i40iw_sc_cqp *cqp,
1017                                 struct i40iw_add_arp_cache_entry_info *info,
1018                                 u64 scratch,
1019                                 bool post_sq)
1020 {
1021         u64 *wqe;
1022         u64 temp, header;
1023
1024         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1025         if (!wqe)
1026                 return I40IW_ERR_RING_FULL;
1027         set_64bit_val(wqe, 8, info->reach_max);
1028
1029         temp = info->mac_addr[5] |
1030                LS_64_1(info->mac_addr[4], 8) |
1031                LS_64_1(info->mac_addr[3], 16) |
1032                LS_64_1(info->mac_addr[2], 24) |
1033                LS_64_1(info->mac_addr[1], 32) |
1034                LS_64_1(info->mac_addr[0], 40);
1035
1036         set_64bit_val(wqe, 16, temp);
1037
1038         header = info->arp_index |
1039                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1040                  LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) |
1041                  LS_64(1, I40IW_CQPSQ_MAT_ENTRYVALID) |
1042                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1043
1044         i40iw_insert_wqe_hdr(wqe, header);
1045
1046         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_ENTRY WQE",
1047                         wqe, I40IW_CQP_WQE_SIZE * 8);
1048
1049         if (post_sq)
1050                 i40iw_sc_cqp_post_sq(cqp);
1051         return 0;
1052 }
1053
1054 /**
1055  * i40iw_sc_del_arp_cache_entry - dele arp cache entry
1056  * @cqp: struct for cqp hw
1057  * @scratch: u64 saved to be used during cqp completion
1058  * @arp_index: arp index to delete arp entry
1059  * @post_sq: flag for cqp db to ring
1060  */
1061 static enum i40iw_status_code i40iw_sc_del_arp_cache_entry(
1062                                         struct i40iw_sc_cqp *cqp,
1063                                         u64 scratch,
1064                                         u16 arp_index,
1065                                         bool post_sq)
1066 {
1067         u64 *wqe;
1068         u64 header;
1069
1070         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1071         if (!wqe)
1072                 return I40IW_ERR_RING_FULL;
1073
1074         header = arp_index |
1075                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1076                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1077         i40iw_insert_wqe_hdr(wqe, header);
1078
1079         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE",
1080                         wqe, I40IW_CQP_WQE_SIZE * 8);
1081
1082         if (post_sq)
1083                 i40iw_sc_cqp_post_sq(cqp);
1084         return 0;
1085 }
1086
1087 /**
1088  * i40iw_sc_query_arp_cache_entry - cqp wqe to query arp and arp index
1089  * @cqp: struct for cqp hw
1090  * @scratch: u64 saved to be used during cqp completion
1091  * @arp_index: arp index to delete arp entry
1092  * @post_sq: flag for cqp db to ring
1093  */
1094 static enum i40iw_status_code i40iw_sc_query_arp_cache_entry(
1095                                 struct i40iw_sc_cqp *cqp,
1096                                 u64 scratch,
1097                                 u16 arp_index,
1098                                 bool post_sq)
1099 {
1100         u64 *wqe;
1101         u64 header;
1102
1103         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1104         if (!wqe)
1105                 return I40IW_ERR_RING_FULL;
1106
1107         header = arp_index |
1108                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1109                  LS_64(1, I40IW_CQPSQ_MAT_QUERY) |
1110                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1111
1112         i40iw_insert_wqe_hdr(wqe, header);
1113
1114         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_ARP_CACHE_ENTRY WQE",
1115                         wqe, I40IW_CQP_WQE_SIZE * 8);
1116
1117         if (post_sq)
1118                 i40iw_sc_cqp_post_sq(cqp);
1119         return 0;
1120 }
1121
1122 /**
1123  * i40iw_sc_manage_apbvt_entry - for adding and deleting apbvt entries
1124  * @cqp: struct for cqp hw
1125  * @info: info for apbvt entry to add or delete
1126  * @scratch: u64 saved to be used during cqp completion
1127  * @post_sq: flag for cqp db to ring
1128  */
1129 static enum i40iw_status_code i40iw_sc_manage_apbvt_entry(
1130                                 struct i40iw_sc_cqp *cqp,
1131                                 struct i40iw_apbvt_info *info,
1132                                 u64 scratch,
1133                                 bool post_sq)
1134 {
1135         u64 *wqe;
1136         u64 header;
1137
1138         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1139         if (!wqe)
1140                 return I40IW_ERR_RING_FULL;
1141
1142         set_64bit_val(wqe, 16, info->port);
1143
1144         header = LS_64(I40IW_CQP_OP_MANAGE_APBVT, I40IW_CQPSQ_OPCODE) |
1145                  LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) |
1146                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1147
1148         i40iw_insert_wqe_hdr(wqe, header);
1149
1150         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_APBVT WQE",
1151                         wqe, I40IW_CQP_WQE_SIZE * 8);
1152
1153         if (post_sq)
1154                 i40iw_sc_cqp_post_sq(cqp);
1155         return 0;
1156 }
1157
1158 /**
1159  * i40iw_sc_manage_qhash_table_entry - manage quad hash entries
1160  * @cqp: struct for cqp hw
1161  * @info: info for quad hash to manage
1162  * @scratch: u64 saved to be used during cqp completion
1163  * @post_sq: flag for cqp db to ring
1164  *
1165  * This is called before connection establishment is started. For passive connections, when
1166  * listener is created, it will call with entry type of  I40IW_QHASH_TYPE_TCP_SYN with local
1167  * ip address and tcp port. When SYN is received (passive connections) or
1168  * sent (active connections), this routine is called with entry type of
1169  * I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info.
1170  *
1171  * When iwarp connection is done and its state moves to RTS, the quad hash entry in
1172  * the hardware will point to iwarp's qp number and requires no calls from the driver.
1173  */
1174 static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
1175                                         struct i40iw_sc_cqp *cqp,
1176                                         struct i40iw_qhash_table_info *info,
1177                                         u64 scratch,
1178                                         bool post_sq)
1179 {
1180         u64 *wqe;
1181         u64 qw1 = 0;
1182         u64 qw2 = 0;
1183         u64 temp;
1184         struct i40iw_sc_vsi *vsi = info->vsi;
1185
1186         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1187         if (!wqe)
1188                 return I40IW_ERR_RING_FULL;
1189
1190         temp = info->mac_addr[5] |
1191                 LS_64_1(info->mac_addr[4], 8) |
1192                 LS_64_1(info->mac_addr[3], 16) |
1193                 LS_64_1(info->mac_addr[2], 24) |
1194                 LS_64_1(info->mac_addr[1], 32) |
1195                 LS_64_1(info->mac_addr[0], 40);
1196
1197         set_64bit_val(wqe, 0, temp);
1198
1199         qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) |
1200               LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT);
1201         if (info->ipv4_valid) {
1202                 set_64bit_val(wqe,
1203                               48,
1204                               LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1205         } else {
1206                 set_64bit_val(wqe,
1207                               56,
1208                               LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1209                               LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1210
1211                 set_64bit_val(wqe,
1212                               48,
1213                               LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1214                               LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1215         }
1216         qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
1217         if (info->vlan_valid)
1218                 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
1219         set_64bit_val(wqe, 16, qw2);
1220         if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
1221                 qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT);
1222                 if (!info->ipv4_valid) {
1223                         set_64bit_val(wqe,
1224                                       40,
1225                                       LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1226                                       LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1227                         set_64bit_val(wqe,
1228                                       32,
1229                                       LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1230                                       LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1231                 } else {
1232                         set_64bit_val(wqe,
1233                                       32,
1234                                       LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1235                 }
1236         }
1237
1238         set_64bit_val(wqe, 8, qw1);
1239         temp = LS_64(cqp->polarity, I40IW_CQPSQ_QHASH_WQEVALID) |
1240                LS_64(I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY, I40IW_CQPSQ_QHASH_OPCODE) |
1241                LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) |
1242                LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) |
1243                LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) |
1244                LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE);
1245
1246         i40iw_insert_wqe_hdr(wqe, temp);
1247
1248         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_QHASH WQE",
1249                         wqe, I40IW_CQP_WQE_SIZE * 8);
1250
1251         if (post_sq)
1252                 i40iw_sc_cqp_post_sq(cqp);
1253         return 0;
1254 }
1255
1256 /**
1257  * i40iw_sc_alloc_local_mac_ipaddr_entry - cqp wqe for loc mac entry
1258  * @cqp: struct for cqp hw
1259  * @scratch: u64 saved to be used during cqp completion
1260  * @post_sq: flag for cqp db to ring
1261  */
1262 static enum i40iw_status_code i40iw_sc_alloc_local_mac_ipaddr_entry(
1263                                         struct i40iw_sc_cqp *cqp,
1264                                         u64 scratch,
1265                                         bool post_sq)
1266 {
1267         u64 *wqe;
1268         u64 header;
1269
1270         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1271         if (!wqe)
1272                 return I40IW_ERR_RING_FULL;
1273         header = LS_64(I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY, I40IW_CQPSQ_OPCODE) |
1274                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1275
1276         i40iw_insert_wqe_hdr(wqe, header);
1277         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ALLOCATE_LOCAL_MAC_IPADDR WQE",
1278                         wqe, I40IW_CQP_WQE_SIZE * 8);
1279         if (post_sq)
1280                 i40iw_sc_cqp_post_sq(cqp);
1281         return 0;
1282 }
1283
1284 /**
1285  * i40iw_sc_add_local_mac_ipaddr_entry - add mac enry
1286  * @cqp: struct for cqp hw
1287  * @info:mac addr info
1288  * @scratch: u64 saved to be used during cqp completion
1289  * @post_sq: flag for cqp db to ring
1290  */
1291 static enum i40iw_status_code i40iw_sc_add_local_mac_ipaddr_entry(
1292                                 struct i40iw_sc_cqp *cqp,
1293                                 struct i40iw_local_mac_ipaddr_entry_info *info,
1294                                 u64 scratch,
1295                                 bool post_sq)
1296 {
1297         u64 *wqe;
1298         u64 temp, header;
1299
1300         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1301         if (!wqe)
1302                 return I40IW_ERR_RING_FULL;
1303         temp = info->mac_addr[5] |
1304                 LS_64_1(info->mac_addr[4], 8) |
1305                 LS_64_1(info->mac_addr[3], 16) |
1306                 LS_64_1(info->mac_addr[2], 24) |
1307                 LS_64_1(info->mac_addr[1], 32) |
1308                 LS_64_1(info->mac_addr[0], 40);
1309
1310         set_64bit_val(wqe, 32, temp);
1311
1312         header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1313                  LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1314                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1315
1316         i40iw_insert_wqe_hdr(wqe, header);
1317
1318         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ADD_LOCAL_MAC_IPADDR WQE",
1319                         wqe, I40IW_CQP_WQE_SIZE * 8);
1320
1321         if (post_sq)
1322                 i40iw_sc_cqp_post_sq(cqp);
1323         return 0;
1324 }
1325
1326 /**
1327  * i40iw_sc_del_local_mac_ipaddr_entry - cqp wqe to dele local mac
1328  * @cqp: struct for cqp hw
1329  * @scratch: u64 saved to be used during cqp completion
1330  * @entry_idx: index of mac entry
1331  * @ ignore_ref_count: to force mac adde delete
1332  * @post_sq: flag for cqp db to ring
1333  */
1334 static enum i40iw_status_code i40iw_sc_del_local_mac_ipaddr_entry(
1335                                 struct i40iw_sc_cqp *cqp,
1336                                 u64 scratch,
1337                                 u8 entry_idx,
1338                                 u8 ignore_ref_count,
1339                                 bool post_sq)
1340 {
1341         u64 *wqe;
1342         u64 header;
1343
1344         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1345         if (!wqe)
1346                 return I40IW_ERR_RING_FULL;
1347         header = LS_64(entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1348                  LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1349                  LS_64(1, I40IW_CQPSQ_MLIPA_FREEENTRY) |
1350                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
1351                  LS_64(ignore_ref_count, I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT);
1352
1353         i40iw_insert_wqe_hdr(wqe, header);
1354
1355         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE",
1356                         wqe, I40IW_CQP_WQE_SIZE * 8);
1357
1358         if (post_sq)
1359                 i40iw_sc_cqp_post_sq(cqp);
1360         return 0;
1361 }
1362
1363 /**
1364  * i40iw_sc_cqp_nop - send a nop wqe
1365  * @cqp: struct for cqp hw
1366  * @scratch: u64 saved to be used during cqp completion
1367  * @post_sq: flag for cqp db to ring
1368  */
1369 static enum i40iw_status_code i40iw_sc_cqp_nop(struct i40iw_sc_cqp *cqp,
1370                                                u64 scratch,
1371                                                bool post_sq)
1372 {
1373         u64 *wqe;
1374         u64 header;
1375
1376         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1377         if (!wqe)
1378                 return I40IW_ERR_RING_FULL;
1379         header = LS_64(I40IW_CQP_OP_NOP, I40IW_CQPSQ_OPCODE) |
1380                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1381         i40iw_insert_wqe_hdr(wqe, header);
1382         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "NOP WQE",
1383                         wqe, I40IW_CQP_WQE_SIZE * 8);
1384
1385         if (post_sq)
1386                 i40iw_sc_cqp_post_sq(cqp);
1387         return 0;
1388 }
1389
1390 /**
1391  * i40iw_sc_ceq_init - initialize ceq
1392  * @ceq: ceq sc structure
1393  * @info: ceq initialization info
1394  */
1395 static enum i40iw_status_code i40iw_sc_ceq_init(struct i40iw_sc_ceq *ceq,
1396                                                 struct i40iw_ceq_init_info *info)
1397 {
1398         u32 pble_obj_cnt;
1399
1400         if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) ||
1401             (info->elem_cnt > I40IW_MAX_CEQ_ENTRIES))
1402                 return I40IW_ERR_INVALID_SIZE;
1403
1404         if (info->ceq_id >= I40IW_MAX_CEQID)
1405                 return I40IW_ERR_INVALID_CEQ_ID;
1406
1407         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1408
1409         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1410                 return I40IW_ERR_INVALID_PBLE_INDEX;
1411
1412         ceq->size = sizeof(*ceq);
1413         ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base;
1414         ceq->ceq_id = info->ceq_id;
1415         ceq->dev = info->dev;
1416         ceq->elem_cnt = info->elem_cnt;
1417         ceq->ceq_elem_pa = info->ceqe_pa;
1418         ceq->virtual_map = info->virtual_map;
1419
1420         ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
1421         ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
1422         ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
1423
1424         ceq->tph_en = info->tph_en;
1425         ceq->tph_val = info->tph_val;
1426         ceq->polarity = 1;
1427         I40IW_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
1428         ceq->dev->ceq[info->ceq_id] = ceq;
1429
1430         return 0;
1431 }
1432
1433 /**
1434  * i40iw_sc_ceq_create - create ceq wqe
1435  * @ceq: ceq sc structure
1436  * @scratch: u64 saved to be used during cqp completion
1437  * @post_sq: flag for cqp db to ring
1438  */
1439 static enum i40iw_status_code i40iw_sc_ceq_create(struct i40iw_sc_ceq *ceq,
1440                                                   u64 scratch,
1441                                                   bool post_sq)
1442 {
1443         struct i40iw_sc_cqp *cqp;
1444         u64 *wqe;
1445         u64 header;
1446
1447         cqp = ceq->dev->cqp;
1448         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1449         if (!wqe)
1450                 return I40IW_ERR_RING_FULL;
1451         set_64bit_val(wqe, 16, ceq->elem_cnt);
1452         set_64bit_val(wqe, 32, (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
1453         set_64bit_val(wqe, 48, (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
1454         set_64bit_val(wqe, 56, LS_64(ceq->tph_val, I40IW_CQPSQ_TPHVAL));
1455
1456         header = ceq->ceq_id |
1457                  LS_64(I40IW_CQP_OP_CREATE_CEQ, I40IW_CQPSQ_OPCODE) |
1458                  LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1459                  LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1460                  LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1461                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1462
1463         i40iw_insert_wqe_hdr(wqe, header);
1464
1465         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_CREATE WQE",
1466                         wqe, I40IW_CQP_WQE_SIZE * 8);
1467
1468         if (post_sq)
1469                 i40iw_sc_cqp_post_sq(cqp);
1470         return 0;
1471 }
1472
1473 /**
1474  * i40iw_sc_cceq_create_done - poll for control ceq wqe to complete
1475  * @ceq: ceq sc structure
1476  */
1477 static enum i40iw_status_code i40iw_sc_cceq_create_done(struct i40iw_sc_ceq *ceq)
1478 {
1479         struct i40iw_sc_cqp *cqp;
1480
1481         cqp = ceq->dev->cqp;
1482         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CEQ, NULL);
1483 }
1484
1485 /**
1486  * i40iw_sc_cceq_destroy_done - poll for destroy cceq to complete
1487  * @ceq: ceq sc structure
1488  */
1489 static enum i40iw_status_code i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq *ceq)
1490 {
1491         struct i40iw_sc_cqp *cqp;
1492
1493         cqp = ceq->dev->cqp;
1494         cqp->process_cqp_sds = i40iw_update_sds_noccq;
1495         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_CEQ, NULL);
1496 }
1497
1498 /**
1499  * i40iw_sc_cceq_create - create cceq
1500  * @ceq: ceq sc structure
1501  * @scratch: u64 saved to be used during cqp completion
1502  */
1503 static enum i40iw_status_code i40iw_sc_cceq_create(struct i40iw_sc_ceq *ceq, u64 scratch)
1504 {
1505         enum i40iw_status_code ret_code;
1506
1507         ret_code = i40iw_sc_ceq_create(ceq, scratch, true);
1508         if (!ret_code)
1509                 ret_code = i40iw_sc_cceq_create_done(ceq);
1510         return ret_code;
1511 }
1512
1513 /**
1514  * i40iw_sc_ceq_destroy - destroy ceq
1515  * @ceq: ceq sc structure
1516  * @scratch: u64 saved to be used during cqp completion
1517  * @post_sq: flag for cqp db to ring
1518  */
1519 static enum i40iw_status_code i40iw_sc_ceq_destroy(struct i40iw_sc_ceq *ceq,
1520                                                    u64 scratch,
1521                                                    bool post_sq)
1522 {
1523         struct i40iw_sc_cqp *cqp;
1524         u64 *wqe;
1525         u64 header;
1526
1527         cqp = ceq->dev->cqp;
1528         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1529         if (!wqe)
1530                 return I40IW_ERR_RING_FULL;
1531         set_64bit_val(wqe, 16, ceq->elem_cnt);
1532         set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
1533         header = ceq->ceq_id |
1534                  LS_64(I40IW_CQP_OP_DESTROY_CEQ, I40IW_CQPSQ_OPCODE) |
1535                  LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1536                  LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1537                  LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1538                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1539         i40iw_insert_wqe_hdr(wqe, header);
1540         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_DESTROY WQE",
1541                         wqe, I40IW_CQP_WQE_SIZE * 8);
1542
1543         if (post_sq)
1544                 i40iw_sc_cqp_post_sq(cqp);
1545         return 0;
1546 }
1547
1548 /**
1549  * i40iw_sc_process_ceq - process ceq
1550  * @dev: sc device struct
1551  * @ceq: ceq sc structure
1552  */
1553 static void *i40iw_sc_process_ceq(struct i40iw_sc_dev *dev, struct i40iw_sc_ceq *ceq)
1554 {
1555         u64 temp;
1556         u64 *ceqe;
1557         struct i40iw_sc_cq *cq = NULL;
1558         u8 polarity;
1559
1560         ceqe = (u64 *)I40IW_GET_CURRENT_CEQ_ELEMENT(ceq);
1561         get_64bit_val(ceqe, 0, &temp);
1562         polarity = (u8)RS_64(temp, I40IW_CEQE_VALID);
1563         if (polarity != ceq->polarity)
1564                 return cq;
1565
1566         cq = (struct i40iw_sc_cq *)(unsigned long)LS_64_1(temp, 1);
1567
1568         I40IW_RING_MOVE_TAIL(ceq->ceq_ring);
1569         if (I40IW_RING_GETCURRENT_TAIL(ceq->ceq_ring) == 0)
1570                 ceq->polarity ^= 1;
1571
1572         if (dev->is_pf)
1573                 i40iw_wr32(dev->hw, I40E_PFPE_CQACK, cq->cq_uk.cq_id);
1574         else
1575                 i40iw_wr32(dev->hw, I40E_VFPE_CQACK1, cq->cq_uk.cq_id);
1576
1577         return cq;
1578 }
1579
1580 /**
1581  * i40iw_sc_aeq_init - initialize aeq
1582  * @aeq: aeq structure ptr
1583  * @info: aeq initialization info
1584  */
1585 static enum i40iw_status_code i40iw_sc_aeq_init(struct i40iw_sc_aeq *aeq,
1586                                                 struct i40iw_aeq_init_info *info)
1587 {
1588         u32 pble_obj_cnt;
1589
1590         if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) ||
1591             (info->elem_cnt > I40IW_MAX_AEQ_ENTRIES))
1592                 return I40IW_ERR_INVALID_SIZE;
1593         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1594
1595         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1596                 return I40IW_ERR_INVALID_PBLE_INDEX;
1597
1598         aeq->size = sizeof(*aeq);
1599         aeq->polarity = 1;
1600         aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base;
1601         aeq->dev = info->dev;
1602         aeq->elem_cnt = info->elem_cnt;
1603
1604         aeq->aeq_elem_pa = info->aeq_elem_pa;
1605         I40IW_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
1606         info->dev->aeq = aeq;
1607
1608         aeq->virtual_map = info->virtual_map;
1609         aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
1610         aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
1611         aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
1612         info->dev->aeq = aeq;
1613         return 0;
1614 }
1615
1616 /**
1617  * i40iw_sc_aeq_create - create aeq
1618  * @aeq: aeq structure ptr
1619  * @scratch: u64 saved to be used during cqp completion
1620  * @post_sq: flag for cqp db to ring
1621  */
1622 static enum i40iw_status_code i40iw_sc_aeq_create(struct i40iw_sc_aeq *aeq,
1623                                                   u64 scratch,
1624                                                   bool post_sq)
1625 {
1626         u64 *wqe;
1627         struct i40iw_sc_cqp *cqp;
1628         u64 header;
1629
1630         cqp = aeq->dev->cqp;
1631         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1632         if (!wqe)
1633                 return I40IW_ERR_RING_FULL;
1634         set_64bit_val(wqe, 16, aeq->elem_cnt);
1635         set_64bit_val(wqe, 32,
1636                       (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
1637         set_64bit_val(wqe, 48,
1638                       (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
1639
1640         header = LS_64(I40IW_CQP_OP_CREATE_AEQ, I40IW_CQPSQ_OPCODE) |
1641                  LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1642                  LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1643                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1644
1645         i40iw_insert_wqe_hdr(wqe, header);
1646         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_CREATE WQE",
1647                         wqe, I40IW_CQP_WQE_SIZE * 8);
1648         if (post_sq)
1649                 i40iw_sc_cqp_post_sq(cqp);
1650         return 0;
1651 }
1652
1653 /**
1654  * i40iw_sc_aeq_destroy - destroy aeq during close
1655  * @aeq: aeq structure ptr
1656  * @scratch: u64 saved to be used during cqp completion
1657  * @post_sq: flag for cqp db to ring
1658  */
1659 static enum i40iw_status_code i40iw_sc_aeq_destroy(struct i40iw_sc_aeq *aeq,
1660                                                    u64 scratch,
1661                                                    bool post_sq)
1662 {
1663         u64 *wqe;
1664         struct i40iw_sc_cqp *cqp;
1665         u64 header;
1666
1667         cqp = aeq->dev->cqp;
1668         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1669         if (!wqe)
1670                 return I40IW_ERR_RING_FULL;
1671         set_64bit_val(wqe, 16, aeq->elem_cnt);
1672         set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
1673         header = LS_64(I40IW_CQP_OP_DESTROY_AEQ, I40IW_CQPSQ_OPCODE) |
1674                  LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1675                  LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1676                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1677         i40iw_insert_wqe_hdr(wqe, header);
1678
1679         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_DESTROY WQE",
1680                         wqe, I40IW_CQP_WQE_SIZE * 8);
1681         if (post_sq)
1682                 i40iw_sc_cqp_post_sq(cqp);
1683         return 0;
1684 }
1685
1686 /**
1687  * i40iw_sc_get_next_aeqe - get next aeq entry
1688  * @aeq: aeq structure ptr
1689  * @info: aeqe info to be returned
1690  */
1691 static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
1692                                                      struct i40iw_aeqe_info *info)
1693 {
1694         u64 temp, compl_ctx;
1695         u64 *aeqe;
1696         u16 wqe_idx;
1697         u8 ae_src;
1698         u8 polarity;
1699
1700         aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq);
1701         get_64bit_val(aeqe, 0, &compl_ctx);
1702         get_64bit_val(aeqe, 8, &temp);
1703         polarity = (u8)RS_64(temp, I40IW_AEQE_VALID);
1704
1705         if (aeq->polarity != polarity)
1706                 return I40IW_ERR_QUEUE_EMPTY;
1707
1708         i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16);
1709
1710         ae_src = (u8)RS_64(temp, I40IW_AEQE_AESRC);
1711         wqe_idx = (u16)RS_64(temp, I40IW_AEQE_WQDESCIDX);
1712         info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID);
1713         info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE);
1714         info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE);
1715         info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
1716         info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
1717         info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
1718         switch (ae_src) {
1719         case I40IW_AE_SOURCE_RQ:
1720         case I40IW_AE_SOURCE_RQ_0011:
1721                 info->qp = true;
1722                 info->wqe_idx = wqe_idx;
1723                 info->compl_ctx = compl_ctx;
1724                 break;
1725         case I40IW_AE_SOURCE_CQ:
1726         case I40IW_AE_SOURCE_CQ_0110:
1727         case I40IW_AE_SOURCE_CQ_1010:
1728         case I40IW_AE_SOURCE_CQ_1110:
1729                 info->cq = true;
1730                 info->compl_ctx = LS_64_1(compl_ctx, 1);
1731                 break;
1732         case I40IW_AE_SOURCE_SQ:
1733         case I40IW_AE_SOURCE_SQ_0111:
1734                 info->qp = true;
1735                 info->sq = true;
1736                 info->wqe_idx = wqe_idx;
1737                 info->compl_ctx = compl_ctx;
1738                 break;
1739         case I40IW_AE_SOURCE_IN_RR_WR:
1740         case I40IW_AE_SOURCE_IN_RR_WR_1011:
1741                 info->qp = true;
1742                 info->compl_ctx = compl_ctx;
1743                 info->in_rdrsp_wr = true;
1744                 break;
1745         case I40IW_AE_SOURCE_OUT_RR:
1746         case I40IW_AE_SOURCE_OUT_RR_1111:
1747                 info->qp = true;
1748                 info->compl_ctx = compl_ctx;
1749                 info->out_rdrsp = true;
1750                 break;
1751         default:
1752                 break;
1753         }
1754         I40IW_RING_MOVE_TAIL(aeq->aeq_ring);
1755         if (I40IW_RING_GETCURRENT_TAIL(aeq->aeq_ring) == 0)
1756                 aeq->polarity ^= 1;
1757         return 0;
1758 }
1759
1760 /**
1761  * i40iw_sc_repost_aeq_entries - repost completed aeq entries
1762  * @dev: sc device struct
1763  * @count: allocate count
1764  */
1765 static enum i40iw_status_code i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev *dev,
1766                                                           u32 count)
1767 {
1768         if (count > I40IW_MAX_AEQ_ALLOCATE_COUNT)
1769                 return I40IW_ERR_INVALID_SIZE;
1770
1771         if (dev->is_pf)
1772                 i40iw_wr32(dev->hw, I40E_PFPE_AEQALLOC, count);
1773         else
1774                 i40iw_wr32(dev->hw, I40E_VFPE_AEQALLOC1, count);
1775
1776         return 0;
1777 }
1778
1779 /**
1780  * i40iw_sc_aeq_create_done - create aeq
1781  * @aeq: aeq structure ptr
1782  */
1783 static enum i40iw_status_code i40iw_sc_aeq_create_done(struct i40iw_sc_aeq *aeq)
1784 {
1785         struct i40iw_sc_cqp *cqp;
1786
1787         cqp = aeq->dev->cqp;
1788         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_AEQ, NULL);
1789 }
1790
1791 /**
1792  * i40iw_sc_aeq_destroy_done - destroy of aeq during close
1793  * @aeq: aeq structure ptr
1794  */
1795 static enum i40iw_status_code i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq *aeq)
1796 {
1797         struct i40iw_sc_cqp *cqp;
1798
1799         cqp = aeq->dev->cqp;
1800         return  i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_AEQ, NULL);
1801 }
1802
1803 /**
1804  * i40iw_sc_ccq_init - initialize control cq
1805  * @cq: sc's cq ctruct
1806  * @info: info for control cq initialization
1807  */
1808 static enum i40iw_status_code i40iw_sc_ccq_init(struct i40iw_sc_cq *cq,
1809                                                 struct i40iw_ccq_init_info *info)
1810 {
1811         u32 pble_obj_cnt;
1812
1813         if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE)
1814                 return I40IW_ERR_INVALID_SIZE;
1815
1816         if (info->ceq_id > I40IW_MAX_CEQID)
1817                 return I40IW_ERR_INVALID_CEQ_ID;
1818
1819         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1820
1821         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1822                 return I40IW_ERR_INVALID_PBLE_INDEX;
1823
1824         cq->cq_pa = info->cq_pa;
1825         cq->cq_uk.cq_base = info->cq_base;
1826         cq->shadow_area_pa = info->shadow_area_pa;
1827         cq->cq_uk.shadow_area = info->shadow_area;
1828         cq->shadow_read_threshold = info->shadow_read_threshold;
1829         cq->dev = info->dev;
1830         cq->ceq_id = info->ceq_id;
1831         cq->cq_uk.cq_size = info->num_elem;
1832         cq->cq_type = I40IW_CQ_TYPE_CQP;
1833         cq->ceqe_mask = info->ceqe_mask;
1834         I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
1835
1836         cq->cq_uk.cq_id = 0;    /* control cq is id 0 always */
1837         cq->ceq_id_valid = info->ceq_id_valid;
1838         cq->tph_en = info->tph_en;
1839         cq->tph_val = info->tph_val;
1840         cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
1841
1842         cq->pbl_list = info->pbl_list;
1843         cq->virtual_map = info->virtual_map;
1844         cq->pbl_chunk_size = info->pbl_chunk_size;
1845         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
1846         cq->cq_uk.polarity = true;
1847
1848         /* following are only for iw cqs so initialize them to zero */
1849         cq->cq_uk.cqe_alloc_reg = NULL;
1850         info->dev->ccq = cq;
1851         return 0;
1852 }
1853
1854 /**
1855  * i40iw_sc_ccq_create_done - poll cqp for ccq create
1856  * @ccq: ccq sc struct
1857  */
1858 static enum i40iw_status_code i40iw_sc_ccq_create_done(struct i40iw_sc_cq *ccq)
1859 {
1860         struct i40iw_sc_cqp *cqp;
1861
1862         cqp = ccq->dev->cqp;
1863         return  i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CQ, NULL);
1864 }
1865
1866 /**
1867  * i40iw_sc_ccq_create - create control cq
1868  * @ccq: ccq sc struct
1869  * @scratch: u64 saved to be used during cqp completion
1870  * @check_overflow: overlow flag for ccq
1871  * @post_sq: flag for cqp db to ring
1872  */
1873 static enum i40iw_status_code i40iw_sc_ccq_create(struct i40iw_sc_cq *ccq,
1874                                                   u64 scratch,
1875                                                   bool check_overflow,
1876                                                   bool post_sq)
1877 {
1878         u64 *wqe;
1879         struct i40iw_sc_cqp *cqp;
1880         u64 header;
1881         enum i40iw_status_code ret_code;
1882
1883         cqp = ccq->dev->cqp;
1884         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1885         if (!wqe)
1886                 return I40IW_ERR_RING_FULL;
1887         set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
1888         set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
1889         set_64bit_val(wqe, 16,
1890                       LS_64(ccq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
1891         set_64bit_val(wqe, 32, (ccq->virtual_map ? 0 : ccq->cq_pa));
1892         set_64bit_val(wqe, 40, ccq->shadow_area_pa);
1893         set_64bit_val(wqe, 48,
1894                       (ccq->virtual_map ? ccq->first_pm_pbl_idx : 0));
1895         set_64bit_val(wqe, 56,
1896                       LS_64(ccq->tph_val, I40IW_CQPSQ_TPHVAL));
1897
1898         header = ccq->cq_uk.cq_id |
1899                  LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
1900                  LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
1901                  LS_64(ccq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
1902                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
1903                  LS_64(ccq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
1904                  LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
1905                  LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
1906                  LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
1907                  LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
1908                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1909
1910         i40iw_insert_wqe_hdr(wqe, header);
1911
1912         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_CREATE WQE",
1913                         wqe, I40IW_CQP_WQE_SIZE * 8);
1914
1915         if (post_sq) {
1916                 i40iw_sc_cqp_post_sq(cqp);
1917                 ret_code = i40iw_sc_ccq_create_done(ccq);
1918                 if (ret_code)
1919                         return ret_code;
1920         }
1921         cqp->process_cqp_sds = i40iw_cqp_sds_cmd;
1922
1923         return 0;
1924 }
1925
1926 /**
1927  * i40iw_sc_ccq_destroy - destroy ccq during close
1928  * @ccq: ccq sc struct
1929  * @scratch: u64 saved to be used during cqp completion
1930  * @post_sq: flag for cqp db to ring
1931  */
1932 static enum i40iw_status_code i40iw_sc_ccq_destroy(struct i40iw_sc_cq *ccq,
1933                                                    u64 scratch,
1934                                                    bool post_sq)
1935 {
1936         struct i40iw_sc_cqp *cqp;
1937         u64 *wqe;
1938         u64 header;
1939         enum i40iw_status_code ret_code = 0;
1940         u32 tail, val, error;
1941
1942         cqp = ccq->dev->cqp;
1943         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1944         if (!wqe)
1945                 return I40IW_ERR_RING_FULL;
1946         set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
1947         set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
1948         set_64bit_val(wqe, 40, ccq->shadow_area_pa);
1949
1950         header = ccq->cq_uk.cq_id |
1951                  LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
1952                  LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
1953                  LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
1954                  LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
1955                  LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
1956                  LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
1957                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1958
1959         i40iw_insert_wqe_hdr(wqe, header);
1960
1961         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_DESTROY WQE",
1962                         wqe, I40IW_CQP_WQE_SIZE * 8);
1963
1964         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
1965         if (error)
1966                 return I40IW_ERR_CQP_COMPL_ERROR;
1967
1968         if (post_sq) {
1969                 i40iw_sc_cqp_post_sq(cqp);
1970                 ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
1971         }
1972
1973         cqp->process_cqp_sds = i40iw_update_sds_noccq;
1974
1975         return ret_code;
1976 }
1977
1978 /**
1979  * i40iw_sc_cq_init - initialize completion q
1980  * @cq: cq struct
1981  * @info: cq initialization info
1982  */
1983 static enum i40iw_status_code i40iw_sc_cq_init(struct i40iw_sc_cq *cq,
1984                                                struct i40iw_cq_init_info *info)
1985 {
1986         u32 __iomem *cqe_alloc_reg = NULL;
1987         enum i40iw_status_code ret_code;
1988         u32 pble_obj_cnt;
1989         u32 arm_offset;
1990
1991         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1992
1993         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1994                 return I40IW_ERR_INVALID_PBLE_INDEX;
1995
1996         cq->cq_pa = info->cq_base_pa;
1997         cq->dev = info->dev;
1998         cq->ceq_id = info->ceq_id;
1999         arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1;
2000         if (i40iw_get_hw_addr(cq->dev))
2001                 cqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(cq->dev) +
2002                                               arm_offset);
2003         info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg;
2004         ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info);
2005         if (ret_code)
2006                 return ret_code;
2007         cq->virtual_map = info->virtual_map;
2008         cq->pbl_chunk_size = info->pbl_chunk_size;
2009         cq->ceqe_mask = info->ceqe_mask;
2010         cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP;
2011
2012         cq->shadow_area_pa = info->shadow_area_pa;
2013         cq->shadow_read_threshold = info->shadow_read_threshold;
2014
2015         cq->ceq_id_valid = info->ceq_id_valid;
2016         cq->tph_en = info->tph_en;
2017         cq->tph_val = info->tph_val;
2018
2019         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2020
2021         return 0;
2022 }
2023
2024 /**
2025  * i40iw_sc_cq_create - create completion q
2026  * @cq: cq struct
2027  * @scratch: u64 saved to be used during cqp completion
2028  * @check_overflow: flag for overflow check
2029  * @post_sq: flag for cqp db to ring
2030  */
2031 static enum i40iw_status_code i40iw_sc_cq_create(struct i40iw_sc_cq *cq,
2032                                                  u64 scratch,
2033                                                  bool check_overflow,
2034                                                  bool post_sq)
2035 {
2036         u64 *wqe;
2037         struct i40iw_sc_cqp *cqp;
2038         u64 header;
2039
2040         if (cq->cq_uk.cq_id > I40IW_MAX_CQID)
2041                 return I40IW_ERR_INVALID_CQ_ID;
2042
2043         if (cq->ceq_id > I40IW_MAX_CEQID)
2044                 return I40IW_ERR_INVALID_CEQ_ID;
2045
2046         cqp = cq->dev->cqp;
2047         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2048         if (!wqe)
2049                 return I40IW_ERR_RING_FULL;
2050
2051         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2052         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2053         set_64bit_val(wqe,
2054                       16,
2055                       LS_64(cq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2056
2057         set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2058
2059         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2060         set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2061         set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2062
2063         header = cq->cq_uk.cq_id |
2064                  LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2065                  LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
2066                  LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2067                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2068                  LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2069                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2070                  LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2071                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2072                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2073                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2074
2075         i40iw_insert_wqe_hdr(wqe, header);
2076
2077         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_CREATE WQE",
2078                         wqe, I40IW_CQP_WQE_SIZE * 8);
2079
2080         if (post_sq)
2081                 i40iw_sc_cqp_post_sq(cqp);
2082         return 0;
2083 }
2084
2085 /**
2086  * i40iw_sc_cq_destroy - destroy completion q
2087  * @cq: cq struct
2088  * @scratch: u64 saved to be used during cqp completion
2089  * @post_sq: flag for cqp db to ring
2090  */
2091 static enum i40iw_status_code i40iw_sc_cq_destroy(struct i40iw_sc_cq *cq,
2092                                                   u64 scratch,
2093                                                   bool post_sq)
2094 {
2095         struct i40iw_sc_cqp *cqp;
2096         u64 *wqe;
2097         u64 header;
2098
2099         cqp = cq->dev->cqp;
2100         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2101         if (!wqe)
2102                 return I40IW_ERR_RING_FULL;
2103         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2104         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2105         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2106         set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2107
2108         header = cq->cq_uk.cq_id |
2109                  LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2110                  LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
2111                  LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2112                  LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2113                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2114                  LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2115                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2116                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2117                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2118
2119         i40iw_insert_wqe_hdr(wqe, header);
2120
2121         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_DESTROY WQE",
2122                         wqe, I40IW_CQP_WQE_SIZE * 8);
2123
2124         if (post_sq)
2125                 i40iw_sc_cqp_post_sq(cqp);
2126         return 0;
2127 }
2128
2129 /**
2130  * i40iw_sc_cq_modify - modify a Completion Queue
2131  * @cq: cq struct
2132  * @info: modification info struct
2133  * @scratch:
2134  * @post_sq: flag to post to sq
2135  */
2136 static enum i40iw_status_code i40iw_sc_cq_modify(struct i40iw_sc_cq *cq,
2137                                                  struct i40iw_modify_cq_info *info,
2138                                                  u64 scratch,
2139                                                  bool post_sq)
2140 {
2141         struct i40iw_sc_cqp *cqp;
2142         u64 *wqe;
2143         u64 header;
2144         u32 cq_size, ceq_id, first_pm_pbl_idx;
2145         u8 pbl_chunk_size;
2146         bool virtual_map, ceq_id_valid, check_overflow;
2147         u32 pble_obj_cnt;
2148
2149         if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID))
2150                 return I40IW_ERR_INVALID_CEQ_ID;
2151
2152         pble_obj_cnt = cq->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2153
2154         if (info->cq_resize && info->virtual_map &&
2155             (info->first_pm_pbl_idx >= pble_obj_cnt))
2156                 return I40IW_ERR_INVALID_PBLE_INDEX;
2157
2158         cqp = cq->dev->cqp;
2159         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2160         if (!wqe)
2161                 return I40IW_ERR_RING_FULL;
2162
2163         cq->pbl_list = info->pbl_list;
2164         cq->cq_pa = info->cq_pa;
2165         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2166
2167         cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size;
2168         if (info->ceq_change) {
2169                 ceq_id_valid = true;
2170                 ceq_id = info->ceq_id;
2171         } else {
2172                 ceq_id_valid = cq->ceq_id_valid;
2173                 ceq_id = ceq_id_valid ? cq->ceq_id : 0;
2174         }
2175         virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map;
2176         first_pm_pbl_idx = (info->cq_resize ?
2177                             (info->virtual_map ? info->first_pm_pbl_idx : 0) :
2178                             (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2179         pbl_chunk_size = (info->cq_resize ?
2180                           (info->virtual_map ? info->pbl_chunk_size : 0) :
2181                           (cq->virtual_map ? cq->pbl_chunk_size : 0));
2182         check_overflow = info->check_overflow_change ? info->check_overflow :
2183                          cq->check_overflow;
2184         cq->cq_uk.cq_size = cq_size;
2185         cq->ceq_id_valid = ceq_id_valid;
2186         cq->ceq_id = ceq_id;
2187         cq->virtual_map = virtual_map;
2188         cq->first_pm_pbl_idx = first_pm_pbl_idx;
2189         cq->pbl_chunk_size = pbl_chunk_size;
2190         cq->check_overflow = check_overflow;
2191
2192         set_64bit_val(wqe, 0, cq_size);
2193         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2194         set_64bit_val(wqe, 16,
2195                       LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2196         set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2197         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2198         set_64bit_val(wqe, 48, (cq->virtual_map ? first_pm_pbl_idx : 0));
2199         set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2200
2201         header = cq->cq_uk.cq_id |
2202                  LS_64(ceq_id, I40IW_CQPSQ_CQ_CEQID) |
2203                  LS_64(I40IW_CQP_OP_MODIFY_CQ, I40IW_CQPSQ_OPCODE) |
2204                  LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) |
2205                  LS_64(pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2206                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2207                  LS_64(virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2208                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2209                  LS_64(ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2210                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2211                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2212                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2213
2214         i40iw_insert_wqe_hdr(wqe, header);
2215
2216         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_MODIFY WQE",
2217                         wqe, I40IW_CQP_WQE_SIZE * 8);
2218
2219         if (post_sq)
2220                 i40iw_sc_cqp_post_sq(cqp);
2221         return 0;
2222 }
2223
2224 /**
2225  * i40iw_sc_qp_init - initialize qp
2226  * @qp: sc qp
2227  * @info: initialization qp info
2228  */
2229 static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2230                                                struct i40iw_qp_init_info *info)
2231 {
2232         u32 __iomem *wqe_alloc_reg = NULL;
2233         enum i40iw_status_code ret_code;
2234         u32 pble_obj_cnt;
2235         u8 wqe_size;
2236         u32 offset;
2237
2238         qp->dev = info->pd->dev;
2239         qp->vsi = info->vsi;
2240         qp->sq_pa = info->sq_pa;
2241         qp->rq_pa = info->rq_pa;
2242         qp->hw_host_ctx_pa = info->host_ctx_pa;
2243         qp->q2_pa = info->q2_pa;
2244         qp->shadow_area_pa = info->shadow_area_pa;
2245
2246         qp->q2_buf = info->q2;
2247         qp->pd = info->pd;
2248         qp->hw_host_ctx = info->host_ctx;
2249         offset = (qp->pd->dev->is_pf) ? I40E_PFPE_WQEALLOC : I40E_VFPE_WQEALLOC1;
2250         if (i40iw_get_hw_addr(qp->pd->dev))
2251                 wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
2252                                               offset);
2253
2254         info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg;
2255         info->qp_uk_init_info.abi_ver = qp->pd->abi_ver;
2256         ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info);
2257         if (ret_code)
2258                 return ret_code;
2259         qp->virtual_map = info->virtual_map;
2260
2261         pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2262
2263         if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) ||
2264             (info->virtual_map && (info->rq_pa >= pble_obj_cnt)))
2265                 return I40IW_ERR_INVALID_PBLE_INDEX;
2266
2267         qp->llp_stream_handle = (void *)(-1);
2268         qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP;
2269
2270         qp->hw_sq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
2271                                                     false);
2272         i40iw_debug(qp->dev, I40IW_DEBUG_WQE, "%s: hw_sq_size[%04d] sq_ring.size[%04d]\n",
2273                     __func__, qp->hw_sq_size, qp->qp_uk.sq_ring.size);
2274
2275         switch (qp->pd->abi_ver) {
2276         case 4:
2277                 ret_code = i40iw_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
2278                                                        &wqe_size);
2279                 if (ret_code)
2280                         return ret_code;
2281                 break;
2282         case 5: /* fallthrough until next ABI version */
2283         default:
2284                 if (qp->qp_uk.max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
2285                         return I40IW_ERR_INVALID_FRAG_COUNT;
2286                 wqe_size = I40IW_MAX_WQE_SIZE_RQ;
2287                 break;
2288         }
2289         qp->hw_rq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.rq_size *
2290                                 (wqe_size / I40IW_QP_WQE_MIN_SIZE), false);
2291         i40iw_debug(qp->dev, I40IW_DEBUG_WQE,
2292                     "%s: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
2293                     __func__, qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
2294         qp->sq_tph_val = info->sq_tph_val;
2295         qp->rq_tph_val = info->rq_tph_val;
2296         qp->sq_tph_en = info->sq_tph_en;
2297         qp->rq_tph_en = info->rq_tph_en;
2298         qp->rcv_tph_en = info->rcv_tph_en;
2299         qp->xmit_tph_en = info->xmit_tph_en;
2300         qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
2301         qp->exception_lan_queue = qp->pd->dev->exception_lan_queue;
2302
2303         return 0;
2304 }
2305
2306 /**
2307  * i40iw_sc_qp_create - create qp
2308  * @qp: sc qp
2309  * @info: qp create info
2310  * @scratch: u64 saved to be used during cqp completion
2311  * @post_sq: flag for cqp db to ring
2312  */
2313 static enum i40iw_status_code i40iw_sc_qp_create(
2314                                 struct i40iw_sc_qp *qp,
2315                                 struct i40iw_create_qp_info *info,
2316                                 u64 scratch,
2317                                 bool post_sq)
2318 {
2319         struct i40iw_sc_cqp *cqp;
2320         u64 *wqe;
2321         u64 header;
2322
2323         if ((qp->qp_uk.qp_id < I40IW_MIN_IW_QP_ID) ||
2324             (qp->qp_uk.qp_id > I40IW_MAX_IW_QP_ID))
2325                 return I40IW_ERR_INVALID_QP_ID;
2326
2327         cqp = qp->pd->dev->cqp;
2328         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2329         if (!wqe)
2330                 return I40IW_ERR_RING_FULL;
2331
2332         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2333
2334         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2335
2336         header = qp->qp_uk.qp_id |
2337                  LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
2338                  LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) |
2339                  LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2340                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2341                  LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2342                  LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2343                  LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2344                  LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2345                  LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2346                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2347
2348         i40iw_insert_wqe_hdr(wqe, header);
2349         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_CREATE WQE",
2350                         wqe, I40IW_CQP_WQE_SIZE * 8);
2351
2352         if (post_sq)
2353                 i40iw_sc_cqp_post_sq(cqp);
2354         return 0;
2355 }
2356
2357 /**
2358  * i40iw_sc_qp_modify - modify qp cqp wqe
2359  * @qp: sc qp
2360  * @info: modify qp info
2361  * @scratch: u64 saved to be used during cqp completion
2362  * @post_sq: flag for cqp db to ring
2363  */
2364 static enum i40iw_status_code i40iw_sc_qp_modify(
2365                                 struct i40iw_sc_qp *qp,
2366                                 struct i40iw_modify_qp_info *info,
2367                                 u64 scratch,
2368                                 bool post_sq)
2369 {
2370         u64 *wqe;
2371         struct i40iw_sc_cqp *cqp;
2372         u64 header;
2373         u8 term_actions = 0;
2374         u8 term_len = 0;
2375
2376         cqp = qp->pd->dev->cqp;
2377         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2378         if (!wqe)
2379                 return I40IW_ERR_RING_FULL;
2380         if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) {
2381                 if (info->dont_send_fin)
2382                         term_actions += I40IWQP_TERM_SEND_TERM_ONLY;
2383                 if (info->dont_send_term)
2384                         term_actions += I40IWQP_TERM_SEND_FIN_ONLY;
2385                 if ((term_actions == I40IWQP_TERM_SEND_TERM_AND_FIN) ||
2386                     (term_actions == I40IWQP_TERM_SEND_TERM_ONLY))
2387                         term_len = info->termlen;
2388         }
2389
2390         set_64bit_val(wqe,
2391                       8,
2392                       LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN));
2393
2394         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2395         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2396
2397         header = qp->qp_uk.qp_id |
2398                  LS_64(I40IW_CQP_OP_MODIFY_QP, I40IW_CQPSQ_OPCODE) |
2399                  LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) |
2400                  LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2401                  LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) |
2402                  LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2403                  LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2404                  LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
2405                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2406                  LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2407                  LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2408                  LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |
2409                  LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
2410                  LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2411                  LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2412                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2413
2414         i40iw_insert_wqe_hdr(wqe, header);
2415
2416         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_MODIFY WQE",
2417                         wqe, I40IW_CQP_WQE_SIZE * 8);
2418
2419         if (post_sq)
2420                 i40iw_sc_cqp_post_sq(cqp);
2421         return 0;
2422 }
2423
2424 /**
2425  * i40iw_sc_qp_destroy - cqp destroy qp
2426  * @qp: sc qp
2427  * @scratch: u64 saved to be used during cqp completion
2428  * @remove_hash_idx: flag if to remove hash idx
2429  * @ignore_mw_bnd: memory window bind flag
2430  * @post_sq: flag for cqp db to ring
2431  */
2432 static enum i40iw_status_code i40iw_sc_qp_destroy(
2433                                         struct i40iw_sc_qp *qp,
2434                                         u64 scratch,
2435                                         bool remove_hash_idx,
2436                                         bool ignore_mw_bnd,
2437                                         bool post_sq)
2438 {
2439         u64 *wqe;
2440         struct i40iw_sc_cqp *cqp;
2441         u64 header;
2442
2443         i40iw_qp_rem_qos(qp);
2444         cqp = qp->pd->dev->cqp;
2445         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2446         if (!wqe)
2447                 return I40IW_ERR_RING_FULL;
2448         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2449         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2450
2451         header = qp->qp_uk.qp_id |
2452                  LS_64(I40IW_CQP_OP_DESTROY_QP, I40IW_CQPSQ_OPCODE) |
2453                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2454                  LS_64(ignore_mw_bnd, I40IW_CQPSQ_QP_IGNOREMWBOUND) |
2455                  LS_64(remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2456                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2457
2458         i40iw_insert_wqe_hdr(wqe, header);
2459         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_DESTROY WQE",
2460                         wqe, I40IW_CQP_WQE_SIZE * 8);
2461
2462         if (post_sq)
2463                 i40iw_sc_cqp_post_sq(cqp);
2464         return 0;
2465 }
2466
2467 /**
2468  * i40iw_sc_qp_flush_wqes - flush qp's wqe
2469  * @qp: sc qp
2470  * @info: dlush information
2471  * @scratch: u64 saved to be used during cqp completion
2472  * @post_sq: flag for cqp db to ring
2473  */
2474 static enum i40iw_status_code i40iw_sc_qp_flush_wqes(
2475                                 struct i40iw_sc_qp *qp,
2476                                 struct i40iw_qp_flush_info *info,
2477                                 u64 scratch,
2478                                 bool post_sq)
2479 {
2480         u64 temp = 0;
2481         u64 *wqe;
2482         struct i40iw_sc_cqp *cqp;
2483         u64 header;
2484         bool flush_sq = false, flush_rq = false;
2485
2486         if (info->rq && !qp->flush_rq)
2487                 flush_rq = true;
2488
2489         if (info->sq && !qp->flush_sq)
2490                 flush_sq = true;
2491
2492         qp->flush_sq |= flush_sq;
2493         qp->flush_rq |= flush_rq;
2494         if (!flush_sq && !flush_rq) {
2495                 if (info->ae_code != I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR)
2496                         return 0;
2497         }
2498
2499         cqp = qp->pd->dev->cqp;
2500         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2501         if (!wqe)
2502                 return I40IW_ERR_RING_FULL;
2503         if (info->userflushcode) {
2504                 if (flush_rq) {
2505                         temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) |
2506                                 LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR);
2507                 }
2508                 if (flush_sq) {
2509                         temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) |
2510                                 LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR);
2511                 }
2512         }
2513         set_64bit_val(wqe, 16, temp);
2514
2515         temp = (info->generate_ae) ?
2516                 info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0;
2517
2518         set_64bit_val(wqe, 8, temp);
2519
2520         header = qp->qp_uk.qp_id |
2521                  LS_64(I40IW_CQP_OP_FLUSH_WQES, I40IW_CQPSQ_OPCODE) |
2522                  LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) |
2523                  LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) |
2524                  LS_64(flush_sq, I40IW_CQPSQ_FWQE_FLUSHSQ) |
2525                  LS_64(flush_rq, I40IW_CQPSQ_FWQE_FLUSHRQ) |
2526                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2527
2528         i40iw_insert_wqe_hdr(wqe, header);
2529
2530         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_FLUSH WQE",
2531                         wqe, I40IW_CQP_WQE_SIZE * 8);
2532
2533         if (post_sq)
2534                 i40iw_sc_cqp_post_sq(cqp);
2535         return 0;
2536 }
2537
2538 /**
2539  * i40iw_sc_qp_upload_context - upload qp's context
2540  * @dev: sc device struct
2541  * @info: upload context info ptr for return
2542  * @scratch: u64 saved to be used during cqp completion
2543  * @post_sq: flag for cqp db to ring
2544  */
2545 static enum i40iw_status_code i40iw_sc_qp_upload_context(
2546                                         struct i40iw_sc_dev *dev,
2547                                         struct i40iw_upload_context_info *info,
2548                                         u64 scratch,
2549                                         bool post_sq)
2550 {
2551         u64 *wqe;
2552         struct i40iw_sc_cqp *cqp;
2553         u64 header;
2554
2555         cqp = dev->cqp;
2556         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2557         if (!wqe)
2558                 return I40IW_ERR_RING_FULL;
2559         set_64bit_val(wqe, 16, info->buf_pa);
2560
2561         header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) |
2562                  LS_64(I40IW_CQP_OP_UPLOAD_CONTEXT, I40IW_CQPSQ_OPCODE) |
2563                  LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) |
2564                  LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) |
2565                  LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) |
2566                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2567
2568         i40iw_insert_wqe_hdr(wqe, header);
2569
2570         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QP_UPLOAD_CTX WQE",
2571                         wqe, I40IW_CQP_WQE_SIZE * 8);
2572
2573         if (post_sq)
2574                 i40iw_sc_cqp_post_sq(cqp);
2575         return 0;
2576 }
2577
2578 /**
2579  * i40iw_sc_qp_setctx - set qp's context
2580  * @qp: sc qp
2581  * @qp_ctx: context ptr
2582  * @info: ctx info
2583  */
2584 static enum i40iw_status_code i40iw_sc_qp_setctx(
2585                                 struct i40iw_sc_qp *qp,
2586                                 u64 *qp_ctx,
2587                                 struct i40iw_qp_host_ctx_info *info)
2588 {
2589         struct i40iwarp_offload_info *iw;
2590         struct i40iw_tcp_offload_info *tcp;
2591         struct i40iw_sc_vsi *vsi;
2592         struct i40iw_sc_dev *dev;
2593         u64 qw0, qw3, qw7 = 0;
2594
2595         iw = info->iwarp_info;
2596         tcp = info->tcp_info;
2597         vsi = qp->vsi;
2598         dev = qp->dev;
2599         if (info->add_to_qoslist) {
2600                 qp->user_pri = info->user_pri;
2601                 i40iw_qp_add_qos(qp);
2602                 i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n",
2603                             __func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle);
2604         }
2605         qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) |
2606               LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
2607               LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) |
2608               LS_64(qp->xmit_tph_en, I40IWQPC_XMITTPHEN) |
2609               LS_64(qp->rq_tph_en, I40IWQPC_RQTPHEN) |
2610               LS_64(qp->sq_tph_en, I40IWQPC_SQTPHEN) |
2611               LS_64(info->push_idx, I40IWQPC_PPIDX) |
2612               LS_64(info->push_mode_en, I40IWQPC_PMENA);
2613
2614         set_64bit_val(qp_ctx, 8, qp->sq_pa);
2615         set_64bit_val(qp_ctx, 16, qp->rq_pa);
2616
2617         qw3 = LS_64(qp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2618               LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
2619               LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE);
2620
2621         set_64bit_val(qp_ctx,
2622                       128,
2623                       LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX));
2624
2625         set_64bit_val(qp_ctx,
2626                       136,
2627                       LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) |
2628                       LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM));
2629
2630         set_64bit_val(qp_ctx,
2631                       168,
2632                       LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX));
2633         set_64bit_val(qp_ctx,
2634                       176,
2635                       LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
2636                       LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
2637                       LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) |
2638                       LS_64(qp->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE));
2639
2640         if (info->iwarp_info_valid) {
2641                 qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) |
2642                        LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER);
2643
2644                 qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX);
2645                 set_64bit_val(qp_ctx,
2646                               144,
2647                               LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) |
2648                               LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX));
2649                 set_64bit_val(qp_ctx,
2650                               152,
2651                               LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT));
2652
2653                 set_64bit_val(qp_ctx,
2654                               160,
2655                               LS_64(iw->ord_size, I40IWQPC_ORDSIZE) |
2656                               LS_64(iw->ird_size, I40IWQPC_IRDSIZE) |
2657                               LS_64(iw->wr_rdresp_en, I40IWQPC_WRRDRSPOK) |
2658                               LS_64(iw->rd_enable, I40IWQPC_RDOK) |
2659                               LS_64(iw->snd_mark_en, I40IWQPC_SNDMARKERS) |
2660                               LS_64(iw->bind_en, I40IWQPC_BINDEN) |
2661                               LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) |
2662                               LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) |
2663                               LS_64((((vsi->stats_fcn_id_alloc) &&
2664                                       (dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0),
2665                                     I40IWQPC_USESTATSINSTANCE) |
2666                               LS_64(1, I40IWQPC_IWARPMODE) |
2667                               LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) |
2668                               LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) |
2669                               LS_64(iw->rcv_no_mpa_crc, I40IWQPC_RCVNOMPACRC) |
2670                               LS_64(iw->rcv_mark_offset, I40IWQPC_RCVMARKOFFSET) |
2671                               LS_64(iw->snd_mark_offset, I40IWQPC_SNDMARKOFFSET));
2672         }
2673         if (info->tcp_info_valid) {
2674                 qw0 |= LS_64(tcp->ipv4, I40IWQPC_IPV4) |
2675                        LS_64(tcp->no_nagle, I40IWQPC_NONAGLE) |
2676                        LS_64(tcp->insert_vlan_tag, I40IWQPC_INSERTVLANTAG) |
2677                        LS_64(tcp->time_stamp, I40IWQPC_TIMESTAMP) |
2678                        LS_64(tcp->cwnd_inc_limit, I40IWQPC_LIMIT) |
2679                        LS_64(tcp->drop_ooo_seg, I40IWQPC_DROPOOOSEG) |
2680                        LS_64(tcp->dup_ack_thresh, I40IWQPC_DUPACK_THRESH);
2681
2682                 qw3 |= LS_64(tcp->ttl, I40IWQPC_TTL) |
2683                        LS_64(tcp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2684                        LS_64(tcp->avoid_stretch_ack, I40IWQPC_AVOIDSTRETCHACK) |
2685                        LS_64(tcp->tos, I40IWQPC_TOS) |
2686                        LS_64(tcp->src_port, I40IWQPC_SRCPORTNUM) |
2687                        LS_64(tcp->dst_port, I40IWQPC_DESTPORTNUM);
2688
2689                 qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
2690                 set_64bit_val(qp_ctx,
2691                               32,
2692                               LS_64(tcp->dest_ip_addr2, I40IWQPC_DESTIPADDR2) |
2693                               LS_64(tcp->dest_ip_addr3, I40IWQPC_DESTIPADDR3));
2694
2695                 set_64bit_val(qp_ctx,
2696                               40,
2697                               LS_64(tcp->dest_ip_addr0, I40IWQPC_DESTIPADDR0) |
2698                               LS_64(tcp->dest_ip_addr1, I40IWQPC_DESTIPADDR1));
2699
2700                 set_64bit_val(qp_ctx,
2701                               48,
2702                               LS_64(tcp->snd_mss, I40IWQPC_SNDMSS) |
2703                                 LS_64(tcp->vlan_tag, I40IWQPC_VLANTAG) |
2704                                 LS_64(tcp->arp_idx, I40IWQPC_ARPIDX));
2705
2706                 qw7 |= LS_64(tcp->flow_label, I40IWQPC_FLOWLABEL) |
2707                        LS_64(tcp->wscale, I40IWQPC_WSCALE) |
2708                        LS_64(tcp->ignore_tcp_opt, I40IWQPC_IGNORE_TCP_OPT) |
2709                        LS_64(tcp->ignore_tcp_uns_opt, I40IWQPC_IGNORE_TCP_UNS_OPT) |
2710                        LS_64(tcp->tcp_state, I40IWQPC_TCPSTATE) |
2711                        LS_64(tcp->rcv_wscale, I40IWQPC_RCVSCALE) |
2712                        LS_64(tcp->snd_wscale, I40IWQPC_SNDSCALE);
2713
2714                 set_64bit_val(qp_ctx,
2715                               72,
2716                               LS_64(tcp->time_stamp_recent, I40IWQPC_TIMESTAMP_RECENT) |
2717                               LS_64(tcp->time_stamp_age, I40IWQPC_TIMESTAMP_AGE));
2718                 set_64bit_val(qp_ctx,
2719                               80,
2720                               LS_64(tcp->snd_nxt, I40IWQPC_SNDNXT) |
2721                               LS_64(tcp->snd_wnd, I40IWQPC_SNDWND));
2722
2723                 set_64bit_val(qp_ctx,
2724                               88,
2725                               LS_64(tcp->rcv_nxt, I40IWQPC_RCVNXT) |
2726                               LS_64(tcp->rcv_wnd, I40IWQPC_RCVWND));
2727                 set_64bit_val(qp_ctx,
2728                               96,
2729                               LS_64(tcp->snd_max, I40IWQPC_SNDMAX) |
2730                               LS_64(tcp->snd_una, I40IWQPC_SNDUNA));
2731                 set_64bit_val(qp_ctx,
2732                               104,
2733                               LS_64(tcp->srtt, I40IWQPC_SRTT) |
2734                               LS_64(tcp->rtt_var, I40IWQPC_RTTVAR));
2735                 set_64bit_val(qp_ctx,
2736                               112,
2737                               LS_64(tcp->ss_thresh, I40IWQPC_SSTHRESH) |
2738                               LS_64(tcp->cwnd, I40IWQPC_CWND));
2739                 set_64bit_val(qp_ctx,
2740                               120,
2741                               LS_64(tcp->snd_wl1, I40IWQPC_SNDWL1) |
2742                               LS_64(tcp->snd_wl2, I40IWQPC_SNDWL2));
2743                 set_64bit_val(qp_ctx,
2744                               128,
2745                               LS_64(tcp->max_snd_window, I40IWQPC_MAXSNDWND) |
2746                               LS_64(tcp->rexmit_thresh, I40IWQPC_REXMIT_THRESH));
2747                 set_64bit_val(qp_ctx,
2748                               184,
2749                               LS_64(tcp->local_ipaddr3, I40IWQPC_LOCAL_IPADDR3) |
2750                               LS_64(tcp->local_ipaddr2, I40IWQPC_LOCAL_IPADDR2));
2751                 set_64bit_val(qp_ctx,
2752                               192,
2753                               LS_64(tcp->local_ipaddr1, I40IWQPC_LOCAL_IPADDR1) |
2754                               LS_64(tcp->local_ipaddr0, I40IWQPC_LOCAL_IPADDR0));
2755         }
2756
2757         set_64bit_val(qp_ctx, 0, qw0);
2758         set_64bit_val(qp_ctx, 24, qw3);
2759         set_64bit_val(qp_ctx, 56, qw7);
2760
2761         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "QP_HOST)CTX WQE",
2762                         qp_ctx, I40IW_QP_CTX_SIZE);
2763         return 0;
2764 }
2765
2766 /**
2767  * i40iw_sc_alloc_stag - mr stag alloc
2768  * @dev: sc device struct
2769  * @info: stag info
2770  * @scratch: u64 saved to be used during cqp completion
2771  * @post_sq: flag for cqp db to ring
2772  */
2773 static enum i40iw_status_code i40iw_sc_alloc_stag(
2774                                 struct i40iw_sc_dev *dev,
2775                                 struct i40iw_allocate_stag_info *info,
2776                                 u64 scratch,
2777                                 bool post_sq)
2778 {
2779         u64 *wqe;
2780         struct i40iw_sc_cqp *cqp;
2781         u64 header;
2782         enum i40iw_page_size page_size;
2783
2784         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2785         cqp = dev->cqp;
2786         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2787         if (!wqe)
2788                 return I40IW_ERR_RING_FULL;
2789         set_64bit_val(wqe,
2790                       8,
2791                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID) |
2792                       LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN));
2793         set_64bit_val(wqe,
2794                       16,
2795                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
2796         set_64bit_val(wqe,
2797                       40,
2798                       LS_64(info->hmc_fcn_index, I40IW_CQPSQ_STAG_HMCFNIDX));
2799
2800         header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
2801                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
2802                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2803                  LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2804                  LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2805                  LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2806                  LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
2807                  LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
2808                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2809
2810         i40iw_insert_wqe_hdr(wqe, header);
2811
2812         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "ALLOC_STAG WQE",
2813                         wqe, I40IW_CQP_WQE_SIZE * 8);
2814
2815         if (post_sq)
2816                 i40iw_sc_cqp_post_sq(cqp);
2817         return 0;
2818 }
2819
2820 /**
2821  * i40iw_sc_mr_reg_non_shared - non-shared mr registration
2822  * @dev: sc device struct
2823  * @info: mr info
2824  * @scratch: u64 saved to be used during cqp completion
2825  * @post_sq: flag for cqp db to ring
2826  */
2827 static enum i40iw_status_code i40iw_sc_mr_reg_non_shared(
2828                                 struct i40iw_sc_dev *dev,
2829                                 struct i40iw_reg_ns_stag_info *info,
2830                                 u64 scratch,
2831                                 bool post_sq)
2832 {
2833         u64 *wqe;
2834         u64 temp;
2835         struct i40iw_sc_cqp *cqp;
2836         u64 header;
2837         u32 pble_obj_cnt;
2838         bool remote_access;
2839         u8 addr_type;
2840         enum i40iw_page_size page_size;
2841
2842         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2843         if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
2844                                    I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
2845                 remote_access = true;
2846         else
2847                 remote_access = false;
2848
2849         pble_obj_cnt = dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2850
2851         if (info->chunk_size && (info->first_pm_pbl_index >= pble_obj_cnt))
2852                 return I40IW_ERR_INVALID_PBLE_INDEX;
2853
2854         cqp = dev->cqp;
2855         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2856         if (!wqe)
2857                 return I40IW_ERR_RING_FULL;
2858
2859         temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
2860         set_64bit_val(wqe, 0, temp);
2861
2862         set_64bit_val(wqe,
2863                       8,
2864                       LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN) |
2865                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
2866
2867         set_64bit_val(wqe,
2868                       16,
2869                       LS_64(info->stag_key, I40IW_CQPSQ_STAG_KEY) |
2870                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
2871         if (!info->chunk_size) {
2872                 set_64bit_val(wqe, 32, info->reg_addr_pa);
2873                 set_64bit_val(wqe, 48, 0);
2874         } else {
2875                 set_64bit_val(wqe, 32, 0);
2876                 set_64bit_val(wqe, 48, info->first_pm_pbl_index);
2877         }
2878         set_64bit_val(wqe, 40, info->hmc_fcn_index);
2879         set_64bit_val(wqe, 56, 0);
2880
2881         addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
2882         header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) |
2883                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
2884                  LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2885                  LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2886                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2887                  LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2888                  LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
2889                  LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
2890                  LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
2891                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2892
2893         i40iw_insert_wqe_hdr(wqe, header);
2894
2895         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_NS WQE",
2896                         wqe, I40IW_CQP_WQE_SIZE * 8);
2897
2898         if (post_sq)
2899                 i40iw_sc_cqp_post_sq(cqp);
2900         return 0;
2901 }
2902
2903 /**
2904  * i40iw_sc_mr_reg_shared - registered shared memory region
2905  * @dev: sc device struct
2906  * @info: info for shared memory registeration
2907  * @scratch: u64 saved to be used during cqp completion
2908  * @post_sq: flag for cqp db to ring
2909  */
2910 static enum i40iw_status_code i40iw_sc_mr_reg_shared(
2911                                         struct i40iw_sc_dev *dev,
2912                                         struct i40iw_register_shared_stag *info,
2913                                         u64 scratch,
2914                                         bool post_sq)
2915 {
2916         u64 *wqe;
2917         struct i40iw_sc_cqp *cqp;
2918         u64 temp, va64, fbo, header;
2919         u32 va32;
2920         bool remote_access;
2921         u8 addr_type;
2922
2923         if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
2924                                    I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
2925                 remote_access = true;
2926         else
2927                 remote_access = false;
2928         cqp = dev->cqp;
2929         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2930         if (!wqe)
2931                 return I40IW_ERR_RING_FULL;
2932         va64 = (uintptr_t)(info->va);
2933         va32 = (u32)(va64 & 0x00000000FFFFFFFF);
2934         fbo = (u64)(va32 & (4096 - 1));
2935
2936         set_64bit_val(wqe,
2937                       0,
2938                       (info->addr_type == I40IW_ADDR_TYPE_VA_BASED ? (uintptr_t)info->va : fbo));
2939
2940         set_64bit_val(wqe,
2941                       8,
2942                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
2943         temp = LS_64(info->new_stag_key, I40IW_CQPSQ_STAG_KEY) |
2944                LS_64(info->new_stag_idx, I40IW_CQPSQ_STAG_IDX) |
2945                LS_64(info->parent_stag_idx, I40IW_CQPSQ_STAG_PARENTSTAGIDX);
2946         set_64bit_val(wqe, 16, temp);
2947
2948         addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
2949         header = LS_64(I40IW_CQP_OP_REG_SMR, I40IW_CQPSQ_OPCODE) |
2950                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
2951                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2952                  LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2953                  LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
2954                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2955
2956         i40iw_insert_wqe_hdr(wqe, header);
2957
2958         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_SHARED WQE",
2959                         wqe, I40IW_CQP_WQE_SIZE * 8);
2960
2961         if (post_sq)
2962                 i40iw_sc_cqp_post_sq(cqp);
2963         return 0;
2964 }
2965
2966 /**
2967  * i40iw_sc_dealloc_stag - deallocate stag
2968  * @dev: sc device struct
2969  * @info: dealloc stag info
2970  * @scratch: u64 saved to be used during cqp completion
2971  * @post_sq: flag for cqp db to ring
2972  */
2973 static enum i40iw_status_code i40iw_sc_dealloc_stag(
2974                                         struct i40iw_sc_dev *dev,
2975                                         struct i40iw_dealloc_stag_info *info,
2976                                         u64 scratch,
2977                                         bool post_sq)
2978 {
2979         u64 header;
2980         u64 *wqe;
2981         struct i40iw_sc_cqp *cqp;
2982
2983         cqp = dev->cqp;
2984         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2985         if (!wqe)
2986                 return I40IW_ERR_RING_FULL;
2987         set_64bit_val(wqe,
2988                       8,
2989                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
2990         set_64bit_val(wqe,
2991                       16,
2992                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
2993
2994         header = LS_64(I40IW_CQP_OP_DEALLOC_STAG, I40IW_CQPSQ_OPCODE) |
2995                  LS_64(info->mr, I40IW_CQPSQ_STAG_MR) |
2996                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2997
2998         i40iw_insert_wqe_hdr(wqe, header);
2999
3000         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "DEALLOC_STAG WQE",
3001                         wqe, I40IW_CQP_WQE_SIZE * 8);
3002
3003         if (post_sq)
3004                 i40iw_sc_cqp_post_sq(cqp);
3005         return 0;
3006 }
3007
3008 /**
3009  * i40iw_sc_query_stag - query hardware for stag
3010  * @dev: sc device struct
3011  * @scratch: u64 saved to be used during cqp completion
3012  * @stag_index: stag index for query
3013  * @post_sq: flag for cqp db to ring
3014  */
3015 static enum i40iw_status_code i40iw_sc_query_stag(struct i40iw_sc_dev *dev,
3016                                                   u64 scratch,
3017                                                   u32 stag_index,
3018                                                   bool post_sq)
3019 {
3020         u64 header;
3021         u64 *wqe;
3022         struct i40iw_sc_cqp *cqp;
3023
3024         cqp = dev->cqp;
3025         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3026         if (!wqe)
3027                 return I40IW_ERR_RING_FULL;
3028         set_64bit_val(wqe,
3029                       16,
3030                       LS_64(stag_index, I40IW_CQPSQ_QUERYSTAG_IDX));
3031
3032         header = LS_64(I40IW_CQP_OP_QUERY_STAG, I40IW_CQPSQ_OPCODE) |
3033                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3034
3035         i40iw_insert_wqe_hdr(wqe, header);
3036
3037         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QUERY_STAG WQE",
3038                         wqe, I40IW_CQP_WQE_SIZE * 8);
3039
3040         if (post_sq)
3041                 i40iw_sc_cqp_post_sq(cqp);
3042         return 0;
3043 }
3044
3045 /**
3046  * i40iw_sc_mw_alloc - mw allocate
3047  * @dev: sc device struct
3048  * @scratch: u64 saved to be used during cqp completion
3049  * @mw_stag_index:stag index
3050  * @pd_id: pd is for this mw
3051  * @post_sq: flag for cqp db to ring
3052  */
3053 static enum i40iw_status_code i40iw_sc_mw_alloc(
3054                                         struct i40iw_sc_dev *dev,
3055                                         u64 scratch,
3056                                         u32 mw_stag_index,
3057                                         u16 pd_id,
3058                                         bool post_sq)
3059 {
3060         u64 header;
3061         struct i40iw_sc_cqp *cqp;
3062         u64 *wqe;
3063
3064         cqp = dev->cqp;
3065         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3066         if (!wqe)
3067                 return I40IW_ERR_RING_FULL;
3068         set_64bit_val(wqe, 8, LS_64(pd_id, I40IW_CQPSQ_STAG_PDID));
3069         set_64bit_val(wqe,
3070                       16,
3071                       LS_64(mw_stag_index, I40IW_CQPSQ_STAG_IDX));
3072
3073         header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3074                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3075
3076         i40iw_insert_wqe_hdr(wqe, header);
3077
3078         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MW_ALLOC WQE",
3079                         wqe, I40IW_CQP_WQE_SIZE * 8);
3080
3081         if (post_sq)
3082                 i40iw_sc_cqp_post_sq(cqp);
3083         return 0;
3084 }
3085
3086 /**
3087  * i40iw_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp
3088  * @qp: sc qp struct
3089  * @info: fast mr info
3090  * @post_sq: flag for cqp db to ring
3091  */
3092 enum i40iw_status_code i40iw_sc_mr_fast_register(
3093                                 struct i40iw_sc_qp *qp,
3094                                 struct i40iw_fast_reg_stag_info *info,
3095                                 bool post_sq)
3096 {
3097         u64 temp, header;
3098         u64 *wqe;
3099         u32 wqe_idx;
3100         enum i40iw_page_size page_size;
3101
3102         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3103         wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE,
3104                                          0, info->wr_id);
3105         if (!wqe)
3106                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3107
3108         i40iw_debug(qp->dev, I40IW_DEBUG_MR, "%s: wr_id[%llxh] wqe_idx[%04d] location[%p]\n",
3109                     __func__, info->wr_id, wqe_idx,
3110                     &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid);
3111         temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3112         set_64bit_val(wqe, 0, temp);
3113
3114         temp = RS_64(info->first_pm_pbl_index >> 16, I40IWQPSQ_FIRSTPMPBLIDXHI);
3115         set_64bit_val(wqe,
3116                       8,
3117                       LS_64(temp, I40IWQPSQ_FIRSTPMPBLIDXHI) |
3118                       LS_64(info->reg_addr_pa >> I40IWQPSQ_PBLADDR_SHIFT, I40IWQPSQ_PBLADDR));
3119
3120         set_64bit_val(wqe,
3121                       16,
3122                       info->total_len |
3123                       LS_64(info->first_pm_pbl_index, I40IWQPSQ_FIRSTPMPBLIDXLO));
3124
3125         header = LS_64(info->stag_key, I40IWQPSQ_STAGKEY) |
3126                  LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) |
3127                  LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) |
3128                  LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) |
3129                  LS_64(page_size, I40IWQPSQ_HPAGESIZE) |
3130                  LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) |
3131                  LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) |
3132                  LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
3133                  LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
3134                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
3135                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3136
3137         i40iw_insert_wqe_hdr(wqe, header);
3138
3139         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "FAST_REG WQE",
3140                         wqe, I40IW_QP_WQE_MIN_SIZE);
3141
3142         if (post_sq)
3143                 i40iw_qp_post_wr(&qp->qp_uk);
3144         return 0;
3145 }
3146
3147 /**
3148  * i40iw_sc_send_lsmm - send last streaming mode message
3149  * @qp: sc qp struct
3150  * @lsmm_buf: buffer with lsmm message
3151  * @size: size of lsmm buffer
3152  * @stag: stag of lsmm buffer
3153  */
3154 static void i40iw_sc_send_lsmm(struct i40iw_sc_qp *qp,
3155                                void *lsmm_buf,
3156                                u32 size,
3157                                i40iw_stag stag)
3158 {
3159         u64 *wqe;
3160         u64 header;
3161         struct i40iw_qp_uk *qp_uk;
3162
3163         qp_uk = &qp->qp_uk;
3164         wqe = qp_uk->sq_base->elem;
3165
3166         set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3167
3168         set_64bit_val(wqe, 8, (size | LS_64(stag, I40IWQPSQ_FRAG_STAG)));
3169
3170         set_64bit_val(wqe, 16, 0);
3171
3172         header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3173                  LS_64(1, I40IWQPSQ_STREAMMODE) |
3174                  LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3175                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3176
3177         i40iw_insert_wqe_hdr(wqe, header);
3178
3179         i40iw_debug_buf(qp->dev, I40IW_DEBUG_QP, "SEND_LSMM WQE",
3180                         wqe, I40IW_QP_WQE_MIN_SIZE);
3181 }
3182
3183 /**
3184  * i40iw_sc_send_lsmm_nostag - for privilege qp
3185  * @qp: sc qp struct
3186  * @lsmm_buf: buffer with lsmm message
3187  * @size: size of lsmm buffer
3188  */
3189 static void i40iw_sc_send_lsmm_nostag(struct i40iw_sc_qp *qp,
3190                                       void *lsmm_buf,
3191                                       u32 size)
3192 {
3193         u64 *wqe;
3194         u64 header;
3195         struct i40iw_qp_uk *qp_uk;
3196
3197         qp_uk = &qp->qp_uk;
3198         wqe = qp_uk->sq_base->elem;
3199
3200         set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3201
3202         set_64bit_val(wqe, 8, size);
3203
3204         set_64bit_val(wqe, 16, 0);
3205
3206         header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3207                  LS_64(1, I40IWQPSQ_STREAMMODE) |
3208                  LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3209                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3210
3211         i40iw_insert_wqe_hdr(wqe, header);
3212
3213         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE",
3214                         wqe, I40IW_QP_WQE_MIN_SIZE);
3215 }
3216
3217 /**
3218  * i40iw_sc_send_rtt - send last read0 or write0
3219  * @qp: sc qp struct
3220  * @read: Do read0 or write0
3221  */
3222 static void i40iw_sc_send_rtt(struct i40iw_sc_qp *qp, bool read)
3223 {
3224         u64 *wqe;
3225         u64 header;
3226         struct i40iw_qp_uk *qp_uk;
3227
3228         qp_uk = &qp->qp_uk;
3229         wqe = qp_uk->sq_base->elem;
3230
3231         set_64bit_val(wqe, 0, 0);
3232         set_64bit_val(wqe, 8, 0);
3233         set_64bit_val(wqe, 16, 0);
3234         if (read) {
3235                 header = LS_64(0x1234, I40IWQPSQ_REMSTAG) |
3236                          LS_64(I40IWQP_OP_RDMA_READ, I40IWQPSQ_OPCODE) |
3237                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3238                 set_64bit_val(wqe, 8, ((u64)0xabcd << 32));
3239         } else {
3240                 header = LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
3241                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3242         }
3243
3244         i40iw_insert_wqe_hdr(wqe, header);
3245
3246         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "RTR WQE",
3247                         wqe, I40IW_QP_WQE_MIN_SIZE);
3248 }
3249
3250 /**
3251  * i40iw_sc_post_wqe0 - send wqe with opcode
3252  * @qp: sc qp struct
3253  * @opcode: opcode to use for wqe0
3254  */
3255 static enum i40iw_status_code i40iw_sc_post_wqe0(struct i40iw_sc_qp *qp, u8 opcode)
3256 {
3257         u64 *wqe;
3258         u64 header;
3259         struct i40iw_qp_uk *qp_uk;
3260
3261         qp_uk = &qp->qp_uk;
3262         wqe = qp_uk->sq_base->elem;
3263
3264         if (!wqe)
3265                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3266         switch (opcode) {
3267         case I40IWQP_OP_NOP:
3268                 set_64bit_val(wqe, 0, 0);
3269                 set_64bit_val(wqe, 8, 0);
3270                 set_64bit_val(wqe, 16, 0);
3271                 header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
3272                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3273
3274                 i40iw_insert_wqe_hdr(wqe, header);
3275                 break;
3276         case I40IWQP_OP_RDMA_SEND:
3277                 set_64bit_val(wqe, 0, 0);
3278                 set_64bit_val(wqe, 8, 0);
3279                 set_64bit_val(wqe, 16, 0);
3280                 header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3281                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID) |
3282                          LS_64(1, I40IWQPSQ_STREAMMODE) |
3283                          LS_64(1, I40IWQPSQ_WAITFORRCVPDU);
3284
3285                 i40iw_insert_wqe_hdr(wqe, header);
3286                 break;
3287         default:
3288                 i40iw_debug(qp->dev, I40IW_DEBUG_QP, "%s: Invalid WQE zero opcode\n",
3289                             __func__);
3290                 break;
3291         }
3292         return 0;
3293 }
3294
3295 /**
3296  * i40iw_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info
3297  * @dev : ptr to i40iw_dev struct
3298  * @hmc_fn_id: hmc function id
3299  */
3300 enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, u8 hmc_fn_id)
3301 {
3302         struct i40iw_hmc_info *hmc_info;
3303         struct i40iw_dma_mem query_fpm_mem;
3304         struct i40iw_virt_mem virt_mem;
3305         struct i40iw_vfdev *vf_dev = NULL;
3306         u32 mem_size;
3307         enum i40iw_status_code ret_code = 0;
3308         bool poll_registers = true;
3309         u16 iw_vf_idx;
3310         u8 wait_type;
3311
3312         if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3313             (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3314                 return I40IW_ERR_INVALID_HMCFN_ID;
3315
3316         i40iw_debug(dev, I40IW_DEBUG_HMC, "hmc_fn_id %u, dev->hmc_fn_id %u\n", hmc_fn_id,
3317                     dev->hmc_fn_id);
3318         if (hmc_fn_id == dev->hmc_fn_id) {
3319                 hmc_info = dev->hmc_info;
3320                 query_fpm_mem.pa = dev->fpm_query_buf_pa;
3321                 query_fpm_mem.va = dev->fpm_query_buf;
3322         } else {
3323                 vf_dev = i40iw_vfdev_from_fpm(dev, hmc_fn_id);
3324                 if (!vf_dev)
3325                         return I40IW_ERR_INVALID_VF_ID;
3326
3327                 hmc_info = &vf_dev->hmc_info;
3328                 iw_vf_idx = vf_dev->iw_vf_idx;
3329                 i40iw_debug(dev, I40IW_DEBUG_HMC, "vf_dev %p, hmc_info %p, hmc_obj %p\n", vf_dev,
3330                             hmc_info, hmc_info->hmc_obj);
3331                 if (!vf_dev->fpm_query_buf) {
3332                         if (!dev->vf_fpm_query_buf[iw_vf_idx].va) {
3333                                 ret_code = i40iw_alloc_query_fpm_buf(dev,
3334                                                                      &dev->vf_fpm_query_buf[iw_vf_idx]);
3335                                 if (ret_code)
3336                                         return ret_code;
3337                         }
3338                         vf_dev->fpm_query_buf = dev->vf_fpm_query_buf[iw_vf_idx].va;
3339                         vf_dev->fpm_query_buf_pa = dev->vf_fpm_query_buf[iw_vf_idx].pa;
3340                 }
3341                 query_fpm_mem.pa = vf_dev->fpm_query_buf_pa;
3342                 query_fpm_mem.va = vf_dev->fpm_query_buf;
3343                 /**
3344                  * It is HARDWARE specific:
3345                  * this call is done by PF for VF and
3346                  * i40iw_sc_query_fpm_values needs ccq poll
3347                  * because PF ccq is already created.
3348                  */
3349                 poll_registers = false;
3350         }
3351
3352         hmc_info->hmc_fn_id = hmc_fn_id;
3353
3354         if (hmc_fn_id != dev->hmc_fn_id) {
3355                 ret_code =
3356                         i40iw_cqp_query_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3357         } else {
3358                 wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3359                             (u8)I40IW_CQP_WAIT_POLL_CQ;
3360
3361                 ret_code = i40iw_sc_query_fpm_values(
3362                                         dev->cqp,
3363                                         0,
3364                                         hmc_info->hmc_fn_id,
3365                                         &query_fpm_mem,
3366                                         true,
3367                                         wait_type);
3368         }
3369         if (ret_code)
3370                 return ret_code;
3371
3372         /* parse the fpm_query_buf and fill hmc obj info */
3373         ret_code =
3374                 i40iw_sc_parse_fpm_query_buf((u64 *)query_fpm_mem.va,
3375                                              hmc_info,
3376                                              &dev->hmc_fpm_misc);
3377         if (ret_code)
3378                 return ret_code;
3379         i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "QUERY FPM BUFFER",
3380                         query_fpm_mem.va, I40IW_QUERY_FPM_BUF_SIZE);
3381
3382         if (hmc_fn_id != dev->hmc_fn_id) {
3383                 i40iw_cqp_commit_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3384
3385                 /* parse the fpm_commit_buf and fill hmc obj info */
3386                 i40iw_sc_parse_fpm_commit_buf((u64 *)query_fpm_mem.va, hmc_info->hmc_obj, &hmc_info->sd_table.sd_cnt);
3387                 mem_size = sizeof(struct i40iw_hmc_sd_entry) *
3388                            (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index);
3389                 ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
3390                 if (ret_code)
3391                         return ret_code;
3392                 hmc_info->sd_table.sd_entry = virt_mem.va;
3393         }
3394
3395         /* fill size of objects which are fixed */
3396         hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].size = 4;
3397         hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].size = 4;
3398         hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size = 8;
3399         hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
3400         hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
3401
3402         return ret_code;
3403 }
3404
3405 /**
3406  * i40iw_sc_configure_iw_fpm() - commits hmc obj cnt values using cqp command and
3407  * populates fpm base address in hmc_info
3408  * @dev : ptr to i40iw_dev struct
3409  * @hmc_fn_id: hmc function id
3410  */
3411 static enum i40iw_status_code i40iw_sc_configure_iw_fpm(struct i40iw_sc_dev *dev,
3412                                                         u8 hmc_fn_id)
3413 {
3414         struct i40iw_hmc_info *hmc_info;
3415         struct i40iw_hmc_obj_info *obj_info;
3416         u64 *buf;
3417         struct i40iw_dma_mem commit_fpm_mem;
3418         u32 i, j;
3419         enum i40iw_status_code ret_code = 0;
3420         bool poll_registers = true;
3421         u8 wait_type;
3422
3423         if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3424             (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3425                 return I40IW_ERR_INVALID_HMCFN_ID;
3426
3427         if (hmc_fn_id == dev->hmc_fn_id) {
3428                 hmc_info = dev->hmc_info;
3429         } else {
3430                 hmc_info = i40iw_vf_hmcinfo_from_fpm(dev, hmc_fn_id);
3431                 poll_registers = false;
3432         }
3433         if (!hmc_info)
3434                 return I40IW_ERR_BAD_PTR;
3435
3436         obj_info = hmc_info->hmc_obj;
3437         buf = dev->fpm_commit_buf;
3438
3439         /* copy cnt values in commit buf */
3440         for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE;
3441              i++, j += 8)
3442                 set_64bit_val(buf, j, (u64)obj_info[i].cnt);
3443
3444         set_64bit_val(buf, 40, 0);   /* APBVT rsvd */
3445
3446         commit_fpm_mem.pa = dev->fpm_commit_buf_pa;
3447         commit_fpm_mem.va = dev->fpm_commit_buf;
3448         wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3449                         (u8)I40IW_CQP_WAIT_POLL_CQ;
3450         ret_code = i40iw_sc_commit_fpm_values(
3451                                         dev->cqp,
3452                                         0,
3453                                         hmc_info->hmc_fn_id,
3454                                         &commit_fpm_mem,
3455                                         true,
3456                                         wait_type);
3457
3458         /* parse the fpm_commit_buf and fill hmc obj info */
3459         if (!ret_code)
3460                 ret_code = i40iw_sc_parse_fpm_commit_buf(dev->fpm_commit_buf,
3461                                                          hmc_info->hmc_obj,
3462                                                          &hmc_info->sd_table.sd_cnt);
3463
3464         i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "COMMIT FPM BUFFER",
3465                         commit_fpm_mem.va, I40IW_COMMIT_FPM_BUF_SIZE);
3466
3467         return ret_code;
3468 }
3469
3470 /**
3471  * cqp_sds_wqe_fill - fill cqp wqe doe sd
3472  * @cqp: struct for cqp hw
3473  * @info; sd info for wqe
3474  * @scratch: u64 saved to be used during cqp completion
3475  */
3476 static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp,
3477                                                struct i40iw_update_sds_info *info,
3478                                                u64 scratch)
3479 {
3480         u64 data;
3481         u64 header;
3482         u64 *wqe;
3483         int mem_entries, wqe_entries;
3484         struct i40iw_dma_mem *sdbuf = &cqp->sdbuf;
3485
3486         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3487         if (!wqe)
3488                 return I40IW_ERR_RING_FULL;
3489
3490         I40IW_CQP_INIT_WQE(wqe);
3491         wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
3492         mem_entries = info->cnt - wqe_entries;
3493
3494         header = LS_64(I40IW_CQP_OP_UPDATE_PE_SDS, I40IW_CQPSQ_OPCODE) |
3495                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
3496                  LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT);
3497
3498         if (mem_entries) {
3499                 memcpy(sdbuf->va, &info->entry[3], (mem_entries << 4));
3500                 data = sdbuf->pa;
3501         } else {
3502                 data = 0;
3503         }
3504         data |= LS_64(info->hmc_fn_id, I40IW_CQPSQ_UPESD_HMCFNID);
3505
3506         set_64bit_val(wqe, 16, data);
3507
3508         switch (wqe_entries) {
3509         case 3:
3510                 set_64bit_val(wqe, 48,
3511                               (LS_64(info->entry[2].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3512                                         LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3513
3514                 set_64bit_val(wqe, 56, info->entry[2].data);
3515                 /* fallthrough */
3516         case 2:
3517                 set_64bit_val(wqe, 32,
3518                               (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3519                                         LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3520
3521                 set_64bit_val(wqe, 40, info->entry[1].data);
3522                 /* fallthrough */
3523         case 1:
3524                 set_64bit_val(wqe, 0,
3525                               LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));
3526
3527                 set_64bit_val(wqe, 8, info->entry[0].data);
3528                 break;
3529         default:
3530                 break;
3531         }
3532
3533         i40iw_insert_wqe_hdr(wqe, header);
3534
3535         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "UPDATE_PE_SDS WQE",
3536                         wqe, I40IW_CQP_WQE_SIZE * 8);
3537         return 0;
3538 }
3539
3540 /**
3541  * i40iw_update_pe_sds - cqp wqe for sd
3542  * @dev: ptr to i40iw_dev struct
3543  * @info: sd info for sd's
3544  * @scratch: u64 saved to be used during cqp completion
3545  */
3546 static enum i40iw_status_code i40iw_update_pe_sds(struct i40iw_sc_dev *dev,
3547                                                   struct i40iw_update_sds_info *info,
3548                                                   u64 scratch)
3549 {
3550         struct i40iw_sc_cqp *cqp = dev->cqp;
3551         enum i40iw_status_code ret_code;
3552
3553         ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
3554         if (!ret_code)
3555                 i40iw_sc_cqp_post_sq(cqp);
3556
3557         return ret_code;
3558 }
3559
3560 /**
3561  * i40iw_update_sds_noccq - update sd before ccq created
3562  * @dev: sc device struct
3563  * @info: sd info for sd's
3564  */
3565 enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev,
3566                                               struct i40iw_update_sds_info *info)
3567 {
3568         u32 error, val, tail;
3569         struct i40iw_sc_cqp *cqp = dev->cqp;
3570         enum i40iw_status_code ret_code;
3571
3572         ret_code = cqp_sds_wqe_fill(cqp, info, 0);
3573         if (ret_code)
3574                 return ret_code;
3575         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3576         if (error)
3577                 return I40IW_ERR_CQP_COMPL_ERROR;
3578
3579         i40iw_sc_cqp_post_sq(cqp);
3580         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
3581
3582         return ret_code;
3583 }
3584
3585 /**
3586  * i40iw_sc_suspend_qp - suspend qp for param change
3587  * @cqp: struct for cqp hw
3588  * @qp: sc qp struct
3589  * @scratch: u64 saved to be used during cqp completion
3590  */
3591 enum i40iw_status_code i40iw_sc_suspend_qp(struct i40iw_sc_cqp *cqp,
3592                                            struct i40iw_sc_qp *qp,
3593                                            u64 scratch)
3594 {
3595         u64 header;
3596         u64 *wqe;
3597
3598         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3599         if (!wqe)
3600                 return I40IW_ERR_RING_FULL;
3601         header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_SUSPENDQP_QPID) |
3602                  LS_64(I40IW_CQP_OP_SUSPEND_QP, I40IW_CQPSQ_OPCODE) |
3603                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3604
3605         i40iw_insert_wqe_hdr(wqe, header);
3606
3607         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SUSPEND_QP WQE",
3608                         wqe, I40IW_CQP_WQE_SIZE * 8);
3609
3610         i40iw_sc_cqp_post_sq(cqp);
3611         return 0;
3612 }
3613
3614 /**
3615  * i40iw_sc_resume_qp - resume qp after suspend
3616  * @cqp: struct for cqp hw
3617  * @qp: sc qp struct
3618  * @scratch: u64 saved to be used during cqp completion
3619  */
3620 enum i40iw_status_code i40iw_sc_resume_qp(struct i40iw_sc_cqp *cqp,
3621                                           struct i40iw_sc_qp *qp,
3622                                           u64 scratch)
3623 {
3624         u64 header;
3625         u64 *wqe;
3626
3627         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3628         if (!wqe)
3629                 return I40IW_ERR_RING_FULL;
3630         set_64bit_val(wqe,
3631                       16,
3632                         LS_64(qp->qs_handle, I40IW_CQPSQ_RESUMEQP_QSHANDLE));
3633
3634         header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_RESUMEQP_QPID) |
3635                  LS_64(I40IW_CQP_OP_RESUME_QP, I40IW_CQPSQ_OPCODE) |
3636                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3637
3638         i40iw_insert_wqe_hdr(wqe, header);
3639
3640         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "RESUME_QP WQE",
3641                         wqe, I40IW_CQP_WQE_SIZE * 8);
3642
3643         i40iw_sc_cqp_post_sq(cqp);
3644         return 0;
3645 }
3646
3647 /**
3648  * i40iw_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages
3649  * @cqp: struct for cqp hw
3650  * @scratch: u64 saved to be used during cqp completion
3651  * @hmc_fn_id: hmc function id
3652  * @post_sq: flag for cqp db to ring
3653  * @poll_registers: flag to poll register for cqp completion
3654  */
3655 enum i40iw_status_code i40iw_sc_static_hmc_pages_allocated(
3656                                         struct i40iw_sc_cqp *cqp,
3657                                         u64 scratch,
3658                                         u8 hmc_fn_id,
3659                                         bool post_sq,
3660                                         bool poll_registers)
3661 {
3662         u64 header;
3663         u64 *wqe;
3664         u32 tail, val, error;
3665         enum i40iw_status_code ret_code = 0;
3666
3667         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3668         if (!wqe)
3669                 return I40IW_ERR_RING_FULL;
3670         set_64bit_val(wqe,
3671                       16,
3672                       LS_64(hmc_fn_id, I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID));
3673
3674         header = LS_64(I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, I40IW_CQPSQ_OPCODE) |
3675                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3676
3677         i40iw_insert_wqe_hdr(wqe, header);
3678
3679         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SHMC_PAGES_ALLOCATED WQE",
3680                         wqe, I40IW_CQP_WQE_SIZE * 8);
3681         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3682         if (error) {
3683                 ret_code = I40IW_ERR_CQP_COMPL_ERROR;
3684                 return ret_code;
3685         }
3686         if (post_sq) {
3687                 i40iw_sc_cqp_post_sq(cqp);
3688                 if (poll_registers)
3689                         /* check for cqp sq tail update */
3690                         ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
3691                 else
3692                         ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
3693                                                                  I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
3694                                                                  NULL);
3695         }
3696
3697         return ret_code;
3698 }
3699
3700 /**
3701  * i40iw_ring_full - check if cqp ring is full
3702  * @cqp: struct for cqp hw
3703  */
3704 static bool i40iw_ring_full(struct i40iw_sc_cqp *cqp)
3705 {
3706         return I40IW_RING_FULL_ERR(cqp->sq_ring);
3707 }
3708
3709 /**
3710  * i40iw_est_sd - returns approximate number of SDs for HMC
3711  * @dev: sc device struct
3712  * @hmc_info: hmc structure, size and count for HMC objects
3713  */
3714 static u64 i40iw_est_sd(struct i40iw_sc_dev *dev, struct i40iw_hmc_info *hmc_info)
3715 {
3716         int i;
3717         u64 size = 0;
3718         u64 sd;
3719
3720         for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_PBLE; i++)
3721                 size += hmc_info->hmc_obj[i].cnt * hmc_info->hmc_obj[i].size;
3722
3723         if (dev->is_pf)
3724                 size += hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3725
3726         if (size & 0x1FFFFF)
3727                 sd = (size >> 21) + 1; /* add 1 for remainder */
3728         else
3729                 sd = size >> 21;
3730
3731         if (!dev->is_pf) {
3732                 /* 2MB alignment for VF PBLE HMC */
3733                 size = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3734                 if (size & 0x1FFFFF)
3735                         sd += (size >> 21) + 1; /* add 1 for remainder */
3736                 else
3737                         sd += size >> 21;
3738         }
3739
3740         return sd;
3741 }
3742
3743 /**
3744  * i40iw_config_fpm_values - configure HMC objects
3745  * @dev: sc device struct
3746  * @qp_count: desired qp count
3747  */
3748 enum i40iw_status_code i40iw_config_fpm_values(struct i40iw_sc_dev *dev, u32 qp_count)
3749 {
3750         struct i40iw_virt_mem virt_mem;
3751         u32 i, mem_size;
3752         u32 qpwantedoriginal, qpwanted, mrwanted, pblewanted;
3753         u32 powerof2;
3754         u64 sd_needed;
3755         u32 loop_count = 0;
3756
3757         struct i40iw_hmc_info *hmc_info;
3758         struct i40iw_hmc_fpm_misc *hmc_fpm_misc;
3759         enum i40iw_status_code ret_code = 0;
3760
3761         hmc_info = dev->hmc_info;
3762         hmc_fpm_misc = &dev->hmc_fpm_misc;
3763
3764         ret_code = i40iw_sc_init_iw_hmc(dev, dev->hmc_fn_id);
3765         if (ret_code) {
3766                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3767                             "i40iw_sc_init_iw_hmc returned error_code = %d\n",
3768                             ret_code);
3769                 return ret_code;
3770         }
3771
3772         for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_MAX; i++)
3773                 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt;
3774         sd_needed = i40iw_est_sd(dev, hmc_info);
3775         i40iw_debug(dev, I40IW_DEBUG_HMC,
3776                     "%s: FW initial max sd_count[%08lld] first_sd_index[%04d]\n",
3777                     __func__, sd_needed, hmc_info->first_sd_index);
3778         i40iw_debug(dev, I40IW_DEBUG_HMC,
3779                     "%s: sd count %d where max sd is %d\n",
3780                     __func__, hmc_info->sd_table.sd_cnt,
3781                     hmc_fpm_misc->max_sds);
3782
3783         qpwanted = min(qp_count, hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt);
3784         qpwantedoriginal = qpwanted;
3785         mrwanted = hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt;
3786         pblewanted = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt;
3787
3788         i40iw_debug(dev, I40IW_DEBUG_HMC,
3789                     "req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d\n",
3790                     qp_count, hmc_fpm_misc->max_sds,
3791                     hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt,
3792                     hmc_info->hmc_obj[I40IW_HMC_IW_CQ].max_cnt,
3793                     hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt,
3794                     hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt);
3795
3796         do {
3797                 ++loop_count;
3798                 hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt = qpwanted;
3799                 hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt =
3800                         min(2 * qpwanted, hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt);
3801                 hmc_info->hmc_obj[I40IW_HMC_IW_SRQ].cnt = 0x00; /* Reserved */
3802                 hmc_info->hmc_obj[I40IW_HMC_IW_HTE].cnt =
3803                                         qpwanted * hmc_fpm_misc->ht_multiplier;
3804                 hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt =
3805                         hmc_info->hmc_obj[I40IW_HMC_IW_ARP].max_cnt;
3806                 hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].cnt = 1;
3807                 hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt = mrwanted;
3808
3809                 hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt = I40IW_MAX_WQ_ENTRIES * qpwanted;
3810                 hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt = 4 * I40IW_MAX_IRD_SIZE * qpwanted;
3811                 hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].cnt =
3812                         hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size;
3813                 hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].cnt =
3814                         hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size;
3815                 hmc_info->hmc_obj[I40IW_HMC_IW_TIMER].cnt =
3816                         ((qpwanted) / 512 + 1) * hmc_fpm_misc->timer_bucket;
3817                 hmc_info->hmc_obj[I40IW_HMC_IW_FSIMC].cnt = 0x00;
3818                 hmc_info->hmc_obj[I40IW_HMC_IW_FSIAV].cnt = 0x00;
3819                 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt = pblewanted;
3820
3821                 /* How much memory is needed for all the objects. */
3822                 sd_needed = i40iw_est_sd(dev, hmc_info);
3823                 if ((loop_count > 1000) ||
3824                     ((!(loop_count % 10)) &&
3825                     (qpwanted > qpwantedoriginal * 2 / 3))) {
3826                         if (qpwanted > FPM_MULTIPLIER) {
3827                                 qpwanted -= FPM_MULTIPLIER;
3828                                 powerof2 = 1;
3829                                 while (powerof2 < qpwanted)
3830                                         powerof2 *= 2;
3831                                 powerof2 /= 2;
3832                                 qpwanted = powerof2;
3833                         } else {
3834                                 qpwanted /= 2;
3835                         }
3836                 }
3837                 if (mrwanted > FPM_MULTIPLIER * 10)
3838                         mrwanted -= FPM_MULTIPLIER * 10;
3839                 if (pblewanted > FPM_MULTIPLIER * 1000)
3840                         pblewanted -= FPM_MULTIPLIER * 1000;
3841         } while (sd_needed > hmc_fpm_misc->max_sds && loop_count < 2000);
3842
3843         sd_needed = i40iw_est_sd(dev, hmc_info);
3844
3845         i40iw_debug(dev, I40IW_DEBUG_HMC,
3846                     "loop_cnt=%d, sd_needed=%lld, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d\n",
3847                     loop_count, sd_needed,
3848                     hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt,
3849                     hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt,
3850                     hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt,
3851                     hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt);
3852
3853         ret_code = i40iw_sc_configure_iw_fpm(dev, dev->hmc_fn_id);
3854         if (ret_code) {
3855                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3856                             "configure_iw_fpm returned error_code[x%08X]\n",
3857                             i40iw_rd32(dev->hw, dev->is_pf ? I40E_PFPE_CQPERRCODES : I40E_VFPE_CQPERRCODES1));
3858                 return ret_code;
3859         }
3860
3861         mem_size = sizeof(struct i40iw_hmc_sd_entry) *
3862                    (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
3863         ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
3864         if (ret_code) {
3865                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3866                             "%s: failed to allocate memory for sd_entry buffer\n",
3867                             __func__);
3868                 return ret_code;
3869         }
3870         hmc_info->sd_table.sd_entry = virt_mem.va;
3871
3872         return ret_code;
3873 }
3874
3875 /**
3876  * i40iw_exec_cqp_cmd - execute cqp cmd when wqe are available
3877  * @dev: rdma device
3878  * @pcmdinfo: cqp command info
3879  */
3880 static enum i40iw_status_code i40iw_exec_cqp_cmd(struct i40iw_sc_dev *dev,
3881                                                  struct cqp_commands_info *pcmdinfo)
3882 {
3883         enum i40iw_status_code status;
3884         struct i40iw_dma_mem values_mem;
3885
3886         dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++;
3887         switch (pcmdinfo->cqp_cmd) {
3888         case OP_DELETE_LOCAL_MAC_IPADDR_ENTRY:
3889                 status = i40iw_sc_del_local_mac_ipaddr_entry(
3890                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.cqp,
3891                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.scratch,
3892                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.entry_idx,
3893                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.ignore_ref_count,
3894                                 pcmdinfo->post_sq);
3895                 break;
3896         case OP_CEQ_DESTROY:
3897                 status = i40iw_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq,
3898                                               pcmdinfo->in.u.ceq_destroy.scratch,
3899                                               pcmdinfo->post_sq);
3900                 break;
3901         case OP_AEQ_DESTROY:
3902                 status = i40iw_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
3903                                               pcmdinfo->in.u.aeq_destroy.scratch,
3904                                               pcmdinfo->post_sq);
3905
3906                 break;
3907         case OP_DELETE_ARP_CACHE_ENTRY:
3908                 status = i40iw_sc_del_arp_cache_entry(
3909                                 pcmdinfo->in.u.del_arp_cache_entry.cqp,
3910                                 pcmdinfo->in.u.del_arp_cache_entry.scratch,
3911                                 pcmdinfo->in.u.del_arp_cache_entry.arp_index,
3912                                 pcmdinfo->post_sq);
3913                 break;
3914         case OP_MANAGE_APBVT_ENTRY:
3915                 status = i40iw_sc_manage_apbvt_entry(
3916                                 pcmdinfo->in.u.manage_apbvt_entry.cqp,
3917                                 &pcmdinfo->in.u.manage_apbvt_entry.info,
3918                                 pcmdinfo->in.u.manage_apbvt_entry.scratch,
3919                                 pcmdinfo->post_sq);
3920                 break;
3921         case OP_CEQ_CREATE:
3922                 status = i40iw_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
3923                                              pcmdinfo->in.u.ceq_create.scratch,
3924                                              pcmdinfo->post_sq);
3925                 break;
3926         case OP_AEQ_CREATE:
3927                 status = i40iw_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq,
3928                                              pcmdinfo->in.u.aeq_create.scratch,
3929                                              pcmdinfo->post_sq);
3930                 break;
3931         case OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY:
3932                 status = i40iw_sc_alloc_local_mac_ipaddr_entry(
3933                                 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.cqp,
3934                                 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.scratch,
3935                                 pcmdinfo->post_sq);
3936                 break;
3937         case OP_ADD_LOCAL_MAC_IPADDR_ENTRY:
3938                 status = i40iw_sc_add_local_mac_ipaddr_entry(
3939                                 pcmdinfo->in.u.add_local_mac_ipaddr_entry.cqp,
3940                                 &pcmdinfo->in.u.add_local_mac_ipaddr_entry.info,
3941                                 pcmdinfo->in.u.add_local_mac_ipaddr_entry.scratch,
3942                                 pcmdinfo->post_sq);
3943                 break;
3944         case OP_MANAGE_QHASH_TABLE_ENTRY:
3945                 status = i40iw_sc_manage_qhash_table_entry(
3946                                 pcmdinfo->in.u.manage_qhash_table_entry.cqp,
3947                                 &pcmdinfo->in.u.manage_qhash_table_entry.info,
3948                                 pcmdinfo->in.u.manage_qhash_table_entry.scratch,
3949                                 pcmdinfo->post_sq);
3950
3951                 break;
3952         case OP_QP_MODIFY:
3953                 status = i40iw_sc_qp_modify(
3954                                 pcmdinfo->in.u.qp_modify.qp,
3955                                 &pcmdinfo->in.u.qp_modify.info,
3956                                 pcmdinfo->in.u.qp_modify.scratch,
3957                                 pcmdinfo->post_sq);
3958
3959                 break;
3960         case OP_QP_UPLOAD_CONTEXT:
3961                 status = i40iw_sc_qp_upload_context(
3962                                 pcmdinfo->in.u.qp_upload_context.dev,
3963                                 &pcmdinfo->in.u.qp_upload_context.info,
3964                                 pcmdinfo->in.u.qp_upload_context.scratch,
3965                                 pcmdinfo->post_sq);
3966
3967                 break;
3968         case OP_CQ_CREATE:
3969                 status = i40iw_sc_cq_create(
3970                                 pcmdinfo->in.u.cq_create.cq,
3971                                 pcmdinfo->in.u.cq_create.scratch,
3972                                 pcmdinfo->in.u.cq_create.check_overflow,
3973                                 pcmdinfo->post_sq);
3974                 break;
3975         case OP_CQ_DESTROY:
3976                 status = i40iw_sc_cq_destroy(
3977                                 pcmdinfo->in.u.cq_destroy.cq,
3978                                 pcmdinfo->in.u.cq_destroy.scratch,
3979                                 pcmdinfo->post_sq);
3980
3981                 break;
3982         case OP_QP_CREATE:
3983                 status = i40iw_sc_qp_create(
3984                                 pcmdinfo->in.u.qp_create.qp,
3985                                 &pcmdinfo->in.u.qp_create.info,
3986                                 pcmdinfo->in.u.qp_create.scratch,
3987                                 pcmdinfo->post_sq);
3988                 break;
3989         case OP_QP_DESTROY:
3990                 status = i40iw_sc_qp_destroy(
3991                                 pcmdinfo->in.u.qp_destroy.qp,
3992                                 pcmdinfo->in.u.qp_destroy.scratch,
3993                                 pcmdinfo->in.u.qp_destroy.remove_hash_idx,
3994                                 pcmdinfo->in.u.qp_destroy.
3995                                 ignore_mw_bnd,
3996                                 pcmdinfo->post_sq);
3997
3998                 break;
3999         case OP_ALLOC_STAG:
4000                 status = i40iw_sc_alloc_stag(
4001                                 pcmdinfo->in.u.alloc_stag.dev,
4002                                 &pcmdinfo->in.u.alloc_stag.info,
4003                                 pcmdinfo->in.u.alloc_stag.scratch,
4004                                 pcmdinfo->post_sq);
4005                 break;
4006         case OP_MR_REG_NON_SHARED:
4007                 status = i40iw_sc_mr_reg_non_shared(
4008                                 pcmdinfo->in.u.mr_reg_non_shared.dev,
4009                                 &pcmdinfo->in.u.mr_reg_non_shared.info,
4010                                 pcmdinfo->in.u.mr_reg_non_shared.scratch,
4011                                 pcmdinfo->post_sq);
4012
4013                 break;
4014         case OP_DEALLOC_STAG:
4015                 status = i40iw_sc_dealloc_stag(
4016                                 pcmdinfo->in.u.dealloc_stag.dev,
4017                                 &pcmdinfo->in.u.dealloc_stag.info,
4018                                 pcmdinfo->in.u.dealloc_stag.scratch,
4019                                 pcmdinfo->post_sq);
4020
4021                 break;
4022         case OP_MW_ALLOC:
4023                 status = i40iw_sc_mw_alloc(
4024                                 pcmdinfo->in.u.mw_alloc.dev,
4025                                 pcmdinfo->in.u.mw_alloc.scratch,
4026                                 pcmdinfo->in.u.mw_alloc.mw_stag_index,
4027                                 pcmdinfo->in.u.mw_alloc.pd_id,
4028                                 pcmdinfo->post_sq);
4029
4030                 break;
4031         case OP_QP_FLUSH_WQES:
4032                 status = i40iw_sc_qp_flush_wqes(
4033                                 pcmdinfo->in.u.qp_flush_wqes.qp,
4034                                 &pcmdinfo->in.u.qp_flush_wqes.info,
4035                                 pcmdinfo->in.u.qp_flush_wqes.
4036                                 scratch, pcmdinfo->post_sq);
4037                 break;
4038         case OP_ADD_ARP_CACHE_ENTRY:
4039                 status = i40iw_sc_add_arp_cache_entry(
4040                                 pcmdinfo->in.u.add_arp_cache_entry.cqp,
4041                                 &pcmdinfo->in.u.add_arp_cache_entry.info,
4042                                 pcmdinfo->in.u.add_arp_cache_entry.scratch,
4043                                 pcmdinfo->post_sq);
4044                 break;
4045         case OP_MANAGE_PUSH_PAGE:
4046                 status = i40iw_sc_manage_push_page(
4047                                 pcmdinfo->in.u.manage_push_page.cqp,
4048                                 &pcmdinfo->in.u.manage_push_page.info,
4049                                 pcmdinfo->in.u.manage_push_page.scratch,
4050                                 pcmdinfo->post_sq);
4051                 break;
4052         case OP_UPDATE_PE_SDS:
4053                 /* case I40IW_CQP_OP_UPDATE_PE_SDS */
4054                 status = i40iw_update_pe_sds(
4055                                 pcmdinfo->in.u.update_pe_sds.dev,
4056                                 &pcmdinfo->in.u.update_pe_sds.info,
4057                                 pcmdinfo->in.u.update_pe_sds.
4058                                 scratch);
4059
4060                 break;
4061         case OP_MANAGE_HMC_PM_FUNC_TABLE:
4062                 status = i40iw_sc_manage_hmc_pm_func_table(
4063                                 pcmdinfo->in.u.manage_hmc_pm.dev->cqp,
4064                                 pcmdinfo->in.u.manage_hmc_pm.scratch,
4065                                 (u8)pcmdinfo->in.u.manage_hmc_pm.info.vf_id,
4066                                 pcmdinfo->in.u.manage_hmc_pm.info.free_fcn,
4067                                 true);
4068                 break;
4069         case OP_SUSPEND:
4070                 status = i40iw_sc_suspend_qp(
4071                                 pcmdinfo->in.u.suspend_resume.cqp,
4072                                 pcmdinfo->in.u.suspend_resume.qp,
4073                                 pcmdinfo->in.u.suspend_resume.scratch);
4074                 break;
4075         case OP_RESUME:
4076                 status = i40iw_sc_resume_qp(
4077                                 pcmdinfo->in.u.suspend_resume.cqp,
4078                                 pcmdinfo->in.u.suspend_resume.qp,
4079                                 pcmdinfo->in.u.suspend_resume.scratch);
4080                 break;
4081         case OP_MANAGE_VF_PBLE_BP:
4082                 status = i40iw_manage_vf_pble_bp(
4083                                 pcmdinfo->in.u.manage_vf_pble_bp.cqp,
4084                                 &pcmdinfo->in.u.manage_vf_pble_bp.info,
4085                                 pcmdinfo->in.u.manage_vf_pble_bp.scratch, true);
4086                 break;
4087         case OP_QUERY_FPM_VALUES:
4088                 values_mem.pa = pcmdinfo->in.u.query_fpm_values.fpm_values_pa;
4089                 values_mem.va = pcmdinfo->in.u.query_fpm_values.fpm_values_va;
4090                 status = i40iw_sc_query_fpm_values(
4091                                 pcmdinfo->in.u.query_fpm_values.cqp,
4092                                 pcmdinfo->in.u.query_fpm_values.scratch,
4093                                 pcmdinfo->in.u.query_fpm_values.hmc_fn_id,
4094                                 &values_mem, true, I40IW_CQP_WAIT_EVENT);
4095                 break;
4096         case OP_COMMIT_FPM_VALUES:
4097                 values_mem.pa = pcmdinfo->in.u.commit_fpm_values.fpm_values_pa;
4098                 values_mem.va = pcmdinfo->in.u.commit_fpm_values.fpm_values_va;
4099                 status = i40iw_sc_commit_fpm_values(
4100                                 pcmdinfo->in.u.commit_fpm_values.cqp,
4101                                 pcmdinfo->in.u.commit_fpm_values.scratch,
4102                                 pcmdinfo->in.u.commit_fpm_values.hmc_fn_id,
4103                                 &values_mem,
4104                                 true,
4105                                 I40IW_CQP_WAIT_EVENT);
4106                 break;
4107         default:
4108                 status = I40IW_NOT_SUPPORTED;
4109                 break;
4110         }
4111
4112         return status;
4113 }
4114
4115 /**
4116  * i40iw_process_cqp_cmd - process all cqp commands
4117  * @dev: sc device struct
4118  * @pcmdinfo: cqp command info
4119  */
4120 enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev,
4121                                              struct cqp_commands_info *pcmdinfo)
4122 {
4123         enum i40iw_status_code status = 0;
4124         unsigned long flags;
4125
4126         spin_lock_irqsave(&dev->cqp_lock, flags);
4127         if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp))
4128                 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4129         else
4130                 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head);
4131         spin_unlock_irqrestore(&dev->cqp_lock, flags);
4132         return status;
4133 }
4134
4135 /**
4136  * i40iw_process_bh - called from tasklet for cqp list
4137  * @dev: sc device struct
4138  */
4139 enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev)
4140 {
4141         enum i40iw_status_code status = 0;
4142         struct cqp_commands_info *pcmdinfo;
4143         unsigned long flags;
4144
4145         spin_lock_irqsave(&dev->cqp_lock, flags);
4146         while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) {
4147                 pcmdinfo = (struct cqp_commands_info *)i40iw_remove_head(&dev->cqp_cmd_head);
4148
4149                 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4150                 if (status)
4151                         break;
4152         }
4153         spin_unlock_irqrestore(&dev->cqp_lock, flags);
4154         return status;
4155 }
4156
4157 /**
4158  * i40iw_iwarp_opcode - determine if incoming is rdma layer
4159  * @info: aeq info for the packet
4160  * @pkt: packet for error
4161  */
4162 static u32 i40iw_iwarp_opcode(struct i40iw_aeqe_info *info, u8 *pkt)
4163 {
4164         __be16 *mpa;
4165         u32 opcode = 0xffffffff;
4166
4167         if (info->q2_data_written) {
4168                 mpa = (__be16 *)pkt;
4169                 opcode = ntohs(mpa[1]) & 0xf;
4170         }
4171         return opcode;
4172 }
4173
4174 /**
4175  * i40iw_locate_mpa - return pointer to mpa in the pkt
4176  * @pkt: packet with data
4177  */
4178 static u8 *i40iw_locate_mpa(u8 *pkt)
4179 {
4180         /* skip over ethernet header */
4181         pkt += I40IW_MAC_HLEN;
4182
4183         /* Skip over IP and TCP headers */
4184         pkt += 4 * (pkt[0] & 0x0f);
4185         pkt += 4 * ((pkt[12] >> 4) & 0x0f);
4186         return pkt;
4187 }
4188
4189 /**
4190  * i40iw_setup_termhdr - termhdr for terminate pkt
4191  * @qp: sc qp ptr for pkt
4192  * @hdr: term hdr
4193  * @opcode: flush opcode for termhdr
4194  * @layer_etype: error layer + error type
4195  * @err: error cod ein the header
4196  */
4197 static void i40iw_setup_termhdr(struct i40iw_sc_qp *qp,
4198                                 struct i40iw_terminate_hdr *hdr,
4199                                 enum i40iw_flush_opcode opcode,
4200                                 u8 layer_etype,
4201                                 u8 err)
4202 {
4203         qp->flush_code = opcode;
4204         hdr->layer_etype = layer_etype;
4205         hdr->error_code = err;
4206 }
4207
4208 /**
4209  * i40iw_bld_terminate_hdr - build terminate message header
4210  * @qp: qp associated with received terminate AE
4211  * @info: the struct contiaing AE information
4212  */
4213 static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4214                                    struct i40iw_aeqe_info *info)
4215 {
4216         u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4217         u16 ddp_seg_len;
4218         int copy_len = 0;
4219         u8 is_tagged = 0;
4220         u32 opcode;
4221         struct i40iw_terminate_hdr *termhdr;
4222
4223         termhdr = (struct i40iw_terminate_hdr *)qp->q2_buf;
4224         memset(termhdr, 0, Q2_BAD_FRAME_OFFSET);
4225
4226         if (info->q2_data_written) {
4227                 /* Use data from offending packet to fill in ddp & rdma hdrs */
4228                 pkt = i40iw_locate_mpa(pkt);
4229                 ddp_seg_len = ntohs(*(__be16 *)pkt);
4230                 if (ddp_seg_len) {
4231                         copy_len = 2;
4232                         termhdr->hdrct = DDP_LEN_FLAG;
4233                         if (pkt[2] & 0x80) {
4234                                 is_tagged = 1;
4235                                 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
4236                                         copy_len += TERM_DDP_LEN_TAGGED;
4237                                         termhdr->hdrct |= DDP_HDR_FLAG;
4238                                 }
4239                         } else {
4240                                 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
4241                                         copy_len += TERM_DDP_LEN_UNTAGGED;
4242                                         termhdr->hdrct |= DDP_HDR_FLAG;
4243                                 }
4244
4245                                 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
4246                                         if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
4247                                                 copy_len += TERM_RDMA_LEN;
4248                                                 termhdr->hdrct |= RDMA_HDR_FLAG;
4249                                         }
4250                                 }
4251                         }
4252                 }
4253         }
4254
4255         opcode = i40iw_iwarp_opcode(info, pkt);
4256
4257         switch (info->ae_id) {
4258         case I40IW_AE_AMP_UNALLOCATED_STAG:
4259                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4260                 if (opcode == I40IW_OP_TYPE_RDMA_WRITE)
4261                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4262                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_STAG);
4263                 else
4264                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4265                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4266                 break;
4267         case I40IW_AE_AMP_BOUNDS_VIOLATION:
4268                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4269                 if (info->q2_data_written)
4270                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4271                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_BOUNDS);
4272                 else
4273                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4274                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_BOUNDS);
4275                 break;
4276         case I40IW_AE_AMP_BAD_PD:
4277                 switch (opcode) {
4278                 case I40IW_OP_TYPE_RDMA_WRITE:
4279                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4280                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_UNASSOC_STAG);
4281                         break;
4282                 case I40IW_OP_TYPE_SEND_INV:
4283                 case I40IW_OP_TYPE_SEND_SOL_INV:
4284                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4285                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_CANT_INV_STAG);
4286                         break;
4287                 default:
4288                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4289                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_UNASSOC_STAG);
4290                 }
4291                 break;
4292         case I40IW_AE_AMP_INVALID_STAG:
4293                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4294                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4295                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4296                 break;
4297         case I40IW_AE_AMP_BAD_QP:
4298                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4299                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4300                 break;
4301         case I40IW_AE_AMP_BAD_STAG_KEY:
4302         case I40IW_AE_AMP_BAD_STAG_INDEX:
4303                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4304                 switch (opcode) {
4305                 case I40IW_OP_TYPE_SEND_INV:
4306                 case I40IW_OP_TYPE_SEND_SOL_INV:
4307                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4308                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_CANT_INV_STAG);
4309                         break;
4310                 default:
4311                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4312                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_STAG);
4313                 }
4314                 break;
4315         case I40IW_AE_AMP_RIGHTS_VIOLATION:
4316         case I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
4317         case I40IW_AE_PRIV_OPERATION_DENIED:
4318                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4319                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4320                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_ACCESS);
4321                 break;
4322         case I40IW_AE_AMP_TO_WRAP:
4323                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4324                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4325                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP);
4326                 break;
4327         case I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
4328                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4329                                     (LAYER_MPA << 4) | DDP_LLP, MPA_MARKER);
4330                 break;
4331         case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4332                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4333                                     (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
4334                 break;
4335         case I40IW_AE_LLP_SEGMENT_TOO_LARGE:
4336         case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
4337                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4338                                     (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4339                 break;
4340         case I40IW_AE_LCE_QP_CATASTROPHIC:
4341         case I40IW_AE_DDP_NO_L_BIT:
4342                 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4343                                     (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4344                 break;
4345         case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN:
4346         case I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
4347                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4348                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE);
4349                 break;
4350         case I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
4351                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4352                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4353                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_TOO_LONG);
4354                 break;
4355         case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
4356                 if (is_tagged)
4357                         i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4358                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_DDP_VER);
4359                 else
4360                         i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4361                                             (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_DDP_VER);
4362                 break;
4363         case I40IW_AE_DDP_UBE_INVALID_MO:
4364                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4365                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MO);
4366                 break;
4367         case I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
4368                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4369                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_NO_BUF);
4370                 break;
4371         case I40IW_AE_DDP_UBE_INVALID_QN:
4372                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4373                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4374                 break;
4375         case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
4376                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4377                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_RDMAP_VER);
4378                 break;
4379         case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
4380                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4381                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNEXPECTED_OP);
4382                 break;
4383         default:
4384                 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4385                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNSPECIFIED);
4386                 break;
4387         }
4388
4389         if (copy_len)
4390                 memcpy(termhdr + 1, pkt, copy_len);
4391
4392         return sizeof(struct i40iw_terminate_hdr) + copy_len;
4393 }
4394
4395 /**
4396  * i40iw_terminate_send_fin() - Send fin for terminate message
4397  * @qp: qp associated with received terminate AE
4398  */
4399 void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp)
4400 {
4401         /* Send the fin only */
4402         i40iw_term_modify_qp(qp,
4403                              I40IW_QP_STATE_TERMINATE,
4404                              I40IWQP_TERM_SEND_FIN_ONLY,
4405                              0);
4406 }
4407
4408 /**
4409  * i40iw_terminate_connection() - Bad AE and send terminate to remote QP
4410  * @qp: qp associated with received terminate AE
4411  * @info: the struct contiaing AE information
4412  */
4413 void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4414 {
4415         u8 termlen = 0;
4416
4417         if (qp->term_flags & I40IW_TERM_SENT)
4418                 return;         /* Sanity check */
4419
4420         /* Eventtype can change from bld_terminate_hdr */
4421         qp->eventtype = TERM_EVENT_QP_FATAL;
4422         termlen = i40iw_bld_terminate_hdr(qp, info);
4423         i40iw_terminate_start_timer(qp);
4424         qp->term_flags |= I40IW_TERM_SENT;
4425         i40iw_term_modify_qp(qp, I40IW_QP_STATE_TERMINATE,
4426                              I40IWQP_TERM_SEND_TERM_ONLY, termlen);
4427 }
4428
4429 /**
4430  * i40iw_terminate_received - handle terminate received AE
4431  * @qp: qp associated with received terminate AE
4432  * @info: the struct contiaing AE information
4433  */
4434 void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4435 {
4436         u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4437         __be32 *mpa;
4438         u8 ddp_ctl;
4439         u8 rdma_ctl;
4440         u16 aeq_id = 0;
4441         struct i40iw_terminate_hdr *termhdr;
4442
4443         mpa = (__be32 *)i40iw_locate_mpa(pkt);
4444         if (info->q2_data_written) {
4445                 /* did not validate the frame - do it now */
4446                 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff;
4447                 rdma_ctl = ntohl(mpa[0]) & 0xff;
4448                 if ((ddp_ctl & 0xc0) != 0x40)
4449                         aeq_id = I40IW_AE_LCE_QP_CATASTROPHIC;
4450                 else if ((ddp_ctl & 0x03) != 1)
4451                         aeq_id = I40IW_AE_DDP_UBE_INVALID_DDP_VERSION;
4452                 else if (ntohl(mpa[2]) != 2)
4453                         aeq_id = I40IW_AE_DDP_UBE_INVALID_QN;
4454                 else if (ntohl(mpa[3]) != 1)
4455                         aeq_id = I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN;
4456                 else if (ntohl(mpa[4]) != 0)
4457                         aeq_id = I40IW_AE_DDP_UBE_INVALID_MO;
4458                 else if ((rdma_ctl & 0xc0) != 0x40)
4459                         aeq_id = I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION;
4460
4461                 info->ae_id = aeq_id;
4462                 if (info->ae_id) {
4463                         /* Bad terminate recvd - send back a terminate */
4464                         i40iw_terminate_connection(qp, info);
4465                         return;
4466                 }
4467         }
4468
4469         qp->term_flags |= I40IW_TERM_RCVD;
4470         qp->eventtype = TERM_EVENT_QP_FATAL;
4471         termhdr = (struct i40iw_terminate_hdr *)&mpa[5];
4472         if (termhdr->layer_etype == RDMAP_REMOTE_PROT ||
4473             termhdr->layer_etype == RDMAP_REMOTE_OP) {
4474                 i40iw_terminate_done(qp, 0);
4475         } else {
4476                 i40iw_terminate_start_timer(qp);
4477                 i40iw_terminate_send_fin(qp);
4478         }
4479 }
4480
4481 /**
4482  * i40iw_sc_vsi_init - Initialize virtual device
4483  * @vsi: pointer to the vsi structure
4484  * @info: parameters to initialize vsi
4485  **/
4486 void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info)
4487 {
4488         int i;
4489
4490         vsi->dev = info->dev;
4491         vsi->back_vsi = info->back_vsi;
4492         vsi->mss = info->params->mss;
4493         i40iw_fill_qos_list(info->params->qs_handle_list);
4494
4495         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
4496                 vsi->qos[i].qs_handle = info->params->qs_handle_list[i];
4497                 i40iw_debug(vsi->dev, I40IW_DEBUG_DCB, "qset[%d]: %d\n", i,
4498                             vsi->qos[i].qs_handle);
4499                 spin_lock_init(&vsi->qos[i].lock);
4500                 INIT_LIST_HEAD(&vsi->qos[i].qplist);
4501         }
4502 }
4503
4504 /**
4505  * i40iw_hw_stats_init - Initiliaze HW stats table
4506  * @stats: pestat struct
4507  * @fcn_idx: PCI fn id
4508  * @is_pf: Is it a PF?
4509  *
4510  * Populate the HW stats table with register offset addr for each
4511  * stats. And start the perioidic stats timer.
4512  */
4513 void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 fcn_idx, bool is_pf)
4514 {
4515         u32 stats_reg_offset;
4516         u32 stats_index;
4517         struct i40iw_dev_hw_stats_offsets *stats_table =
4518                 &stats->hw_stats_offsets;
4519         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4520
4521         if (is_pf) {
4522                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4523                                 I40E_GLPES_PFIP4RXDISCARD(fcn_idx);
4524                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4525                                 I40E_GLPES_PFIP4RXTRUNC(fcn_idx);
4526                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4527                                 I40E_GLPES_PFIP4TXNOROUTE(fcn_idx);
4528                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4529                                 I40E_GLPES_PFIP6RXDISCARD(fcn_idx);
4530                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4531                                 I40E_GLPES_PFIP6RXTRUNC(fcn_idx);
4532                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4533                                 I40E_GLPES_PFIP6TXNOROUTE(fcn_idx);
4534                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4535                                 I40E_GLPES_PFTCPRTXSEG(fcn_idx);
4536                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4537                                 I40E_GLPES_PFTCPRXOPTERR(fcn_idx);
4538                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4539                                 I40E_GLPES_PFTCPRXPROTOERR(fcn_idx);
4540
4541                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4542                                 I40E_GLPES_PFIP4RXOCTSLO(fcn_idx);
4543                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4544                                 I40E_GLPES_PFIP4RXPKTSLO(fcn_idx);
4545                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4546                                 I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx);
4547                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4548                                 I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx);
4549                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4550                                 I40E_GLPES_PFIP4TXOCTSLO(fcn_idx);
4551                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4552                                 I40E_GLPES_PFIP4TXPKTSLO(fcn_idx);
4553                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4554                                 I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx);
4555                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4556                                 I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx);
4557                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4558                                 I40E_GLPES_PFIP6RXOCTSLO(fcn_idx);
4559                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4560                                 I40E_GLPES_PFIP6RXPKTSLO(fcn_idx);
4561                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4562                                 I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx);
4563                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4564                                 I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx);
4565                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4566                                 I40E_GLPES_PFIP6TXOCTSLO(fcn_idx);
4567                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4568                                 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4569                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4570                                 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4571                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4572                                 I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx);
4573                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4574                                 I40E_GLPES_PFTCPRXSEGSLO(fcn_idx);
4575                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4576                                 I40E_GLPES_PFTCPTXSEGLO(fcn_idx);
4577                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4578                                 I40E_GLPES_PFRDMARXRDSLO(fcn_idx);
4579                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4580                                 I40E_GLPES_PFRDMARXSNDSLO(fcn_idx);
4581                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4582                                 I40E_GLPES_PFRDMARXWRSLO(fcn_idx);
4583                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4584                                 I40E_GLPES_PFRDMATXRDSLO(fcn_idx);
4585                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4586                                 I40E_GLPES_PFRDMATXSNDSLO(fcn_idx);
4587                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4588                                 I40E_GLPES_PFRDMATXWRSLO(fcn_idx);
4589                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4590                                 I40E_GLPES_PFRDMAVBNDLO(fcn_idx);
4591                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4592                                 I40E_GLPES_PFRDMAVINVLO(fcn_idx);
4593         } else {
4594                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4595                                 I40E_GLPES_VFIP4RXDISCARD(fcn_idx);
4596                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4597                                 I40E_GLPES_VFIP4RXTRUNC(fcn_idx);
4598                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4599                                 I40E_GLPES_VFIP4TXNOROUTE(fcn_idx);
4600                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4601                                 I40E_GLPES_VFIP6RXDISCARD(fcn_idx);
4602                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4603                                 I40E_GLPES_VFIP6RXTRUNC(fcn_idx);
4604                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4605                                 I40E_GLPES_VFIP6TXNOROUTE(fcn_idx);
4606                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4607                                 I40E_GLPES_VFTCPRTXSEG(fcn_idx);
4608                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4609                                 I40E_GLPES_VFTCPRXOPTERR(fcn_idx);
4610                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4611                                 I40E_GLPES_VFTCPRXPROTOERR(fcn_idx);
4612
4613                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4614                                 I40E_GLPES_VFIP4RXOCTSLO(fcn_idx);
4615                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4616                                 I40E_GLPES_VFIP4RXPKTSLO(fcn_idx);
4617                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4618                                 I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx);
4619                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4620                                 I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx);
4621                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4622                                 I40E_GLPES_VFIP4TXOCTSLO(fcn_idx);
4623                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4624                                 I40E_GLPES_VFIP4TXPKTSLO(fcn_idx);
4625                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4626                                 I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx);
4627                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4628                                 I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx);
4629                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4630                                 I40E_GLPES_VFIP6RXOCTSLO(fcn_idx);
4631                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4632                                 I40E_GLPES_VFIP6RXPKTSLO(fcn_idx);
4633                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4634                                 I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx);
4635                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4636                                 I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx);
4637                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4638                                 I40E_GLPES_VFIP6TXOCTSLO(fcn_idx);
4639                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4640                                 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4641                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4642                                 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4643                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4644                                 I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx);
4645                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4646                                 I40E_GLPES_VFTCPRXSEGSLO(fcn_idx);
4647                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4648                                 I40E_GLPES_VFTCPTXSEGLO(fcn_idx);
4649                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4650                                 I40E_GLPES_VFRDMARXRDSLO(fcn_idx);
4651                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4652                                 I40E_GLPES_VFRDMARXSNDSLO(fcn_idx);
4653                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4654                                 I40E_GLPES_VFRDMARXWRSLO(fcn_idx);
4655                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4656                                 I40E_GLPES_VFRDMATXRDSLO(fcn_idx);
4657                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4658                                 I40E_GLPES_VFRDMATXSNDSLO(fcn_idx);
4659                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4660                                 I40E_GLPES_VFRDMATXWRSLO(fcn_idx);
4661                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4662                                 I40E_GLPES_VFRDMAVBNDLO(fcn_idx);
4663                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4664                                 I40E_GLPES_VFRDMAVINVLO(fcn_idx);
4665         }
4666
4667         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4668              stats_index++) {
4669                 stats_reg_offset = stats_table->stats_offset_64[stats_index];
4670                 last_rd_stats->stats_value_64[stats_index] =
4671                         readq(stats->hw->hw_addr + stats_reg_offset);
4672         }
4673
4674         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4675              stats_index++) {
4676                 stats_reg_offset = stats_table->stats_offset_32[stats_index];
4677                 last_rd_stats->stats_value_32[stats_index] =
4678                         i40iw_rd32(stats->hw, stats_reg_offset);
4679         }
4680 }
4681
4682 /**
4683  * i40iw_hw_stats_read_32 - Read 32-bit HW stats counters and accommodates for roll-overs.
4684  * @stat: pestat struct
4685  * @index: index in HW stats table which contains offset reg-addr
4686  * @value: hw stats value
4687  */
4688 void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats,
4689                             enum i40iw_hw_stats_index_32b index,
4690                             u64 *value)
4691 {
4692         struct i40iw_dev_hw_stats_offsets *stats_table =
4693                 &stats->hw_stats_offsets;
4694         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4695         struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4696         u64 new_stats_value = 0;
4697         u32 stats_reg_offset = stats_table->stats_offset_32[index];
4698
4699         new_stats_value = i40iw_rd32(stats->hw, stats_reg_offset);
4700         /*roll-over case */
4701         if (new_stats_value < last_rd_stats->stats_value_32[index])
4702                 hw_stats->stats_value_32[index] += new_stats_value;
4703         else
4704                 hw_stats->stats_value_32[index] +=
4705                         new_stats_value - last_rd_stats->stats_value_32[index];
4706         last_rd_stats->stats_value_32[index] = new_stats_value;
4707         *value = hw_stats->stats_value_32[index];
4708 }
4709
4710 /**
4711  * i40iw_hw_stats_read_64 - Read HW stats counters (greater than 32-bit) and accommodates for roll-overs.
4712  * @stats: pestat struct
4713  * @index: index in HW stats table which contains offset reg-addr
4714  * @value: hw stats value
4715  */
4716 void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats,
4717                             enum i40iw_hw_stats_index_64b index,
4718                             u64 *value)
4719 {
4720         struct i40iw_dev_hw_stats_offsets *stats_table =
4721                 &stats->hw_stats_offsets;
4722         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4723         struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4724         u64 new_stats_value = 0;
4725         u32 stats_reg_offset = stats_table->stats_offset_64[index];
4726
4727         new_stats_value = readq(stats->hw->hw_addr + stats_reg_offset);
4728         /*roll-over case */
4729         if (new_stats_value < last_rd_stats->stats_value_64[index])
4730                 hw_stats->stats_value_64[index] += new_stats_value;
4731         else
4732                 hw_stats->stats_value_64[index] +=
4733                         new_stats_value - last_rd_stats->stats_value_64[index];
4734         last_rd_stats->stats_value_64[index] = new_stats_value;
4735         *value = hw_stats->stats_value_64[index];
4736 }
4737
4738 /**
4739  * i40iw_hw_stats_read_all - read all HW stat counters
4740  * @stats: pestat struct
4741  * @stats_values: hw stats structure
4742  *
4743  * Read all the HW stat counters and populates hw_stats structure
4744  * of passed-in vsi's pestat as well as copy created in stat_values.
4745  */
4746 void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats,
4747                              struct i40iw_dev_hw_stats *stats_values)
4748 {
4749         u32 stats_index;
4750         unsigned long flags;
4751
4752         spin_lock_irqsave(&stats->lock, flags);
4753
4754         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4755              stats_index++)
4756                 i40iw_hw_stats_read_32(stats, stats_index,
4757                                        &stats_values->stats_value_32[stats_index]);
4758         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4759              stats_index++)
4760                 i40iw_hw_stats_read_64(stats, stats_index,
4761                                        &stats_values->stats_value_64[stats_index]);
4762         spin_unlock_irqrestore(&stats->lock, flags);
4763 }
4764
4765 /**
4766  * i40iw_hw_stats_refresh_all - Update all HW stats structs
4767  * @stats: pestat struct
4768  *
4769  * Read all the HW stats counters to refresh values in hw_stats structure
4770  * of passed-in dev's pestat
4771  */
4772 void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats)
4773 {
4774         u64 stats_value;
4775         u32 stats_index;
4776         unsigned long flags;
4777
4778         spin_lock_irqsave(&stats->lock, flags);
4779
4780         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4781              stats_index++)
4782                 i40iw_hw_stats_read_32(stats, stats_index, &stats_value);
4783         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4784              stats_index++)
4785                 i40iw_hw_stats_read_64(stats, stats_index, &stats_value);
4786         spin_unlock_irqrestore(&stats->lock, flags);
4787 }
4788
4789 /**
4790  * i40iw_get_fcn_id - Return the function id
4791  * @dev: pointer to the device
4792  */
4793 static u8 i40iw_get_fcn_id(struct i40iw_sc_dev *dev)
4794 {
4795         u8 fcn_id = I40IW_INVALID_FCN_ID;
4796         u8 i;
4797
4798         for (i = I40IW_FIRST_NON_PF_STAT; i < I40IW_MAX_STATS_COUNT; i++)
4799                 if (!dev->fcn_id_array[i]) {
4800                         fcn_id = i;
4801                         dev->fcn_id_array[i] = true;
4802                         break;
4803                 }
4804         return fcn_id;
4805 }
4806
4807 /**
4808  * i40iw_vsi_stats_init - Initialize the vsi statistics
4809  * @vsi: pointer to the vsi structure
4810  * @info: The info structure used for initialization
4811  */
4812 enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info)
4813 {
4814         u8 fcn_id = info->fcn_id;
4815
4816         if (info->alloc_fcn_id)
4817                 fcn_id = i40iw_get_fcn_id(vsi->dev);
4818
4819         if (fcn_id == I40IW_INVALID_FCN_ID)
4820                 return I40IW_ERR_NOT_READY;
4821
4822         vsi->pestat = info->pestat;
4823         vsi->pestat->hw = vsi->dev->hw;
4824
4825         if (info->stats_initialize) {
4826                 i40iw_hw_stats_init(vsi->pestat, fcn_id, true);
4827                 spin_lock_init(&vsi->pestat->lock);
4828                 i40iw_hw_stats_start_timer(vsi);
4829         }
4830         vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
4831         vsi->fcn_id = fcn_id;
4832         return I40IW_SUCCESS;
4833 }
4834
4835 /**
4836  * i40iw_vsi_stats_free - Free the vsi stats
4837  * @vsi: pointer to the vsi structure
4838  */
4839 void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi)
4840 {
4841         u8 fcn_id = vsi->fcn_id;
4842
4843         if ((vsi->stats_fcn_id_alloc) && (fcn_id != I40IW_INVALID_FCN_ID))
4844                 vsi->dev->fcn_id_array[fcn_id] = false;
4845         i40iw_hw_stats_stop_timer(vsi);
4846 }
4847
4848 static struct i40iw_cqp_ops iw_cqp_ops = {
4849         .cqp_init = i40iw_sc_cqp_init,
4850         .cqp_create = i40iw_sc_cqp_create,
4851         .cqp_post_sq = i40iw_sc_cqp_post_sq,
4852         .cqp_get_next_send_wqe = i40iw_sc_cqp_get_next_send_wqe,
4853         .cqp_destroy = i40iw_sc_cqp_destroy,
4854         .poll_for_cqp_op_done = i40iw_sc_poll_for_cqp_op_done
4855 };
4856
4857 static struct i40iw_ccq_ops iw_ccq_ops = {
4858         .ccq_init = i40iw_sc_ccq_init,
4859         .ccq_create = i40iw_sc_ccq_create,
4860         .ccq_destroy = i40iw_sc_ccq_destroy,
4861         .ccq_create_done = i40iw_sc_ccq_create_done,
4862         .ccq_get_cqe_info = i40iw_sc_ccq_get_cqe_info,
4863         .ccq_arm = i40iw_sc_ccq_arm
4864 };
4865
4866 static struct i40iw_ceq_ops iw_ceq_ops = {
4867         .ceq_init = i40iw_sc_ceq_init,
4868         .ceq_create = i40iw_sc_ceq_create,
4869         .cceq_create_done = i40iw_sc_cceq_create_done,
4870         .cceq_destroy_done = i40iw_sc_cceq_destroy_done,
4871         .cceq_create = i40iw_sc_cceq_create,
4872         .ceq_destroy = i40iw_sc_ceq_destroy,
4873         .process_ceq = i40iw_sc_process_ceq
4874 };
4875
4876 static struct i40iw_aeq_ops iw_aeq_ops = {
4877         .aeq_init = i40iw_sc_aeq_init,
4878         .aeq_create = i40iw_sc_aeq_create,
4879         .aeq_destroy = i40iw_sc_aeq_destroy,
4880         .get_next_aeqe = i40iw_sc_get_next_aeqe,
4881         .repost_aeq_entries = i40iw_sc_repost_aeq_entries,
4882         .aeq_create_done = i40iw_sc_aeq_create_done,
4883         .aeq_destroy_done = i40iw_sc_aeq_destroy_done
4884 };
4885
4886 /* iwarp pd ops */
4887 static struct i40iw_pd_ops iw_pd_ops = {
4888         .pd_init = i40iw_sc_pd_init,
4889 };
4890
4891 static struct i40iw_priv_qp_ops iw_priv_qp_ops = {
4892         .qp_init = i40iw_sc_qp_init,
4893         .qp_create = i40iw_sc_qp_create,
4894         .qp_modify = i40iw_sc_qp_modify,
4895         .qp_destroy = i40iw_sc_qp_destroy,
4896         .qp_flush_wqes = i40iw_sc_qp_flush_wqes,
4897         .qp_upload_context = i40iw_sc_qp_upload_context,
4898         .qp_setctx = i40iw_sc_qp_setctx,
4899         .qp_send_lsmm = i40iw_sc_send_lsmm,
4900         .qp_send_lsmm_nostag = i40iw_sc_send_lsmm_nostag,
4901         .qp_send_rtt = i40iw_sc_send_rtt,
4902         .qp_post_wqe0 = i40iw_sc_post_wqe0,
4903         .iw_mr_fast_register = i40iw_sc_mr_fast_register
4904 };
4905
4906 static struct i40iw_priv_cq_ops iw_priv_cq_ops = {
4907         .cq_init = i40iw_sc_cq_init,
4908         .cq_create = i40iw_sc_cq_create,
4909         .cq_destroy = i40iw_sc_cq_destroy,
4910         .cq_modify = i40iw_sc_cq_modify,
4911 };
4912
4913 static struct i40iw_mr_ops iw_mr_ops = {
4914         .alloc_stag = i40iw_sc_alloc_stag,
4915         .mr_reg_non_shared = i40iw_sc_mr_reg_non_shared,
4916         .mr_reg_shared = i40iw_sc_mr_reg_shared,
4917         .dealloc_stag = i40iw_sc_dealloc_stag,
4918         .query_stag = i40iw_sc_query_stag,
4919         .mw_alloc = i40iw_sc_mw_alloc
4920 };
4921
4922 static struct i40iw_cqp_misc_ops iw_cqp_misc_ops = {
4923         .manage_push_page = i40iw_sc_manage_push_page,
4924         .manage_hmc_pm_func_table = i40iw_sc_manage_hmc_pm_func_table,
4925         .set_hmc_resource_profile = i40iw_sc_set_hmc_resource_profile,
4926         .commit_fpm_values = i40iw_sc_commit_fpm_values,
4927         .query_fpm_values = i40iw_sc_query_fpm_values,
4928         .static_hmc_pages_allocated = i40iw_sc_static_hmc_pages_allocated,
4929         .add_arp_cache_entry = i40iw_sc_add_arp_cache_entry,
4930         .del_arp_cache_entry = i40iw_sc_del_arp_cache_entry,
4931         .query_arp_cache_entry = i40iw_sc_query_arp_cache_entry,
4932         .manage_apbvt_entry = i40iw_sc_manage_apbvt_entry,
4933         .manage_qhash_table_entry = i40iw_sc_manage_qhash_table_entry,
4934         .alloc_local_mac_ipaddr_table_entry = i40iw_sc_alloc_local_mac_ipaddr_entry,
4935         .add_local_mac_ipaddr_entry = i40iw_sc_add_local_mac_ipaddr_entry,
4936         .del_local_mac_ipaddr_entry = i40iw_sc_del_local_mac_ipaddr_entry,
4937         .cqp_nop = i40iw_sc_cqp_nop,
4938         .commit_fpm_values_done = i40iw_sc_commit_fpm_values_done,
4939         .query_fpm_values_done = i40iw_sc_query_fpm_values_done,
4940         .manage_hmc_pm_func_table_done = i40iw_sc_manage_hmc_pm_func_table_done,
4941         .update_suspend_qp = i40iw_sc_suspend_qp,
4942         .update_resume_qp = i40iw_sc_resume_qp
4943 };
4944
4945 static struct i40iw_hmc_ops iw_hmc_ops = {
4946         .init_iw_hmc = i40iw_sc_init_iw_hmc,
4947         .parse_fpm_query_buf = i40iw_sc_parse_fpm_query_buf,
4948         .configure_iw_fpm = i40iw_sc_configure_iw_fpm,
4949         .parse_fpm_commit_buf = i40iw_sc_parse_fpm_commit_buf,
4950         .create_hmc_object = i40iw_sc_create_hmc_obj,
4951         .del_hmc_object = i40iw_sc_del_hmc_obj
4952 };
4953
4954 /**
4955  * i40iw_device_init - Initialize IWARP device
4956  * @dev: IWARP device pointer
4957  * @info: IWARP init info
4958  */
4959 enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
4960                                          struct i40iw_device_init_info *info)
4961 {
4962         u32 val;
4963         u32 vchnl_ver = 0;
4964         u16 hmc_fcn = 0;
4965         enum i40iw_status_code ret_code = 0;
4966         u8 db_size;
4967
4968         spin_lock_init(&dev->cqp_lock);
4969         INIT_LIST_HEAD(&dev->cqp_cmd_head);             /* for the cqp commands backlog. */
4970
4971         i40iw_device_init_uk(&dev->dev_uk);
4972
4973         dev->debug_mask = info->debug_mask;
4974
4975         dev->hmc_fn_id = info->hmc_fn_id;
4976         dev->exception_lan_queue = info->exception_lan_queue;
4977         dev->is_pf = info->is_pf;
4978
4979         dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
4980         dev->fpm_query_buf = info->fpm_query_buf;
4981
4982         dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
4983         dev->fpm_commit_buf = info->fpm_commit_buf;
4984
4985         dev->hw = info->hw;
4986         dev->hw->hw_addr = info->bar0;
4987
4988         if (dev->is_pf) {
4989                 val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID);
4990                 dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID);
4991
4992                 val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL);
4993                 db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE);
4994                 if ((db_size != I40IW_PE_DB_SIZE_4M) &&
4995                     (db_size != I40IW_PE_DB_SIZE_8M)) {
4996                         i40iw_debug(dev, I40IW_DEBUG_DEV,
4997                                     "%s: PE doorbell is not enabled in CSR val 0x%x\n",
4998                                     __func__, val);
4999                         ret_code = I40IW_ERR_PE_DOORBELL_NOT_ENABLED;
5000                         return ret_code;
5001                 }
5002                 dev->db_addr = dev->hw->hw_addr + I40IW_DB_ADDR_OFFSET;
5003                 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_pf;
5004         } else {
5005                 dev->db_addr = dev->hw->hw_addr + I40IW_VF_DB_ADDR_OFFSET;
5006         }
5007
5008         dev->cqp_ops = &iw_cqp_ops;
5009         dev->ccq_ops = &iw_ccq_ops;
5010         dev->ceq_ops = &iw_ceq_ops;
5011         dev->aeq_ops = &iw_aeq_ops;
5012         dev->cqp_misc_ops = &iw_cqp_misc_ops;
5013         dev->iw_pd_ops = &iw_pd_ops;
5014         dev->iw_priv_qp_ops = &iw_priv_qp_ops;
5015         dev->iw_priv_cq_ops = &iw_priv_cq_ops;
5016         dev->mr_ops = &iw_mr_ops;
5017         dev->hmc_ops = &iw_hmc_ops;
5018         dev->vchnl_if.vchnl_send = info->vchnl_send;
5019         if (dev->vchnl_if.vchnl_send)
5020                 dev->vchnl_up = true;
5021         else
5022                 dev->vchnl_up = false;
5023         if (!dev->is_pf) {
5024                 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_vf;
5025                 ret_code = i40iw_vchnl_vf_get_ver(dev, &vchnl_ver);
5026                 if (!ret_code) {
5027                         i40iw_debug(dev, I40IW_DEBUG_DEV,
5028                                     "%s: Get Channel version rc = 0x%0x, version is %u\n",
5029                                 __func__, ret_code, vchnl_ver);
5030                         ret_code = i40iw_vchnl_vf_get_hmc_fcn(dev, &hmc_fcn);
5031                         if (!ret_code) {
5032                                 i40iw_debug(dev, I40IW_DEBUG_DEV,
5033                                             "%s Get HMC function rc = 0x%0x, hmc fcn is %u\n",
5034                                             __func__, ret_code, hmc_fcn);
5035                                 dev->hmc_fn_id = (u8)hmc_fcn;
5036                         }
5037                 }
5038         }
5039         dev->iw_vf_cqp_ops = &iw_vf_cqp_ops;
5040
5041         return ret_code;
5042 }